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IDF master c13afea63 (#5214)

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esp-dsp: master 7cc5073
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 6f8489e
esp_littlefs: master b58f00c
This commit is contained in:
Me No Dev
2021-05-31 16:32:51 +03:00
committed by GitHub
parent 0db9e2f45b
commit a618fc1361
616 changed files with 11842 additions and 4932 deletions
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18
tools/sdk/esp32c3/include/app_trace/include/esp_app_trace.h
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@ -1,16 +1,8 @@
// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ESP_APP_TRACE_H_
#define ESP_APP_TRACE_H_

18
tools/sdk/esp32c3/include/app_trace/include/esp_app_trace_util.h
View File

@ -1,16 +1,8 @@
// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ESP_APP_TRACE_UTIL_H_
#define ESP_APP_TRACE_UTIL_H_

18
tools/sdk/esp32c3/include/app_trace/include/esp_sysview_trace.h
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@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ESP_SYSVIEW_TRACE_H_
#define ESP_SYSVIEW_TRACE_H_

18
tools/sdk/esp32c3/include/app_update/include/esp_ota_ops.h
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@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _OTA_OPS_H
#define _OTA_OPS_H

13
tools/sdk/esp32c3/include/bootloader_support/include/bootloader_random.h
View File

@ -24,13 +24,14 @@ extern "C" {
* @brief Enable early entropy source for RNG
*
* Uses the SAR ADC to feed entropy into the HWRNG. The ADC is put
* into a test mode that reads the 1.1V internal reference source and
* feeds the LSB of data into the HWRNG.
* into a test mode that reads an internal reference voltage and
* constantly feeds the LSB of data into the HWRNG. Consult the
* SoC Technical Reference Manual for more information.
*
* Can also be used from app code early during operation, if entropy
* is required before WiFi stack is initialised. Call this function
* from app code only if WiFi/BT are not yet enabled and I2S and SAR
* ADC are not in use.
* Can also be used from app code early during operation, if true
* random numbers are required before WiFi stack is initialised.
* Call this function from app code only if WiFi/BT are not yet
* enabled and I2S and ADC are not in use.
*
* Call bootloader_random_disable() when done.
*/

16
tools/sdk/esp32c3/include/bt/include/esp32c3/include/esp_bt.h
View File

@ -26,7 +26,7 @@ extern "C" {
#endif
#define ESP_BT_CTRL_CONFIG_MAGIC_VAL 0x5A5AA5A5
#define ESP_BT_CTRL_CONFIG_VERSION 0x02103080
#define ESP_BT_CTRL_CONFIG_VERSION 0x02103310
#define ESP_BT_HCI_TL_MAGIC_VALUE 0xfadebead
#define ESP_BT_HCI_TL_VERSION 0x00010000
@ -93,9 +93,17 @@ enum {
ESP_BT_COEX_PHY_CODED_TX_RX_TIME_LIMIT_FORCE_ENABLE, /*!< Always Enable the limit */
};
#define ESP_BT_HCI_TL_STATUS_OK (0) /*!< HCI_TL Tx/Rx operation status OK */
/**
* @brief callback function for HCI Transport Layer send/receive operations
*/
typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
#ifdef CONFIG_BT_ENABLED
#define BT_CTRL_BLE_MAX_ACT_LIMIT 10 //Maximum BLE activity limitation
#define SLAVE_CE_LEN_MIN_DEFAULT 5
#ifdef CONFIG_BT_CTRL_SCAN_DUPL_TYPE
#define SCAN_DUPLICATE_TYPE_VALUE CONFIG_BT_CTRL_SCAN_DUPL_TYPE
@ -161,6 +169,7 @@ enum {
.mesh_adv_size = MESH_DUPLICATE_SCAN_CACHE_SIZE, \
.coex_phy_coded_tx_rx_time_limit = CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF, \
.hw_target_code = BLE_HW_TARGET_CODE_ESP32C3_CHIP_ECO0, \
.slave_ce_len_min = SLAVE_CE_LEN_MIN_DEFAULT, \
};
#else
@ -178,8 +187,8 @@ typedef struct {
int (* _open)(void); /* hci tl open */
void (* _close)(void); /* hci tl close */
void (* _finish_transfers)(void); /* hci tl finish trasnfers */
void (* _recv)(uint8_t *buf, uint32_t len, void (*callback) (void*, uint8_t), void* dummy); /* hci tl recv */
void (* _send)(uint8_t *buf, uint32_t len, void (*callback) (void*, uint8_t), void* dummy); /* hci tl send */
void (* _recv)(uint8_t *buf, uint32_t len, esp_bt_hci_tl_callback_t callback, void* arg); /* hci tl recv */
void (* _send)(uint8_t *buf, uint32_t len, esp_bt_hci_tl_callback_t callback, void* arg); /* hci tl send */
bool (* _flow_off)(void); /* hci tl flow off */
void (* _flow_on)(void); /* hci tl flow on */
} esp_bt_hci_tl_t;
@ -225,6 +234,7 @@ typedef struct {
uint16_t mesh_adv_size; /*!< Mesh adv size for scan duplicate */
uint8_t coex_phy_coded_tx_rx_time_limit; /*!< limit on max tx/rx time in case of connection using CODED-PHY with Wi-Fi coexistence */
uint32_t hw_target_code; /*!< hardware target */
uint8_t slave_ce_len_min;
} esp_bt_controller_config_t;
/**

13
tools/sdk/esp32c3/include/config/sdkconfig.h
View File

@ -113,9 +113,11 @@
#define CONFIG_BT_BLE_ENABLED 1
#define CONFIG_BT_GATTS_ENABLE 1
#define CONFIG_BT_BLE_BLUFI_ENABLE 1
#define CONFIG_BT_GATT_SR_PROFILES 8
#define CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_AUTO 1
#define CONFIG_BT_GATTS_SEND_SERVICE_CHANGE_MODE 0
#define CONFIG_BT_GATTC_ENABLE 1
#define CONFIG_BT_GATTC_CONNECT_RETRY_COUNT 3
#define CONFIG_BT_BLE_SMP_ENABLE 1
#define CONFIG_BT_LOG_HCI_TRACE_LEVEL_WARNING 1
#define CONFIG_BT_LOG_HCI_TRACE_LEVEL 2
@ -160,12 +162,14 @@
#define CONFIG_BT_LOG_BLUFI_TRACE_LEVEL_WARNING 1
#define CONFIG_BT_LOG_BLUFI_TRACE_LEVEL 2
#define CONFIG_BT_ACL_CONNECTIONS 4
#define CONFIG_BT_MULTI_CONNECTION_ENBALE 1
#define CONFIG_BT_SMP_ENABLE 1
#define CONFIG_BT_BLE_ESTAB_LINK_CONN_TOUT 30
#define CONFIG_BT_BLE_RPA_SUPPORTED 1
#define CONFIG_BT_BLE_50_FEATURES_SUPPORTED 1
#define CONFIG_BT_BLE_42_FEATURES_SUPPORTED 1
#define CONFIG_BT_RESERVE_DRAM 0xdb5c
#define CONFIG_BT_NIMBLE_ENABLE_CONN_REATTEMPT 1
#define CONFIG_COAP_MBEDTLS_PSK 1
#define CONFIG_COAP_LOG_DEFAULT_LEVEL 0
#define CONFIG_ADC_DISABLE_DAC 1
@ -252,8 +256,6 @@
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
#define CONFIG_ESP_WIFI_FTM_INITIATOR_SUPPORT 1
#define CONFIG_ESP_WIFI_FTM_RESPONDER_SUPPORT 1
#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20
#define CONFIG_ESP32_PHY_MAX_TX_POWER 20
#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1
@ -313,6 +315,8 @@
#define CONFIG_HEAP_TRACING_OFF 1
#define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1
#define CONFIG_LOG_DEFAULT_LEVEL 1
#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1
#define CONFIG_LOG_MAXIMUM_LEVEL 1
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
#define CONFIG_LWIP_LOCAL_HOSTNAME "espressif"
#define CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES 1
@ -330,6 +334,7 @@
#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
#define CONFIG_LWIP_IPV6 1
#define CONFIG_LWIP_IPV6_NUM_ADDRESSES 3
#define CONFIG_LWIP_NETIF_LOOPBACK 1
#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8
#define CONFIG_LWIP_MAX_ACTIVE_TCP 16
@ -360,6 +365,7 @@
#define CONFIG_LWIP_ESP_LWIP_ASSERT 1
#define CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT 1
#define CONFIG_LWIP_HOOK_IP6_ROUTE_NONE 1
#define CONFIG_LWIP_HOOK_ND6_GET_GW_NONE 1
#define CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE 1
#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1
#define CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN 1
@ -370,6 +376,7 @@
#define CONFIG_MBEDTLS_HARDWARE_AES 1
#define CONFIG_MBEDTLS_HARDWARE_MPI 1
#define CONFIG_MBEDTLS_HARDWARE_SHA 1
#define CONFIG_MBEDTLS_ROM_MD5 1
#define CONFIG_MBEDTLS_HAVE_TIME 1
#define CONFIG_MBEDTLS_ECDSA_DETERMINISTIC 1
#define CONFIG_MBEDTLS_SHA512_C 1
@ -598,5 +605,5 @@
#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
#define CONFIG_TOOLPREFIX CONFIG_SDK_TOOLPREFIX
#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE
#define CONFIG_ARDUINO_IDF_COMMIT "cf457d412"
#define CONFIG_ARDUINO_IDF_COMMIT "c13afea63"
#define CONFIG_ARDUINO_IDF_BRANCH "master"

6
tools/sdk/esp32c3/include/driver/include/driver/adc_common.h
View File

@ -49,8 +49,8 @@ typedef enum {
ADC1_CHANNEL_5, /*!< ADC1 channel 5 is GPIO6 */
ADC1_CHANNEL_6, /*!< ADC1 channel 6 is GPIO7 */
ADC1_CHANNEL_7, /*!< ADC1 channel 7 is GPIO8 */
ADC1_CHANNEL_8, /*!< ADC1 channel 6 is GPIO9 */
ADC1_CHANNEL_9, /*!< ADC1 channel 7 is GPIO10 */
ADC1_CHANNEL_8, /*!< ADC1 channel 8 is GPIO9 */
ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */
ADC1_CHANNEL_MAX,
} adc1_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3
@ -135,7 +135,7 @@ typedef enum {
* @brief Digital ADC DMA configuration
*/
typedef struct adc_digi_init_config_s {
uint32_t max_store_buf_size; ///< Max length of the converted data that driver can store before they are processed. When this length is reached, driver will dump out all the old data and start to store them again.
uint32_t max_store_buf_size; ///< Max length of the converted data that driver can store before they are processed.
uint32_t conv_num_each_intr; ///< Bytes of data that can be converted in 1 interrupt.
uint32_t adc1_chan_mask; ///< Channel list of ADC1 to be initialized.
uint32_t adc2_chan_mask; ///< Channel list of ADC2 to be initialized.

4
tools/sdk/esp32c3/include/driver/include/driver/gpio.h
View File

@ -35,6 +35,8 @@
#include "esp32s3/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/gpio.h"
#endif
#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
@ -215,9 +217,9 @@ esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num);
* per-GPIO ISRs.
*
* @param fn Interrupt handler function.
* @param arg Parameter for handler function
* @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
* ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
* @param arg Parameter for handler function
* @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will be returned here.
*
* \verbatim embed:rst:leading-asterisk

5
tools/sdk/esp32c3/include/driver/include/driver/ledc.h
View File

@ -76,6 +76,7 @@ esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
/**
* @brief Set LEDC output gpio.
* @deprecated This function is redundant, please use ledc_channel_config to set gpio pins.
*
* @param gpio_num The LEDC output gpio
* @param speed_mode Select the LEDC channel group with specified speed mode. Note that not all targets support high speed mode.
@ -85,8 +86,8 @@ esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc_channel);
esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc_channel)
__attribute__((deprecated("use ledc_channel_config instead")));
/**
* @brief LEDC stop.
* Disable LEDC output, and set idle level

1
tools/sdk/esp32c3/include/driver/include/driver/mcpwm.h
View File

@ -568,6 +568,7 @@ esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_
* @param cap_edge set capture edge, BIT(0) - negative edge, BIT(1) - positive edge
* @param cap_sig capture pin, which needs to be enabled
* @param num_of_pulse count time between rising/falling edge between 2 *(pulses mentioned), counter uses APB_CLK
* [0~MCPWM_LL_MAX_PRESCALE] (MCPWM_LL_MAX_PRESCALE = 255 on ESP32);
*
* @return
* - ESP_OK Success

2
tools/sdk/esp32c3/include/driver/include/driver/spi_slave_hd.h
View File

@ -58,7 +58,9 @@ typedef enum {
typedef struct {
slave_cb_t cb_buffer_tx; ///< Callback when master reads from shared buffer
slave_cb_t cb_buffer_rx; ///< Callback when master writes to shared buffer
slave_cb_t cb_send_dma_ready; ///< Callback when TX data buffer is loaded to the hardware (DMA)
slave_cb_t cb_sent; ///< Callback when data are sent
slave_cb_t cb_recv_dma_ready; ///< Callback when RX data buffer is loaded to the hardware (DMA)
slave_cb_t cb_recv; ///< Callback when data are received
slave_cb_t cb_cmd9; ///< Callback when CMD9 received
slave_cb_t cb_cmdA; ///< Callback when CMDA received

8
tools/sdk/esp32c3/include/driver/include/driver/timer.h
View File

@ -432,6 +432,8 @@ void timer_group_clr_intr_sta_in_isr(timer_group_t group_num, timer_intr_t intr_
bool timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer_idx_t timer_num);
/** @brief Take timer spinlock to enter critical protect
*
* @note Deprecated, the recommended way is to use ISR callbacks instead, see timer_group_example_main
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
*
@ -439,9 +441,11 @@ bool timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer_idx_t tim
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_spinlock_take(timer_group_t group_num);
esp_err_t timer_spinlock_take(timer_group_t group_num) __attribute__ ((deprecated));
/** @brief Give timer spinlock to exit critical protect
*
* @note Deprecated, the recommended way is to use ISR callbacks instead, see timer_group_example_main
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
*
@ -449,7 +453,7 @@ esp_err_t timer_spinlock_take(timer_group_t group_num);
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t timer_spinlock_give(timer_group_t group_num);
esp_err_t timer_spinlock_give(timer_group_t group_num) __attribute__ ((deprecated));
#ifdef __cplusplus
}

13
tools/sdk/esp32c3/include/driver/include/esp_private/gdma.h
View File

@ -155,6 +155,7 @@ esp_err_t gdma_new_channel(const gdma_channel_alloc_config_t *config, gdma_chann
* @brief Connect GDMA channel to trigger peripheral
*
* @note Suggest to use helper macro `GDMA_MAKE_TRIGGER` to construct parameter `trig_periph`. e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SHA,0)
* @note Connecting to a peripheral will also reset the DMA FIFO and FSM automatically
*
* @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel`
* @param[in] trig_periph GDMA trigger peripheral
@ -279,6 +280,18 @@ esp_err_t gdma_stop(gdma_channel_handle_t dma_chan);
*/
esp_err_t gdma_append(gdma_channel_handle_t dma_chan);
/**
* @brief Reset DMA channel FIFO and internal finite state machine
* @note Resetting a DMA channel won't break the connection with the target peripheral
*
* @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel`
* @return
* - ESP_OK: DMA channel reset successfully
* - ESP_ERR_INVALID_ARG: DMA channel reset failed due to invalid arguments
* - ESP_FAIL: DMA channel reset failed due to other errors
*/
esp_err_t gdma_reset(gdma_channel_handle_t dma_chan);
#ifdef __cplusplus
}
#endif

8
tools/sdk/esp32c3/include/efuse/esp32c3/include/esp_efuse_table.h
View File

@ -17,7 +17,7 @@ extern "C" {
#endif
// md5_digest_table f9a84eb22f94a7bc083b4c6817a33a59
// md5_digest_table 61baa79d296df996c838bc2adc1837e5
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -138,6 +138,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
#ifdef __cplusplus
}

43
tools/sdk/esp32c3/include/esp_eth/include/esp_eth.h
View File

@ -86,6 +86,47 @@ typedef struct {
*/
esp_err_t (*on_lowlevel_deinit_done)(esp_eth_handle_t eth_handle);
/**
* @brief Read PHY register
*
* @note Usually the PHY register read/write function is provided by MAC (SMI interface),
* but if the PHY device is managed by other interface (e.g. I2C), then user needs to
* implement the corresponding read/write.
* Setting this to NULL means your PHY device is managed by MAC's SMI interface.
*
* @param[in] eth_handle: handle of Ethernet driver
* @param[in] phy_addr: PHY chip address (0~31)
* @param[in] phy_reg: PHY register index code
* @param[out] reg_value: PHY register value
*
* @return
* - ESP_OK: read PHY register successfully
* - ESP_ERR_INVALID_ARG: read PHY register failed because of invalid argument
* - ESP_ERR_TIMEOUT: read PHY register failed because of timeout
* - ESP_FAIL: read PHY register failed because some other error occurred
*/
esp_err_t (*read_phy_reg)(esp_eth_handle_t eth_handle, uint32_t phy_addr, uint32_t phy_reg, uint32_t *reg_value);
/**
* @brief Write PHY register
*
* @note Usually the PHY register read/write function is provided by MAC (SMI interface),
* but if the PHY device is managed by other interface (e.g. I2C), then user needs to
* implement the corresponding read/write.
* Setting this to NULL means your PHY device is managed by MAC's SMI interface.
*
* @param[in] eth_handle: handle of Ethernet driver
* @param[in] phy_addr: PHY chip address (0~31)
* @param[in] phy_reg: PHY register index code
* @param[in] reg_value: PHY register value
*
* @return
* - ESP_OK: write PHY register successfully
* - ESP_ERR_INVALID_ARG: read PHY register failed because of invalid argument
* - ESP_ERR_TIMEOUT: write PHY register failed because of timeout
* - ESP_FAIL: write PHY register failed because some other error occurred
*/
esp_err_t (*write_phy_reg)(esp_eth_handle_t eth_handle, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value);
} esp_eth_config_t;
/**
@ -100,6 +141,8 @@ typedef struct {
.stack_input = NULL, \
.on_lowlevel_init_done = NULL, \
.on_lowlevel_deinit_done = NULL, \
.read_phy_reg = NULL, \
.write_phy_reg = NULL, \
}
/**

33
tools/sdk/esp32c3/include/esp_eth/include/esp_eth_mac.h
View File

@ -396,6 +396,39 @@ typedef struct {
esp_eth_mac_t *esp_eth_mac_new_w5500(const eth_w5500_config_t *w5500_config, const eth_mac_config_t *mac_config);
#endif // CONFIG_ETH_SPI_ETHERNET_W5500
#if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL
/**
* @brief KSZ8851SNL specific configuration
*
*/
typedef struct {
void *spi_hdl; /*!< Handle of SPI device driver */
int int_gpio_num; /*!< Interrupt GPIO number */
} eth_ksz8851snl_config_t;
/**
* @brief Default KSZ8851SNL specific configuration
*
*/
#define ETH_KSZ8851SNL_DEFAULT_CONFIG(spi_device) \
{ \
.spi_hdl = spi_device, \
.int_gpio_num = 14, \
}
/**
* @brief Create KSZ8851SNL Ethernet MAC instance
*
* @param ksz8851snl_config: KSZ8851SNL specific configuration
* @param mac_config: Ethernet MAC configuration
*
* @return
* - instance: create MAC instance successfully
* - NULL: create MAC instance failed because some error occurred
*/
esp_eth_mac_t *esp_eth_mac_new_ksz8851snl(const eth_ksz8851snl_config_t *ksz8851snl_config, const eth_mac_config_t *mac_config);
#endif // CONFIG_ETH_SPI_ETHERNET_KSZ8851
#if CONFIG_ETH_USE_OPENETH
/**
* @brief Create OpenCores Ethernet MAC instance

13
tools/sdk/esp32c3/include/esp_eth/include/esp_eth_phy.h
View File

@ -300,6 +300,19 @@ esp_eth_phy_t *esp_eth_phy_new_dm9051(const eth_phy_config_t *config);
*/
esp_eth_phy_t *esp_eth_phy_new_w5500(const eth_phy_config_t *config);
#endif
#if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL
/**
* @brief Create a PHY instance of KSZ8851SNL
*
* @param[in] config: configuration of PHY
*
* @return
* - instance: create PHY instance successfully
* - NULL: create PHY instance failed because some error occurred
*/
esp_eth_phy_t *esp_eth_phy_new_ksz8851snl(const eth_phy_config_t *config);
#endif
#ifdef __cplusplus
}
#endif

1
tools/sdk/esp32c3/include/esp_event/include/esp_event_legacy.h
View File

@ -58,6 +58,7 @@ typedef enum {
SYSTEM_EVENT_ETH_CONNECTED, /*!< ESP32 ethernet phy link up */
SYSTEM_EVENT_ETH_DISCONNECTED, /*!< ESP32 ethernet phy link down */
SYSTEM_EVENT_ETH_GOT_IP, /*!< ESP32 ethernet got IP from connected AP */
SYSTEM_EVENT_ETH_LOST_IP, /*!< ESP32 ethernet lost IP and the IP is reset to 0 */
SYSTEM_EVENT_MAX /*!< Number of members in this enum */
} system_event_id_t;

1
tools/sdk/esp32c3/include/esp_hid/include/esp_hidh.h
View File

@ -100,6 +100,7 @@ typedef union {
typedef struct {
esp_event_handler_t callback;
uint16_t event_stack_size;
} esp_hidh_config_t;
/**

14
tools/sdk/esp32c3/include/esp_http_client/include/esp_http_client.h
View File

@ -334,7 +334,7 @@ esp_err_t esp_http_client_get_password(esp_http_client_handle_t client, char **v
* - ESP_OK
* - ESP_ERR_INVALID_ARG
*/
esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, char *password);
esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, const char *password);
/**
* @brief Set http request auth_type.
@ -360,6 +360,18 @@ esp_err_t esp_http_client_set_authtype(esp_http_client_handle_t client, esp_http
*/
esp_err_t esp_http_client_set_method(esp_http_client_handle_t client, esp_http_client_method_t method);
/**
* @brief Set http request timeout
*
* @param[in] client The esp_http_client handle
* @param[in] timeout_ms The timeout value
*
* @return
* - ESP_OK
* - ESP_ERR_INVALID_ARG
*/
esp_err_t esp_http_client_set_timeout_ms(esp_http_client_handle_t client, int timeout_ms);
/**
* @brief Delete http request header
*

15
tools/sdk/esp32c3/include/esp_https_ota/include/esp_https_ota.h
View File

@ -201,6 +201,21 @@ esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, es
*/
int esp_https_ota_get_image_len_read(esp_https_ota_handle_t https_ota_handle);
/**
* @brief This function returns OTA image total size.
*
* @note This API should be called after esp_https_ota_begin() has been already called.
* This can be used to create some sort of progress indication
* (in combination with esp_https_ota_get_image_len_read())
*
* @param[in] https_ota_handle pointer to esp_https_ota_handle_t structure
*
* @return
* - -1 On failure or chunked encoding
* - total bytes of image
*/
int esp_https_ota_get_image_size(esp_https_ota_handle_t https_ota_handle);
#ifdef __cplusplus
}
#endif

42
tools/sdk/esp32c3/include/esp_hw_support/include/esp_mac.h
View File

@ -47,17 +47,17 @@ typedef enum {
* @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
* external storage e.g. flash and EEPROM.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
* address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
* WiFi/BT/Ethernet.
* Base MAC address is used to generate the MAC addresses used by network interfaces.
*
* If using a custom base MAC address, call this API before initializing any network interfaces.
* Refer to the ESP-IDF Programming Guide for details about how the Base MAC is used.
*
* @note Base MAC must be a unicast MAC (least significant bit of first byte must be zero).
*
* @note If not using a valid OUI, set the "locally administered" bit
* (bit value 0x02 in the first byte) to avoid collisions.
*
* @param mac base MAC address, length: 6 bytes.
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_ARG If mac is NULL or is not a unicast MAC
@ -67,7 +67,9 @@ esp_err_t esp_base_mac_addr_set(const uint8_t *mac);
/**
* @brief Return base MAC address which is set using esp_base_mac_addr_set.
*
* @param mac base MAC address, length: 6 bytes.
* @note If no custom Base MAC has been set, this returns the pre-programmed Espressif base MAC address.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
* ESP_ERR_INVALID_MAC base MAC address has not been set
@ -78,10 +80,14 @@ esp_err_t esp_base_mac_addr_get(uint8_t *mac);
* @brief Return base MAC address which was previously written to BLK3 of EFUSE.
*
* Base MAC address is used to generate the MAC addresses used by the networking interfaces.
* This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
* This API returns the custom base MAC address which was previously written to EFUSE BLK3 in
* a specified format.
*
* Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
* possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
*
* @note This function is currently only supported on ESP32.
*
* @param mac base MAC address, length: 6 bytes.
*
* @return ESP_OK on success
@ -91,7 +97,7 @@ esp_err_t esp_base_mac_addr_get(uint8_t *mac);
esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
/**
* @brief Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
* @brief Return base MAC address which is factory-programmed by Espressif in EFUSE.
*
* @param mac base MAC address, length: 6 bytes.
*
@ -102,12 +108,12 @@ esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
/**
* @brief Read base MAC address and set MAC address of the interface.
*
* This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
* from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
* bluetooth and ethernet.
* This function first get base MAC address using esp_base_mac_addr_get().
* Then calculates the MAC address of the specific interface requested,
* refer to ESP-IDF Programming Guide for the algorithm.
*
* @param mac MAC address of the interface, length: 6 bytes.
* @param type type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
* @param type Type of MAC address to return
*
* @return ESP_OK on success
*/
@ -116,11 +122,13 @@ esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
/**
* @brief Derive local MAC address from universal MAC address.
*
* This function derives a local MAC address from an universal MAC address.
* A `definition of local vs universal MAC address can be found on Wikipedia
* <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
* In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
* Local MAC address is derived from the universal MAC address.
* This function copies a universal MAC address and then sets the "locally
* administered" bit (bit 0x2) in the first octet, creating a locally
* administered MAC address.
*
* If the universal MAC address argument is already a locally administered MAC
* address, then the first octet is XORed with 0x4 in order to create a different
* locally administered MAC address.
*
* @param local_mac Derived local MAC address, length: 6 bytes.
* @param universal_mac Source universal MAC address, length: 6 bytes.

27
tools/sdk/esp32c3/include/esp_hw_support/include/esp_random.h
View File

@ -24,16 +24,27 @@ extern "C" {
/**
* @brief Get one random 32-bit word from hardware RNG
*
* The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For
* random values, call this function after WiFi or Bluetooth are started.
* The hardware RNG produces true random numbers under any of the following conditions:
*
* If the RF subsystem is not used by the program, the function bootloader_random_enable() can be called to enable an
* entropy source. bootloader_random_disable() must be called before RF subsystem or I2S peripheral are used. See these functions'
* documentation for more details.
* - An RF subsystem is running (i.e. Bluetooth or WiFi is enabled)
* - An internal entropy source has been enabled by calling bootloader_random_enable()
* and not yet disabled by calling bootloader_random_disable()
* - While the ESP-IDF bootloader is running (due to the internal entropy source being enabled
* for the duration of bootloader execution).
*
* Any time the app is running without an RF subsystem (or bootloader_random) enabled, RNG hardware should be
* considered a PRNG. A very small amount of entropy is available due to pre-seeding while the IDF
* bootloader is running, but this should not be relied upon for any use.
* If none of the above conditions are true, the hardware RNG will produce pseudo-random numbers only.
*
* When the hardware RNG is producing true random numbers, external entropy (noise samples) are
* continuously mixed into the internal hardware RNG state. Consult the SoC Technical Reference Manual
* for more details.
*
* This function automatically busy-waits to ensure enough external entropy has been
* introduced into the hardware RNG state, before returning a new random number.
*
* If generating random numbers from an app which has not yet enabled Bluetooth or Wi-Fi, call the
* API function bootloader_random_enable() before generating random numbers and then call
* bootloader_random_disable() before using any APIs for Bluetooth, Wi-Fi, ADC, or I2S. Consult the
* bootloader_random.h header for more details.
*
* @return Random value between 0 and UINT32_MAX
*/

6
tools/sdk/esp32c3/include/esp_hw_support/include/esp_sleep.h
View File

@ -303,6 +303,12 @@ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num);
*/
esp_err_t esp_sleep_enable_wifi_wakeup(void);
/**
* @brief Disable wakeup by WiFi MAC
* @return
* - ESP_OK on success
*/
esp_err_t esp_sleep_disable_wifi_wakeup(void);
/**
* @brief Get the bit mask of GPIOs which caused wakeup (ext1)

33
tools/sdk/esp32c3/include/esp_hw_support/port/esp32c3/regi2c_ctrl.h
View File

@ -64,20 +64,45 @@ uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, ui
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, ROM functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg rom_i2c_readReg
#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask
#define regi2c_ctrl_write_reg rom_i2c_writeReg
#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask
#else
#define i2c_read_reg_raw rom_i2c_readReg
#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask
#define i2c_write_reg_raw rom_i2c_writeReg
#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#endif // BOOTLOADER_BUILD
/* Convenience macros for the above functions, these use register definitions
* from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/regi2c_bias.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
rom_i2c_readReg(block, block##_HOSTID, reg_add)
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
#ifdef __cplusplus
}

201
tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_io.h Normal file
View File

@ -0,0 +1,201 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "esp_lcd_types.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef void *esp_lcd_spi_bus_handle_t; /*!< Type of LCD SPI bus handle */
typedef void *esp_lcd_i2c_bus_handle_t; /*!< Type of LCD I2C bus handle */
typedef struct esp_lcd_i80_bus_t *esp_lcd_i80_bus_handle_t; /*!< Type of LCD intel 8080 bus handle */
/**
* @brief Transmit LCD command and corresponding parameters
*
* @note Commands sent by this function are short, so they are sent using polling transactions.
* The function does not return before the command tranfer is completed.
* If any queued transactions sent by `esp_lcd_panel_io_tx_color()` are still pending when this function is called,
* this function will wait until they are finished and the queue is empty before sending the command(s).
*
* @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()`
* @param[in] lcd_cmd The specific LCD command
* @param[in] lcd_cmd_bits Length of LCD command, in bits (e.g. 8 bits or 16 bits)
* @param[in] param Buffer that holds the command specific parameters, set to NULL if no parameter is needed for the command
* @param[in] param_size Size of `param` in memory, in bytes, set to zero if no parameter is needed for the command
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_io_tx_param(esp_lcd_panel_io_handle_t io, int lcd_cmd, int lcd_cmd_bits, const void *param, size_t param_size);
/**
* @brief Transmit LCD RGB data
*
* @note This function will package the command and RGB data into a transaction, and push into a queue.
* The real transmission is performed in the background (DMA+interrupt).
* The caller should take care of the lifecycle of the `color` buffer.
* Recycling of color buffer should be done in the callback `on_color_trans_done()`.
*
* @param[in] io LCD panel IO handle, which is created by factory API like `esp_lcd_new_panel_io_spi()`
* @param[in] lcd_cmd The specific LCD command
* @param[in] lcd_cmd_bits Length of LCD command, in bits (e.g. 8 bits or 16 bits)
* @param[in] color Buffer that holds the RGB color data
* @param[in] color_size Size of `color` in memory, in bytes
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_io_tx_color(esp_lcd_panel_io_handle_t io, int lcd_cmd, int lcd_cmd_bits, const void *color, size_t color_size);
/**
* @brief Destory LCD panel IO handle (deinitialize panel and free all corresponding resource)
*
* @param[in] io LCD panel IO handle, which is created by factory API like `esp_lcd_new_panel_io_spi()`
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_io_del(esp_lcd_panel_io_handle_t io);
/**
* @brief Panel IO configuration structure, for SPI interface
*/
typedef struct {
int cs_gpio_num; /*!< GPIO used for CS line */
int dc_gpio_num; /*!< GPIO used to select the D/C line, set this to -1 if the D/C line not controlled by manually pulling high/low GPIO */
int spi_mode; /*!< Traditional SPI mode (0~3) */
unsigned int pclk_hz; /*!< Frequency of pixel clock */
size_t trans_queue_depth; /*!< Size of internal transaction queue */
bool (*on_color_trans_done)(esp_lcd_panel_io_handle_t panel_io, void *user_data, void *event_data); /*!< Callback, invoked when color data transfer has finished */
void *user_data; /*!< User private data, passed directly to on_trans_frame_done's user_data */
struct {
unsigned int dc_as_cmd_phase: 1; /*!< D/C line value is encoded into SPI transaction command phase */
unsigned int dc_low_on_data: 1; /*!< If this flag is enabled, DC line = 0 means transfer data, DC line = 1 means transfer command; vice versa */
} flags;
} esp_lcd_panel_io_spi_config_t;
/**
* @brief Create LCD panel IO handle, for SPI interface
*
* @param[in] bus SPI bus handle
* @param[in] io_config IO configuration, for SPI interface
* @param[out] ret_io Returned IO handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NO_MEM if out of memory
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_panel_io_spi(esp_lcd_spi_bus_handle_t bus, const esp_lcd_panel_io_spi_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io);
typedef struct {
uint32_t dev_addr; /*!< I2C device address */
bool (*on_color_trans_done)(esp_lcd_panel_io_handle_t panel_io, void *user_data, void *event_data); /*!< Callback, invoked when color data transfer has finished */
void *user_data; /*!< User private data, passed directly to on_trans_frame_done's user_data */
size_t control_phase_bytes; /*!< I2C LCD panel will encode control information (e.g. D/C seclection) into control phase, in several bytes */
unsigned int dc_bit_offset; /*!< Offset of the D/C selection bit in control phase */
struct {
unsigned int dc_low_on_data: 1; /*!< If this flag is enabled, DC line = 0 means transfer data, DC line = 1 means transfer command; vice versa */
} flags;
} esp_lcd_panel_io_i2c_config_t;
/**
* @brief Create LCD panel IO handle, for I2C interface
*
* @param[in] bus I2C bus handle
* @param[in] io_config IO configuration, for I2C interface
* @param[out] ret_io Returned IO handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NO_MEM if out of memory
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_panel_io_i2c(esp_lcd_i2c_bus_handle_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io);
#if SOC_LCD_I80_SUPPORTED
/**
* @brief LCD Intel 8080 bus configuration structure
*/
typedef struct {
int dc_gpio_num; /*!< GPIO used for D/C line */
int wr_gpio_num; /*!< GPIO used for WR line */
int data_gpio_nums[SOC_LCD_I80_BUS_WIDTH]; /*!< GPIOs used for data lines */
size_t data_width; /*!< Number of data lines, 8 or 16 */
size_t max_transfer_bytes; /*!< Maximum transfer size, this determines the length of internal DMA link */
} esp_lcd_i80_bus_config_t;
/**
* @brief Create Intel 8080 bus handle
*
* @param[in] bus_config Bus configuration
* @param[out] ret_bus Returned bus handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NO_MEM if out of memory
* - ESP_ERR_NOT_FOUND if no free bus is available
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lcd_i80_bus_handle_t *ret_bus);
/**
* @brief Destory Intel 8080 bus handle
*
* @param[in] bus Intel 8080 bus handle, created by `esp_lcd_new_i80_bus()`
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_INVALID_STATE if there still be some device attached to the bus
* - ESP_OK on success
*/
esp_err_t esp_lcd_del_i80_bus(esp_lcd_i80_bus_handle_t bus);
/**
* @brief Panel IO configuration structure, for intel 8080 interface
*/
typedef struct {
int cs_gpio_num; /*!< GPIO used for CS line */
unsigned int pclk_hz; /*!< Frequency of pixel clock */
size_t trans_queue_depth; /*!< Transaction queue size, larger queue, higher throughput */
bool (*on_color_trans_done)(esp_lcd_panel_io_handle_t panel_io, void *user_data, void *event_data); /*!< Callback, invoked when color data was tranferred done */
void *user_data; /*!< User private data, passed directly to on_trans_done's user_data */
struct {
unsigned int dc_idle_level: 1; /*!< Level of DC line in IDLE phase */
unsigned int dc_cmd_level: 1; /*!< Level of DC line in CMD phase */
unsigned int dc_dummy_level: 1; /*!< Level of DC line in DUMMY phase */
unsigned int dc_data_level: 1; /*!< Level of DC line in DATA phase */
} dc_levels; /*!< Each i80 device might have its own D/C control logic */
struct {
unsigned int invert_cs: 1; /*!< Whether to invert the CS line */
unsigned int reverse_color_bits: 1; /*!< Reverse the data bits, D[N:0] -> D[0:N] */
unsigned int swap_color_bytes: 1; /*!< Swap adjacent two color bytes */
unsigned int pclk_active_neg: 1; /*!< The display will write data lines when there's a falling edge on WR signal (a.k.a the PCLK) */
unsigned int pclk_idle_low: 1; /*!< The WR signal (a.k.a the PCLK) stays at low level in IDLE phase */
} flags;
} esp_lcd_panel_io_i80_config_t;
/**
* @brief Create LCD panel IO, for Intel 8080 interface
*
* @param[in] bus Intel 8080 bus handle, created by `esp_lcd_new_i80_bus()`
* @param[in] io_config IO configuration, for i80 interface
* @param[out] ret_io Returned panel IO handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NOT_SUPPORTED if some configuration can't be satisfied, e.g. pixel clock out of the range
* - ESP_ERR_NO_MEM if out of memory
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_panel_io_i80_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io);
#endif // SOC_LCD_I80_SUPPORTED
#ifdef __cplusplus
}
#endif

126
tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_ops.h Normal file
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@ -0,0 +1,126 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "esp_lcd_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Reset LCD panel
*
* @note Panel reset must be called before attempting to initialize the panel using `esp_lcd_panel_init()`.
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @return
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_reset(esp_lcd_panel_handle_t panel);
/**
* @brief Initialize LCD panel
*
* @note Before calling this function, make sure the LCD panel has finished the `reset` stage by `esp_lcd_panel_reset()`.
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @return
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_init(esp_lcd_panel_handle_t panel);
/**
* @brief Deinitialize the LCD panel
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @return
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_del(esp_lcd_panel_handle_t panel);
/**
* @brief Draw bitmap on LCD panel
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] x_start Start index on x-axis (x_start included)
* @param[in] y_start Start index on y-axis (y_start included)
* @param[in] x_end End index on x-axis (x_end not included)
* @param[in] y_end End index on y-axis (y_end not included)
* @param[in] color_data RGB color data that will be dumped to the specific window range
* @return
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_draw_bitmap(esp_lcd_panel_handle_t panel, int x_start, int y_start, int x_end, int y_end, const void *color_data);
/**
* @brief Mirror the LCD panel on specific axis
*
* @note Combined with `esp_lcd_panel_swap_xy()`, one can realize screen rotation
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] mirror_x Whether the panel will be mirrored about the x axis
* @param[in] mirror_y Whether the panel will be mirrored about the y axis
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if this function is not supported by the panel
*/
esp_err_t esp_lcd_panel_mirror(esp_lcd_panel_handle_t panel, bool mirror_x, bool mirror_y);
/**
* @brief Swap/Exchange x and y axis
*
* @note Combined with `esp_lcd_panel_mirror()`, one can realize screen rotation
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] swap_axes Whether to swap the x and y axis
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if this function is not supported by the panel
*/
esp_err_t esp_lcd_panel_swap_xy(esp_lcd_panel_handle_t panel, bool swap_axes);
/**
* @brief Set extra gap in x and y axis
*
* The gap is the space (in pixels) between the left/top sides of the LCD panel and the first row/column respectively of the actual contents displayed.
*
* @note Setting a gap is useful when positioning or centering a frame that is smaller than the LCD.
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] x_gap Extra gap on x axis, in pixels
* @param[in] y_gap Extra gap on y axis, in pixels
* @return
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_set_gap(esp_lcd_panel_handle_t panel, int x_gap, int y_gap);
/**
* @brief Invert the color (bit-wise invert the color data line)
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] invert_color_data Whether to invert the color data
* @return
* - ESP_OK on success
*/
esp_err_t esp_lcd_panel_invert_color(esp_lcd_panel_handle_t panel, bool invert_color_data);
/**
* @brief Turn off the display
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] off Whether to turn off the screen
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if this function is not supported by the panel
*/
esp_err_t esp_lcd_panel_disp_off(esp_lcd_panel_handle_t panel, bool off);
#ifdef __cplusplus
}
#endif

77
tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_rgb.h Normal file
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@ -0,0 +1,77 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "esp_lcd_types.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LCD_RGB_SUPPORTED
/**
* @brief LCD RGB timing structure
*/
typedef struct {
unsigned int pclk_hz; /*!< Frequency of pixel clock */
unsigned int h_res; /*!< Horizontal resolution, i.e. the number of pixels in a line */
unsigned int v_res; /*!< Vertical resolution, i.e. the number of lines in the frame */
unsigned int hsync_pulse_width; /*!< Horizontal sync width, unit: PCLK period */
unsigned int hsync_back_porch; /*!< Horizontal back porch, number of PCLK between hsync and start of line active data */
unsigned int hsync_front_porch; /*!< Horizontal front porch, number of PCLK between the end of active data and the next hsync */
unsigned int vsync_pulse_width; /*!< Vertical sync width, unit: number of lines */
unsigned int vsync_back_porch; /*!< Vertical back porch, number of invalid lines between vsync and start of frame */
unsigned int vsync_front_porch; /*!< Vertical front porch, number of invalid lines between then end of frame and the next vsync */
struct {
unsigned int hsync_idle_low: 1; /*!< The hsync signal is low in IDLE state */
unsigned int vsync_idle_low: 1; /*!< The vsync signal is low in IDLE state */
unsigned int de_idle_high: 1; /*!< The de signal is high in IDLE state */
unsigned int pclk_active_neg: 1; /*!< The display will write data lines when there's a falling edge on PCLK */
unsigned int pclk_idle_low: 1; /*!< The PCLK stays at low level in IDLE phase */
} flags;
} esp_lcd_rgb_timing_t;
/**
* @brief LCD RGB panel configuration structure
*/
typedef struct {
esp_lcd_rgb_timing_t timings; /*!< RGB timing parameters */
size_t data_width; /*!< Number of data lines */
int hsync_gpio_num; /*!< GPIO used for HSYNC signal */
int vsync_gpio_num; /*!< GPIO used for VSYNC signal */
int de_gpio_num; /*!< GPIO used for DE signal, set to -1 if it's not used */
int pclk_gpio_num; /*!< GPIO used for PCLK signal */
int data_gpio_nums[SOC_LCD_RGB_DATA_WIDTH]; /*!< GPIOs used for data lines */
int disp_gpio_num; /*!< GPIO used for display control signal, set to -1 if it's not used */
bool (*on_frame_trans_done)(esp_lcd_panel_handle_t panel, void *user_data); /*!< Callback, invoked when one frame buffer has transferred done */
void *user_data; /*!< User data which would be passed to on_frame_trans_done's user_data */
struct {
unsigned int disp_active_low: 1; /*!< If this flag is enabled, a low level of display control signal can turn the screen on; vice versa */
unsigned int relax_on_idle: 1; /*!< If this flag is enabled, the host won't refresh the LCD if nothing changed in host's frame buffer (this is usefull for LCD with built-in GRAM) */
} flags;
} esp_lcd_rgb_panel_config_t;
/**
* @brief Create RGB LCD panel
*
* @param rgb_panel_config RGB panel configuration
* @param ret_panel Returned LCD panel handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NO_MEM if out of memory
* - ESP_ERR_NOT_FOUND if no free RGB panel is available
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_config, esp_lcd_panel_handle_t *ret_panel);
#endif // SOC_LCD_RGB_SUPPORTED
#ifdef __cplusplus
}
#endif

57
tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_panel_vendor.h Normal file
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@ -0,0 +1,57 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "esp_lcd_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configuration structure for panel device
*/
typedef struct {
int reset_gpio_num; /*!< GPIO used to reset the LCD panel, set to -1 if it's not used */
esp_lcd_color_space_t color_space; /*!< Set the color space used by the LCD panel */
unsigned int bits_per_pixel; /*!< Color depth, in bpp */
struct {
unsigned int reset_active_high: 1; /*!< Setting this if the panel reset is high level active */
} flags;
void *vendor_config; /* vendor specific configuration, optional, left as NULL if not used */
} esp_lcd_panel_dev_config_t;
/**
* @brief Create LCD panel for model ST7789
*
* @param[in] io LCD panel IO handle
* @param[in] panel_dev_config general panel device configuration
* @param[out] ret_panel Returned LCD panel handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NO_MEM if out of memory
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_panel_st7789(const esp_lcd_panel_io_handle_t io, const esp_lcd_panel_dev_config_t *panel_dev_config, esp_lcd_panel_handle_t *ret_panel);
/**
* @brief Create LCD panel for model SSD1306
*
* @param[in] io LCD panel IO handle
* @param[in] panel_dev_config general panel device configuration
* @param[out] ret_panel Returned LCD panel handle
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_ERR_NO_MEM if out of memory
* - ESP_OK on success
*/
esp_err_t esp_lcd_new_panel_ssd1306(const esp_lcd_panel_io_handle_t io, const esp_lcd_panel_dev_config_t *panel_dev_config, esp_lcd_panel_handle_t *ret_panel);
#ifdef __cplusplus
}
#endif

26
tools/sdk/esp32c3/include/esp_lcd/include/esp_lcd_types.h Normal file
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@ -0,0 +1,26 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef struct esp_lcd_panel_io_t *esp_lcd_panel_io_handle_t; /*!< Type of LCD panel IO handle */
typedef struct esp_lcd_panel_t *esp_lcd_panel_handle_t; /*!< Type of LCD panel handle */
/**
* @brief LCD color space type definition
*/
typedef enum {
ESP_LCD_COLOR_SPACE_RGB, /*!< Color space: RGB */
ESP_LCD_COLOR_SPACE_BGR, /*!< Color space: BGR */
ESP_LCD_COLOR_SPACE_MONOCHROME, /*!< Color space: monochrome */
} esp_lcd_color_space_t;
#ifdef __cplusplus
}
#endif

126
tools/sdk/esp32c3/include/esp_lcd/interface/esp_lcd_panel_interface.h Normal file
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@ -0,0 +1,126 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct esp_lcd_panel_t esp_lcd_panel_t; /*!< Type of LCD panel */
/**
* @brief LCD panel interface
*/
struct esp_lcd_panel_t {
/**
* @brief Reset LCD panel
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @return
* - ESP_OK on success
*/
esp_err_t (*reset)(esp_lcd_panel_t *panel);
/**
* @brief Initialize LCD panel
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @return
* - ESP_OK on success
*/
esp_err_t (*init)(esp_lcd_panel_t *panel);
/**
* @brief Destory LCD panel
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @return
* - ESP_OK on success
*/
esp_err_t (*del)(esp_lcd_panel_t *panel);
/**
* @brief Draw bitmap on LCD panel
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] x_start Start index on x-axis (x_start included)
* @param[in] y_start Start index on y-axis (y_start included)
* @param[in] x_end End index on x-axis (x_end not included)
* @param[in] y_end End index on y-axis (y_end not included)
* @param[in] color_data RGB color data that will be dumped to the specific window range
* @return
* - ESP_OK on success
*/
esp_err_t (*draw_bitmap)(esp_lcd_panel_t *panel, int x_start, int y_start, int x_end, int y_end, const void *color_data);
/**
* @brief Mirror the LCD panel on specific axis
*
* @note Combine this function with `swap_xy`, one can realize screen rotatation
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] x_axis Whether the panel will be mirrored about the x_axis
* @param[in] y_axis Whether the panel will be mirrored about the y_axis
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if this function is not supported by the panel
*/
esp_err_t (*mirror)(esp_lcd_panel_t *panel, bool x_axis, bool y_axis);
/**
* @brief Swap/Exchange x and y axis
*
* @note Combine this function with `mirror`, one can realize screen rotatation
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] swap_axes Whether to swap the x and y axis
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if this function is not supported by the panel
*/
esp_err_t (*swap_xy)(esp_lcd_panel_t *panel, bool swap_axes);
/**
* @brief Set extra gap in x and y axis
*
* @note The gap is only used for calculating the real coordinates.
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] x_gap Extra gap on x axis, in pixels
* @param[in] y_gap Extra gap on y axis, in pixels
* @return
* - ESP_OK on success
*/
esp_err_t (*set_gap)(esp_lcd_panel_t *panel, int x_gap, int y_gap);
/**
* @brief Invert the color (bit 1 -> 0 for color data line, and vice versa)
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] invert_color_data Whether to invert the color data
* @return
* - ESP_OK on success
*/
esp_err_t (*invert_color)(esp_lcd_panel_t *panel, bool invert_color_data);
/**
* @brief Turn off the display
*
* @param[in] panel LCD panel handle, which is created by other factory API like `esp_lcd_new_panel_st7789()`
* @param[in] off Whether to turn off the screen
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_SUPPORTED if this function is not supported by the panel
*/
esp_err_t (*disp_off)(esp_lcd_panel_t *panel, bool off);
};
#ifdef __cplusplus
}
#endif

66
tools/sdk/esp32c3/include/esp_lcd/interface/esp_lcd_panel_io_interface.h Normal file
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@ -0,0 +1,66 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct esp_lcd_panel_io_t esp_lcd_panel_io_t; /*!< Type of LCD panel IO */
/**
* @brief LCD panel IO interface
*/
struct esp_lcd_panel_io_t {
/**
* @brief Transmit LCD command and corresponding parameters
*
* @note This is the panel-specific interface called by function `esp_lcd_panel_io_tx_param()`.
*
* @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()`
* @param[in] lcd_cmd The specific LCD command
* @param[in] lcd_cmd_bits Length of LCD command, in bits (e.g. 8 bits or 16 bits)
* @param[in] param Buffer that holds the command specific parameters, set to NULL if no parameter is needed for the command
* @param[in] param_size Size of `param` in memory, in bytes, set to zero if no parameter is needed for the command
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_OK on success
*/
esp_err_t (*tx_param)(esp_lcd_panel_io_t *io, int lcd_cmd, int lcd_cmd_bits, const void *param, size_t param_size);
/**
* @brief Transmit LCD RGB data
*
* @note This is the panel-specific interface called by function `esp_lcd_panel_io_tx_color()`.
*
* @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()`
* @param[in] lcd_cmd The specific LCD command
* @param[in] lcd_cmd_bits Length of LCD command, in bits (e.g. 8 bits or 16 bits)
* @param[in] color Buffer that holds the RGB color data
* @param[in] color_size Size of `color` in memory, in bytes
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_OK on success
*/
esp_err_t (*tx_color)(esp_lcd_panel_io_t *io, int lcd_cmd, int lcd_cmd_bits, const void *color, size_t color_size);
/**
* @brief Destory LCD panel IO handle (deinitialize all and free resource)
*
* @param[in] io LCD panel IO handle, which is created by other factory API like `esp_lcd_new_panel_io_spi()`
* @return
* - ESP_ERR_INVALID_ARG if parameter is invalid
* - ESP_OK on success
*/
esp_err_t (*del)(esp_lcd_panel_io_t *io);
};
#ifdef __cplusplus
}
#endif

2
tools/sdk/esp32c3/include/esp_netif/include/esp_netif_defaults.h
View File

@ -55,7 +55,7 @@ extern "C" {
ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(mac) \
ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(ip_info) \
.get_ip_event = IP_EVENT_ETH_GOT_IP, \
.lost_ip_event = 0, \
.lost_ip_event = IP_EVENT_ETH_LOST_IP, \
.if_key = "ETH_DEF", \
.if_desc = "eth", \
.route_prio = 50 \

1
tools/sdk/esp32c3/include/esp_netif/include/esp_netif_types.h
View File

@ -88,6 +88,7 @@ typedef enum {
IP_EVENT_AP_STAIPASSIGNED, /*!< soft-AP assign an IP to a connected station */
IP_EVENT_GOT_IP6, /*!< station or ap or ethernet interface v6IP addr is preferred */
IP_EVENT_ETH_GOT_IP, /*!< ethernet got IP from connected AP */
IP_EVENT_ETH_LOST_IP, /*!< ethernet lost IP and the IP is reset to 0 */
IP_EVENT_PPP_GOT_IP, /*!< PPP interface got IP */
IP_EVENT_PPP_LOST_IP, /*!< PPP interface lost IP */
} ip_event_t;

1
tools/sdk/esp32c3/include/esp_rom/esp32c3/esp_rom_caps.h
View File

@ -18,3 +18,4 @@
#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library
#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM.

2
tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/ets_sys.h
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@ -191,7 +191,7 @@ int ets_printf(const char *fmt, ...);
* @brief Set the uart channel of ets_printf(uart_tx_one_char).
* ROM will set it base on the efuse and gpio setting, however, this can be changed after booting.
*
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2.
* @param uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/

2
tools/sdk/esp32c3/include/esp_rom/include/esp32c3/rom/uart.h
View File

@ -260,7 +260,7 @@ void uart_tx_flush(uint8_t uart_no);
/**
* @brief Wait until uart tx full empty and the last char send ok.
*
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2
* @param uart_no : 0 for UART0, 1 for UART1
*
* The function defined in ROM code has a bug, so we define the correct version
* here for compatibility.

40
tools/sdk/esp32c3/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h
View File

@ -28,7 +28,7 @@ extern "C"
////////////////////////////////////////////////////////////////////////////////
/**
* @brief Read the shared buffer from the slave.
* @brief Read the shared buffer from the slave in ISR way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
@ -46,7 +46,25 @@ extern "C"
esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags);
/**
* @brief Write the shared buffer of the slave.
* @brief Read the shared buffer from the slave in polling way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
* overwritten, even the ``len`` is shorter than a word.
*
* @param spi SPI device handle representing the slave
* @param out_data Buffer for read data, strongly suggested to be in the DRAM and align to 4
* @param addr Address of the slave shared buffer
* @param len Length to read
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: on success
* - or other return value from :cpp:func:`spi_device_transmit`.
*/
esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags);
/**
* @brief Write the shared buffer of the slave in ISR way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
@ -63,6 +81,24 @@ esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, i
*/
esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags);
/**
* @brief Write the shared buffer of the slave in polling way
*
* @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words
* by the DMA. When a byte is written, the remaining bytes in the same word will also be
* overwritten, even the ``len`` is shorter than a word.
*
* @param spi SPI device handle representing the slave
* @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4
* @param addr Address of the slave shared buffer,
* @param len Length to write
* @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send.
* @return
* - ESP_OK: success
* - or other return value from :cpp:func:`spi_device_polling_transmit`.
*/
esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags);
/**
* @brief Receive long buffer in segments from the slave through its DMA.
*

135
tools/sdk/esp32c3/include/esp_wifi/esp32c3/include/phy_init_data.h
View File

@ -38,78 +38,82 @@ extern "C" {
#define PHY_SUPPORT_MULTIPLE_BIN_OFFSET 125
#endif
static const char phy_init_magic_pre[] = PHY_INIT_MAGIC;
static const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_MAGIC;
/**
* @brief Structure containing default recommended PHY initialization parameters.
*/
static const esp_phy_init_data_t phy_init_data= { {
3,
3,
0x05,
0x09,
0x06,
0x05,
0x03,
0x06,
0x05,
0x04,
0x06,
0x04,
0x05,
0x00,
0x00,
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x44),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4a),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x46),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x46),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x42),
0x00,
0x00,
0x00,
0x00,
0x05,
0x09,
0x06,
0x05,
0x03,
0x06,
0x05,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xfc,
0xfc,
0xfe,
0xf0,
0xf0,
0xf0,
0xe0,
0xe0,
0xe0,
0x18,
0x18,
0x18,
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 84),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 72),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 66),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 56),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52),
0,
1,
1,
2,
2,
3,
4,
5,
0,
0,
0,
0,
0,
0,
0,
0,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0,
0,
0,
@ -151,9 +155,10 @@ static const esp_phy_init_data_t phy_init_data= { {
0,
0,
0,
0x74
} };
static const char phy_init_magic_post[] = PHY_INIT_MAGIC;
static const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
/**

14
tools/sdk/esp32c3/include/esp_wifi/include/esp_mesh.h
View File

@ -655,7 +655,7 @@ esp_err_t esp_mesh_stop(void);
* - If the packet is to the root ("to" parameter isn't NULL) or to external IP network, MESH_DATA_TODS should be set.
* - If the packet is from the root to an internal device, MESH_DATA_FROMDS should be set.
* - Specify whether this API is block or non-block, block by default
* - If needs non-block, MESH_DATA_NONBLOCK should be set.
* - If needs non-blocking, MESH_DATA_NONBLOCK should be set. Otherwise, may use esp_mesh_send_block_time() to specify a blocking time.
* - In the situation of the root change, MESH_DATA_DROP identifies this packet can be dropped by the new root
* for upstream data to external IP network, we try our best to avoid data loss caused by the root change, but
* there is a risk that the new root is running out of memory because most of memory is occupied by the pending data which
@ -688,6 +688,17 @@ esp_err_t esp_mesh_stop(void);
*/
esp_err_t esp_mesh_send(const mesh_addr_t *to, const mesh_data_t *data,
int flag, const mesh_opt_t opt[], int opt_count);
/**
* @brief Set blocking time of esp_mesh_send()
*
* @attention This API shall be called before mesh is started.
*
* @param[in] time_ms blocking time of esp_mesh_send(), unit:ms
*
* @return
* - ESP_OK
*/
esp_err_t esp_mesh_send_block_time(uint32_t time_ms);
/**
* @brief Receive a packet targeted to self over the mesh network
@ -1665,7 +1676,6 @@ int esp_mesh_get_running_active_duty_cycle(void);
* - ESP_OK
*/
esp_err_t esp_mesh_ps_duty_signaling(int fwd_times);
#ifdef __cplusplus
}
#endif

22
tools/sdk/esp32c3/include/esp_wifi/include/esp_private/wifi.h
View File

@ -72,17 +72,6 @@ typedef enum {
WIFI_LOG_MODULE_MESH, /*logs related to Mesh*/
} wifi_log_module_t;
/**
* @brief FTM Report log levels configuration
*
*/
typedef struct {
uint8_t show_rtt:1; /**< Display all valid Round-Trip-Time readings for FTM frames */
uint8_t show_diag:1; /**< Display dialogue tokens for all FTM frames with valid readings */
uint8_t show_t1t2t3t4:1;/**< Display all valid T1, T2, T3, T4 readings considered while calculating RTT */
uint8_t show_rxrssi:1; /**< Display RSSI for each FTM frame with valid readings */
} ftm_report_log_level_t;
/**
* @brief WiFi log submodule definition
*
@ -598,17 +587,6 @@ void esp_wifi_set_sleep_delay_time(uint32_t return_to_sleep_delay);
*/
void esp_wifi_set_keep_alive_time(uint32_t keep_alive_time);
/**
* @brief Set FTM Report log level
*
* @param log_lvl Log levels configuration
*
* @return
* - ESP_OK: succeed
* - ESP_ERR_NOT_SUPPORTED: No FTM support
*/
esp_err_t esp_wifi_set_ftm_report_log_level(ftm_report_log_level_t *log_lvl);
#ifdef __cplusplus
}
#endif

16
tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi_default.h
View File

@ -70,6 +70,9 @@ esp_err_t esp_wifi_clear_default_wifi_driver_and_handlers(void *esp_netif);
/**
* @brief Creates default WIFI AP. In case of any init error this API aborts.
*
* @note The API creates esp_netif object with default WiFi access point config,
* attaches the netif to wifi and registers default wifi handlers.
*
* @return pointer to esp-netif instance
*/
esp_netif_t* esp_netif_create_default_wifi_ap(void);
@ -77,10 +80,23 @@ esp_netif_t* esp_netif_create_default_wifi_ap(void);
/**
* @brief Creates default WIFI STA. In case of any init error this API aborts.
*
* @note The API creates esp_netif object with default WiFi station config,
* attaches the netif to wifi and registers default wifi handlers.
*
* @return pointer to esp-netif instance
*/
esp_netif_t* esp_netif_create_default_wifi_sta(void);
/**
* @brief Destroys default WIFI netif created with esp_netif_create_default_wifi_...() API.
*
* @param[in] esp_netif object to detach from WiFi and destroy
*
* @note This API unregisters wifi handlers and detaches the created object from the wifi.
* (this function is a no-operation if esp_netif is NULL)
*/
void esp_netif_destroy_default_wifi(void *esp_netif);
/**
* @brief Creates esp_netif WiFi object based on the custom configuration.
*

1
tools/sdk/esp32c3/include/esp_wifi/include/esp_wifi_types.h
View File

@ -233,6 +233,7 @@ typedef struct {
uint8_t max_connection; /**< Max number of stations allowed to connect in, default 4, max 10 */
uint16_t beacon_interval; /**< Beacon interval which should be multiples of 100. Unit: TU(time unit, 1 TU = 1024 us). Range: 100 ~ 60000. Default value: 100 */
wifi_cipher_type_t pairwise_cipher; /**< pairwise cipher of SoftAP, group cipher will be derived using this. cipher values are valid starting from WIFI_CIPHER_TYPE_TKIP, enum values before that will be considered as invalid and default cipher suites(TKIP+CCMP) will be used. Valid cipher suites in softAP mode are WIFI_CIPHER_TYPE_TKIP, WIFI_CIPHER_TYPE_CCMP and WIFI_CIPHER_TYPE_TKIP_CCMP. */
bool ftm_responder; /**< Enable FTM Responder mode */
} wifi_ap_config_t;
/** @brief STA configuration settings for the ESP32 */

13
tools/sdk/esp32c3/include/espcoredump/include/esp_core_dump.h
View File

@ -104,6 +104,19 @@ void esp_core_dump_to_uart(panic_info_t *info);
/*********************************** USER MODE API ************************************/
/**************************************************************************************/
/**
* @brief Check integrity of coredump data in flash.
* This function reads the coredump data while calculating their checksum. If it
* doesn't match the checksum written on flash, it means data are corrupted,
* an error will be returned. Else, ESP_OK is returned.
*
* @return `ESP_OK` if core dump is present and valid, `ESP_ERR_NOT_FOUND` if no core dump
* is stored in the partition, `ESP_ERR_INVALID_SIZE` or `ESP_ERR_INVALID_CRC`
* if the core dump is corrupted, other errors when unable to access flash, in that
* case please refer to \see esp_err_t
*/
esp_err_t esp_core_dump_image_check(void);
/**
* @brief Retrieves address and size of coredump data in flash.
* This function is always available, even when core dump is disabled in menuconfig.

2
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/cpu_ll.h
View File

@ -15,7 +15,7 @@
#include <stdint.h>
#include "soc/cpu_caps.h"
#include "soc/soc_caps.h"
#include "esp_bit_defs.h"
#include "soc/assist_debug_reg.h"
#include "esp_attr.h"

10
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/ds_ll.h
View File

@ -24,7 +24,7 @@
#include <string.h>
#include "soc/hwcrypto_reg.h"
#include "soc/ds_caps.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
@ -69,7 +69,7 @@ static inline ds_key_check_t ds_ll_key_error_source(void)
*/
static inline void ds_ll_configure_iv(const uint32_t *iv)
{
for (size_t i = 0; i < (DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]);
}
}
@ -99,9 +99,9 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
*/
typedef struct { uint32_t addr; size_t len; } frag_t;
const frag_t frags[] = {
{DS_C_Y_BASE, DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_C_M_BASE, DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_C_RB_BASE, DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_C_Y_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_C_M_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
{DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE},
};
const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);

106
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/gdma_ll.h
View File

@ -17,7 +17,6 @@
#include <stdbool.h>
#include "soc/gdma_struct.h"
#include "soc/gdma_reg.h"
#include "soc/gdma_caps.h"
#ifdef __cplusplus
extern "C" {
@ -25,6 +24,9 @@ extern "C" {
#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
#define GDMA_LL_RX_EVENT_MASK (0x06A7)
#define GDMA_LL_TX_EVENT_MASK (0x1958)
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<12)
#define GDMA_LL_EVENT_TX_FIFO_OVF (1<<11)
#define GDMA_LL_EVENT_RX_FIFO_UDF (1<<10)
@ -47,40 +49,12 @@ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bo
{
dev->channel[channel].in.in_conf0.mem_trans_en = enable;
if (enable) {
// only have to give it a valid value
// to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value
dev->channel[channel].in.in_peri_sel.sel = 0;
dev->channel[channel].out.out_peri_sel.sel = 0;
}
}
/**
* @brief Get DMA interrupt status word
*/
static inline uint32_t gdma_ll_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->intr[channel].st.val;
}
/**
* @brief Enable DMA interrupt
*/
static inline void gdma_ll_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->intr[channel].ena.val |= mask;
} else {
dev->intr[channel].ena.val &= ~mask;
}
}
/**
* @brief Clear DMA interrupt
*/
static inline void gdma_ll_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->intr[channel].clr.val = mask;
}
/**
* @brief Enable DMA clock gating
*/
@ -90,6 +64,42 @@ static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word
*/
static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->intr[channel].st.val & GDMA_LL_RX_EVENT_MASK;
}
/**
* @brief Enable DMA RX channel interrupt
*/
static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->intr[channel].ena.val |= (mask & GDMA_LL_RX_EVENT_MASK);
} else {
dev->intr[channel].ena.val &= ~(mask & GDMA_LL_RX_EVENT_MASK);
}
}
/**
* @brief Clear DMA RX channel interrupt
*/
static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->intr[channel].clr.val = (mask & GDMA_LL_RX_EVENT_MASK);
}
/**
* @brief Get DMA RX channel interrupt status register address
*/
static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->intr[channel].st);
}
/**
* @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
*/
@ -248,6 +258,42 @@ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
}
///////////////////////////////////// TX /////////////////////////////////////////
/**
* @brief Get DMA TX channel interrupt status word
*/
static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->intr[channel].st.val & GDMA_LL_TX_EVENT_MASK;
}
/**
* @brief Enable DMA TX channel interrupt
*/
static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->intr[channel].ena.val |= (mask & GDMA_LL_TX_EVENT_MASK);
} else {
dev->intr[channel].ena.val &= ~(mask & GDMA_LL_TX_EVENT_MASK);
}
}
/**
* @brief Clear DMA TX channel interrupt
*/
static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->intr[channel].clr.val = (mask & GDMA_LL_TX_EVENT_MASK);
}
/**
* @brief Get DMA TX channel interrupt status register address
*/
static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
{
return (volatile void *)(&dev->intr[channel].st);
}
/**
* @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
*/

40
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/interrupt_controller_ll.h
View File

@ -49,6 +49,16 @@ static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
}
/**
* @brief Read the current interrupt mask of the CPU running this code.
*
* @return The current interrupt bitmask.
*/
static inline uint32_t intr_cntrl_ll_read_interrupt_mask(void)
{
return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
}
/**
* @brief checks if given interrupt number has a valid handler
*
@ -85,36 +95,6 @@ static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
return intr_handler_get_arg(intr);
}
/**
* @brief Disables interrupts that are not located in iram
*
* @param newmask mask of interrupts TO KEEP ENABLED (note: this is probably a bug, see IDF-2308)
* @return oldmask previous interrupt mask value
*/
static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask)
{
// Disable interrupts in order to atomically update the interrupt enable register
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
uint32_t old_int_enable = REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
REG_WRITE(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, old_int_enable & newmask);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
return old_int_enable;
}
/**
* @brief Enables interrupts that are not located in iram
*
* @param newmask mask of interrupts needs to be enabled
*/
static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
{
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
esprv_intc_int_enable(newmask);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
}
/**
* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
*

4
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/mpu_ll.h
View File

@ -14,7 +14,7 @@
#include <stdint.h>
#include "soc/mpu_caps.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
@ -22,7 +22,7 @@ extern "C" {
/* This LL is currently unused for ESP32-C3 - cleanup is TODO ESP32-C3 IDF-2375 */
static inline uint32_t mpu_ll_id_to_addr(int id)
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{
abort();
}

157
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h Normal file
View File

@ -0,0 +1,157 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The Lowlevel layer for SPI Flash Encryption.
#include "soc/system_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/soc.h"
#include "string.h"
#include "assert.h"
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/// Choose type of chip you want to encrypt manully
typedef enum
{
FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
} flash_encrypt_ll_type_t;
/**
* Enable the flash encryption function under spi boot mode and download boot mode.
*/
static inline void spi_flash_encrypt_ll_enable(void)
{
REG_SET_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
}
/*
* Disable the flash encryption mode.
*/
static inline void spi_flash_encrypt_ll_disable(void)
{
REG_CLR_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
}
/**
* Choose type of chip you want to encrypt manully
*
* @param type The type of chip to be encrypted
*
* @note The hardware currently support flash encryption.
*/
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
assert(type == FLASH_ENCRYPTION_MANU);
REG_WRITE(AES_XTS_DESTINATION_REG, type);
}
/**
* Configure the data size of a single encryption.
*
* @param block_size Size of the desired block.
*/
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
// Desired block should not be larger than the block size.
REG_WRITE(AES_XTS_SIZE_REG, size >> 5);
}
/**
* Save 32-bit piece of plaintext.
*
* @param address the address of written flash partition.
* @param buffer Buffer to store the input data.
* @param size Buffer size.
*
*/
static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
{
uint32_t plaintext_offs = (address % 64);
memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size);
}
/**
* Copy the flash address to XTS_AES physical address
*
* @param flash_addr flash address to write.
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr);
}
/**
* Start flash encryption
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
REG_WRITE(AES_XTS_TRIGGER_REG, 1);
}
/**
* Wait for flash encryption termination
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
}
}
/**
* Finish the flash encryption and make encrypted result accessible to SPI.
*/
static inline void spi_flash_encrypt_ll_done(void)
{
REG_WRITE(AES_XTS_RELEASE_REG, 1);
while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
}
}
/**
* Set to destroy encrypted result
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
REG_WRITE(AES_XTS_DESTROY_REG, 1);
}
/**
* Check if is qualified to encrypt the buffer
*
* @param address the address of written flash partition.
* @param length Buffer size.
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
return ((address % length) == 0) ? true : false;
}
#ifdef __cplusplus
}
#endif

2
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/spi_ll.h
View File

@ -1005,7 +1005,7 @@ static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
{
#define CLR_INTR(intr_bit, _, __, clr_op) if (intr_mask & (intr_bit)) hw->clr_op;
#define CLR_INTR(intr_bit, _, __, clr_reg) if (intr_mask & (intr_bit)) hw->clr_reg;
FOR_EACH_ITEM(CLR_INTR, INTR_LIST);
#undef CLR_INTR
}

137
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/systimer_ll.h
View File

@ -13,139 +13,150 @@
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "soc/systimer_struct.h"
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
#define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick
#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
#define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/systimer_reg.h"
// All these functions get invoked either from ISR or HAL that linked to IRAM.
// Always inline these functions even no gcc optimization is applied.
/*******************counter*************************/
/******************* Clock *************************/
__attribute__((always_inline)) static inline void systimer_ll_enable_clock(void)
__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, SYS_TIMER_CLK_EN);
dev->conf.clk_en = en;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_counter(uint32_t counter_id)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (30 - counter_id));
}
/******************* Counter *************************/
__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can)
__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
{
if (can) {
REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id));
if (en) {
dev->conf.val |= 1 << (30 - counter_id);
} else {
REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << ((28 - counter_id * 2) - cpu_id));
dev->conf.val &= ~(1 << (30 - counter_id));
}
}
__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(uint32_t counter_id)
__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 30);
if (can) {
dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
} else {
dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
}
}
__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(uint32_t counter_id)
__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
{
return REG_GET_BIT(SYS_TIMER_SYSTIMER_UNIT0_OP_REG + 4 * counter_id, 1 << 29);
dev->unit_op[counter_id].timer_unit_update = 1;
}
__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(uint32_t counter_id, uint64_t value)
__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
{
REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG + 8 * counter_id, value & 0xFFFFFFFF);
REG_WRITE(SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG, (value >> 32) & 0xFFFFF);
return dev->unit_op[counter_id].timer_unit_value_valid;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(uint32_t counter_id)
__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
{
return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG + 8 * counter_id);
dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
}
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(uint32_t counter_id)
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
{
return REG_READ(SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG + 8 * counter_id);
return dev->unit_val[counter_id].lo.timer_unit_value_lo;
}
__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(uint32_t counter_id)
__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG + 4 * counter_id, SYS_TIMER_TIMER_UNIT0_LOAD);
return dev->unit_val[counter_id].hi.timer_unit_value_hi;
}
/*******************alarm*************************/
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(uint32_t alarm_id, uint64_t value)
__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
{
REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF);
REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value >> 32) & 0xFFFFF);
dev->unit_load[counter_id].val = 0x01;
}
__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(uint32_t alarm_id)
/******************* Alarm *************************/
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
{
return ((uint64_t) REG_READ(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8) << 32) \
| REG_READ(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8);
dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
}
__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(uint32_t alarm_id, uint32_t counter_id)
__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
{
REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + 4 * alarm_id, SYS_TIMER_TARGET0_TIMER_UNIT_SEL, counter_id);
return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
{
REG_CLR_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE);
dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD_MODE);
dev->target_conf[alarm_id].target_period_mode = 0;
}
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(uint32_t alarm_id, uint32_t period)
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
{
REG_SET_FIELD(SYS_TIMER_SYSTIMER_TARGET0_CONF_REG + alarm_id * 4, SYS_TIMER_TARGET0_PERIOD, period);
dev->target_conf[alarm_id].target_period_mode = 1;
}
__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_COMP0_LOAD_REG + alarm_id * 4, SYS_TIMER_TIMER_COMP0_LOAD);
assert(period < (1 << 26));
dev->target_conf[alarm_id].target_period = period;
}
__attribute__((always_inline)) static inline void systimer_ll_disable_alarm(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
{
REG_CLR_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id));
dev->comp_load[alarm_id].val = 0x01;
}
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_CONF_REG, 1 << (24 - alarm_id));
if (en) {
dev->conf.val |= 1 << (24 - alarm_id);
} else {
dev->conf.val &= ~(1 << (24 - alarm_id));
}
}
/*******************interrupt*************************/
/******************* Interrupt *************************/
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, 1 << alarm_id);
if (en) {
dev->int_ena.val |= 1 << alarm_id;
} else {
dev->int_ena.val &= ~(1 << alarm_id);
}
}
__attribute__((always_inline)) static inline void systimer_ll_disable_alarm_int(uint32_t alarm_id)
__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
{
REG_CLR_BIT(SYS_TIMER_SYSTIMER_INT_ENA_REG, 1 << alarm_id);
return dev->int_st.val & (1 << alarm_id);
}
__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(uint32_t alarm_id)
__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
{
return REG_GET_BIT(SYS_TIMER_SYSTIMER_INT_RAW_REG, 1 << alarm_id);
}
__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(uint32_t alarm_id)
{
REG_SET_BIT(SYS_TIMER_SYSTIMER_INT_CLR_REG, 1 << alarm_id);
dev->int_clr.val |= 1 << alarm_id;
}
#ifdef __cplusplus

3
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/uart_ll.h
View File

@ -32,6 +32,9 @@ extern "C" {
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),

62
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/uhci_ll.h
View File

@ -20,12 +20,16 @@
#include <stdio.h>
#include "uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/gdma_struct.h"
#define UHCI_DMA_INDEX 0
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
UHCI_RX_LEN_EOF = 0x4,
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
@ -38,7 +42,8 @@ static inline void uhci_ll_init(uhci_dev_t *hw)
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
abort(); // TODO ESP32-C3 IDF-2117
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
@ -90,20 +95,6 @@ static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_c
hw->escape_conf.val = escape_conf_reg.val;
}
static inline void uhci_ll_dma_in_reset(uhci_dev_t *hw)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].in.in_conf0.in_rst = 1;
GDMA.channel[UHCI_DMA_INDEX].in.in_conf0.in_rst = 0;
}
static inline void uhci_ll_dma_out_reset(uhci_dev_t *hw)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].out.out_conf0.out_rst = 1;
GDMA.channel[UHCI_DMA_INDEX].out.out_conf0.out_rst = 0;
}
static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val |= intr_mask;
@ -124,41 +115,6 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
return hw->int_st.val;
}
static inline void uhci_ll_set_rx_dma(uhci_dev_t *hw, uint32_t addr)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].in.in_link.addr = addr;
}
static inline void uhci_ll_set_tx_dma(uhci_dev_t *hw, uint32_t addr)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].out.out_link.addr = addr;
}
static inline void uhci_ll_rx_dma_start(uhci_dev_t *hw)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].in.in_link.start = 1;
}
static inline void uhci_ll_tx_dma_start(uhci_dev_t *hw)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].out.out_link.start = 1;
}
static inline void uhci_ll_rx_dma_stop(uhci_dev_t *hw)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].in.in_link.stop = 1;
}
static inline void uhci_ll_tx_dma_stop(uhci_dev_t *hw)
{
(void)hw;
GDMA.channel[UHCI_DMA_INDEX].out.out_link.stop = 1;
}
static inline void uhci_ll_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{

54
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/uhci_types.h Normal file
View File

@ -0,0 +1,54 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Though the UHCI driver hasn't been published, some types are defined here
// for users to develop over the HAL. See example: controller_hci_uart_esp32c3
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
/**
* @brief UHCI escape sequence
*/
typedef struct {
uint8_t seper_chr; /*!< escape sequence character */
uint8_t sub_chr1; /*!< escape sequence sub-character 1 */
uint8_t sub_chr2; /*!< escape sequence sub-character 2 */
bool sub_chr_en; /*!< enable use of sub-chaacter of escape sequence */
} uhci_seper_chr_t;
/**
* @brief UHCI software flow control
*/
typedef struct {
uint8_t xon_chr; /*!< character for XON */
uint8_t xon_sub1; /*!< sub-character 1 for XON */
uint8_t xon_sub2; /*!< sub-character 2 for XON */
uint8_t xoff_chr; /*!< character 2 for XOFF */
uint8_t xoff_sub1; /*!< sub-character 1 for XOFF */
uint8_t xoff_sub2; /*!< sub-character 2 for XOFF */
uint8_t flow_en; /*!< enable use of software flow control */
} uhci_swflow_ctrl_sub_chr_t;
#ifdef __cplusplus
}
#endif

169
tools/sdk/esp32c3/include/hal/esp32c3/include/hal/usb_serial_jtag_ll.h Normal file
View File

@ -0,0 +1,169 @@
// Copyright 2021 Espressif Systems (Shanghai)
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// The LL layer of the USB-serial-jtag controller
#pragma once
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
//The in and out endpoints are this long.
#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask
// Define USB_SERIAL_JTAG interrupts
// Note the hardware has more interrupts, but they're only useful for debugging
// the hardware.
typedef enum {
USB_SERIAL_JTAG_INTR_SOF = (1 << 1),
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2),
USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3),
USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8),
USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9),
USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10),
} usb_serial_jtag_intr_t;
/**
* @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask.
*
* @param mask The bitmap of the interrupts need to be enabled.
*
* @return None
*/
static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_ena.val |= mask;
}
/**
* @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask.
*
* @param mask The bitmap of the interrupts need to be disabled.
*
* @return None
*/
static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_ena.val &= (~mask);
}
/**
* @brief Get the USB_SERIAL_JTAG interrupt status.
*
* @return The USB_SERIAL_JTAG interrupt status.
*/
static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
{
return USB_SERIAL_JTAG.int_st.val;
}
/**
* @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask.
*
* @param mask The bitmap of the interrupts need to be cleared.
*
* @return None
*/
static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_clr.val = mask;
}
/**
* @brief Get status of enabled interrupt.
*
* @return interrupt enable value
*/
static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void)
{
return USB_SERIAL_JTAG.int_ena.val;
}
/**
* @brief Read the bytes from the USB_SERIAL_JTAG rxfifo.
*
* @param buf The data buffer.
* @param rd_len The data length needs to be read.
*
* @return amount of bytes read
*/
static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
{
int i;
for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
}
return i;
}
/**
* @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there
* is room in the buffer.
*
* @param buf The data buffer.
* @param wr_len The data length needs to be writen.
*
* @return Amount of bytes actually written. May be less than wr_len.
*/
static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len)
{
int i;
for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
}
return i;
}
/**
* @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available.
*
* @return 0 if no data available, 1 if data available
*/
static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
{
return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
}
/**
* @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room.
*
* @return 0 if no data available, 1 if data available
*/
static inline int usb_serial_jtag_ll_txfifo_writable(void)
{
return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free;
}
/**
* @brief Flushes the TX buffer, that is, make it available for the
* host to pick up.
*
* @return na
*/
static inline void usb_serial_jtag_ll_txfifo_flush(void)
{
USB_SERIAL_JTAG.ep1_conf.wr_done=1;
}
#ifdef __cplusplus
}
#endif

5
tools/sdk/esp32c3/include/hal/include/hal/ds_hal.h
View File

@ -60,11 +60,6 @@ void ds_hal_start(void);
*/
void ds_hal_finish(void);
/**
* @brief Check whether the key input (HMAC on ESP32-C3) is correct.
*/
ds_key_check_t ds_hal_check_decryption_key(void);
/**
* @brief Write the initialization vector.
*/

4
tools/sdk/esp32c3/include/hal/include/hal/gpio_types.h
View File

@ -76,6 +76,9 @@ typedef enum {
#define GPIO_SEL_44 ((uint64_t)(((uint64_t)1)<<44)) /*!< Pin 44 selected */
#define GPIO_SEL_45 ((uint64_t)(((uint64_t)1)<<45)) /*!< Pin 45 selected */
#define GPIO_SEL_46 ((uint64_t)(((uint64_t)1)<<46)) /*!< Pin 46 selected */
#if CONFIG_IDF_TARGET_ESP32S3
#define GPIO_SEL_47 ((uint64_t)(((uint64_t)1)<<47)) /*!< Pin 47 selected */
#endif
#endif
#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
@ -125,6 +128,7 @@ typedef enum {
#define GPIO_PIN_REG_44 IO_MUX_GPIO44_REG
#define GPIO_PIN_REG_45 IO_MUX_GPIO45_REG
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG
#if CONFIG_IDF_TARGET_ESP32
typedef enum {

31
tools/sdk/esp32c3/include/hal/include/hal/interrupt_controller_hal.h
View File

@ -135,6 +135,16 @@ static inline void interrupt_controller_hal_disable_interrupts(uint32_t mask)
intr_cntrl_ll_disable_interrupts(mask);
}
/**
* @brief Read the current interrupt mask.
*
* @return The bitmask of current interrupts
*/
static inline uint32_t interrupt_controller_hal_read_interrupt_mask(void)
{
return intr_cntrl_ll_read_interrupt_mask();
}
/**
* @brief checks if given interrupt number has a valid handler
*
@ -171,27 +181,6 @@ static inline void * interrupt_controller_hal_get_int_handler_arg(uint8_t intr)
return intr_cntrl_ll_get_int_handler_arg(intr);
}
/**
* @brief Disables interrupts that are not located in iram
*
* @param newmask mask of interrupts needs to be disabled
* @return oldmask where to store old interrupts state
*/
static inline uint32_t interrupt_controller_hal_disable_int_mask(uint32_t newmask)
{
return intr_cntrl_ll_disable_int_mask(newmask);
}
/**
* @brief Enables interrupts that are not located in iram
*
* @param newmask mask of interrupts needs to be disabled
*/
static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask)
{
intr_cntrl_ll_enable_int_mask(newmask);
}
/**
* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
*

4
tools/sdk/esp32c3/include/hal/include/hal/ledc_types.h
View File

@ -134,6 +134,10 @@ typedef struct {
ledc_timer_t timer_sel; /*!< Select the timer source of channel (0 - 3) */
uint32_t duty; /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
int hpoint; /*!< LEDC channel hpoint value, the max value is 0xfffff */
struct {
unsigned int output_invert: 1;/*!< Enable (1) or disable (0) gpio output invert */
} flags; /*!< LEDC flags */
} ledc_channel_config_t;
/**

62
tools/sdk/esp32c3/include/hal/include/hal/spi_flash_encrypt_hal.h Normal file
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@ -0,0 +1,62 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The HAL is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI Flash Encryption
#include "hal/spi_flash_encrypted_ll.h"
/**
* @brief Enable the flash encryption
*/
void spi_flash_encryption_hal_enable(void);
/**
* @brief Disable the flash encryption
*/
void spi_flash_encryption_hal_disable(void);
/**
* Prepare flash encryption before operation.
*
* @param address The destination address in flash for the write operation.
* @param buffer Data for programming
* @param size Size to program.
*
* @note address and buffer must be 8-word aligned.
*/
void spi_flash_encryption_hal_prepare(uint32_t address, const uint32_t* buffer, uint32_t size);
/**
* @brief flash data encryption operation is done.
*/
void spi_flash_encryption_hal_done(void);
/**
* Destroy encrypted result
*/
void spi_flash_encryption_hal_destroy(void);
/**
* Check if is qualified to encrypt the buffer
*
* @param address the address of written flash partition.
* @param length Buffer size.
*/
bool spi_flash_encryption_hal_check(uint32_t address, uint32_t length);

38
tools/sdk/esp32c3/include/hal/include/hal/spi_flash_types.h
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@ -86,6 +86,44 @@ typedef struct {
};
} spi_flash_sus_cmd_conf;
/// Structure for flash encryption operations.
typedef struct
{
/**
* @brief Enable the flash encryption
*/
void (*flash_encryption_enable)(void);
/**
* @brief Disable the flash encryption
*/
void (*flash_encryption_disable)(void);
/**
* Prepare flash encryption before operation.
*
* @param address The destination address in flash for the write operation.
* @param buffer Data for programming
* @param size Size to program.
*
* @note address and buffer must be 8-word aligned.
*/
void (*flash_encryption_data_prepare)(uint32_t address, const uint32_t* buffer, uint32_t size);
/**
* @brief flash data encryption operation is done.
*/
void (*flash_encryption_done)(void);
/**
* Destroy encrypted result
*/
void (*flash_encryption_destroy)(void);
/**
* Check if is qualified to encrypt the buffer
*
* @param address the address of written flash partition.
* @param length Buffer size.
*/
bool (*flash_encryption_check)(uint32_t address, uint32_t length);
} spi_flash_encryption_t;
///Slowest io mode supported by ESP32, currently SlowRd
#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD

18
tools/sdk/esp32c3/include/hal/include/hal/spi_types.h
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@ -31,13 +31,17 @@ typedef enum {
/// SPI Events
typedef enum {
SPI_EV_BUF_TX = BIT(0), ///< The buffer has sent data to master, Slave HD only
SPI_EV_BUF_RX = BIT(1), ///< The buffer has received data from master, Slave HD only
SPI_EV_SEND = BIT(2), ///< Slave has loaded some data to DMA, and master has received certain number of the data, the number is determined by master. Slave HD only
SPI_EV_RECV = BIT(3), ///< Slave has received certain number of data from master, the number is determined by master. Slave HD only.
SPI_EV_CMD9 = BIT(4), ///< Received CMD9 from master, Slave HD only
SPI_EV_CMDA = BIT(5), ///< Received CMDA from master, Slave HD only
SPI_EV_TRANS = BIT(6), ///< A transaction has done
/* Slave HD Only */
SPI_EV_BUF_TX = BIT(0), ///< The buffer has sent data to master.
SPI_EV_BUF_RX = BIT(1), ///< The buffer has received data from master.
SPI_EV_SEND_DMA_READY = BIT(2), ///< Slave has loaded its TX data buffer to the hardware (DMA).
SPI_EV_SEND = BIT(3), ///< Master has received certain number of the data, the number is determined by Master.
SPI_EV_RECV_DMA_READY = BIT(4), ///< Slave has loaded its RX data buffer to the hardware (DMA).
SPI_EV_RECV = BIT(5), ///< Slave has received certain number of data from master, the number is determined by Master.
SPI_EV_CMD9 = BIT(6), ///< Received CMD9 from master.
SPI_EV_CMDA = BIT(7), ///< Received CMDA from master.
/* Common Event */
SPI_EV_TRANS = BIT(8), ///< A transaction has done
} spi_event_t;
FLAG_ATTR(spi_event_t)

125
tools/sdk/esp32c3/include/hal/include/hal/systimer_hal.h
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@ -14,78 +14,91 @@
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "soc/systimer_struct.h"
#include "hal/systimer_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "hal/systimer_types.h"
/**
* @brief enable systimer counter
*/
void systimer_hal_enable_counter(systimer_counter_id_t counter_id);
/**
* @brief get current counter value
*/
uint64_t systimer_hal_get_counter_value(systimer_counter_id_t counter_id);
/**
* @brief get current time (in microseconds)
*/
uint64_t systimer_hal_get_time(systimer_counter_id_t counter_id);
/*
* @brief set alarm target value (used in one-shot mode)
*/
void systimer_hal_set_alarm_target(systimer_alarm_id_t alarm_id, uint64_t target);
/**
* @brief set alarm period value (used in period mode)
*/
void systimer_hal_set_alarm_period(systimer_alarm_id_t alarm_id, uint32_t period);
/**
* @brief get alarm time
*/
uint64_t systimer_hal_get_alarm_value(systimer_alarm_id_t alarm_id);
/**
* @brief enable alarm interrupt
*/
void systimer_hal_enable_alarm_int(systimer_alarm_id_t alarm_id);
/**
* @brief select alarm mode
*/
void systimer_hal_select_alarm_mode(systimer_alarm_id_t alarm_id, systimer_alarm_mode_t mode);
/**
* @brief update systimer step when apb clock gets changed
*/
void systimer_hal_on_apb_freq_update(uint32_t apb_ticks_per_us);
/**
* @brief move systimer counter value forward or backward
*/
void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_t time_us);
typedef struct {
systimer_dev_t *dev;
} systimer_hal_context_t;
/**
* @brief initialize systimer in HAL layer
*/
void systimer_hal_init(void);
void systimer_hal_init(systimer_hal_context_t *hal);
/**
* @brief enable systimer counter
*/
void systimer_hal_enable_counter(systimer_hal_context_t *hal, uint32_t counter_id);
/**
* @brief get current counter value
*/
uint64_t systimer_hal_get_counter_value(systimer_hal_context_t *hal, uint32_t counter_id);
/**
* @brief get current time (in microseconds)
*/
uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id);
/*
* @brief set alarm target value (used in one-shot mode)
*/
void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target);
/**
* @brief set alarm period value (used in period mode)
*/
void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period);
/**
* @brief get alarm time
*/
uint64_t systimer_hal_get_alarm_value(systimer_hal_context_t *hal, uint32_t alarm_id);
/**
* @brief enable alarm interrupt
*/
void systimer_hal_enable_alarm_int(systimer_hal_context_t *hal, uint32_t alarm_id);
/**
* @brief select alarm mode
*/
void systimer_hal_select_alarm_mode(systimer_hal_context_t *hal, uint32_t alarm_id, systimer_alarm_mode_t mode);
/**
* @brief update systimer step when apb clock gets changed
*/
void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_ticks_per_us);
/**
* @brief move systimer counter value forward or backward
*/
void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t counter_id, int64_t time_us);
/**
* @brief connect alarm unit to selected counter
*/
void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id);
void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t counter_id);
/**
* @brief set if a counter should be stalled when CPU is halted by the debugger
*/
void systimer_hal_counter_can_stall_by_cpu(uint32_t counter_id, uint32_t cpu_id, bool can);
void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can);
#if !SOC_SYSTIMER_FIXED_TICKS_US
/**
* @brief set increase steps for systimer counter on different clock source
*/
void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps);
#endif
#ifdef __cplusplus
}

27
tools/sdk/esp32c3/include/hal/include/hal/systimer_types.h
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@ -14,13 +14,13 @@
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc/soc_caps.h"
/*
* @brief The structure of the counter value in systimer
*
@ -39,27 +39,6 @@ typedef struct {
_Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t should occupy 8 bytes in memory");
/** @endcond */
/**
* @brief systimer counter ID
*
*/
typedef enum {
SYSTIMER_COUNTER_0, /*!< systimer counter 0 */
#if SOC_SYSTIMER_COUNTER_NUM > 1
SYSTIMER_COUNTER_1, /*!< systimer counter 1 */
#endif
} systimer_counter_id_t;
/**
* @brief systimer alarm ID
*
*/
typedef enum {
SYSTIMER_ALARM_0, /*!< systimer alarm 0 */
SYSTIMER_ALARM_1, /*!< systimer alarm 1 */
SYSTIMER_ALARM_2, /*!< systimer alarm 2 */
} systimer_alarm_id_t;
/**
* @brief systimer alarm mode
*

452
tools/sdk/esp32c3/include/hal/include/hal/usb_types.h
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@ -1,452 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#define USB_CTRL_REQ_ATTR __attribute__((packed))
#define USB_DESC_ATTR __attribute__((packed))
/* -----------------------------------------------------------------------------
------------------------------- Common USB Types -------------------------------
----------------------------------------------------------------------------- */
// ----------------------------- Device Related --------------------------------
/**
* @brief Enumeration of USB PHY type
*/
typedef enum {
USB_PHY_INTERNAL = 0, /**< Use the chip's internal USB PHY */
USB_PHY_EXTERNAL, /**< Use an external USB PHY */
} usb_phy_t;
// ------------------------------ Bus Related ----------------------------------
/**
* @brief USB Standard Speeds
*/
typedef enum {
USB_SPEED_LOW = 0, /**< USB Low Speed (1.5 Mbit/s) */
USB_SPEED_FULL, /**< USB Full Speed (12 Mbit/s) */
} usb_speed_t;
// ---------------------------- Transfer Related -------------------------------
/**
* @brief The type of USB transfer
*
* @note The enum values need to match the bmAttributes field of an EP descriptor
*/
typedef enum {
USB_XFER_TYPE_CTRL = 0,
USB_XFER_TYPE_ISOCHRONOUS,
USB_XFER_TYPE_BULK,
USB_XFER_TYPE_INTR,
} usb_xfer_type_t;
/**
* @brief The status of a particular transfer
*/
typedef enum {
USB_TRANSFER_STATUS_COMPLETED, /**< The transfer was successful (but may be short) */
USB_TRANSFER_STATUS_ERROR, /**< The transfer failed because due to excessive errors (e.g. no response or CRC error) */
USB_TRANSFER_STATUS_TIMED_OUT, /**< The transfer failed due to to a time out */
USB_TRANSFER_STATUS_CANCELLED, /**< The transfer was cancelled */
USB_TRANSFER_STATUS_STALL, /**< The transfer was stalled */
USB_TRANSFER_STATUS_NO_DEVICE, /**< The transfer failed because the device is no longer valid (e.g., disconencted */
USB_TRANSFER_STATUS_OVERFLOW, /**< The transfer as more data was sent than was requested */
} usb_transfer_status_t;
/**
* @brief Isochronous packet descriptor
*
* If the number of bytes in an IRP transfer is larger than the MPS of the
* endpoint, the IRP is split over multiple packets (one packet per bInterval
* of the endpoint). An array of Isochronous packet descriptos describes how
* an IRP should be split over multiple packets.
*/
typedef struct {
int length; /**< Number of bytes to transmit/receive in the packet */
int actual_length; /**< Actual number of bytes transmitted/received in the packet */
usb_transfer_status_t status; /**< Status of the packet */
} usb_iso_packet_desc_t;
/**
* @brief USB IRP (I/O Request Packet). See USB2.0 Spec
*
* An identifiable request by a software client to move data between itself (on the
* host) and an endpoint of a device in an appropriate direction.
*
* This structure represents the barebones of the request. Different layers of
* USB drivers will wrap their own objects around this.
*
* See 10.5.3.1 os USB2.0 specification
* Bulk: Represnts a single bulk transfer which a pipe will transparently split
* into multiple MPS transactions (until the last)
* Control: Represents a single contorl transfer with the setup packet at the
* first 8 bytes of the buffer.
* Interrupt: Represnts a single interrupt transaction
* Isochronous: Represnts a buffer of a stream of bytes which the pipe will transparently
* transfer the stream of bytes one or more service periods
*/
typedef struct {
int num_bytes; /**< Number of bytes in IRP. Control should exclude size of setup. IN should be integer multiple of MPS */
int actual_num_bytes; /**< Actual number of bytes transmitted/receives in the IRP */
uint8_t *data_buffer; /**< Pointer to data buffer. Must be DMA capable memory */
usb_transfer_status_t status; /**< Status of the transfer */
int num_iso_packets; /**< Only relevant to isochronous. Number of service periods to transfer data buffer over. Set to 0 for non-iso transfers */
usb_iso_packet_desc_t iso_packet_desc[0]; /**< Descriptors for each ISO packet */
} usb_irp_t;
/* -----------------------------------------------------------------------------
----------------------------------- Chapter 9 ----------------------------------
----------------------------------------------------------------------------- */
// ------------------------------ Control Request ------------------------------
/**
* @brief Size of a USB control transfer setup packet in bytes
*/
#define USB_CTRL_REQ_SIZE 8
/**
* @brief Structure representing a USB control transfer setup packet
*/
typedef union {
struct {
uint8_t bRequestType;
uint8_t bRequest;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} USB_CTRL_REQ_ATTR;
uint8_t val[USB_CTRL_REQ_SIZE];
} usb_ctrl_req_t;
_Static_assert(sizeof(usb_ctrl_req_t) == USB_CTRL_REQ_SIZE, "Size of usb_ctrl_req_t incorrect");
/**
* @brief Bit masks pertaining to the bRequestType field of a setup packet
*/
#define USB_B_REQUEST_TYPE_DIR_OUT (0X00 << 7)
#define USB_B_REQUEST_TYPE_DIR_IN (0x01 << 7)
#define USB_B_REQUEST_TYPE_TYPE_STANDARD (0x00 << 5)
#define USB_B_REQUEST_TYPE_TYPE_CLASS (0x01 << 5)
#define USB_B_REQUEST_TYPE_TYPE_VENDOR (0x02 << 5)
#define USB_B_REQUEST_TYPE_TYPE_RESERVED (0x03 << 5)
#define USB_B_REQUEST_TYPE_TYPE_MASK (0x03 << 5)
#define USB_B_REQUEST_TYPE_RECIP_DEVICE (0x00 << 0)
#define USB_B_REQUEST_TYPE_RECIP_INTERFACE (0x01 << 0)
#define USB_B_REQUEST_TYPE_RECIP_ENDPOINT (0x02 << 0)
#define USB_B_REQUEST_TYPE_RECIP_OTHER (0x03 << 0)
#define USB_B_REQUEST_TYPE_RECIP_MASK (0x1f << 0)
/**
* @brief Bit masks pertaining to the bRequest field of a setup packet
*/
#define USB_B_REQUEST_GET_STATUS 0x00
#define USB_B_REQUEST_CLEAR_FEATURE 0x01
#define USB_B_REQUEST_SET_FEATURE 0x03
#define USB_B_REQUEST_SET_ADDRESS 0x05
#define USB_B_REQUEST_GET_DESCRIPTOR 0x06
#define USB_B_REQUEST_SET_DESCRIPTOR 0x07
#define USB_B_REQUEST_GET_CONFIGURATION 0x08
#define USB_B_REQUEST_SET_CONFIGURATION 0x09
#define USB_B_REQUEST_GET_INTERFACE 0x0A
#define USB_B_REQUEST_SET_INTERFACE 0x0B
#define USB_B_REQUEST_SYNCH_FRAME 0x0C
/**
* @brief Bit masks pertaining to the wValue field of a setup packet
*/
#define USB_W_VALUE_DT_DEVICE 0x01
#define USB_W_VALUE_DT_CONFIG 0x02
#define USB_W_VALUE_DT_STRING 0x03
#define USB_W_VALUE_DT_INTERFACE 0x04
#define USB_W_VALUE_DT_ENDPOINT 0x05
#define USB_W_VALUE_DT_DEVICE_QUALIFIER 0x06
#define USB_W_VALUE_DT_OTHER_SPEED_CONFIG 0x07
#define USB_W_VALUE_DT_INTERFACE_POWER 0x08
/**
* @brief Initializer for a SET_ADDRESS request
*
* Sets the address of a connected device
*/
#define USB_CTRL_REQ_INIT_SET_ADDR(ctrl_req_ptr, addr) ({ \
(ctrl_req_ptr)->bRequestType = USB_B_REQUEST_TYPE_DIR_OUT | USB_B_REQUEST_TYPE_TYPE_STANDARD |USB_B_REQUEST_TYPE_RECIP_DEVICE; \
(ctrl_req_ptr)->bRequest = USB_B_REQUEST_SET_ADDRESS; \
(ctrl_req_ptr)->wValue = (addr); \
(ctrl_req_ptr)->wIndex = 0; \
(ctrl_req_ptr)->wLength = 0; \
})
/**
* @brief Initializer for a request to get a device's device descriptor
*/
#define USB_CTRL_REQ_INIT_GET_DEVC_DESC(ctrl_req_ptr) ({ \
(ctrl_req_ptr)->bRequestType = USB_B_REQUEST_TYPE_DIR_IN | USB_B_REQUEST_TYPE_TYPE_STANDARD | USB_B_REQUEST_TYPE_RECIP_DEVICE; \
(ctrl_req_ptr)->bRequest = USB_B_REQUEST_GET_DESCRIPTOR; \
(ctrl_req_ptr)->wValue = (USB_W_VALUE_DT_DEVICE << 8); \
(ctrl_req_ptr)->wIndex = 0; \
(ctrl_req_ptr)->wLength = 18; \
})
/**
* @brief Initializer for a request to get a device's current configuration number
*/
#define USB_CTRL_REQ_INIT_GET_CONFIG(ctrl_req_ptr) ({ \
(ctrl_req_ptr)->bRequestType = USB_B_REQUEST_TYPE_DIR_IN | USB_B_REQUEST_TYPE_TYPE_STANDARD | USB_B_REQUEST_TYPE_RECIP_DEVICE; \
(ctrl_req_ptr)->bRequest = USB_B_REQUEST_GET_CONFIGURATION; \
(ctrl_req_ptr)->wValue = 0; \
(ctrl_req_ptr)->wIndex = 0; \
(ctrl_req_ptr)->wLength = 1; \
})
/**
* @brief Initializer for a request to get one of the device's current configuration descriptor
*
* - desc_index indicates the configuration's index number
* - Number of bytes of the configuration descriptor to get
*/
#define USB_CTRL_REQ_INIT_GET_CFG_DESC(ctrl_req_ptr, desc_index, desc_len) ({ \
(ctrl_req_ptr)->bRequestType = USB_B_REQUEST_TYPE_DIR_IN | USB_B_REQUEST_TYPE_TYPE_STANDARD | USB_B_REQUEST_TYPE_RECIP_DEVICE; \
(ctrl_req_ptr)->bRequest = USB_B_REQUEST_GET_DESCRIPTOR; \
(ctrl_req_ptr)->wValue = (USB_W_VALUE_DT_CONFIG << 8) | ((desc_index) & 0xFF); \
(ctrl_req_ptr)->wIndex = 0; \
(ctrl_req_ptr)->wLength = (desc_len); \
})
/**
* @brief Initializer for a request to set a device's current configuration number
*/
#define USB_CTRL_REQ_INIT_SET_CONFIG(ctrl_req_ptr, config_num) ({ \
(ctrl_req_ptr)->bRequestType = USB_B_REQUEST_TYPE_DIR_OUT | USB_B_REQUEST_TYPE_TYPE_STANDARD | USB_B_REQUEST_TYPE_RECIP_DEVICE; \
(ctrl_req_ptr)->bRequest = USB_B_REQUEST_SET_CONFIGURATION; \
(ctrl_req_ptr)->wValue = (config_num); \
(ctrl_req_ptr)->wIndex = 0; \
(ctrl_req_ptr)->wLength = 0; \
})
// ---------------------------- Device Descriptor ------------------------------
/**
* @brief Size of a USB device descriptor in bytes
*/
#define USB_DESC_DEV_SIZE 18
/**
* @brief Structure representing a USB device descriptor
*/
typedef union {
struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} USB_DESC_ATTR;
uint8_t val[USB_DESC_DEV_SIZE];
} usb_desc_devc_t;
_Static_assert(sizeof(usb_desc_devc_t) == USB_DESC_DEV_SIZE, "Size of usb_desc_devc_t incorrect");
/**
* @brief Possible base class values of the bDeviceClass field of a USB device descriptor
*/
#define USB_CLASS_PER_INTERFACE 0x00
#define USB_CLASS_AUDIO 0x01
#define USB_CLASS_COMM 0x02
#define USB_CLASS_HID 0x03
#define USB_CLASS_PHYSICAL 0x05
#define USB_CLASS_STILL_IMAGE 0x06
#define USB_CLASS_PRINTER 0x07
#define USB_CLASS_MASS_STORAGE 0x08
#define USB_CLASS_HUB 0x09
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_CSCID 0x0b
#define USB_CLASS_CONTENT_SEC 0x0d
#define USB_CLASS_VIDEO 0x0e
#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
#define USB_CLASS_PERSONAL_HEALTHCARE 0x0f
#define USB_CLASS_AUDIO_VIDEO 0x10
#define USB_CLASS_BILLBOARD 0x11
#define USB_CLASS_USB_TYPE_C_BRIDGE 0x12
#define USB_CLASS_MISC 0xef
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
/**
* @brief Vendor specific subclass code
*/
#define USB_SUBCLASS_VENDOR_SPEC 0xff
// ----------------------- Configuration Descriptor ----------------------------
/**
* @brief Size of a short USB configuration descriptor in bytes
*
* @note The size of a full USB configuration includes all the interface and endpoint
* descriptors of that configuration.
*/
#define USB_DESC_CFG_SIZE 9
/**
* @brief Structure representing a short USB configuration descriptor
*
* @note The full USB configuration includes all the interface and endpoint
* descriptors of that configuration.
*/
typedef union {
struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t bMaxPower;
} USB_DESC_ATTR;
uint8_t val[USB_DESC_CFG_SIZE];
} usb_desc_cfg_t;
_Static_assert(sizeof(usb_desc_cfg_t) == USB_DESC_CFG_SIZE, "Size of usb_desc_cfg_t incorrect");
/**
* @brief Bit masks pertaining to the bmAttributes field of a configuration descriptor
*/
#define USB_BM_ATTRIBUTES_ONE (1 << 7) //Must be set
#define USB_BM_ATTRIBUTES_SELFPOWER (1 << 6) //Self powered
#define USB_BM_ATTRIBUTES_WAKEUP (1 << 5) //Can wakeup
#define USB_BM_ATTRIBUTES_BATTERY (1 << 4) //Battery powered
// ------------------------- Interface Descriptor ------------------------------
/**
* @brief Size of a USB interface descriptor in bytes
*/
#define USB_DESC_INTF_SIZE 9
/**
* @brief Structure representing a USB interface descriptor
*/
typedef union {
struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} USB_DESC_ATTR;
uint8_t val[USB_DESC_INTF_SIZE];
} usb_desc_intf_t;
_Static_assert(sizeof(usb_desc_intf_t) == USB_DESC_INTF_SIZE, "Size of usb_desc_intf_t incorrect");
// ------------------------- Endpoint Descriptor -------------------------------
/**
* @brief Size of a USB endpoint descriptor in bytes
*/
#define USB_DESC_EP_SIZE 7
/**
* @brief Structure representing a USB endp;oint descriptor
*/
typedef union {
struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
} USB_DESC_ATTR;
uint8_t val[USB_DESC_EP_SIZE];
} usb_desc_ep_t;
_Static_assert(sizeof(usb_desc_ep_t) == USB_DESC_EP_SIZE, "Size of usb_desc_ep_t incorrect");
/**
* @brief Bit masks pertaining to the bEndpointAddress field of an endpoint descriptor
*/
#define USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK 0x0f
#define USB_B_ENDPOINT_ADDRESS_EP_DIR_MASK 0x80
/**
* @brief Bit masks pertaining to the bmAttributes field of an endpoint descriptor
*/
#define USB_BM_ATTRIBUTES_XFERTYPE_MASK 0x03
#define USB_BM_ATTRIBUTES_XFER_CONTROL (0 << 0)
#define USB_BM_ATTRIBUTES_XFER_ISOC (1 << 0)
#define USB_BM_ATTRIBUTES_XFER_BULK (2 << 0)
#define USB_BM_ATTRIBUTES_XFER_INT (3 << 0)
#define USB_BM_ATTRIBUTES_SYNCTYPE_MASK 0x0C /* in bmAttributes */
#define USB_BM_ATTRIBUTES_SYNC_NONE (0 << 2)
#define USB_BM_ATTRIBUTES_SYNC_ASYNC (1 << 2)
#define USB_BM_ATTRIBUTES_SYNC_ADAPTIVE (2 << 2)
#define USB_BM_ATTRIBUTES_SYNC_SYNC (3 << 2)
#define USB_BM_ATTRIBUTES_USAGETYPE_MASK 0x30
#define USB_BM_ATTRIBUTES_USAGE_DATA (0 << 4)
#define USB_BM_ATTRIBUTES_USAGE_FEEDBACK (1 << 4)
#define USB_BM_ATTRIBUTES_USAGE_IMPLICIT_FB (2 << 4)
/**
* @brief Macro helpers to get information about an endpoint from its descriptor
*/
#define USB_DESC_EP_GET_XFERTYPE(desc_ptr) ((usb_xfer_type_t) ((desc_ptr)->bmAttributes & USB_BM_ATTRIBUTES_XFERTYPE_MASK))
#define USB_DESC_EP_GET_EP_NUM(desc_ptr) ((desc_ptr)->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK)
#define USB_DESC_EP_GET_EP_DIR(desc_ptr) (((desc_ptr)->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_DIR_MASK) ? 1 : 0)
#define USB_DESC_EP_GET_MPS(desc_ptr) ((desc_ptr)->wMaxPacketSize & 0x7FF)
// --------------------------- String Descriptor -------------------------------
/**
* @brief Size of a short USB string descriptor in bytes
*/
#define USB_DESC_STR_SIZE 4
/**
* @brief Structure representing a USB string descriptor
*/
typedef union {
struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wData[1]; /* UTF-16LE encoded */
} USB_DESC_ATTR;
uint8_t val[USB_DESC_STR_SIZE];
} usb_desc_str_t;
_Static_assert(sizeof(usb_desc_str_t) == USB_DESC_STR_SIZE, "Size of usb_desc_str_t incorrect");
#ifdef __cplusplus
}
#endif

55
tools/sdk/esp32c3/include/log/include/esp_log.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __ESP_LOG_H__
#define __ESP_LOG_H__
@ -48,13 +40,22 @@ typedef enum {
typedef int (*vprintf_like_t)(const char *, va_list);
/**
* @brief Default log level
*
* This is used by the definition of ESP_EARLY_LOGx macros. It is not
* recommended to set this directly, call esp_log_level_set("*", level)
* instead.
*/
extern esp_log_level_t esp_log_default_level;
/**
* @brief Set log level for given tag
*
* If logging for given component has already been enabled, changes previous setting.
*
* Note that this function can not raise log level above the level set using
* CONFIG_LOG_DEFAULT_LEVEL setting in menuconfig.
* CONFIG_LOG_MAXIMUM_LEVEL setting in menuconfig.
*
* To raise log level above the default one for a given file, define
* LOG_LOCAL_LEVEL to one of the ESP_LOG_* values, before including
@ -145,7 +146,7 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
#ifndef LOG_LOCAL_LEVEL
#ifndef BOOTLOADER_BUILD
#define LOG_LOCAL_LEVEL CONFIG_LOG_DEFAULT_LEVEL
#define LOG_LOCAL_LEVEL CONFIG_LOG_MAXIMUM_LEVEL
#else
#define LOG_LOCAL_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
#endif
@ -279,7 +280,7 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
/** @endcond */
/// macro to output logs in startup code, before heap allocator and syscalls have been initialized. log at ``ESP_LOG_ERROR`` level. @see ``printf``,``ESP_LOGE``
/// macro to output logs in startup code, before heap allocator and syscalls have been initialized. log at ``ESP_LOG_ERROR`` level. @see ``printf``,``ESP_LOGE``,``ESP_DRAM_LOGE``
#define ESP_EARLY_LOGE( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_ERROR, E, ##__VA_ARGS__)
/// macro to output logs in startup code at ``ESP_LOG_WARN`` level. @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
#define ESP_EARLY_LOGW( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_WARN, W, ##__VA_ARGS__)
@ -290,8 +291,16 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
/// macro to output logs in startup code at ``ESP_LOG_VERBOSE`` level. @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
#define ESP_EARLY_LOGV( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__)
#ifdef BOOTLOADER_BUILD
#define _ESP_LOG_EARLY_ENABLED(log_level) (LOG_LOCAL_LEVEL >= (log_level))
#else
/* For early log, there is no log tag filtering. So we want to log only if both the LOG_LOCAL_LEVEL and the
currently configured min log level are higher than the log level */
#define _ESP_LOG_EARLY_ENABLED(log_level) (LOG_LOCAL_LEVEL >= (log_level) && esp_log_default_level >= (log_level))
#endif
#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \
if (LOG_LOCAL_LEVEL >= log_level) { \
if (_ESP_LOG_EARLY_ENABLED(log_level)) { \
esp_rom_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \
}} while(0)
@ -303,7 +312,9 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
#define ESP_LOGV( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_VERBOSE, tag, format, ##__VA_ARGS__)
#else
/**
* macro to output logs at ESP_LOG_ERROR level.
* Macro to output logs at ESP_LOG_ERROR level.
*
* @note This macro cannot be used when interrupts are disabled or inside an ISR. @see ``ESP_DRAM_LOGE``.
*
* @param tag tag of the log, which can be used to change the log level by ``esp_log_level_set`` at runtime.
*
@ -359,7 +370,11 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
/**
* @brief Macro to output logs when the cache is disabled. log at ``ESP_LOG_ERROR`` level.
*
* Similar to `ESP_EARLY_LOGE`, the log level cannot be changed by `esp_log_level_set`.
* @note Unlike normal logging macros, it's possible to use this macro when interrupts are
* disabled or inside an ISR.
*
* Similar to @see ``ESP_EARLY_LOGE``, the log level cannot be changed per-tag, however
* esp_log_level_set("*", level) will set the default level which controls these log lines also.
*
* Usage: `ESP_DRAM_LOGE(DRAM_STR("my_tag"), "format", or `ESP_DRAM_LOGE(TAG, "format", ...)`,
* where TAG is a char* that points to a str in the DRAM.
@ -382,7 +397,7 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
#define _ESP_LOG_DRAM_LOG_FORMAT(letter, format) DRAM_STR(#letter " %s: " format "\n")
#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \
if (LOG_LOCAL_LEVEL >= log_level) { \
if (_ESP_LOG_EARLY_ENABLED(log_level)) { \
esp_rom_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \
}} while(0)
/** @endcond */

18
tools/sdk/esp32c3/include/log/include/esp_log_internal.h
View File

@ -1,16 +1,8 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __ESP_LOG_INTERNAL_H__
#define __ESP_LOG_INTERNAL_H__

8
tools/sdk/esp32c3/include/lwip/port/esp32/include/arch/cc.h
View File

@ -39,8 +39,13 @@
#include <assert.h>
#include <stdio.h>
#include "sdkconfig.h"
#include "arch/sys_arch.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef BYTE_ORDER
#define BYTE_ORDER LITTLE_ENDIAN
#endif // BYTE_ORDER
@ -103,5 +108,8 @@ typedef int sys_prot_t;
#endif /* NDEBUG */
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_CC_H__ */

6
tools/sdk/esp32c3/include/lwip/port/esp32/include/lwip_default_hooks.h
View File

@ -42,6 +42,12 @@ lwip_hook_ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest);
#define LWIP_HOOK_IP6_ROUTE lwip_hook_ip6_route
#endif /* CONFIG_LWIP_HOOK_IP6_ROUTE... */
#if defined(CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM) || defined(CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT)
const ip6_addr_t *lwip_hook_nd6_get_gw(struct netif *netif, const ip6_addr_t *dest);
#define LWIP_HOOK_ND6_GET_GW lwip_hook_nd6_get_gw
#endif /* CONFIG_LWIP_HOOK_ND6_GET_GATEWAY... */
#if defined(CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM) || defined(CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT)
int lwip_hook_netconn_external_resolve(const char *name, ip_addr_t *addr, u8_t addrtype, err_t *err);

12
tools/sdk/esp32c3/include/lwip/port/esp32/include/lwipopts.h
View File

@ -249,6 +249,10 @@
*/
#define DHCP_DOES_ARP_CHECK CONFIG_LWIP_DHCP_DOES_ARP_CHECK
/**
* LWIP_DHCP_DISABLE_CLIENT_ID==1: Do not add option 61 (client-id) to DHCP packets
*/
#define ESP_DHCP_DISABLE_CLIENT_ID CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID
/**
* CONFIG_LWIP_DHCP_RESTORE_LAST_IP==1: Last valid IP address obtained from DHCP server
@ -453,6 +457,8 @@
*/
#define LWIP_NETIF_API CONFIG_LWIP_NETIF_API
#define LWIP_NETIF_STATUS_CALLBACK CONFIG_LWIP_NETIF_STATUS_CALLBACK
/*
------------------------------------
---------- LOOPIF options ----------
@ -688,7 +694,7 @@
* Some modems do not support IPV6 addressing in local link and
* the only option available is to disable IPV6 address negotiation.
*/
#define PPP_IPV6_SUPPORT CONFIG_LWIP_PPP_ENABLE_IPV6
#define PPP_IPV6_SUPPORT CONFIG_LWIP_PPP_ENABLE_IPV6
/**
* PPP_NOTIFY_PHASE==1: Support PPP notify phase.
@ -957,6 +963,10 @@
*/
#define LWIP_SOCKET_OFFSET (FD_SETSIZE - CONFIG_LWIP_MAX_SOCKETS)
#define LWIP_IPV6_FORWARD CONFIG_LWIP_IPV6_FORWARD
#define LWIP_IPV6_NUM_ADDRESSES CONFIG_LWIP_IPV6_NUM_ADDRESSES
/* Enable all Espressif-only options */
#define ESP_LWIP 1

24
tools/sdk/esp32c3/include/mbedtls/port/include/mbedtls/esp_config.h
View File

@ -144,6 +144,15 @@
#undef MBEDTLS_SHA512_ALT
#endif
/* MBEDTLS_MDx_ALT to enable ROM MD support
with software fallback.
*/
#ifdef CONFIG_MBEDTLS_ROM_MD5
#define MBEDTLS_MD5_ALT
#else
#undef MBEDTLS_MD5_ALT
#endif
/* The following MPI (bignum) functions have ESP32 hardware support.
For exponential mod, both software and hardware implementation
will be compiled. If CONFIG_MBEDTLS_HARDWARE_MPI is enabled, mod APIs
@ -2451,6 +2460,21 @@
#undef MBEDTLS_THREADING_PTHREAD
#endif
/**
* \def MBEDTLS_NIST_KW_C
*
* Enable AES key wrapping as per NIST
*
* Requires: MBEDTLS_AES_C
*
* Uncomment this to enable aes key wrap.
*/
#ifdef CONFIG_MBEDTLS_NIST_KW_C
#define MBEDTLS_NIST_KW_C
#else
#undef MBEDTLS_NIST_KW_C
#endif
/* \} name SECTION: Module configuration options */
#if defined(TARGET_LIKE_MBED)

154
tools/sdk/esp32c3/include/mbedtls/port/include/md/esp_md.h Normal file
View File

@ -0,0 +1,154 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
#pragma once
#include "esp_rom_md5.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct MD5Context mbedtls_md5_context;
/**
* \brief Initialize MD5 context
*
* \param ctx MD5 context to be initialized
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
int esp_md5_init_ret( mbedtls_md5_context *ctx );
/**
* \brief Clear MD5 context
*
* \param ctx MD5 context to be cleared
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
void esp_md5_free( mbedtls_md5_context *ctx );
/**
* \brief Clone (the state of) an MD5 context
*
* \param dst The destination context
* \param src The context to be cloned
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
void esp_md5_clone( mbedtls_md5_context *dst, const mbedtls_md5_context *src );
/**
* \brief MD5 process buffer
*
* \param ctx MD5 context
* \param input buffer holding the data
* \param ilen length of the input data
*
* \return 0 if successful
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
int esp_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief MD5 final digest
*
* \param ctx MD5 context
* \param output MD5 checksum result
*
* \return 0 if successful
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
int esp_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] );
/**
* \brief MD5 process data block (internal use only)
*
* \param ctx MD5 context
* \param data buffer holding one block of data
*
* \return 0 if successful
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
int esp_md5_process( mbedtls_md5_context *ctx, const unsigned char data[64] );
/**
* \brief MD5 context setup
*
* \deprecated Superseded by mbedtls_md5_starts_ret() in 2.7.0
*
* \param ctx context to be initialized
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
void esp_md5_init( mbedtls_md5_context *ctx );
/**
* \brief MD5 process buffer
*
* \deprecated Superseded by mbedtls_md5_update_ret() in 2.7.0
*
* \param ctx MD5 context
* \param input buffer holding the data
* \param ilen length of the input data
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
void esp_md5_update( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen );
/**
* \brief MD5 final digest
*
* \deprecated Superseded by mbedtls_md5_finish_ret() in 2.7.0
*
* \param ctx MD5 context
* \param output MD5 checksum result
*
* \warning MD5 is considered a weak message digest and its use
* constitutes a security risk. We recommend considering
* stronger message digests instead.
*
*/
void esp_md5_finish( mbedtls_md5_context *ctx, unsigned char output[16] );
#ifdef __cplusplus
}
#endif

50
tools/sdk/esp32c3/include/mbedtls/port/include/md5_alt.h Normal file
View File

@ -0,0 +1,50 @@
/**
* \file md5_alt.h
*
* \brief MD5 block cipher
*
* Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*
*/
#ifndef MD5_ALT_H
#define MD5_ALT_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(MBEDTLS_MD5_ALT)
#include "md/esp_md.h"
#define mbedtls_md5_init esp_md5_init
#define mbedtls_md5_update esp_md5_update
#define mbedtls_md5_finish esp_md5_finish
#define mbedtls_md5_starts_ret esp_md5_init_ret
#define mbedtls_md5_update_ret esp_md5_update_ret
#define mbedtls_md5_finish_ret esp_md5_finish_ret
#define mbedtls_md5_free esp_md5_free
#define mbedtls_md5_clone esp_md5_clone
#define mbedtls_internal_md5_process esp_md5_process
#endif /* MBEDTLS_MD5_ALT */
#ifdef __cplusplus
}
#endif
#endif

7
tools/sdk/esp32c3/include/newlib/platform_include/sys/dirent.h
View File

@ -42,7 +42,12 @@ struct dirent {
#define DT_UNKNOWN 0
#define DT_REG 1
#define DT_DIR 2
char d_name[256]; /*!< zero-terminated file name */
#if __BSD_VISIBLE
#define MAXNAMLEN 255
char d_name[MAXNAMLEN+1]; /*!< zero-terminated file name */
#else
char d_name[256];
#endif
};
DIR* opendir(const char* name);

25
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/brownout_caps.h
View File

@ -1,25 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_BROWNOUT_RESET_SUPPORTED 1
#ifdef __cplusplus
}
#endif

21
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/cpu_caps.h
View File

@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes

25
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/ds_caps.h
View File

@ -1,25 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/** The maximum length of a Digital Signature in bits. */
#define DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define DS_KEY_CHECK_MAX_WAIT_US (1100)

18
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gdma_caps.h
View File

@ -1,18 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_GDMA_GROUPS (1)
#define SOC_GDMA_PAIRS_PER_GROUP (3)

42
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gpio_caps.h
View File

@ -1,42 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (22)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure slept status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
#ifdef __cplusplus
}
#endif

37
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/i2c_caps.h
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@ -1,37 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define I2C_INTR_MASK (0x3ffff) /*!< I2C all interrupt bitmap */
//ESP32-C3 support hardware FSM reset
#define I2C_SUPPORT_HW_FSM_RST (1)
//ESP32-C3 support hardware clear bus
#define I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#ifdef __cplusplus
}
#endif

22
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/i2s_caps.h
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@ -1,22 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_NUM (1)

26
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/ledc_caps.h
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@ -1,26 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
#ifdef __cplusplus
}
#endif

21
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/mpu_caps.h
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@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0

9
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc.h
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@ -122,6 +122,15 @@ set sleep_init default param
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
storing in efuse (based on ATE 5k ECO3 chips)
*/
#define K_RTC_MID_MUL10000 215
#define K_DIG_MID_MUL10000 213
#define V_RTC_MID_MUL10000 10800
#define V_DIG_MID_MUL10000 10860
/**
* @brief Possible main XTAL frequency values.
*

22
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc_caps.h
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@ -1,22 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (RTC_CNTL_CPU_PD_REG_FILE_NUM * (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))

21
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc_io_caps.h
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@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define RTCIO_LL_PIN_FUNC 0

25
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/sigmadelta_caps.h
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@ -1,25 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
#ifdef __cplusplus
}
#endif

18
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc.h
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@ -58,7 +58,7 @@
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_SYS_TIMER_BASE 0x60023000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
@ -67,14 +67,14 @@
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_AES_XTS_BASE 0x600CC000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)

295
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h
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@ -5,85 +5,18 @@
#pragma once
#define SOC_CPU_CORES_NUM 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#include "i2c_caps.h"
#include "mpu_caps.h"
#include "sigmadelta_caps.h"
#include "systimer_caps.h"
#include "uart_caps.h"
#include "brownout_caps.h"
#include "gdma_caps.h"
#include "i2s_caps.h"
#include "rtc_io_caps.h"
#include "soc_caps.h"
#include "cpu_caps.h"
#include "gpio_caps.h"
#include "ledc_caps.h"
#include "spi_caps.h"
#include "uart_caps.h"
#include "rtc_caps.h"
#define SOC_CPU_CORES_NUM 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
/*-------------------------- AES CAPS -----------------------------------------*/
@ -112,6 +45,207 @@
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 8
#define SOC_CPU_WATCHPOINTS_NUM 8
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (22)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
/*-------------------------- MPU CAPS ----------------------------------------*/
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
/*-------------------------- RTC CAPS --------------------------------------*/
#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed
#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 16384
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C3 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
@ -125,13 +259,6 @@
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)

38
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/spi_caps.h
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@ -1,38 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16

1
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/spi_struct.h
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@ -18,7 +18,6 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {

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tools/sdk/esp32c3/include/soc/esp32c3/include/soc/systimer_reg.h
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@ -1,424 +1,567 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYS_TIMER_REG_H_
#define _SOC_SYS_TIMER_REG_H_
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000)
/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating*/
#define SYS_TIMER_CLK_EN (BIT(31))
#define SYS_TIMER_CLK_EN_M (BIT(31))
#define SYS_TIMER_CLK_EN_V 0x1
#define SYS_TIMER_CLK_EN_S 31
/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: timer unit0 work enable*/
#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30
/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer unit1 work enable*/
#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29
/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core0 stalled*/
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28))
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core1 stalled*/
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27))
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core0 stalled*/
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26))
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core1 stalled*/
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25))
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: target0 work enable*/
#define SYS_TIMER_TARGET0_WORK_EN (BIT(24))
#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24))
#define SYS_TIMER_TARGET0_WORK_EN_V 0x1
#define SYS_TIMER_TARGET0_WORK_EN_S 24
/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: target1 work enable*/
#define SYS_TIMER_TARGET1_WORK_EN (BIT(23))
#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23))
#define SYS_TIMER_TARGET1_WORK_EN_V 0x1
#define SYS_TIMER_TARGET1_WORK_EN_S 23
/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: target2 work enable*/
#define SYS_TIMER_TARGET2_WORK_EN (BIT(22))
#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22))
#define SYS_TIMER_TARGET2_WORK_EN_V 0x1
#define SYS_TIMER_TARGET2_WORK_EN_S 22
/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: systimer clock force on*/
#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0))
#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1
#define SYS_TIMER_SYSTIMER_CLK_FO_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004)
/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer_unit0*/
#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1
#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30
/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_CONF_REG register
* SYSTIMER_CONF.
*/
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
* systimer clock force on
*/
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET2_WORK_EN_S 22
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET1_WORK_EN_S 23
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET0_WORK_EN_S 24
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
#define SYSTIMER_CLK_EN_V 0x00000001
#define SYSTIMER_CLK_EN_S 31
#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008)
/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer unit1*/
#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1
#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30
/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer value is sync and valid*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_UNIT0_OP_REG register
* SYSTIMER_UNIT0_OP.
*/
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* reg_timer_unit0_value_valid
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C)
/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit0 load high 32 bit*/
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S))
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0
/** SYSTIMER_UNIT1_OP_REG register
* SYSTIMER_UNIT1_OP.
*/
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010)
/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit0 load low 32 bit*/
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S))
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0
/** SYSTIMER_UNIT0_LOAD_HI_REG register
* SYSTIMER_UNIT0_LOAD_HI.
*/
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 32 bit
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014)
/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit1 load high 32 bit*/
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S))
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0
/** SYSTIMER_UNIT0_LOAD_LO_REG register
* SYSTIMER_UNIT0_LOAD_LO.
*/
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bit
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018)
/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit1 load low 32 bit*/
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S))
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0
/** SYSTIMER_UNIT1_LOAD_HI_REG register
* SYSTIMER_UNIT1_LOAD_HI.
*/
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 32 bit
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C)
/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget0 high 32 bit*/
#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S))
#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET0_HI_S 0
/** SYSTIMER_UNIT1_LOAD_LO_REG register
* SYSTIMER_UNIT1_LOAD_LO.
*/
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bit
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020)
/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget0 low 32 bit*/
#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S))
#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET0_LO_S 0
/** SYSTIMER_TARGET0_HI_REG register
* SYSTIMER_TARGET0_HI.
*/
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 32 bit
*/
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_TARGET0_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024)
/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget1 high 32 bit*/
#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S))
#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET1_HI_S 0
/** SYSTIMER_TARGET0_LO_REG register
* SYSTIMER_TARGET0_LO.
*/
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bit
*/
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET0_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028)
/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget1 low 32 bit*/
#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S))
#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET1_LO_S 0
/** SYSTIMER_TARGET1_HI_REG register
* SYSTIMER_TARGET1_HI.
*/
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 32 bit
*/
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_TARGET1_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C)
/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget2 high 32 bit*/
#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S))
#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET2_HI_S 0
/** SYSTIMER_TARGET1_LO_REG register
* SYSTIMER_TARGET1_LO.
*/
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bit
*/
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET1_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030)
/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget2 low 32 bit*/
#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S))
#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET2_LO_S 0
/** SYSTIMER_TARGET2_HI_REG register
* SYSTIMER_TARGET2_HI.
*/
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 32 bit
*/
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_TARGET2_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034)
/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target0 to period mode*/
#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target0 period*/
#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S))
#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET2_LO_REG register
* SYSTIMER_TARGET2_LO.
*/
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bit
*/
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET2_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038)
/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target1 to period mode*/
#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target1 period*/
#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S))
#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET0_CONF_REG register
* SYSTIMER_TARGET0_CONF.
*/
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF
#define SYSTIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C)
/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target2 to period mode*/
#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target2 period*/
#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S))
#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET1_CONF_REG register
* SYSTIMER_TARGET1_CONF.
*/
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF
#define SYSTIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040)
/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 32bit*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S))
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0
/** SYSTIMER_TARGET2_CONF_REG register
* SYSTIMER_TARGET2_CONF.
*/
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF
#define SYSTIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044)
/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bit*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S))
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0
/** SYSTIMER_UNIT0_VALUE_HI_REG register
* SYSTIMER_UNIT0_VALUE_HI.
*/
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 32bit
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048)
/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 32bit*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S))
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0
/** SYSTIMER_UNIT0_VALUE_LO_REG register
* SYSTIMER_UNIT0_VALUE_LO.
*/
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bit
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C)
/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bit*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S))
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0
/** SYSTIMER_UNIT1_VALUE_HI_REG register
* SYSTIMER_UNIT1_VALUE_HI.
*/
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 32bit
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050)
/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp0 load value*/
#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP0_LOAD_S 0
/** SYSTIMER_UNIT1_VALUE_LO_REG register
* SYSTIMER_UNIT1_VALUE_LO.
*/
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bit
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054)
/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp1 load value*/
#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP1_LOAD_S 0
/** SYSTIMER_COMP0_LOAD_REG register
* SYSTIMER_COMP0_LOAD.
*/
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
* timer comp0 load value
*/
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058)
/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp2 load value*/
#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP2_LOAD_S 0
/** SYSTIMER_COMP1_LOAD_REG register
* SYSTIMER_COMP1_LOAD.
*/
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
* timer comp1 load value
*/
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C)
/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit0 load value*/
#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1
#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0
/** SYSTIMER_COMP2_LOAD_REG register
* SYSTIMER_COMP2_LOAD.
*/
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
* timer comp2 load value
*/
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060)
/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit1 load value*/
#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1
#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0
/** SYSTIMER_UNIT0_LOAD_REG register
* SYSTIMER_UNIT0_LOAD.
*/
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
* timer unit0 load value
*/
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064)
/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 enable*/
#define SYS_TIMER_TARGET2_INT_ENA (BIT(2))
#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_ENA_V 0x1
#define SYS_TIMER_TARGET2_INT_ENA_S 2
/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 enable*/
#define SYS_TIMER_TARGET1_INT_ENA (BIT(1))
#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_ENA_V 0x1
#define SYS_TIMER_TARGET1_INT_ENA_S 1
/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 enable*/
#define SYS_TIMER_TARGET0_INT_ENA (BIT(0))
#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_ENA_V 0x1
#define SYS_TIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_UNIT1_LOAD_REG register
* SYSTIMER_UNIT1_LOAD.
*/
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
* timer unit1 load value
*/
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068)
/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 raw*/
#define SYS_TIMER_TARGET2_INT_RAW (BIT(2))
#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_RAW_V 0x1
#define SYS_TIMER_TARGET2_INT_RAW_S 2
/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 raw*/
#define SYS_TIMER_TARGET1_INT_RAW (BIT(1))
#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_RAW_V 0x1
#define SYS_TIMER_TARGET1_INT_RAW_S 1
/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 raw*/
#define SYS_TIMER_TARGET0_INT_RAW (BIT(0))
#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_RAW_V 0x1
#define SYS_TIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_INT_ENA_REG register
* SYSTIMER_INT_ENA.
*/
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET1_INT_ENA_S 1
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET2_INT_ENA_S 2
#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c)
/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 clear*/
#define SYS_TIMER_TARGET2_INT_CLR (BIT(2))
#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_CLR_V 0x1
#define SYS_TIMER_TARGET2_INT_CLR_S 2
/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 clear*/
#define SYS_TIMER_TARGET1_INT_CLR (BIT(1))
#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_CLR_V 0x1
#define SYS_TIMER_TARGET1_INT_CLR_S 1
/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 clear*/
#define SYS_TIMER_TARGET0_INT_CLR (BIT(0))
#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_CLR_V 0x1
#define SYS_TIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_INT_RAW_REG register
* SYSTIMER_INT_RAW.
*/
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET1_INT_RAW_S 1
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET2_INT_RAW_S 2
#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070)
/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TARGET2_INT_ST (BIT(2))
#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_ST_V 0x1
#define SYS_TIMER_TARGET2_INT_ST_S 2
/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TARGET1_INT_ST (BIT(1))
#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_ST_V 0x1
#define SYS_TIMER_TARGET1_INT_ST_S 1
/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TARGET0_INT_ST (BIT(0))
#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_ST_V 0x1
#define SYS_TIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_INT_CLR_REG register
* SYSTIMER_INT_CLR.
*/
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET1_INT_CLR_S 1
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET2_INT_CLR_S 2
#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc)
/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2006171 ; */
/*description: */
#define SYS_TIMER_DATE 0xFFFFFFFF
#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S))
#define SYS_TIMER_DATE_V 0xFFFFFFFF
#define SYS_TIMER_DATE_S 0
/** SYSTIMER_INT_ST_REG register
* SYSTIMER_INT_ST.
*/
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
* reg_target0_int_st
*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001
#define SYSTIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
* reg_target1_int_st
*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001
#define SYSTIMER_TARGET1_INT_ST_S 1
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
* reg_target2_int_st
*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001
#define SYSTIMER_TARGET2_INT_ST_S 2
/** SYSTIMER_DATE_REG register
* SYSTIMER_DATE.
*/
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
* reg_date
*/
#define SYSTIMER_DATE 0xFFFFFFFF
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
#define SYSTIMER_DATE_V 0xFFFFFFFF
#define SYSTIMER_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYS_TIMER_REG_H_ */

559
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/systimer_struct.h
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@ -1,251 +1,370 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYS_TIMER_STRUCT_H_
#define _SOC_SYS_TIMER_STRUCT_H_
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
/** Configuration Register */
/** Type of conf register
* SYSTIMER_CONF.
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
* systimer clock force on
*/
uint32_t systimer_clk_fo: 1;
uint32_t reserved_1: 21;
/** target2_work_en : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
uint32_t target2_work_en: 1;
/** target1_work_en : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
uint32_t target1_work_en: 1;
/** target0_work_en : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
uint32_t target0_work_en: 1;
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
uint32_t timer_unit1_core1_stall_en: 1;
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
uint32_t timer_unit1_core0_stall_en: 1;
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
uint32_t timer_unit0_core1_stall_en: 1;
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
uint32_t timer_unit0_core0_stall_en: 1;
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
uint32_t timer_unit1_work_en: 1;
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
uint32_t timer_unit0_work_en: 1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
uint32_t clk_en: 1;
};
uint32_t val;
} systimer_conf_reg_t;
/** Type of unit_op register
* SYSTIMER_UNIT_OP.
*/
typedef union {
struct {
uint32_t reserved_0: 29;
/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
* reg_timer_unit0_value_valid
*/
uint32_t timer_unit_value_valid: 1;
/** timer_unit_update : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
uint32_t timer_unit_update: 1;
};
uint32_t val;
} systimer_unit_op_reg_t;
/** Type of unit_load register
* SYSTIMER_UNIT_LOAD
*/
typedef struct {
union {
struct {
uint32_t systimer_clk_fo: 1; /*systimer clock force on*/
uint32_t reserved1: 21;
uint32_t target2_work_en: 1; /*target2 work enable*/
uint32_t target1_work_en: 1; /*target1 work enable*/
uint32_t target0_work_en: 1; /*target0 work enable*/
uint32_t timer_unit1_core1_stall_en: 1; /*If timer unit1 is stalled when core1 stalled*/
uint32_t timer_unit1_core0_stall_en: 1; /*If timer unit1 is stalled when core0 stalled*/
uint32_t timer_unit0_core1_stall_en: 1; /*If timer unit0 is stalled when core1 stalled*/
uint32_t timer_unit0_core0_stall_en: 1; /*If timer unit0 is stalled when core0 stalled*/
uint32_t timer_unit1_work_en: 1; /*timer unit1 work enable*/
uint32_t timer_unit0_work_en: 1; /*timer unit0 work enable*/
uint32_t clk_en: 1; /*register file clk gating*/
/** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
* timer unit load high 32 bit
*/
uint32_t timer_unit_load_hi: 20;
};
uint32_t val;
} systimer_conf;
} hi;
union {
struct {
uint32_t reserved0: 29;
uint32_t timer_unit0_value_valid: 1;
uint32_t timer_unit0_update: 1; /*update timer_unit0*/
uint32_t reserved31: 1;
/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
* timer unit load low 32 bit
*/
uint32_t timer_unit_load_lo: 32;
};
uint32_t val;
} systimer_unit0_op;
} lo;
} systimer_unit_load_val_reg_t;
/** Type of target register
* SYSTIMER_TARGET.
*/
typedef struct {
union {
struct {
uint32_t reserved0: 29;
uint32_t timer_unit1_value_valid: 1; /*timer value is sync and valid*/
uint32_t timer_unit1_update: 1; /*update timer unit1*/
uint32_t reserved31: 1;
/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
* timer target high 32 bit
*/
uint32_t timer_target_hi: 20;
};
uint32_t val;
} systimer_unit1_op;
} hi;
union {
struct {
uint32_t timer_unit0_load_hi:20; /*timer unit0 load high 32 bit*/
uint32_t reserved20: 12;
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
* timer target low 32 bit
*/
uint32_t timer_target_lo: 32;
};
uint32_t val;
} systimer_unit0_load_hi;
uint32_t systimer_unit0_load_lo; /**/
} lo;
} systimer_target_val_reg_t;
/** Type of target_conf register
* SYSTIMER_TARGET_CONF.
*/
typedef union {
struct {
/** target_period : R/W; bitpos: [25:0]; default: 0;
* target period
*/
uint32_t target_period: 26;
uint32_t reserved_26: 4;
/** target_period_mode : R/W; bitpos: [30]; default: 0;
* Set target to period mode
*/
uint32_t target_period_mode: 1;
/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
uint32_t target_timer_unit_sel: 1;
};
uint32_t val;
} systimer_target_conf_reg_t;
/** Type of unit_value_hi register
* SYSTIMER_UNIT_VALUE_HI.
*/
typedef struct {
union {
struct {
uint32_t timer_unit1_load_hi:20; /*timer unit1 load high 32 bit*/
uint32_t reserved20: 12;
/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
* timer read value high 20bit
*/
uint32_t timer_unit_value_hi: 20;
};
uint32_t val;
} systimer_unit1_load_hi;
uint32_t systimer_unit1_load_lo; /**/
} hi;
union {
struct {
uint32_t timer_target0_hi:20; /*timer taget0 high 32 bit*/
uint32_t reserved20: 12;
/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bit
*/
uint32_t timer_unit_value_lo: 32;
};
uint32_t val;
} systimer_target0_hi;
uint32_t systimer_target0_lo; /**/
union {
struct {
uint32_t timer_target1_hi:20; /*timer taget1 high 32 bit*/
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_target1_hi;
uint32_t systimer_target1_lo; /**/
union {
struct {
uint32_t timer_target2_hi:20; /*timer taget2 high 32 bit*/
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_target2_hi;
uint32_t systimer_target2_lo; /**/
union {
struct {
uint32_t target0_period: 26; /*target0 period*/
uint32_t reserved26: 4;
uint32_t target0_period_mode: 1; /*Set target0 to period mode*/
uint32_t target0_timer_unit_sel: 1; /*select which unit to compare*/
};
uint32_t val;
} systimer_target0_conf;
union {
struct {
uint32_t target1_period: 26; /*target1 period*/
uint32_t reserved26: 4;
uint32_t target1_period_mode: 1; /*Set target1 to period mode*/
uint32_t target1_timer_unit_sel: 1; /*select which unit to compare*/
};
uint32_t val;
} systimer_target1_conf;
union {
struct {
uint32_t target2_period: 26; /*target2 period*/
uint32_t reserved26: 4;
uint32_t target2_period_mode: 1; /*Set target2 to period mode*/
uint32_t target2_timer_unit_sel: 1; /*select which unit to compare*/
};
uint32_t val;
} systimer_target2_conf;
union {
struct {
uint32_t timer_unit0_value_hi:20; /*timer read value high 32bit*/
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_unit0_value_hi;
uint32_t systimer_unit0_value_lo; /**/
union {
struct {
uint32_t timer_unit1_value_hi:20; /*timer read value high 32bit*/
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_unit1_value_hi;
uint32_t systimer_unit1_value_lo; /**/
union {
struct {
uint32_t timer_comp0_load: 1; /*timer comp0 load value*/
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp0_load;
union {
struct {
uint32_t timer_comp1_load: 1; /*timer comp1 load value*/
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp1_load;
union {
struct {
uint32_t timer_comp2_load: 1; /*timer comp2 load value*/
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp2_load;
union {
struct {
uint32_t timer_unit0_load: 1; /*timer unit0 load value*/
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_unit0_load;
union {
struct {
uint32_t timer_unit1_load: 1; /*timer unit1 load value*/
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_unit1_load;
union {
struct {
uint32_t target0: 1; /*interupt0 enable*/
uint32_t target1: 1; /*interupt1 enable*/
uint32_t target2: 1; /*interupt2 enable*/
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena;
union {
struct {
uint32_t target0: 1; /*interupt0 raw*/
uint32_t target1: 1; /*interupt1 raw*/
uint32_t target2: 1; /*interupt2 raw*/
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw;
union {
struct {
uint32_t target0: 1; /*interupt0 clear*/
uint32_t target1: 1; /*interupt1 clear*/
uint32_t target2: 1; /*interupt2 clear*/
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr;
union {
struct {
uint32_t target0: 1;
uint32_t target1: 1;
uint32_t target2: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_st;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t systimer_date; /**/
} sys_timer_dev_t;
extern sys_timer_dev_t SYS_TIMER;
} lo;
} systimer_unit_value_reg_t;
/** Type of comp_load register
* SYSTIMER_COMP_LOAD.
*/
typedef union {
struct {
/** timer_comp_load : WT; bitpos: [0]; default: 0;
* timer comp load value
*/
uint32_t timer_comp_load: 1;
};
uint32_t val;
} systimer_comp_load_reg_t;
/** Type of unit_load register
* SYSTIMER_UNIT_LOAD.
*/
typedef union {
struct {
/** timer_unit_load : WT; bitpos: [0]; default: 0;
* timer unit load value
*/
uint32_t timer_unit_load: 1;
};
uint32_t val;
} systimer_unit_load_reg_t;
/** Interrupt Register */
/** Type of int_ena register
* SYSTIMER_INT_ENA.
*/
typedef union {
struct {
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
uint32_t target0_int_ena: 1;
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
uint32_t target1_int_ena: 1;
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
uint32_t target2_int_ena: 1;
};
uint32_t val;
} systimer_int_ena_reg_t;
/** Type of int_raw register
* SYSTIMER_INT_RAW.
*/
typedef union {
struct {
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
uint32_t target0_int_raw: 1;
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
uint32_t target1_int_raw: 1;
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
uint32_t target2_int_raw: 1;
};
uint32_t val;
} systimer_int_raw_reg_t;
/** Type of int_clr register
* SYSTIMER_INT_CLR.
*/
typedef union {
struct {
/** target0_int_clr : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
uint32_t target0_int_clr: 1;
/** target1_int_clr : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
uint32_t target1_int_clr: 1;
/** target2_int_clr : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
uint32_t target2_int_clr: 1;
};
uint32_t val;
} systimer_int_clr_reg_t;
/** Type of int_st register
* SYSTIMER_INT_ST.
*/
typedef union {
struct {
/** target0_int_st : RO; bitpos: [0]; default: 0;
* reg_target0_int_st
*/
uint32_t target0_int_st: 1;
/** target1_int_st : RO; bitpos: [1]; default: 0;
* reg_target1_int_st
*/
uint32_t target1_int_st: 1;
/** target2_int_st : RO; bitpos: [2]; default: 0;
* reg_target2_int_st
*/
uint32_t target2_int_st: 1;
};
uint32_t val;
} systimer_int_st_reg_t;
/** Version Register */
/** Type of date register
* SYSTIMER_DATE.
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 33579377;
* reg_date
*/
uint32_t date: 32;
};
uint32_t val;
} systimer_date_reg_t;
typedef struct {
volatile systimer_conf_reg_t conf;
volatile systimer_unit_op_reg_t unit_op[2];
volatile systimer_unit_load_val_reg_t unit_load_val[2];
volatile systimer_target_val_reg_t target_val[3];
volatile systimer_target_conf_reg_t target_conf[3];
volatile systimer_unit_value_reg_t unit_val[2];
volatile systimer_comp_load_reg_t comp_load[3];
volatile systimer_unit_load_reg_t unit_load[2];
volatile systimer_int_ena_reg_t int_ena;
volatile systimer_int_raw_reg_t int_raw;
volatile systimer_int_clr_reg_t int_clr;
volatile systimer_int_st_reg_t int_st;
uint32_t reserved_074;
uint32_t reserved_078;
uint32_t reserved_07c;
uint32_t reserved_080;
uint32_t reserved_084;
uint32_t reserved_088;
uint32_t reserved_08c;
uint32_t reserved_090;
uint32_t reserved_094;
uint32_t reserved_098;
uint32_t reserved_09c;
uint32_t reserved_0a0;
uint32_t reserved_0a4;
uint32_t reserved_0a8;
uint32_t reserved_0ac;
uint32_t reserved_0b0;
uint32_t reserved_0b4;
uint32_t reserved_0b8;
uint32_t reserved_0bc;
uint32_t reserved_0c0;
uint32_t reserved_0c4;
uint32_t reserved_0c8;
uint32_t reserved_0cc;
uint32_t reserved_0d0;
uint32_t reserved_0d4;
uint32_t reserved_0d8;
uint32_t reserved_0dc;
uint32_t reserved_0e0;
uint32_t reserved_0e4;
uint32_t reserved_0e8;
uint32_t reserved_0ec;
uint32_t reserved_0f0;
uint32_t reserved_0f4;
uint32_t reserved_0f8;
volatile systimer_date_reg_t date;
} systimer_dev_t;
extern systimer_dev_t SYSTIMER;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SYS_TIMER_STRUCT_H_ */

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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
// ESP32-C3 have 2 UART
#define SOC_UART_NUM (2)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define UART_FSM_IDLE (0x0)
#define UART_FSM_TX_WAIT_SEND (0xf)
#ifdef __cplusplus
}
#endif

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/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Configuration Registers */
/** USB_SERIAL_JTAG_EP1_REG register
* USB_SERIAL_JTAG_EP1_REG.
*/
#define USB_SERIAL_JTAG_EP1_REG (SOC_DPORT_USB_BASE + 0x0)
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field.
* When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write
* data (up to 64 bytes) into UART Tx FIFO. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
* know how many data is received, then read that amount of data from UART
* Rx
* FIFO.
*/
#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF
#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FF
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
/** USB_SERIAL_JTAG_CONF0_REG register
* USB_SERIAL_JTAG_CONF0_REG.
*/
#define USB_SERIAL_JTAG_CONF0_REG (SOC_DPORT_USB_BASE + 0x18)
/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
* PHY
*/
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001
#define USB_SERIAL_JTAG_PHY_SEL_S 0
/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D-
* exchange
*/
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
* USB D+ D-
* exchange
*/
#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001
#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
* Control single-end input high threshold. 1.76V to 2V, step
* 80mV
*/
#define USB_SERIAL_JTAG_VREFL 0x00000003
#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
#define USB_SERIAL_JTAG_VREFL_V 0x00000003
#define USB_SERIAL_JTAG_VREFL_S 3
/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
* Control single-end input low threshold. 0.8V to 1.04V, step
* 80mV
*/
#define USB_SERIAL_JTAG_VREFH 0x00000003
#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
#define USB_SERIAL_JTAG_VREFH_V 0x00000003
#define USB_SERIAL_JTAG_VREFH_S 5
/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
* Enable software control input
* threshold
*/
#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001
#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup
* pulldown
*/
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull
* up.
*/
#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001
#define USB_SERIAL_JTAG_DP_PULLUP_S 9
/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull
* down.
*/
#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001
#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
* Control USB D- pull
* up.
*/
#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001
#define USB_SERIAL_JTAG_DM_PULLUP_S 11
/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
* Control USB D- pull
* down.
*/
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
* Control pull up
* value.
*/
#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001
#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
* Enable USB pad
* function.
*/
#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
/** USB_SERIAL_JTAG_TEST_REG register
* USB_SERIAL_JTAG_TEST_REG.
*/
#define USB_SERIAL_JTAG_TEST_REG (SOC_DPORT_USB_BASE + 0x1c)
/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
* Enable test of the USB
* pad
*/
#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001
#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
* USB pad oen in
* test
*/
#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001
#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in
* test
*/
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
* USB D- tx value in
* test
*/
#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
/** USB_SERIAL_JTAG_MISC_CONF_REG register
* USB_SERIAL_JTAG_MISC_CONF_REG.
*/
#define USB_SERIAL_JTAG_MISC_CONF_REG (SOC_DPORT_USB_BASE + 0x44)
/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when
* application writes
* registers.
*/
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_CLK_EN_S 0
/** USB_SERIAL_JTAG_MEM_CONF_REG register
* USB_SERIAL_JTAG_MEM_CONF_REG.
*/
#define USB_SERIAL_JTAG_MEM_CONF_REG (SOC_DPORT_USB_BASE + 0x48)
/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
* 1: power down usb
* memory.
*/
#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001
#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb
* memory.
*/
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
/** Status Registers */
/** USB_SERIAL_JTAG_EP1_CONF_REG register
* USB_SERIAL_JTAG_EP1_CONF_REG.
*/
#define USB_SERIAL_JTAG_EP1_CONF_REG (SOC_DPORT_USB_BASE + 0x4)
/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
* This bit then stays 0 until data in UART Tx FIFO is read by the USB
* Host.
*/
#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001
#define USB_SERIAL_JTAG_WR_DONE_S 0
/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and data can be written into
* in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
* data is sent to the USB
* Host.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx
* FIFO.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
/** USB_SERIAL_JTAG_JFIFO_ST_REG register
* USB_SERIAL_JTAG_JFIFO_ST_REG.
*/
#define USB_SERIAL_JTAG_JFIFO_ST_REG (SOC_DPORT_USB_BASE + 0x20)
/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
* JTAG in fifo
* counter.
*/
#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003
#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is
* empty.
*/
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is
* full.
*/
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
* JTAT out fifo
* counter.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is
* empty.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is
* full.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in
* fifo.
*/
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out
* fifo.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
/** USB_SERIAL_JTAG_FRAM_NUM_REG register
* USB_SERIAL_JTAG_FRAM_NUM_REG.
*/
#define USB_SERIAL_JTAG_FRAM_NUM_REG (SOC_DPORT_USB_BASE + 0x24)
/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
* Frame index of received SOF
* frame.
*/
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FF
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
* USB_SERIAL_JTAG_IN_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x28)
/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
* USB_SERIAL_JTAG_IN_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x2c)
/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
* USB_SERIAL_JTAG_IN_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x30)
/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
* USB_SERIAL_JTAG_IN_EP3_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (SOC_DPORT_USB_BASE + 0x34)
/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
* USB_SERIAL_JTAG_OUT_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x38)
/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
* 0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of OUT endpoint 0. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
* EP0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of OUT endpoint
* 0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
* USB_SERIAL_JTAG_OUT_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x3c)
/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
* 1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003
#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of OUT endpoint 1. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
* EP1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of OUT endpoint
* 1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is
* received.
*/
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
* USB_SERIAL_JTAG_OUT_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x40)
/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
* 2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003
#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of OUT endpoint 2. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
* EP2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of OUT endpoint
* 2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
/** Interrupt Registers */
/** USB_SERIAL_JTAG_INT_RAW_REG register
* USB_SERIAL_JTAG_INT_RAW_REG.
*/
#define USB_SERIAL_JTAG_INT_RAW_REG (SOC_DPORT_USB_BASE + 0x8)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when a flush command is
* received for IN endpoint 2 of
* JTAG.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when a SOF frame is
* received.
*/
#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when the Serial Port OUT
* Endpoint received one
* packet.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when the Serial Port IN
* Endpoint is
* empty.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when a PID error is
* detected.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when a CRC5 error is
* detected.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when a CRC16 error is
* detected.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when a bit stuffing error is
* detected.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when an IN token for IN
* endpoint 1 is
* received.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when a USB bus reset is
* detected.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received
* packet with zero
* payload.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received
* packet with zero
* payload.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
/** USB_SERIAL_JTAG_INT_ST_REG register
* USB_SERIAL_JTAG_INT_ST_REG.
*/
#define USB_SERIAL_JTAG_INT_ST_REG (SOC_DPORT_USB_BASE + 0xc)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
/** USB_SERIAL_JTAG_INT_ENA_REG register
* USB_SERIAL_JTAG_INT_ENA_REG.
*/
#define USB_SERIAL_JTAG_INT_ENA_REG (SOC_DPORT_USB_BASE + 0x10)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
/** USB_SERIAL_JTAG_INT_CLR_REG register
* USB_SERIAL_JTAG_INT_CLR_REG.
*/
#define USB_SERIAL_JTAG_INT_CLR_REG (SOC_DPORT_USB_BASE + 0x14)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
/** Version Registers */
/** USB_SERIAL_JTAG_DATE_REG register
* USB_SERIAL_JTAG_DATE_REG.
*/
#define USB_SERIAL_JTAG_DATE_REG (SOC_DPORT_USB_BASE + 0x80)
/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
* register
* version.
*/
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF
#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF
#define USB_SERIAL_JTAG_DATE_S 0
#ifdef __cplusplus
}
#endif

263
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/usb_serial_jtag_struct.h Normal file
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@ -0,0 +1,263 @@
// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t rdwr_byte : 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} ep1;
union {
struct {
uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done. This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/
uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/
uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} ep1_conf;
union {
struct {
uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when a SOF frame is received.*/
uint32_t serial_out_recv_pkt_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/
uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/
uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when a PID error is detected.*/
uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/
uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/
uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/
uint32_t in_token_rec_in_ep1_int_raw : 1; /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/
uint32_t out_ep1_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/
uint32_t out_ep2_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/
uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t phy_sel : 1; /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/
uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/
uint32_t exchg_pins : 1; /*USB D+ D- exchange*/
uint32_t vrefh : 2; /*Control single-end input high threshold. 1.76V to 2V, step 80mV */
uint32_t vrefl : 2; /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/
uint32_t vref_override : 1; /*Enable software control input threshold*/
uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/
uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/
uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/
uint32_t dm_pullup : 1; /*Control USB D- pull up.*/
uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/
uint32_t pullup_value : 1; /*Control pull up value.*/
uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/
uint32_t reserved15 : 17;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t test_enable : 1; /*Enable test of the USB pad*/
uint32_t test_usb_oe : 1; /*USB pad oen in test*/
uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/
uint32_t test_tx_dm : 1; /*USB D- tx value in test*/
uint32_t reserved4 : 28;
};
uint32_t val;
} test;
union {
struct {
uint32_t in_fifo_cnt : 2; /*JTAG in fifo counter.*/
uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/
uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/
uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/
uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/
uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/
uint32_t reserved10 : 22;
};
uint32_t val;
} jfifo_st;
union {
struct {
uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/
uint32_t reserved11 : 21;
};
uint32_t val;
} fram_num;
union {
struct {
uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/
uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep0_st;
union {
struct {
uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/
uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/
uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep1_st;
union {
struct {
uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/
uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/
uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep2_st;
union {
struct {
uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/
uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/
uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep3_st;
union {
struct {
uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/
uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */
uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} out_ep0_st;
union {
struct {
uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/
uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} out_ep1_st;
union {
struct {
uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/
uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} out_ep2_st;
union {
struct {
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
uint32_t reserved1 : 31;
};
uint32_t val;
} misc_conf;
union {
struct {
uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/
uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/
uint32_t reserved2 : 30;
};
uint32_t val;
} mem_conf;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t date;
} usb_serial_jtag_dev_t;
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */

3
tools/sdk/esp32c3/include/soc/include/soc/gdma_periph.h
View File

@ -25,7 +25,8 @@ typedef struct {
struct {
const periph_module_t module;
struct {
const int irq_id;
const int rx_irq_id;
const int tx_irq_id;
} pairs[SOC_GDMA_PAIRS_PER_GROUP];
} groups[SOC_GDMA_GROUPS];
} gdma_signal_conn_t;

4
tools/sdk/esp32c3/include/soc/include/soc/lcd_periph.h
View File

@ -25,7 +25,7 @@ typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_LCD_MAX_DATA_WIDTH];
const int data_sigs[SOC_LCD_I80_BUS_WIDTH];
const int cs_sig;
const int dc_sig;
const int wr_sig;
@ -33,7 +33,7 @@ typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_LCD_MAX_DATA_WIDTH];
const int data_sigs[SOC_LCD_RGB_DATA_WIDTH];
const int hsync_sig;
const int vsync_sig;
const int pclk_sig;

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