mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-06-29 20:10:59 +02:00
IDF master c13afea63 (#5214)
esp-dsp: master 7cc5073 esp-face: master 420fc7e esp-rainmaker: f1b82c7 esp32-camera: master 6f8489e esp_littlefs: master b58f00c
This commit is contained in:
Me No Dev
GitHub
@ -113,6 +113,9 @@ extern "C" {
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#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
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#define RTC_CNTL_SCK_DCAP_DEFAULT 255
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#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP (0xFF)
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#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT (0x10)
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/*
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set sleep_init default param
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*/
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@ -149,7 +149,7 @@
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/*-------------------------- MPU CAPS ----------------------------------------*/
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//TODO: correct the caller and remove unsupported lines
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#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
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#define SOC_MPU_REGIONS_MAX_NUM 8
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#define SOC_MPU_REGION_RO_SUPPORTED 0
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#define SOC_MPU_REGION_WO_SUPPORTED 0
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@ -210,10 +210,9 @@
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#define SOC_MEMSPI_IS_INDEPENDENT 1
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/*-------------------------- SYS TIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
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#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
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#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part
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@ -291,6 +290,9 @@
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#define SOC_AES_SUPPORT_DMA (1)
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#define SOC_AES_SUPPORT_GCM (1)
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/*-------------------------- Flash Encryption CAPS----------------------------*/
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#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
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/* Has "crypto DMA", which is shared with SHA */
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#define SOC_AES_CRYPTO_DMA (1)
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@ -1,16 +1,17 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <stdint.h>
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@ -38,7 +39,6 @@ extern "C" {
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#define SYSTIMER_CLK_EN_V 0x00000001
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#define SYSTIMER_CLK_EN_S 31
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/** SYSTIMER_LOAD_REG register
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* load value to system timer
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*/
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@ -51,12 +51,11 @@ extern "C" {
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#define SYSTIMER_TIMER_LOAD_V 0x00000001
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#define SYSTIMER_TIMER_LOAD_S 31
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/** SYSTIMER_LOAD_HI_REG register
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* High 32-bit load to system timer
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*/
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#define SYSTIMER_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x8)
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/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [31:0]; default: 0;
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* High 32-bit load to system timer
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*/
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#define SYSTIMER_TIMER_LOAD_HI 0xFFFFFFFF
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@ -64,12 +63,11 @@ extern "C" {
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#define SYSTIMER_TIMER_LOAD_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_LOAD_HI_S 0
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/** SYSTIMER_LOAD_LO_REG register
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* Low 32-bit load to system timer
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*/
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#define SYSTIMER_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0xc)
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/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
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* Low 32-bit load to system timer
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*/
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#define SYSTIMER_TIMER_LOAD_LO 0xFFFFFFFF
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@ -77,19 +75,18 @@ extern "C" {
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#define SYSTIMER_TIMER_LOAD_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_LOAD_LO_S 0
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/** SYSTIMER_STEP_REG register
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* system timer accumulation step
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*/
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#define SYSTIMER_STEP_REG (DR_REG_SYSTIMER_BASE + 0x10)
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/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [10:0]; default: 80;
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/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [9:0]; default: 80;
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* system timer accumulation step when using XTAL
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*/
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#define SYSTIMER_TIMER_XTAL_STEP 0x000003FF
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#define SYSTIMER_TIMER_XTAL_STEP_M (SYSTIMER_TIMER_XTAL_STEP_V << SYSTIMER_TIMER_XTAL_STEP_S)
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#define SYSTIMER_TIMER_XTAL_STEP_V 0x000003FF
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#define SYSTIMER_TIMER_XTAL_STEP_S 0
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/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [20:10]; default: 1;
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/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [19:10]; default: 1;
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* system timer accumulation step when using PLL
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*/
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#define SYSTIMER_TIMER_PLL_STEP 0x000003FF
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@ -97,12 +94,11 @@ extern "C" {
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#define SYSTIMER_TIMER_PLL_STEP_V 0x000003FF
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#define SYSTIMER_TIMER_PLL_STEP_S 10
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/** SYSTIMER_TARGET0_HI_REG register
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* System timer target0 high 32-bit
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*/
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#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
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/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [31:0]; default: 0;
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* System timer target0 high 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET0_HI 0xFFFFFFFF
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@ -110,12 +106,11 @@ extern "C" {
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#define SYSTIMER_TIMER_TARGET0_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET0_HI_S 0
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/** SYSTIMER_TARGET0_LO_REG register
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* System timer target0 low 32-bit
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*/
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#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
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/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
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* System timer target0 low 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF
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@ -123,12 +118,11 @@ extern "C" {
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#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET0_LO_S 0
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/** SYSTIMER_TARGET1_HI_REG register
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* System timer target1 high 32-bit
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*/
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#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
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/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [31:0]; default: 0;
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* System timer target1 high 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET1_HI 0xFFFFFFFF
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@ -136,12 +130,11 @@ extern "C" {
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#define SYSTIMER_TIMER_TARGET1_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET1_HI_S 0
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/** SYSTIMER_TARGET1_LO_REG register
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* System timer target1 low 32-bit
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*/
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#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
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/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
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* System timer target1 low 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF
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@ -149,12 +142,11 @@ extern "C" {
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#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET1_LO_S 0
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/** SYSTIMER_TARGET2_HI_REG register
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* System timer target2 high 32-bit
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*/
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#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
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/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [31:0]; default: 0;
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* System timer target2 high 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET2_HI 0xFFFFFFFF
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@ -162,12 +154,11 @@ extern "C" {
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#define SYSTIMER_TIMER_TARGET2_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET2_HI_S 0
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/** SYSTIMER_TARGET2_LO_REG register
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* System timer target2 low 32-bit
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*/
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#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
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/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
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* System timer target2 low 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF
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@ -175,12 +166,11 @@ extern "C" {
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#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET2_LO_S 0
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/** SYSTIMER_TARGET0_CONF_REG register
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* Configure system timer target0 work mode
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*/
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#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x2c)
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/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [30:0]; default: 0;
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/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [29:0]; default: 0;
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* System timer target0 alarm period
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*/
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#define SYSTIMER_TARGET0_PERIOD 0x3FFFFFFF
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@ -202,12 +192,11 @@ extern "C" {
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#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
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#define SYSTIMER_TARGET0_WORK_EN_S 31
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/** SYSTIMER_TARGET1_CONF_REG register
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* Configure system timer target1 work mode
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*/
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#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x30)
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/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [30:0]; default: 0;
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/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [29:0]; default: 0;
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* System timer target1 alarm period
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*/
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#define SYSTIMER_TARGET1_PERIOD 0x3FFFFFFF
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@ -229,12 +218,11 @@ extern "C" {
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#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
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#define SYSTIMER_TARGET1_WORK_EN_S 31
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/** SYSTIMER_TARGET2_CONF_REG register
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* Configure system timer target2 work mode
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*/
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#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
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/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [30:0]; default: 0;
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/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [29:0]; default: 0;
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* System timer target2 alarm period
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*/
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#define SYSTIMER_TARGET2_PERIOD 0x3FFFFFFF
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@ -256,7 +244,6 @@ extern "C" {
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#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
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#define SYSTIMER_TARGET2_WORK_EN_S 31
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/** SYSTIMER_UPDATE_REG register
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* Read out system timer value
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*/
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@ -276,12 +263,11 @@ extern "C" {
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#define SYSTIMER_TIMER_UPDATE_V 0x00000001
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#define SYSTIMER_TIMER_UPDATE_S 31
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/** SYSTIMER_VALUE_HI_REG register
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* system timer high 32-bit
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*/
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#define SYSTIMER_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x3c)
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/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [31:0]; default: 0;
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* system timer high 32-bit
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*/
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#define SYSTIMER_TIMER_VALUE_HI 0xFFFFFFFF
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@ -289,12 +275,11 @@ extern "C" {
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#define SYSTIMER_TIMER_VALUE_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_VALUE_HI_S 0
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/** SYSTIMER_VALUE_LO_REG register
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* system timer low 32-bit
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*/
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#define SYSTIMER_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x40)
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/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [32:0]; default: 0;
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/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [31:0]; default: 0;
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* system timer low 32-bit
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*/
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#define SYSTIMER_TIMER_VALUE_LO 0xFFFFFFFF
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@ -302,93 +287,89 @@ extern "C" {
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#define SYSTIMER_TIMER_VALUE_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_VALUE_LO_S 0
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/** SYSTIMER_INT_ENA_REG register
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* system timer interrupt enable
|
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*/
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#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x44)
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/** SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0;
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/** SYSTIMER_SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0;
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* system timer target0 interrupt enable
|
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*/
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#define SYSTIMER_INT0_ENA (BIT(0))
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#define SYSTIMER_INT0_ENA_M (SYSTIMER_INT0_ENA_V << SYSTIMER_INT0_ENA_S)
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#define SYSTIMER_INT0_ENA_V 0x00000001
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#define SYSTIMER_INT0_ENA_S 0
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/** SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0;
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#define SYSTIMER_SYSTIMER_INT0_ENA (BIT(0))
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#define SYSTIMER_SYSTIMER_INT0_ENA_M (SYSTIMER_SYSTIMER_INT0_ENA_V << SYSTIMER_SYSTIMER_INT0_ENA_S)
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#define SYSTIMER_SYSTIMER_INT0_ENA_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT0_ENA_S 0
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/** SYSTIMER_SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0;
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* system timer target1 interrupt enable
|
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*/
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#define SYSTIMER_INT1_ENA (BIT(1))
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#define SYSTIMER_INT1_ENA_M (SYSTIMER_INT1_ENA_V << SYSTIMER_INT1_ENA_S)
|
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#define SYSTIMER_INT1_ENA_V 0x00000001
|
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#define SYSTIMER_INT1_ENA_S 1
|
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/** SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0;
|
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#define SYSTIMER_SYSTIMER_INT1_ENA (BIT(1))
|
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#define SYSTIMER_SYSTIMER_INT1_ENA_M (SYSTIMER_SYSTIMER_INT1_ENA_V << SYSTIMER_SYSTIMER_INT1_ENA_S)
|
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#define SYSTIMER_SYSTIMER_INT1_ENA_V 0x00000001
|
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#define SYSTIMER_SYSTIMER_INT1_ENA_S 1
|
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/** SYSTIMER_SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0;
|
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* system timer target2 interrupt enable
|
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*/
|
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#define SYSTIMER_INT2_ENA (BIT(2))
|
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#define SYSTIMER_INT2_ENA_M (SYSTIMER_INT2_ENA_V << SYSTIMER_INT2_ENA_S)
|
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#define SYSTIMER_INT2_ENA_V 0x00000001
|
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#define SYSTIMER_INT2_ENA_S 2
|
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#define SYSTIMER_SYSTIMER_INT2_ENA (BIT(2))
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#define SYSTIMER_SYSTIMER_INT2_ENA_M (SYSTIMER_SYSTIMER_INT2_ENA_V << SYSTIMER_SYSTIMER_INT2_ENA_S)
|
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#define SYSTIMER_SYSTIMER_INT2_ENA_V 0x00000001
|
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#define SYSTIMER_SYSTIMER_INT2_ENA_S 2
|
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|
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/** SYSTIMER_INT_RAW_REG register
|
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* system timer interrupt raw
|
||||
*/
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
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/** SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0;
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/** SYSTIMER_SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0;
|
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* system timer target0 interrupt raw
|
||||
*/
|
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#define SYSTIMER_INT0_RAW (BIT(0))
|
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#define SYSTIMER_INT0_RAW_M (SYSTIMER_INT0_RAW_V << SYSTIMER_INT0_RAW_S)
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#define SYSTIMER_INT0_RAW_V 0x00000001
|
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#define SYSTIMER_INT0_RAW_S 0
|
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/** SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0;
|
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#define SYSTIMER_SYSTIMER_INT0_RAW (BIT(0))
|
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#define SYSTIMER_SYSTIMER_INT0_RAW_M (SYSTIMER_SYSTIMER_INT0_RAW_V << SYSTIMER_SYSTIMER_INT0_RAW_S)
|
||||
#define SYSTIMER_SYSTIMER_INT0_RAW_V 0x00000001
|
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#define SYSTIMER_SYSTIMER_INT0_RAW_S 0
|
||||
/** SYSTIMER_SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0;
|
||||
* system timer target1 interrupt raw
|
||||
*/
|
||||
#define SYSTIMER_INT1_RAW (BIT(1))
|
||||
#define SYSTIMER_INT1_RAW_M (SYSTIMER_INT1_RAW_V << SYSTIMER_INT1_RAW_S)
|
||||
#define SYSTIMER_INT1_RAW_V 0x00000001
|
||||
#define SYSTIMER_INT1_RAW_S 1
|
||||
/** SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0;
|
||||
#define SYSTIMER_SYSTIMER_INT1_RAW (BIT(1))
|
||||
#define SYSTIMER_SYSTIMER_INT1_RAW_M (SYSTIMER_SYSTIMER_INT1_RAW_V << SYSTIMER_SYSTIMER_INT1_RAW_S)
|
||||
#define SYSTIMER_SYSTIMER_INT1_RAW_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_INT1_RAW_S 1
|
||||
/** SYSTIMER_SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0;
|
||||
* system timer target2 interrupt raw
|
||||
*/
|
||||
#define SYSTIMER_INT2_RAW (BIT(2))
|
||||
#define SYSTIMER_INT2_RAW_M (SYSTIMER_INT2_RAW_V << SYSTIMER_INT2_RAW_S)
|
||||
#define SYSTIMER_INT2_RAW_V 0x00000001
|
||||
#define SYSTIMER_INT2_RAW_S 2
|
||||
|
||||
#define SYSTIMER_SYSTIMER_INT2_RAW (BIT(2))
|
||||
#define SYSTIMER_SYSTIMER_INT2_RAW_M (SYSTIMER_SYSTIMER_INT2_RAW_V << SYSTIMER_SYSTIMER_INT2_RAW_S)
|
||||
#define SYSTIMER_SYSTIMER_INT2_RAW_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_INT2_RAW_S 2
|
||||
|
||||
/** SYSTIMER_INT_CLR_REG register
|
||||
* system timer interrupt clear
|
||||
*/
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x4c)
|
||||
/** SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0;
|
||||
/** SYSTIMER_SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0;
|
||||
* system timer target0 interrupt clear
|
||||
*/
|
||||
#define SYSTIMER_INT0_CLR (BIT(0))
|
||||
#define SYSTIMER_INT0_CLR_M (SYSTIMER_INT0_CLR_V << SYSTIMER_INT0_CLR_S)
|
||||
#define SYSTIMER_INT0_CLR_V 0x00000001
|
||||
#define SYSTIMER_INT0_CLR_S 0
|
||||
/** SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0;
|
||||
#define SYSTIMER_SYSTIMER_INT0_CLR (BIT(0))
|
||||
#define SYSTIMER_SYSTIMER_INT0_CLR_M (SYSTIMER_SYSTIMER_INT0_CLR_V << SYSTIMER_SYSTIMER_INT0_CLR_S)
|
||||
#define SYSTIMER_SYSTIMER_INT0_CLR_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_INT0_CLR_S 0
|
||||
/** SYSTIMER_SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0;
|
||||
* system timer target1 interrupt clear
|
||||
*/
|
||||
#define SYSTIMER_INT1_CLR (BIT(1))
|
||||
#define SYSTIMER_INT1_CLR_M (SYSTIMER_INT1_CLR_V << SYSTIMER_INT1_CLR_S)
|
||||
#define SYSTIMER_INT1_CLR_V 0x00000001
|
||||
#define SYSTIMER_INT1_CLR_S 1
|
||||
/** SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0;
|
||||
#define SYSTIMER_SYSTIMER_INT1_CLR (BIT(1))
|
||||
#define SYSTIMER_SYSTIMER_INT1_CLR_M (SYSTIMER_SYSTIMER_INT1_CLR_V << SYSTIMER_SYSTIMER_INT1_CLR_S)
|
||||
#define SYSTIMER_SYSTIMER_INT1_CLR_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_INT1_CLR_S 1
|
||||
/** SYSTIMER_SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0;
|
||||
* system timer target2 interrupt clear
|
||||
*/
|
||||
#define SYSTIMER_INT2_CLR (BIT(2))
|
||||
#define SYSTIMER_INT2_CLR_M (SYSTIMER_INT2_CLR_V << SYSTIMER_INT2_CLR_S)
|
||||
#define SYSTIMER_INT2_CLR_V 0x00000001
|
||||
#define SYSTIMER_INT2_CLR_S 2
|
||||
|
||||
#define SYSTIMER_SYSTIMER_INT2_CLR (BIT(2))
|
||||
#define SYSTIMER_SYSTIMER_INT2_CLR_M (SYSTIMER_SYSTIMER_INT2_CLR_V << SYSTIMER_SYSTIMER_INT2_CLR_S)
|
||||
#define SYSTIMER_SYSTIMER_INT2_CLR_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_INT2_CLR_S 2
|
||||
|
||||
/** SYSTIMER_DATE_REG register
|
||||
* system timer register version
|
||||
*/
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [32:0]; default: 25194848;
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 25194848;
|
||||
* system timer register version
|
||||
*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFF
|
||||
@ -396,7 +377,6 @@ extern "C" {
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFF
|
||||
#define SYSTIMER_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,330 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SYSTEM TIMER REGISTER */
|
||||
/** Type of conf register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_fo : R/W; bitpos: [0]; default: 0;
|
||||
* system timer force clock enable
|
||||
*/
|
||||
uint32_t clk_fo: 1;
|
||||
uint32_t reserved_1: 30;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* register clock enable
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_conf_reg_t;
|
||||
|
||||
/** Type of load register
|
||||
* load value to system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 31;
|
||||
/** timer_load : WO; bitpos: [31]; default: 0;
|
||||
* load value to system timer
|
||||
*/
|
||||
uint32_t timer_load: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_load_reg_t;
|
||||
|
||||
/** Type of load_hi register
|
||||
* High 32-bit load to system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_load_hi : R/W; bitpos: [31:0]; default: 0;
|
||||
* High 32-bit load to system timer
|
||||
*/
|
||||
uint32_t timer_load_hi: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_load_hi_reg_t;
|
||||
|
||||
/** Type of load_lo register
|
||||
* Low 32-bit load to system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32-bit load to system timer
|
||||
*/
|
||||
uint32_t timer_load_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_load_lo_reg_t;
|
||||
|
||||
/** Type of step register
|
||||
* system timer accumulation step
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_xtal_step : R/W; bitpos: [9:0]; default: 80;
|
||||
* system timer accumulation step when using XTAL
|
||||
*/
|
||||
uint32_t timer_xtal_step: 10;
|
||||
/** timer_pll_step : R/W; bitpos: [19:10]; default: 1;
|
||||
* system timer accumulation step when using PLL
|
||||
*/
|
||||
uint32_t timer_pll_step: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_step_reg_t;
|
||||
|
||||
/** Type of target_val register
|
||||
* System timer target value
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_target_hi : R/W; bitpos: [31:0]; default: 0;
|
||||
* System timer target0 high 32-bit
|
||||
*/
|
||||
uint32_t timer_target_hi: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* System timer target0 low 32-bit
|
||||
*/
|
||||
uint32_t timer_target_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_target_val_reg_t;
|
||||
|
||||
/** Type of target_conf register
|
||||
* Configure system timer target work mode
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target_period : R/W; bitpos: [29:0]; default: 0;
|
||||
* System timer target alarm period
|
||||
*/
|
||||
uint32_t target_period: 30;
|
||||
/** target_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Whether system timer target work in period mode
|
||||
*/
|
||||
uint32_t target_period_mode: 1;
|
||||
/** target_work_en : R/W; bitpos: [31]; default: 0;
|
||||
* system timer target work enable
|
||||
*/
|
||||
uint32_t target_work_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target_conf_reg_t;
|
||||
|
||||
/** Type of update register
|
||||
* Read out system timer value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 30;
|
||||
/** timer_value_valid : RO; bitpos: [30]; default: 0;
|
||||
* If it is valid to read out timer value from register
|
||||
*/
|
||||
uint32_t timer_value_valid: 1;
|
||||
/** timer_update : WO; bitpos: [31]; default: 0;
|
||||
* Update system timer value to register
|
||||
*/
|
||||
uint32_t timer_update: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_update_reg_t;
|
||||
|
||||
/** Type of value_hi register
|
||||
* system timer high 32-bit
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_value_hi : RO; bitpos: [31:0]; default: 0;
|
||||
* system timer high 32-bit
|
||||
*/
|
||||
uint32_t timer_value_hi: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_value_hi_reg_t;
|
||||
|
||||
/** Type of value_lo register
|
||||
* system timer low 32-bit
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* system timer low 32-bit
|
||||
*/
|
||||
uint32_t timer_value_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_value_lo_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* system timer interrupt enable
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** systimer_int0_ena : R/W; bitpos: [0]; default: 0;
|
||||
* system timer target0 interrupt enable
|
||||
*/
|
||||
uint32_t systimer_int0_ena: 1;
|
||||
/** systimer_int1_ena : R/W; bitpos: [1]; default: 0;
|
||||
* system timer target1 interrupt enable
|
||||
*/
|
||||
uint32_t systimer_int1_ena: 1;
|
||||
/** systimer_int2_ena : R/W; bitpos: [2]; default: 0;
|
||||
* system timer target2 interrupt enable
|
||||
*/
|
||||
uint32_t systimer_int2_ena: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* system timer interrupt raw
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** systimer_int0_raw : RO; bitpos: [0]; default: 0;
|
||||
* system timer target0 interrupt raw
|
||||
*/
|
||||
uint32_t systimer_int0_raw: 1;
|
||||
/** systimer_int1_raw : RO; bitpos: [1]; default: 0;
|
||||
* system timer target1 interrupt raw
|
||||
*/
|
||||
uint32_t systimer_int1_raw: 1;
|
||||
/** systimer_int2_raw : RO; bitpos: [2]; default: 0;
|
||||
* system timer target2 interrupt raw
|
||||
*/
|
||||
uint32_t systimer_int2_raw: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* system timer interrupt clear
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** systimer_int0_clr : WO; bitpos: [0]; default: 0;
|
||||
* system timer target0 interrupt clear
|
||||
*/
|
||||
uint32_t systimer_int0_clr: 1;
|
||||
/** systimer_int1_clr : WO; bitpos: [1]; default: 0;
|
||||
* system timer target1 interrupt clear
|
||||
*/
|
||||
uint32_t systimer_int1_clr: 1;
|
||||
/** systimer_int2_clr : WO; bitpos: [2]; default: 0;
|
||||
* system timer target2 interrupt clear
|
||||
*/
|
||||
uint32_t systimer_int2_clr: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_clr_reg_t;
|
||||
|
||||
|
||||
/** DATE */
|
||||
/** Type of date register
|
||||
* system timer register version
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 25194848;
|
||||
* system timer register version
|
||||
*/
|
||||
uint32_t date: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile systimer_conf_reg_t conf;
|
||||
volatile systimer_load_reg_t load;
|
||||
volatile systimer_load_hi_reg_t load_hi;
|
||||
volatile systimer_load_lo_reg_t load_lo;
|
||||
volatile systimer_step_reg_t step;
|
||||
volatile systimer_target_val_reg_t target_val[3];
|
||||
volatile systimer_target_conf_reg_t target_conf[3];
|
||||
volatile systimer_update_reg_t update;
|
||||
volatile systimer_value_hi_reg_t value_hi;
|
||||
volatile systimer_value_lo_reg_t value_lo;
|
||||
volatile systimer_int_ena_reg_t int_ena;
|
||||
volatile systimer_int_raw_reg_t int_raw;
|
||||
volatile systimer_int_clr_reg_t int_clr;
|
||||
uint32_t reserved_050;
|
||||
uint32_t reserved_054;
|
||||
uint32_t reserved_058;
|
||||
uint32_t reserved_05c;
|
||||
uint32_t reserved_060;
|
||||
uint32_t reserved_064;
|
||||
uint32_t reserved_068;
|
||||
uint32_t reserved_06c;
|
||||
uint32_t reserved_070;
|
||||
uint32_t reserved_074;
|
||||
uint32_t reserved_078;
|
||||
uint32_t reserved_07c;
|
||||
uint32_t reserved_080;
|
||||
uint32_t reserved_084;
|
||||
uint32_t reserved_088;
|
||||
uint32_t reserved_08c;
|
||||
uint32_t reserved_090;
|
||||
uint32_t reserved_094;
|
||||
uint32_t reserved_098;
|
||||
uint32_t reserved_09c;
|
||||
uint32_t reserved_0a0;
|
||||
uint32_t reserved_0a4;
|
||||
uint32_t reserved_0a8;
|
||||
uint32_t reserved_0ac;
|
||||
uint32_t reserved_0b0;
|
||||
uint32_t reserved_0b4;
|
||||
uint32_t reserved_0b8;
|
||||
uint32_t reserved_0bc;
|
||||
uint32_t reserved_0c0;
|
||||
uint32_t reserved_0c4;
|
||||
uint32_t reserved_0c8;
|
||||
uint32_t reserved_0cc;
|
||||
uint32_t reserved_0d0;
|
||||
uint32_t reserved_0d4;
|
||||
uint32_t reserved_0d8;
|
||||
uint32_t reserved_0dc;
|
||||
uint32_t reserved_0e0;
|
||||
uint32_t reserved_0e4;
|
||||
uint32_t reserved_0e8;
|
||||
uint32_t reserved_0ec;
|
||||
uint32_t reserved_0f0;
|
||||
uint32_t reserved_0f4;
|
||||
uint32_t reserved_0f8;
|
||||
volatile systimer_date_reg_t date;
|
||||
} systimer_dev_t;
|
||||
|
||||
extern systimer_dev_t SYSTIMER;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@ -25,7 +25,8 @@ typedef struct {
|
||||
struct {
|
||||
const periph_module_t module;
|
||||
struct {
|
||||
const int irq_id;
|
||||
const int rx_irq_id;
|
||||
const int tx_irq_id;
|
||||
} pairs[SOC_GDMA_PAIRS_PER_GROUP];
|
||||
} groups[SOC_GDMA_GROUPS];
|
||||
} gdma_signal_conn_t;
|
||||
|
||||
@ -25,7 +25,7 @@ typedef struct {
|
||||
struct {
|
||||
const periph_module_t module;
|
||||
const int irq_id;
|
||||
const int data_sigs[SOC_LCD_MAX_DATA_WIDTH];
|
||||
const int data_sigs[SOC_LCD_I80_BUS_WIDTH];
|
||||
const int cs_sig;
|
||||
const int dc_sig;
|
||||
const int wr_sig;
|
||||
@ -33,7 +33,7 @@ typedef struct {
|
||||
struct {
|
||||
const periph_module_t module;
|
||||
const int irq_id;
|
||||
const int data_sigs[SOC_LCD_MAX_DATA_WIDTH];
|
||||
const int data_sigs[SOC_LCD_RGB_DATA_WIDTH];
|
||||
const int hsync_sig;
|
||||
const int vsync_sig;
|
||||
const int pclk_sig;
|
||||
|
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Reference in New Issue
Block a user