mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-01 04:50:58 +02:00
Update IDF to 9a26296
This commit is contained in:
me-no-dev
72
tools/sdk/include/soc/soc/adc_channel.h
Normal file
72
tools/sdk/include/soc/soc/adc_channel.h
Normal file
@ -0,0 +1,72 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_ADC_CHANNEL_H
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||||
#define _SOC_ADC_CHANNEL_H
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#define ADC1_GPIO36_CHANNEL ADC1_CHANNEL_0
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#define ADC1_CHANNEL_0_GPIO_NUM 36
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||||
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||||
#define ADC1_GPIO37_CHANNEL ADC1_CHANNEL_1
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#define ADC1_CHANNEL_1_GPIO_NUM 37
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#define ADC1_GPIO38_CHANNEL ADC1_CHANNEL_2
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#define ADC1_CHANNEL_2_GPIO_NUM 38
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#define ADC1_GPIO39_CHANNEL ADC1_CHANNEL_3
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#define ADC1_CHANNEL_3_GPIO_NUM 39
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#define ADC1_GPIO32_CHANNEL ADC1_CHANNEL_4
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#define ADC1_CHANNEL_4_GPIO_NUM 32
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#define ADC1_GPIO33_CHANNEL ADC1_CHANNEL_5
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#define ADC1_CHANNEL_5_GPIO_NUM 33
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#define ADC1_GPIO34_CHANNEL ADC1_CHANNEL_6
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#define ADC1_CHANNEL_6_GPIO_NUM 34
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#define ADC1_GPIO35_CHANNEL ADC1_CHANNEL_7
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#define ADC1_CHANNEL_7_GPIO_NUM 35
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#define ADC2_GPIO4_CHANNEL ADC2_CHANNEL_0
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#define ADC2_CHANNEL_0_GPIO_NUM 4
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#define ADC2_GPIO0_CHANNEL ADC2_CHANNEL_1
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#define ADC2_CHANNEL_1_GPIO_NUM 0
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#define ADC2_GPIO2_CHANNEL ADC2_CHANNEL_2
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#define ADC2_CHANNEL_2_GPIO_NUM 2
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#define ADC2_GPIO15_CHANNEL ADC2_CHANNEL_3
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#define ADC2_CHANNEL_3_GPIO_NUM 15
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#define ADC2_GPIO13_CHANNEL ADC2_CHANNEL_4
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#define ADC2_CHANNEL_4_GPIO_NUM 13
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#define ADC2_GPIO12_CHANNEL ADC2_CHANNEL_5
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#define ADC2_CHANNEL_5_GPIO_NUM 12
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#define ADC2_GPIO14_CHANNEL ADC2_CHANNEL_6
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#define ADC2_CHANNEL_6_GPIO_NUM 14
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#define ADC2_GPIO27_CHANNEL ADC2_CHANNEL_7
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#define ADC2_CHANNEL_7_GPIO_NUM 27
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#define ADC2_GPIO25_CHANNEL ADC2_CHANNEL_8
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#define ADC2_CHANNEL_8_GPIO_NUM 25
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#define ADC2_GPIO26_CHANNEL ADC2_CHANNEL_9
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#define ADC2_CHANNEL_9_GPIO_NUM 26
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#endif
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@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_APB_CTRL_STRUCT_H_
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||||
#define _SOC_APB_CTRL_STRUCT_H_
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||||
|
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#ifdef __cplusplus
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||||
extern "C" {
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||||
#endif
|
||||
|
||||
typedef struct {
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||||
union {
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||||
struct {
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@ -117,4 +122,9 @@ typedef struct {
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volatile uint32_t date; /**/
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} apb_ctrl_dev_t;
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|
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#ifdef __cplusplus
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}
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||||
#endif
|
||||
|
||||
#endif /* _SOC_APB_CTRL_STRUCT_H_ */
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||||
|
||||
26
tools/sdk/include/soc/soc/clkout_channel.h
Normal file
26
tools/sdk/include/soc/soc/clkout_channel.h
Normal file
@ -0,0 +1,26 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_CLKOUT_CHANNEL_H
|
||||
#define _SOC_CLKOUT_CHANNEL_H
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||||
|
||||
//CLKOUT channels
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||||
#define CLKOUT_GPIO0_DIRECT_CHANNEL CLKOUT_CHANNEL_1
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||||
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 0
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#define CLKOUT_GPIO3_DIRECT_CHANNEL CLKOUT_CHANNEL_2
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#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 3
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#define CLKOUT_GPIO1_DIRECT_CHANNEL CLKOUT_CHANNEL_3
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#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 1
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|
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#endif
|
||||
24
tools/sdk/include/soc/soc/dac_channel.h
Normal file
24
tools/sdk/include/soc/soc/dac_channel.h
Normal file
@ -0,0 +1,24 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_DAC_CHANNEL_H
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||||
#define _SOC_DAC_CHANNEL_H
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||||
#define DAC_GPIO25_CHANNEL DAC_CHANNEL_1
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#define DAC_CHANNEL_1_GPIO_NUM 25
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#define DAC_GPIO26_CHANNEL DAC_CHANNEL_2
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#define DAC_CHANNEL_2_GPIO_NUM 26
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#endif
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@ -25,14 +25,21 @@ extern "C" {
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||||
|
||||
//Registers Operation {{
|
||||
|
||||
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
|
||||
// The _DPORT_xxx register read macros access DPORT memory directly (as opposed to
|
||||
// DPORT_REG_READ which applies SMP-safe protections).
|
||||
//
|
||||
// Use DPORT_REG_READ versions to be SMP-safe in IDF apps. If you want to
|
||||
// make a sequence of DPORT reads, use DPORT_STALL_OTHER_CPU_START() macro
|
||||
// explicitly and then use _DPORT_REG_READ macro while other CPU is stalled.
|
||||
//
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||||
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
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||||
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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||||
|
||||
//write value to register
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// Write value to DPORT register (does not require protecting)
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
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||||
//read value from register
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// Read value from register, SMP-safe version.
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||||
static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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||||
{
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uint32_t val;
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@ -40,7 +47,7 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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||||
DPORT_STALL_OTHER_CPU_START();
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val = _DPORT_REG_READ(reg);
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||||
DPORT_STALL_OTHER_CPU_END();
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||||
|
||||
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return val;
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||||
}
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||||
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||||
@ -81,8 +88,10 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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||||
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||||
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
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||||
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
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||||
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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||||
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
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||||
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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||||
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
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#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
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||||
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||||
//read value from register
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static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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@ -1055,6 +1055,8 @@
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#define DPORT_WIFI_CLK_BT_EN_S 11
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/* Remaining single bit clock masks */
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#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4)
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#define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5)
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#define DPORT_WIFI_CLK_UNUSED_BIT12 BIT(12)
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#define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13)
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#define DPORT_WIFI_CLK_EMAC_EN BIT(14)
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#define DPORT_WIFI_CLK_RNG_EN BIT(15)
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@ -32,12 +32,15 @@
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||||
#define FRC_TIMER_COUNT_S 0
|
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#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
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#define FRC_TIMER_INT_ENABLE (BIT(8)) // enable interrupt
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#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO)
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#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
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#define FRC_TIMER_AUTOLOAD (BIT(6)) // enable autoload
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#define FRC_TIMER_PRESCALER 0x00000007 // 0: divide by 1, 2: divide by 16, 4: divide by 256
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#define FRC_TIMER_PRESCALER 0x00000007
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#define FRC_TIMER_PRESCALER_S 1
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#define FRC_TIMER_EDGE_INT (BIT(0)) // 0: level, 1: edge
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#define FRC_TIMER_PRESCALER_1 (0 << FRC_TIMER_PRESCALER_S)
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#define FRC_TIMER_PRESCALER_16 (2 << FRC_TIMER_PRESCALER_S)
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#define FRC_TIMER_PRESCALER_256 (4 << FRC_TIMER_PRESCALER_S)
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#define FRC_TIMER_LEVEL_INT (BIT(0)) // 1: level, 0: edge
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#define FRC_TIMER_INT_REG(i) (REG_FRC_TIMER_BASE(i) + 0xC)
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#define FRC_TIMER_INT_CLR (BIT(0)) // clear interrupt
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||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_GPIO_SD_STRUCT_H_
|
||||
#define _SOC_GPIO_SD_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
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||||
union {
|
||||
struct {
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||||
@ -45,4 +50,9 @@ typedef volatile struct {
|
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} version;
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} gpio_sd_dev_t;
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extern gpio_sd_dev_t SIGMADELTA;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_GPIO_SD_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_GPIO_STRUCT_H_
|
||||
#define _SOC_GPIO_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t bt_select; /*NA*/
|
||||
uint32_t out; /*GPIO0~31 output value*/
|
||||
@ -201,4 +206,9 @@ typedef volatile struct {
|
||||
} func_out_sel_cfg[40];
|
||||
} gpio_dev_t;
|
||||
extern gpio_dev_t GPIO;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_GPIO_STRUCT_H_ */
|
||||
|
||||
@ -57,4 +57,12 @@
|
||||
#define SHA_512_LOAD_REG ((DR_REG_SHA_BASE) + 0xb8)
|
||||
#define SHA_512_BUSY_REG ((DR_REG_SHA_BASE) + 0xbc)
|
||||
|
||||
/* AES acceleration registers */
|
||||
#define AES_START_REG ((DR_REG_AES_BASE) + 0x00)
|
||||
#define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04)
|
||||
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08)
|
||||
#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x10)
|
||||
#define AES_TEXT_BASE ((DR_REG_AES_BASE) + 0x30)
|
||||
#define AES_ENDIAN ((DR_REG_AES_BASE) + 0x40)
|
||||
|
||||
#endif
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_I2C_STRUCT_H_
|
||||
#define _SOC_I2C_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -286,4 +291,9 @@ typedef volatile struct {
|
||||
} i2c_dev_t;
|
||||
extern i2c_dev_t I2C0;
|
||||
extern i2c_dev_t I2C1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_I2C_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_I2S_STRUCT_H_
|
||||
#define _SOC_I2S_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
@ -458,4 +463,8 @@ typedef volatile struct {
|
||||
extern i2s_dev_t I2S0;
|
||||
extern i2s_dev_t I2S1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_I2S_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_LEDC_STRUCT_H_
|
||||
#define _SOC_LEDC_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
struct {
|
||||
struct {
|
||||
@ -243,4 +248,9 @@ typedef volatile struct {
|
||||
uint32_t date; /*This register represents the version .*/
|
||||
} ledc_dev_t;
|
||||
extern ledc_dev_t LEDC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_LEDC_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_MCPWM_STRUCT_H__
|
||||
#define _SOC_MCPWM_STRUCT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -449,4 +454,9 @@ typedef volatile struct {
|
||||
} mcpwm_dev_t;
|
||||
extern mcpwm_dev_t MCPWM0;
|
||||
extern mcpwm_dev_t MCPWM1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_MCPWM_STRUCT_H__ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_PCNT_STRUCT_H_
|
||||
#define _SOC_PCNT_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
struct{
|
||||
union {
|
||||
@ -169,4 +174,9 @@ typedef volatile struct {
|
||||
uint32_t date; /**/
|
||||
} pcnt_dev_t;
|
||||
extern pcnt_dev_t PCNT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_PCNT_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RMT_STRUCT_H_
|
||||
#define _SOC_RMT_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
|
||||
struct{
|
||||
@ -259,4 +264,8 @@ typedef volatile struct {
|
||||
} rmt_mem_t;
|
||||
extern rmt_mem_t RMTMEM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_RMT_STRUCT_H_ */
|
||||
|
||||
@ -393,6 +393,7 @@ typedef struct {
|
||||
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
|
||||
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
|
||||
uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags
|
||||
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
|
||||
} rtc_sleep_config_t;
|
||||
|
||||
/**
|
||||
@ -419,7 +420,8 @@ typedef struct {
|
||||
.dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
|
||||
.rtc_dbias_wak = RTC_CNTL_DBIAS_0V90, \
|
||||
.rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
|
||||
.lslp_meminf_pd = 1 \
|
||||
.lslp_meminf_pd = 1, \
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
|
||||
};
|
||||
|
||||
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
|
||||
@ -427,6 +429,7 @@ typedef struct {
|
||||
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory
|
||||
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
|
||||
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
|
||||
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
|
||||
|
||||
/**
|
||||
* @brief Prepare the chip to enter sleep mode
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RTC_CNTL_STRUCT_H_
|
||||
#define _SOC_RTC_CNTL_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -550,4 +555,10 @@ typedef volatile struct {
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_cntl_dev_t;
|
||||
extern rtc_cntl_dev_t RTCCNTL;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_RTC_CNTL_STRUCT_H_ */
|
||||
|
||||
73
tools/sdk/include/soc/soc/rtc_gpio_channel.h
Normal file
73
tools/sdk/include/soc/soc/rtc_gpio_channel.h
Normal file
@ -0,0 +1,73 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_RTC_GPIO_CHANNEL_H
|
||||
#define _SOC_RTC_GPIO_CHANNEL_H
|
||||
|
||||
//RTC GPIO channels
|
||||
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
|
||||
#define RTCIO_CHANNEL_0_GPIO_NUM 36
|
||||
|
||||
#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1
|
||||
#define RTCIO_CHANNEL_1_GPIO_NUM 37
|
||||
|
||||
#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2
|
||||
#define RTCIO_CHANNEL_2_GPIO_NUM 38
|
||||
|
||||
#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3
|
||||
#define RTCIO_CHANNEL_3_GPIO_NUM 39
|
||||
|
||||
#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4
|
||||
#define RTCIO_CHANNEL_4_GPIO_NUM 34
|
||||
|
||||
#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5
|
||||
#define RTCIO_CHANNEL_5_GPIO_NUM 35
|
||||
|
||||
#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6
|
||||
#define RTCIO_CHANNEL_6_GPIO_NUM 25
|
||||
|
||||
#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7
|
||||
#define RTCIO_CHANNEL_7_GPIO_NUM 26
|
||||
|
||||
#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8
|
||||
#define RTCIO_CHANNEL_8_GPIO_NUM 33
|
||||
|
||||
#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9
|
||||
#define RTCIO_CHANNEL_9_GPIO_NUM 32
|
||||
|
||||
#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10
|
||||
#define RTCIO_CHANNEL_10_GPIO_NUM 4
|
||||
|
||||
#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11
|
||||
#define RTCIO_CHANNEL_11_GPIO_NUM 0
|
||||
|
||||
#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12
|
||||
#define RTCIO_CHANNEL_12_GPIO_NUM 2
|
||||
|
||||
#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13
|
||||
#define RTCIO_CHANNEL_13_GPIO_NUM 15
|
||||
|
||||
#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14
|
||||
#define RTCIO_CHANNEL_14_GPIO_NUM 13
|
||||
|
||||
#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15
|
||||
#define RTCIO_CHANNEL_15_GPIO_NUM 12
|
||||
|
||||
#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16
|
||||
#define RTCIO_CHANNEL_16_GPIO_NUM 14
|
||||
|
||||
#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17
|
||||
#define RTCIO_CHANNEL_17_GPIO_NUM 27
|
||||
|
||||
#endif
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RTC_IO_STRUCT_H_
|
||||
#define _SOC_RTC_IO_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -277,4 +282,10 @@ typedef volatile struct {
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_io_dev_t;
|
||||
extern rtc_io_dev_t RTCIO;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_RTC_IO_STRUCT_H_ */
|
||||
|
||||
@ -16,6 +16,10 @@
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t disable_int_on_completion: 1;
|
||||
@ -366,6 +370,8 @@ extern sdmmc_dev_t SDMMC;
|
||||
|
||||
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //_SOC_SDMMC_STRUCT_H_
|
||||
|
||||
326
tools/sdk/include/soc/soc/sens_struct.h
Normal file
326
tools/sdk/include/soc/soc/sens_struct.h
Normal file
@ -0,0 +1,326 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SENS_STRUCT_H_
|
||||
#define _SOC_SENS_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_clk_div: 8;
|
||||
uint32_t sar1_sample_cycle: 8;
|
||||
uint32_t sar1_sample_bit: 2;
|
||||
uint32_t sar1_clk_gated: 1;
|
||||
uint32_t sar1_sample_num: 8;
|
||||
uint32_t sar1_dig_force: 1;
|
||||
uint32_t sar1_data_inv: 1;
|
||||
uint32_t reserved29: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_read_ctrl;
|
||||
uint32_t sar_read_status1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_amp_wait1:16;
|
||||
uint32_t sar_amp_wait2:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_wait1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_amp_wait3: 16;
|
||||
uint32_t force_xpd_amp: 2;
|
||||
uint32_t force_xpd_sar: 2;
|
||||
uint32_t sar2_rstb_wait: 8;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_wait2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xpd_sar_amp_fsm: 4;
|
||||
uint32_t amp_rst_fb_fsm: 4;
|
||||
uint32_t amp_short_ref_fsm: 4;
|
||||
uint32_t amp_short_ref_gnd_fsm: 4;
|
||||
uint32_t xpd_sar_fsm: 4;
|
||||
uint32_t sar_rstb_fsm: 4;
|
||||
uint32_t sar2_xpd_wait: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_ctrl;
|
||||
uint32_t sar_read_status2; /**/
|
||||
uint32_t ulp_cp_sleep_cyc0; /**/
|
||||
uint32_t ulp_cp_sleep_cyc1; /**/
|
||||
uint32_t ulp_cp_sleep_cyc2; /**/
|
||||
uint32_t ulp_cp_sleep_cyc3; /**/
|
||||
uint32_t ulp_cp_sleep_cyc4; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_bit_width: 2;
|
||||
uint32_t sar2_bit_width: 2;
|
||||
uint32_t sar2_en_test: 1;
|
||||
uint32_t sar2_pwdet_cct: 3;
|
||||
uint32_t ulp_cp_force_start_top: 1;
|
||||
uint32_t ulp_cp_start_top: 1;
|
||||
uint32_t sarclk_en: 1;
|
||||
uint32_t pc_init: 11;
|
||||
uint32_t sar2_stop: 1;
|
||||
uint32_t sar1_stop: 1;
|
||||
uint32_t sar2_pwdet_en: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_start_force;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mem_wr_addr_init: 11;
|
||||
uint32_t mem_wr_addr_size: 11;
|
||||
uint32_t rtc_mem_wr_offst_clr: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_mem_wr_ctrl;
|
||||
uint32_t sar_atten1; /**/
|
||||
uint32_t sar_atten2; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr1: 11;
|
||||
uint32_t i2c_slave_addr0: 11;
|
||||
uint32_t meas_status: 8;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr3:11;
|
||||
uint32_t i2c_slave_addr2:11;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr5:11;
|
||||
uint32_t i2c_slave_addr4:11;
|
||||
uint32_t tsens_out: 8;
|
||||
uint32_t tsens_rdy_out: 1;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr7:11;
|
||||
uint32_t i2c_slave_addr6:11;
|
||||
uint32_t i2c_rdata: 8;
|
||||
uint32_t i2c_done: 1;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_xpd_wait: 12;
|
||||
uint32_t tsens_xpd_force: 1;
|
||||
uint32_t tsens_clk_inv: 1;
|
||||
uint32_t tsens_clk_gated: 1;
|
||||
uint32_t tsens_in_inv: 1;
|
||||
uint32_t tsens_clk_div: 8;
|
||||
uint32_t tsens_power_up: 1;
|
||||
uint32_t tsens_power_up_force: 1;
|
||||
uint32_t tsens_dump_out: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_i2c_ctrl: 28;
|
||||
uint32_t sar_i2c_start: 1;
|
||||
uint32_t sar_i2c_start_force: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_i2c_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas1_data_sar: 16;
|
||||
uint32_t meas1_done_sar: 1;
|
||||
uint32_t meas1_start_sar: 1;
|
||||
uint32_t meas1_start_force: 1;
|
||||
uint32_t sar1_en_pad: 12;
|
||||
uint32_t sar1_en_pad_force: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_start1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_meas_delay:16;
|
||||
uint32_t touch_xpd_wait: 8;
|
||||
uint32_t touch_out_sel: 1;
|
||||
uint32_t touch_out_1en: 1;
|
||||
uint32_t xpd_hall_force: 1;
|
||||
uint32_t hall_phase_force: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t l_thresh: 16;
|
||||
uint32_t h_thresh: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_thresh[5];
|
||||
union {
|
||||
struct {
|
||||
uint32_t l_val: 16;
|
||||
uint32_t h_val: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_meas[5];
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_meas_en: 10;
|
||||
uint32_t touch_meas_done: 1;
|
||||
uint32_t touch_start_fsm_en: 1;
|
||||
uint32_t touch_start_en: 1;
|
||||
uint32_t touch_start_force: 1;
|
||||
uint32_t touch_sleep_cycles:16;
|
||||
uint32_t touch_meas_en_clr: 1;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_ctrl2;
|
||||
uint32_t reserved_88;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad_worken:10;
|
||||
uint32_t touch_pad_outen2:10;
|
||||
uint32_t touch_pad_outen1:10;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_enable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_clk_div: 8;
|
||||
uint32_t sar2_sample_cycle: 8;
|
||||
uint32_t sar2_sample_bit: 2;
|
||||
uint32_t sar2_clk_gated: 1;
|
||||
uint32_t sar2_sample_num: 8;
|
||||
uint32_t sar2_pwdet_force: 1;
|
||||
uint32_t sar2_dig_force: 1;
|
||||
uint32_t sar2_data_inv: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_read_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas2_data_sar: 16;
|
||||
uint32_t meas2_done_sar: 1;
|
||||
uint32_t meas2_start_sar: 1;
|
||||
uint32_t meas2_start_force: 1;
|
||||
uint32_t sar2_en_pad: 12;
|
||||
uint32_t sar2_en_pad_force: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_start2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_fstep: 16;
|
||||
uint32_t sw_tone_en: 1;
|
||||
uint32_t debug_bit_sel: 5;
|
||||
uint32_t dac_dig_force: 1;
|
||||
uint32_t dac_clk_force_low: 1;
|
||||
uint32_t dac_clk_force_high: 1;
|
||||
uint32_t dac_clk_inv: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_dac_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dac_dc1: 8;
|
||||
uint32_t dac_dc2: 8;
|
||||
uint32_t dac_scale1: 2;
|
||||
uint32_t dac_scale2: 2;
|
||||
uint32_t dac_inv1: 2;
|
||||
uint32_t dac_inv2: 2;
|
||||
uint32_t dac_cw_en1: 1;
|
||||
uint32_t dac_cw_en2: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_dac_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm: 4;
|
||||
uint32_t sar1_dac_xpd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_amp_fsm_idle: 1;
|
||||
uint32_t amp_rst_fb_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_gnd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_fsm_idle: 1;
|
||||
uint32_t sar_rstb_fsm_idle: 1;
|
||||
uint32_t sar2_rstb_force: 2;
|
||||
uint32_t amp_rst_fb_force: 2;
|
||||
uint32_t amp_short_ref_force: 2;
|
||||
uint32_t amp_short_ref_gnd_force: 2;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas_ctrl2;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t sar_nouse; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sardate;
|
||||
} sens_dev_t;
|
||||
extern sens_dev_t SENS;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SENS_STRUCT_H_ */
|
||||
@ -67,11 +67,15 @@
|
||||
#define SOC_RTC_IRAM_HIGH 0x400C2000
|
||||
#define SOC_RTC_DATA_LOW 0x50000000
|
||||
#define SOC_RTC_DATA_HIGH 0x50002000
|
||||
#define SOC_EXTRAM_DATA_LOW 0x3F800000
|
||||
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
|
||||
|
||||
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_DPORT_END 0x3ff00FFC
|
||||
#define DR_REG_AES_BASE 0x3ff01000
|
||||
#define DR_REG_RSA_BASE 0x3ff02000
|
||||
#define DR_REG_SHA_BASE 0x3ff03000
|
||||
#define DR_REG_DPORT_END 0x3ff03FFC
|
||||
#define DR_REG_UART_BASE 0x3ff40000
|
||||
#define DR_REG_SPI1_BASE 0x3ff42000
|
||||
#define DR_REG_SPI0_BASE 0x3ff43000
|
||||
@ -118,7 +122,7 @@
|
||||
#define DR_REG_UART2_BASE 0x3ff6E000
|
||||
#define DR_REG_PWM2_BASE 0x3ff6F000
|
||||
#define DR_REG_PWM3_BASE 0x3ff70000
|
||||
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
|
||||
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
@ -376,7 +380,7 @@
|
||||
* 7 1 software BT/BLE VHCI BT/BLE VHCI
|
||||
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
|
||||
* 9 1 extern level
|
||||
* 10 1 extern edge Internal Timer
|
||||
* 10 1 extern edge
|
||||
* 11 3 profiling
|
||||
* 12 1 extern level
|
||||
* 13 1 extern level
|
||||
@ -388,7 +392,7 @@
|
||||
* 19 2 extern level
|
||||
* 20 2 extern level
|
||||
* 21 2 extern level
|
||||
* 22 3 extern edge FRC1 timer
|
||||
* 22 3 extern edge
|
||||
* 23 3 extern level
|
||||
* 24 4 extern level TG1_WDT
|
||||
* 25 4 extern level CACHEERR
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SPI_STRUCT_H_
|
||||
#define _SOC_SPI_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -36,7 +41,7 @@ typedef volatile struct {
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
uint32_t addr; /*addr to slave / from master */
|
||||
uint32_t addr; /*addr to slave / from master. SPI transfer from the MSB to the LSB. If length > 32 bits, then address continues from MSB of slv_wr_status.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10; /*reserved*/
|
||||
@ -143,7 +148,7 @@ typedef volatile struct {
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value: 16; /*The value of command.*/
|
||||
uint32_t usr_command_value: 16; /*The value of command. Output sequence: bit 7-0 and then 15-8.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
|
||||
};
|
||||
@ -673,4 +678,9 @@ extern spi_dev_t SPI0; /* SPI0 IS FOR INTER
|
||||
extern spi_dev_t SPI1;
|
||||
extern spi_dev_t SPI2;
|
||||
extern spi_dev_t SPI3;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SPI_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SYSCON_STRUCT_H_
|
||||
#define _SOC_SYSCON_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
@ -117,4 +122,8 @@ typedef struct {
|
||||
volatile uint32_t date; /**/
|
||||
} syscon_dev_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SYSCON_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_TIMG_STRUCT_H_
|
||||
#define _SOC_TIMG_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
struct{
|
||||
union {
|
||||
@ -192,4 +197,9 @@ typedef volatile struct {
|
||||
} timg_dev_t;
|
||||
extern timg_dev_t TIMERG0;
|
||||
extern timg_dev_t TIMERG1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_TIMG_STRUCT_H_ */
|
||||
|
||||
49
tools/sdk/include/soc/soc/touch_channel.h
Normal file
49
tools/sdk/include/soc/soc/touch_channel.h
Normal file
@ -0,0 +1,49 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_TOUCH_CHANNEL_H
|
||||
#define _SOC_TOUCH_CHANNEL_H
|
||||
|
||||
//Touch channels
|
||||
#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM0
|
||||
#define TOUCH_PAD_NUM0_GPIO_NUM 4
|
||||
|
||||
#define TOUCH_PAD_GPIO0_CHANNEL TOUCH_PAD_NUM1
|
||||
#define TOUCH_PAD_NUM1_GPIO_NUM 0
|
||||
|
||||
#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2
|
||||
#define TOUCH_PAD_NUM2_GPIO_NUM 2
|
||||
|
||||
#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3
|
||||
#define TOUCH_PAD_NUM3_GPIO_NUM 15
|
||||
|
||||
#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4
|
||||
#define TOUCH_PAD_NUM4_GPIO_NUM 13
|
||||
|
||||
#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5
|
||||
#define TOUCH_PAD_NUM5_GPIO_NUM 12
|
||||
|
||||
#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6
|
||||
#define TOUCH_PAD_NUM6_GPIO_NUM 14
|
||||
|
||||
#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7
|
||||
#define TOUCH_PAD_NUM7_GPIO_NUM 27
|
||||
|
||||
#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8
|
||||
#define TOUCH_PAD_NUM8_GPIO_NUM 33
|
||||
|
||||
#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9
|
||||
#define TOUCH_PAD_NUM9_GPIO_NUM 32
|
||||
|
||||
#endif
|
||||
61
tools/sdk/include/soc/soc/uart_channel.h
Normal file
61
tools/sdk/include/soc/soc/uart_channel.h
Normal file
@ -0,0 +1,61 @@
|
||||
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_UART_CHANNEL_H
|
||||
#define _SOC_UART_CHANNEL_H
|
||||
|
||||
//UART channels
|
||||
#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1
|
||||
#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3
|
||||
#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19
|
||||
#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22
|
||||
|
||||
#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL
|
||||
#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL
|
||||
#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL
|
||||
|
||||
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
|
||||
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9
|
||||
#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6
|
||||
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
|
||||
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11
|
||||
|
||||
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
|
||||
#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL
|
||||
#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
|
||||
|
||||
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17
|
||||
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16
|
||||
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8
|
||||
#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2
|
||||
#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7
|
||||
|
||||
#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
|
||||
#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
|
||||
#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL
|
||||
|
||||
#endif
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_UART_STRUCT_H_
|
||||
#define _SOC_UART_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -362,4 +367,9 @@ typedef volatile struct {
|
||||
extern uart_dev_t UART0;
|
||||
extern uart_dev_t UART1;
|
||||
extern uart_dev_t UART2;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_UART_STRUCT_H_ */
|
||||
|
||||
@ -13,6 +13,11 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_UHCI_STRUCT_H_
|
||||
#define _SOC_UHCI_STRUCT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
@ -334,4 +339,9 @@ typedef volatile struct {
|
||||
} uhci_dev_t;
|
||||
extern uhci_dev_t UHCI0;
|
||||
extern uhci_dev_t UHCI1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_UHCI_STRUCT_H_ */
|
||||
|
||||
Reference in New Issue
Block a user