mirror of
https://github.com/0xFEEDC0DE64/arduino-esp32.git
synced 2025-07-01 04:50:58 +02:00
Update IDF libs to 9314bf0
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me-no-dev
@ -1,21 +0,0 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __ESP_BROWNOUT_H
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#define __ESP_BROWNOUT_H
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void esp_brownout_init();
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#endif
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@ -17,25 +17,20 @@
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp_dport_access.h"
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void esp_dport_access_stall_other_cpu_start(void);
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void esp_dport_access_stall_other_cpu_end(void);
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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#define DPORT_STALL_OTHER_CPU_START()
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#define DPORT_STALL_OTHER_CPU_END()
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#else
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#define DPORT_STALL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STALL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#ifdef __cplusplus
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extern "C" {
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#endif
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//Registers Operation {{
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//Origin access operation for the base and some special scene
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//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
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#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
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#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//write value to register
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE(_r, _v)
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
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//read value from register
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static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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@ -65,7 +60,7 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
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//set field to register, used when _f is not left shifted by _f##_S
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#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f) << (_f##_S))))|(((_v) & (_f))<<(_f##_S))))
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#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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@ -85,8 +80,9 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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#define _READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
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#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
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#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
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#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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//read value from register
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static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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@ -94,14 +90,14 @@ static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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uint32_t val;
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DPORT_STALL_OTHER_CPU_START();
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val = _READ_PERI_REG(addr);
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val = _DPORT_READ_PERI_REG(addr);
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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//write value to register
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#define DPORT_WRITE_PERI_REG(addr, val) _WRITE_PERI_REG(addr, val)
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#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
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//clear bits of register controlled by mask
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#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
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@ -116,11 +112,14 @@ static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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//set bits of register controlled by mask and shift
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#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg),(DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))
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#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
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//get field of register
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#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
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//}}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DPORT_ACCESS_H_ */
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@ -958,7 +958,7 @@
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#define DPORT_CAN_CLK_EN (BIT(19))
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#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
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#define DPORT_PWM0_CLK_EN (BIT(17))
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#define DPORT_SPI_CLK_EN (BIT(16))
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#define DPORT_SPI_CLK_EN_2 (BIT(16))
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#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
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#define DPORT_EFUSE_CLK_EN (BIT(14))
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#define DPORT_TIMERGROUP_CLK_EN (BIT(13))
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@ -968,7 +968,7 @@
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#define DPORT_RMT_CLK_EN (BIT(9))
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#define DPORT_UHCI0_CLK_EN (BIT(8))
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#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
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#define DPORT_SPI_CLK_EN_2 (BIT(6))
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#define DPORT_SPI_CLK_EN (BIT(6))
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#define DPORT_UART1_CLK_EN (BIT(5))
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#define DPORT_I2S0_CLK_EN (BIT(4))
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#define DPORT_WDG_CLK_EN (BIT(3))
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@ -992,7 +992,7 @@
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#define DPORT_CAN_RST (BIT(19))
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#define DPORT_I2C_EXT1_RST (BIT(18))
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#define DPORT_PWM0_RST (BIT(17))
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#define DPORT_SPI_RST (BIT(16))
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#define DPORT_SPI_RST_2 (BIT(16))
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#define DPORT_TIMERGROUP1_RST (BIT(15))
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#define DPORT_EFUSE_RST (BIT(14))
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#define DPORT_TIMERGROUP_RST (BIT(13))
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@ -1002,7 +1002,7 @@
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#define DPORT_RMT_RST (BIT(9))
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#define DPORT_UHCI0_RST (BIT(8))
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#define DPORT_I2C_EXT0_RST (BIT(7))
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#define DPORT_SPI_RST_2 (BIT(6))
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#define DPORT_SPI_RST (BIT(6))
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#define DPORT_UART1_RST (BIT(5))
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#define DPORT_I2S0_RST (BIT(4))
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#define DPORT_WDG_RST (BIT(3))
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@ -4261,7 +4261,9 @@
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/* Flash MMU table for APP CPU */
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#define DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000)
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#define DPORT_FLASH_MMU_TABLE_SIZE 0x100
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#define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100
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#endif /*_SOC_DPORT_REG_H_ */
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@ -432,6 +432,7 @@
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#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
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#define RTC_CNTL_MIN_SLP_VAL_V 0xFF
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#define RTC_CNTL_MIN_SLP_VAL_S 8
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#define RTC_CNTL_MIN_SLP_VAL_MIN 2
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/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */
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/*description: */
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#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF
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@ -1717,6 +1718,7 @@
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#define RTC_WDT_STG_SEL_INT 1
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#define RTC_WDT_STG_SEL_RESET_CPU 2
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#define RTC_WDT_STG_SEL_RESET_SYSTEM 3
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#define RTC_WDT_STG_SEL_RESET_RTC 4
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#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90)
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/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */
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@ -142,14 +142,14 @@
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//write value to register
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#define REG_WRITE(_r, _v) ({ \
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ASSERT_IF_DPORT_REG(_r, REG_WRITE); \
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
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(*(volatile uint32_t *)(_r)) = (_v); \
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})
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//read value from register
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)_r); \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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@ -269,6 +269,28 @@
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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//}}
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/* Overall memory map */
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_IRAM_LOW 0x40080000
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#define SOC_IRAM_HIGH 0x400A0000
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define SOC_DIRAM_IRAM_LOW 0x400A0000
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#define SOC_DIRAM_IRAM_HIGH 0x400BFFFC
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#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
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#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FFAE000
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#define SOC_DMA_HIGH 0x40000000
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//Interrupt hardware source table
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//This table is decided by hardware, don't touch this.
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#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
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@ -370,12 +392,12 @@
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* 23 3 extern level
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* 24 4 extern level TG1_WDT
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* 25 4 extern level CACHEERR
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* 26 5 extern level Reserved Reserved
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* 26 5 extern level
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge
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* 28 4 extern edge DPORT ACCESS DPORT ACCESS
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* 29 3 software Reserved Reserved
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level DPORT ACCESS DPORT ACCESS
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* 31 5 extern level
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*************************************************************************************************************
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*/
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@ -387,7 +409,7 @@
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_INUM 24
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#define ETS_CACHEERR_INUM 25
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#define ETS_DPORT_INUM 31
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#define ETS_DPORT_INUM 28
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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@ -395,5 +417,7 @@
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#define ETS_UART1_INUM 5
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//Other interrupt number should be managed by the user
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 6
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#endif /* _ESP32_SOC_H_ */
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@ -17,8 +17,8 @@
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#include "soc.h"
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#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )
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#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )
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#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
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#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
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#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
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#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
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