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Update IDF and Fix Error 88 for Client::available

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This commit is contained in:
me-no-dev
2016-12-30 01:28:30 +02:00
parent 668c3811b8
commit f6d4843680
72 changed files with 3006 additions and 1350 deletions
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2
tools/sdk/include/esp32/soc/gpio_sig_map.h
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@ -418,5 +418,5 @@
#define SIG_IN_FUNC226_IDX 226
#define SIG_IN_FUNC227_IDX 227
#define SIG_IN_FUNC228_IDX 228
#define SIG_GPIO_OUT_IDX 256
#endif /* _SOC_GPIO_SIG_MAP_H_ */

13
tools/sdk/include/esp32/soc/soc.h
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@ -79,8 +79,8 @@
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
//get field from register, used when _f is not left shifted by _f##_S
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f))
//get field from register, uses field _S & _V to determine mask
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
@ -264,14 +264,14 @@
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host VHCI Reserved
* 2 1 extern level FROM_CPU FROM_CPU
* 3 1 extern level TG0_WDT Reserved
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software Reserved Reserved
* 8 1 extern level BLE Controller
* 9 1 extern level EMAC
* 9 1 extern level
* 10 1 extern edge Internal Timer
* 11 3 profiling
* 12 1 extern level
@ -300,10 +300,7 @@
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_FROM_CPU_INUM 2
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_EMAC_INUM 9
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24

4
tools/sdk/include/esp32/soc/spi_reg.h
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@ -69,14 +69,14 @@
#define SPI_FLASH_PP_V 0x1
#define SPI_FLASH_PP_S 25
/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: Sector erase enable(4KB). Sector erase operation will be triggered
/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered
when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_FLASH_SE (BIT(24))
#define SPI_FLASH_SE_M (BIT(24))
#define SPI_FLASH_SE_V 0x1
#define SPI_FLASH_SE_S 24
/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: Block erase enable(32KB) . Block erase operation will be triggered
/*description: Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered
when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
#define SPI_FLASH_BE (BIT(23))
#define SPI_FLASH_BE_M (BIT(23))

2
tools/sdk/include/esp32/soc/wdev_reg.h
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@ -14,5 +14,7 @@
#pragma once
#include "soc.h"
/* Hardware random number generator register */
#define WDEV_RND_REG 0x60035144