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https://github.com/0xFEEDC0DE64/arduino-esp32.git
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a59eafbc9d
* fix sdmmc config * Fix warnings in EEPROM from @Curclamas * remove leftover TAG in EEPROM * Initial add of @stickbreaker i2c * Add log_n * fix warnings when log is off * i2c code clean up and reorganization * add flags to interrupt allocator * fix sdmmc config * Fix warnings in EEPROM from @Curclamas * remove leftover TAG in EEPROM * fix errors with latest IDF * fix debug optimization (#1365) incorrect optimization for debugging tick markers. * Fix some missing BT header * Change BTSerial log calls * Update BLE lib * Arduino-ESP32 release management scripted (#1515) * Calculate an absolute path for a custom partitions table (#1452) * * Arduino-ESP32 release management scripted (ready-to-merge) * * secure env for espressif/arduino-esp32 * * build tests enabled * gitter webhook enabled * * gitter room link fixed * better comment * * filepaths fixed * BT Serial adjustments * * don't run sketch builds & tests for tagged builds * Return false from WiFi.hostByName() if hostname is not resolved * Free BT Memory when BT is not used * WIFI_MODE_NULL is not supported anymore * Select some key examples to build with PlatformIO to save some time * Update BLE lib * Fixed BLE lib * Major WiFi overhaul - auto reconnect on connection loss now works - moved to event groups - some code clean up and procedure optimizations - new methods to get a more elaborate system ststus * Add cmake tests to travis * Add initial AsyncUDP * Add NetBIOS lib and fix CMake includes * Add Initial WebServer * Fix WebServer and examples * travis not quiting on build fail * Try different travis build * Update IDF to aaf1239 * Fix WPS Example * fix script permission and add some fail tests to sketch builder * Add missing space in WiFiClient::write(Stream &stream)
186 lines
8.3 KiB
C
186 lines
8.3 KiB
C
/*
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* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
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*
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* (In previous releases, these were defined in specreg.h, a generated file.
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* This file is not generated, ie. it is processor configuration independent.)
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*/
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/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
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/*
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* Copyright (c) 2005-2011 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef XTENSA_COREBITS_H
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#define XTENSA_COREBITS_H
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/* EXCCAUSE register fields: */
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#define EXCCAUSE_EXCCAUSE_SHIFT 0
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#define EXCCAUSE_EXCCAUSE_MASK 0x3F
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/* EXCCAUSE register values: */
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/*
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* General Exception Causes
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* (values of EXCCAUSE special register set by general exceptions,
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* which vector to the user, kernel, or double-exception vectors).
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*/
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#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
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#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
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#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
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# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
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#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
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# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
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#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
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# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
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#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
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#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
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#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
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#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
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#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
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/* Reserved 10..11 */
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#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
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#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
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#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
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#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
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#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
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#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
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#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
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/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
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#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
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/* Reserved 21..23 */
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#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
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#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
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#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
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/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
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#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
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#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
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/* Reserved 30..31 */
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#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
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#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
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#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
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#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
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#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
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#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
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#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
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#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
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#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
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/* Reserved 40..63 */
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/* PS register fields: */
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#define PS_WOE_SHIFT 18
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#define PS_WOE_MASK 0x00040000
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#define PS_WOE PS_WOE_MASK
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#define PS_CALLINC_SHIFT 16
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#define PS_CALLINC_MASK 0x00030000
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#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
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#define PS_OWB_SHIFT 8
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#define PS_OWB_MASK 0x00000F00
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#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
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#define PS_RING_SHIFT 6
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#define PS_RING_MASK 0x000000C0
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#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
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#define PS_UM_SHIFT 5
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#define PS_UM_MASK 0x00000020
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#define PS_UM PS_UM_MASK
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#define PS_EXCM_SHIFT 4
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#define PS_EXCM_MASK 0x00000010
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#define PS_EXCM PS_EXCM_MASK
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#define PS_INTLEVEL_SHIFT 0
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#define PS_INTLEVEL_MASK 0x0000000F
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#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
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/* Backward compatibility (deprecated): */
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#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
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#define PS_PROGSTACK_MASK PS_UM_MASK
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#define PS_PROG_SHIFT PS_UM_SHIFT
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#define PS_PROG_MASK PS_UM_MASK
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#define PS_PROG PS_UM
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/* DBREAKCn register fields: */
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#define DBREAKC_MASK_SHIFT 0
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#define DBREAKC_MASK_MASK 0x0000003F
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#define DBREAKC_LOADBREAK_SHIFT 30
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#define DBREAKC_LOADBREAK_MASK 0x40000000
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#define DBREAKC_STOREBREAK_SHIFT 31
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#define DBREAKC_STOREBREAK_MASK 0x80000000
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/* DEBUGCAUSE register fields: */
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#define DEBUGCAUSE_DEBUGINT_SHIFT 5
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#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
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#define DEBUGCAUSE_BREAKN_SHIFT 4
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#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
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#define DEBUGCAUSE_BREAK_SHIFT 3
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#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
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#define DEBUGCAUSE_DBREAK_SHIFT 2
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#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
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#define DEBUGCAUSE_IBREAK_SHIFT 1
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#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
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#define DEBUGCAUSE_ICOUNT_SHIFT 0
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#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
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/* MESR register fields: */
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#define MESR_MEME 0x00000001 /* memory error */
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#define MESR_MEME_SHIFT 0
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#define MESR_DME 0x00000002 /* double memory error */
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#define MESR_DME_SHIFT 1
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#define MESR_RCE 0x00000010 /* recorded memory error */
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#define MESR_RCE_SHIFT 4
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#define MESR_LCE
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#define MESR_LCE_SHIFT ?
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#define MESR_LCE_L
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#define MESR_ERRENAB 0x00000100
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#define MESR_ERRENAB_SHIFT 8
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#define MESR_ERRTEST 0x00000200
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#define MESR_ERRTEST_SHIFT 9
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#define MESR_DATEXC 0x00000400
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#define MESR_DATEXC_SHIFT 10
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#define MESR_INSEXC 0x00000800
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#define MESR_INSEXC_SHIFT 11
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#define MESR_WAYNUM_SHIFT 16
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#define MESR_ACCTYPE_SHIFT 20
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#define MESR_MEMTYPE_SHIFT 24
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#define MESR_ERRTYPE_SHIFT 30
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/* MEMCTL register fields: */
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#define MEMCTL_SNOOP_EN_SHIFT 1
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#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
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#define MEMCTL_L0IBUF_EN_SHIFT 0
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#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
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#define MEMCTL_INV_EN_SHIFT 23
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#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
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#define MEMCTL_DCWU_SHIFT 8
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#define MEMCTL_DCWU_BITS 5
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#define MEMCTL_DCWA_SHIFT 13
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#define MEMCTL_DCWA_BITS 5
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#define MEMCTL_ICWU_SHIFT 18
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#define MEMCTL_ICWU_BITS 5
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#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
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#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
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#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
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#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
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#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
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#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
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#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
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#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
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#endif /*XTENSA_COREBITS_H*/
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