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https://github.com/0xFEEDC0DE64/arduino-esp32.git
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118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* Xtensa Special Register symbolic names
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*/
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/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
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/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef XTENSA_SPECREG_H
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#define XTENSA_SPECREG_H
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/* Include these special register bitfield definitions, for historical reasons: */
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#include <xtensa/corebits.h>
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/* Special registers: */
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#define LBEG 0
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#define LEND 1
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#define LCOUNT 2
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#define SAR 3
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#define BR 4
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#define SCOMPARE1 12
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#define ACCLO 16
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#define ACCHI 17
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#define MR_0 32
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#define MR_1 33
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#define MR_2 34
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#define MR_3 35
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#define WINDOWBASE 72
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#define WINDOWSTART 73
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#define IBREAKENABLE 96
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#define MEMCTL 97
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#define ATOMCTL 99
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#define DDR 104
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#define IBREAKA_0 128
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#define IBREAKA_1 129
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#define DBREAKA_0 144
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#define DBREAKA_1 145
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#define DBREAKC_0 160
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#define DBREAKC_1 161
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#define EPC_1 177
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#define EPC_2 178
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#define EPC_3 179
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#define EPC_4 180
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#define EPC_5 181
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#define EPC_6 182
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#define EPC_7 183
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#define DEPC 192
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#define EPS_2 194
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#define EPS_3 195
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#define EPS_4 196
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#define EPS_5 197
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#define EPS_6 198
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#define EPS_7 199
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#define EXCSAVE_1 209
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#define EXCSAVE_2 210
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#define EXCSAVE_3 211
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#define EXCSAVE_4 212
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#define EXCSAVE_5 213
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#define EXCSAVE_6 214
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#define EXCSAVE_7 215
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#define CPENABLE 224
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#define INTERRUPT 226
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#define INTENABLE 228
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#define PS 230
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#define VECBASE 231
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#define EXCCAUSE 232
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#define DEBUGCAUSE 233
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#define CCOUNT 234
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#define PRID 235
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#define ICOUNT 236
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#define ICOUNTLEVEL 237
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#define EXCVADDR 238
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#define CCOMPARE_0 240
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#define CCOMPARE_1 241
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#define CCOMPARE_2 242
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#define MISC_REG_0 244
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#define MISC_REG_1 245
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#define MISC_REG_2 246
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#define MISC_REG_3 247
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/* Special cases (bases of special register series): */
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#define MR 32
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#define IBREAKA 128
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#define DBREAKA 144
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#define DBREAKC 160
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#define EPC 176
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#define EPS 192
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#define EXCSAVE 208
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#define CCOMPARE 240
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/* Special names for read-only and write-only interrupt registers: */
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#define INTREAD 226
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#define INTSET 226
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#define INTCLEAR 227
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#endif /* XTENSA_SPECREG_H */
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