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457 lines
17 KiB
C
Executable File
457 lines
17 KiB
C
Executable File
/*
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* xtensa/core-macros.h -- C specific definitions
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* that depend on CORE configuration
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*/
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/*
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* Copyright (c) 2012 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef XTENSA_CACHE_H
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#define XTENSA_CACHE_H
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#include <xtensa/config/core.h>
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/* Only define things for C code. */
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#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
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/*************************** CACHE ***************************/
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/* All the macros are in the lower case now and some of them
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* share the name with the existing functions from hal.h.
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* Including this header file will define XTHAL_USE_CACHE_MACROS
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* which directs hal.h not to use the functions.
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*/
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/*
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* Single-cache-line operations in C-callable inline assembly.
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* Essentially macro versions (uppercase) of:
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*
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* xthal_icache_line_invalidate(void *addr);
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* xthal_icache_line_lock(void *addr);
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* xthal_icache_line_unlock(void *addr);
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* xthal_icache_sync(void);
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*
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* NOTE: unlike the above functions, the following macros do NOT
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* execute the xthal_icache_sync() as part of each line operation.
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* This sync must be called explicitly by the caller. This is to
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* allow better optimization when operating on more than one line.
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*
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* xthal_dcache_line_invalidate(void *addr);
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* xthal_dcache_line_writeback(void *addr);
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* xthal_dcache_line_writeback_inv(void *addr);
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* xthal_dcache_line_lock(void *addr);
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* xthal_dcache_line_unlock(void *addr);
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* xthal_dcache_sync(void);
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* xthal_dcache_line_prefetch_for_write(void *addr);
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* xthal_dcache_line_prefetch_for_read(void *addr);
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*
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* All are made memory-barriers, given that's how they're typically used
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* (ops operate on a whole line, so clobbers all memory not just *addr).
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*
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* NOTE: All the block block cache ops and line prefetches are implemented
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* using intrinsics so they are better optimized regarding memory barriers etc.
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*
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* All block downgrade functions exist in two forms: with and without
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* the 'max' parameter: This parameter allows compiler to optimize
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* the functions whenever the parameter is smaller than the cache size.
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*
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* xthal_dcache_block_invalidate(void *addr, unsigned size);
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* xthal_dcache_block_writeback(void *addr, unsigned size);
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* xthal_dcache_block_writeback_inv(void *addr, unsigned size);
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* xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
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* xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
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* xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
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*
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* xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
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* xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
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*
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* xthal_dcache_block_wait();
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* xthal_dcache_block_required_wait();
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* xthal_dcache_block_abort();
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* xthal_dcache_block_prefetch_end();
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* xthal_dcache_block_newgrp();
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*/
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/*** INSTRUCTION CACHE ***/
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#define XTHAL_USE_CACHE_MACROS
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#if XCHAL_ICACHE_SIZE > 0
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# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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#else
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# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0)
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#endif
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#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
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# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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#else
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# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0)
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# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0)
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#endif
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/*
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* Even if a config doesn't have caches, an isync is still needed
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* when instructions in any memory are modified, whether by a loader
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* or self-modifying code. Therefore, this macro always produces
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* an isync, whether or not an icache is present.
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*/
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#define xthal_icache_sync() \
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__asm__ __volatile__("isync":::"memory")
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/*** DATA CACHE ***/
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#if XCHAL_DCACHE_SIZE > 0
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# include <xtensa/tie/xt_datacache.h>
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# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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# define xthal_dcache_sync() \
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__asm__ __volatile__("" /*"dsync"?*/:::"memory")
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# define xthal_dcache_line_prefetch_for_read(addr) do { \
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XT_DPFR((const int*)addr, 0); \
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} while(0)
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#else
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# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
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# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
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# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0)
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# define xthal_dcache_sync() __asm__ __volatile__("":::"memory")
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# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0)
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#endif
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#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
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# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \
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__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \
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} while(0)
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#else
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# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0)
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# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0)
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#endif
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#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
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# define xthal_dcache_line_prefetch_for_write(addr) do { \
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XT_DPFW((const int*)addr, 0); \
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} while(0)
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#else
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# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0)
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#endif
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/***** Block Operations *****/
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#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
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/* upgrades */
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# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \
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{ \
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type((const int*)addr, size); \
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}
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/*downgrades */
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# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
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unsigned _s = size; \
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unsigned _a = addr; \
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do { \
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unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
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XCHAL_DCACHE_SIZE : _s; \
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type((const int*)_a, __s); \
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_s -= __s; \
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_a += __s; \
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} while(_s > 0);
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# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
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if (max <= XCHAL_DCACHE_SIZE) { \
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unsigned _s = size; \
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unsigned _a = addr; \
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type((const int*)_a, _s); \
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} \
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else { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \
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}
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# define xthal_dcache_block_invalidate(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \
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} while(0)
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# define xthal_dcache_block_writeback(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \
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} while(0)
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# define xthal_dcache_block_writeback_inv(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \
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} while(0)
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# define xthal_dcache_block_invalidate_max(addr, size, max) do { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \
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} while(0)
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# define xthal_dcache_block_writeback_max(addr, size, max) do { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \
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} while(0)
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# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \
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_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \
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} while(0)
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/* upgrades that are performed even with write-thru caches */
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# define xthal_dcache_block_prefetch_read_write(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
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} while(0)
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# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
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} while(0)
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# define xthal_dcache_block_prefetch_for_read(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \
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} while(0)
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# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \
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} while(0)
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/* abort all or end optional block cache operations */
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# define xthal_dcache_block_abort() do { \
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XT_PFEND_A(); \
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} while(0)
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# define xthal_dcache_block_end() do { \
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XT_PFEND_O(); \
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} while(0)
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/* wait for all/required block cache operations to finish */
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# define xthal_dcache_block_wait() do { \
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XT_PFWAIT_A(); \
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} while(0)
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# define xthal_dcache_block_required_wait() do { \
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XT_PFWAIT_R(); \
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} while(0)
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/* Start a new group */
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# define xthal_dcache_block_newgrp() do { \
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XT_PFNXT_F(); \
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} while(0)
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#else
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# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0)
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# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0)
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# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_end() do {/*nothing*/} while(0)
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# define xthal_dcache_block_abort() do {/*nothing*/} while(0)
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# define xthal_dcache_block_wait() do {/*nothing*/} while(0)
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# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0)
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# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0)
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#endif
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#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
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# define xthal_dcache_block_prefetch_for_write(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
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} while(0)
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# define xthal_dcache_block_prefetch_modify(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \
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} while(0)
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# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
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} while(0)
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# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \
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_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \
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} while(0)
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#else
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# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0)
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# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0)
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#endif
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/*************************** INTERRUPTS ***************************/
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/*
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* Macro versions of:
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* unsigned xthal_get_intenable( void );
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* void xthal_set_intenable( unsigned );
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* unsigned xthal_get_interrupt( void );
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* void xthal_set_intset( unsigned );
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* void xthal_set_intclear( unsigned );
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* unsigned xthal_get_ccount(void);
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* void xthal_set_ccompare(int, unsigned);
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* unsigned xthal_get_ccompare(int);
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*
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* NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
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*/
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#if XCHAL_HAVE_INTERRUPTS
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# define XTHAL_GET_INTENABLE() ({ int __intenable; \
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__asm__("rsr.intenable %0" : "=a"(__intenable)); \
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__intenable; })
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# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
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__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
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} while(0)
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# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
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__asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
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__interrupt; })
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# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
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__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
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} while(0)
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# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \
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__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
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} while(0)
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# define XTHAL_GET_CCOUNT() ({ int __ccount; \
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__asm__("rsr.ccount %0" : "=a"(__ccount)); \
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__ccount; })
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# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
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__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
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} while(0)
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# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
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__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
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__ccompare; })
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# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n)
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# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
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__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
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} while(0)
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# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
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#else
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# define XTHAL_GET_INTENABLE() 0
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# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0)
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# define XTHAL_GET_INTERRUPT() 0
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# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0)
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# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0)
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# define XTHAL_GET_CCOUNT() 0
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# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0)
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# define XTHAL_GET_CCOMPARE(n) 0
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# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
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#endif
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/*************************** MISC ***************************/
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/*
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* Macro or inline versions of:
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* void xthal_clear_regcached_code( void );
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* unsigned xthal_get_prid( void );
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* unsigned xthal_compare_and_set( int *addr, int testval, int setval );
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*/
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#if XCHAL_HAVE_LOOPS
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# define XTHAL_CLEAR_REGCACHED_CODE() \
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__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
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#else
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# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0)
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#endif
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#if XCHAL_HAVE_PRID
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# define XTHAL_GET_PRID() ({ int __prid; \
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__asm__("rsr.prid %0" : "=a"(__prid)); \
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__prid; })
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#else
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# define XTHAL_GET_PRID() 0
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#endif
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static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
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{
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int result;
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#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
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__asm__ __volatile__ (
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" wsr.scompare1 %2 \n"
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" s32c1i %0, %3, 0 \n"
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: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
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: "memory");
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#elif XCHAL_HAVE_INTERRUPTS
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int tmp;
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__asm__ __volatile__ (
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" rsil %4, 15 \n" // %4 == saved ps
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" l32i %0, %3, 0 \n" // %0 == value to test, return val
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" bne %2, %0, 9f \n" // test
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" s32i %1, %3, 0 \n" // write the new value
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"9: wsr.ps %4 ; rsync \n" // restore the PS
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: "=a"(result)
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: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
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: "memory");
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#else
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__asm__ __volatile__ (
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" l32i %0, %3, 0 \n" // %0 == value to test, return val
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" bne %2, %0, 9f \n" // test
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" s32i %1, %3, 0 \n" // write the new value
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"9: \n"
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: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
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: "memory");
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#endif
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return result;
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}
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#if XCHAL_HAVE_EXTERN_REGS
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static inline unsigned XTHAL_RER (unsigned int reg)
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{
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unsigned result;
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__asm__ __volatile__ (
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" rer %0, %1"
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: "=a" (result) : "a" (reg) : "memory");
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return result;
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}
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static inline void XTHAL_WER (unsigned reg, unsigned value)
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{
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__asm__ __volatile__ (
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" wer %0, %1"
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: : "a" (value), "a" (reg) : "memory");
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}
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#endif /* XCHAL_HAVE_EXTERN_REGS */
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#endif /* C code */
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#endif /*XTENSA_CACHE_H*/
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