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53 lines
1.9 KiB
Plaintext
53 lines
1.9 KiB
Plaintext
/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.common.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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/*
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*
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* Automatically generated file; DO NOT EDIT.
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* Espressif IoT Development Framework Configuration
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*
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*/
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + 0x0,
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len = 0x50000 - 0x0 - 0x0
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + 0,
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len = 0x1000 - 0
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}
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000 - 0x0;
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