esp-idf/components/esp32/Kconfig

menu "ESP32-specific"
    # TODO: this component simply shouldn't be included
    # in the build at the CMake level, but this is currently
    # not working so we just hide all items here
    visible if IDF_TARGET_ESP32

    config ESP32_ECO3_CACHE_LOCK_FIX
        bool
        default y
        depends on !FREERTOS_UNICORE && ESP32_SPIRAM_SUPPORT

    config ESP32_DPORT_WORKAROUND
        bool
        default "y" if !FREERTOS_UNICORE  && ESP32_REV_MIN < 2

        # Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM
        # instead
    config ESP32_SPIRAM_SUPPORT
        bool "Support for external, SPI-connected RAM"
        default "n"
        select SPIRAM
        help
            This enables support for an external SPI RAM chip, connected in parallel with the
            main SPI flash chip.

    menu "SPI RAM config"
        depends on ESP32_SPIRAM_SUPPORT

        config SPIRAM_MODE_QUAD
            bool
            default "y"

        choice SPIRAM_TYPE
            prompt "Type of SPI RAM chip in use"
            default SPIRAM_TYPE_AUTO

            config SPIRAM_TYPE_AUTO
                bool "Auto-detect"

            config SPIRAM_TYPE_ESPPSRAM16
                bool "ESP-PSRAM16 or APS1604"

            config SPIRAM_TYPE_ESPPSRAM32
                bool "ESP-PSRAM32"

            config SPIRAM_TYPE_ESPPSRAM64
                bool "ESP-PSRAM64 or LY68L6400"

        endchoice

        config SPIRAM_SIZE
            int
            default -1 if SPIRAM_TYPE_AUTO
            default 2097152 if SPIRAM_TYPE_ESPPSRAM16
            default 4194304 if SPIRAM_TYPE_ESPPSRAM32
            default 8388608 if SPIRAM_TYPE_ESPPSRAM64
            default 0

        choice SPIRAM_SPEED
            prompt "Set RAM clock speed"
            default SPIRAM_SPEED_40M
            help
                Select the speed for the SPI RAM chip.
                If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:

                1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
                2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
                3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz

                Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
                will be occupied by the system. Which SPI host to use can be selected by the config item
                SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
                option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
                (ESPTOOLPY_FLASHFREQ_80M is true)

            config SPIRAM_SPEED_40M
                bool "40MHz clock speed"
            config SPIRAM_SPEED_80M
                depends on ESPTOOLPY_FLASHFREQ_80M
                bool "80MHz clock speed"
        endchoice

        # insert non-chip-specific items here
        source "$IDF_PATH/components/esp_hw_support/Kconfig.spiram.common"

        config SPIRAM_CACHE_WORKAROUND
            bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
            depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
            default "y"
            help
                Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
                when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
                fix in the compiler (-mfix-esp32-psram-cache-issue) that makes sure the specific code that is
                vulnerable to this will not be emitted.

                This will also not use any bits of newlib that are located in ROM, opting for a version that is
                compiled with the workaround and located in flash instead.

                The workaround is not required for ESP32 revision 3 and above.

        menu "SPIRAM cache workaround debugging"

            choice SPIRAM_CACHE_WORKAROUND_STRATEGY
                prompt "Workaround strategy"
                depends on SPIRAM_CACHE_WORKAROUND
                default SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
                help
                    Select the workaround strategy. Note that the strategy for precompiled
                    libraries (libgcc, newlib, bt, wifi) is not affected by this selection.

                    Unless you know you need a different strategy, it's suggested you stay
                    with the default MEMW strategy. Note that DUPLDST can interfere with hardware
                    encryption and this will be automatically disabled if this workaround is selected.
                    'Insert nops' is the workaround that was used in older esp-idf versions. This workaround
                    still can cause faulty data transfers from/to SPI RAM in some situation.

                config SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW
                    bool "Insert memw after vulnerable instructions (default)"

                config SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
                    bool "Duplicate LD/ST for 32-bit, memw for 8/16 bit"

                config SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS
                    bool "Insert nops between vulnerable loads/stores (old strategy, obsolete)"
            endchoice

            #This needs to be Y only for the dupldst workaround
            config SPIRAM_WORKAROUND_NEED_VOLATILE_SPINLOCK
                bool
                default "y" if SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST
        endmenu

        menu "SPIRAM workaround libraries placement"
            visible if SPIRAM_CACHE_WORKAROUND

            config SPIRAM_CACHE_LIBJMP_IN_IRAM
                bool "Put libc's jump related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: longjmp and setjmp.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBMATH_IN_IRAM
                bool "Put libc's math related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: abs, div, labs, ldiv, quorem, fpclassify,
                    and nan.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM
                bool "Put libc's number parsing related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: utoa, itoa, atoi, atol, strtol, and strtoul.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBIO_IN_IRAM
                bool "Put libc's I/O related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: wcrtomb, fvwrite, wbuf, wsetup, fputwc, wctomb_r,
                    ungetc, makebuf, fflush, refill, and sccl.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBTIME_IN_IRAM
                bool "Put libc's time related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: asctime, asctime_r, ctime, ctime_r, lcltime, lcltime_r,
                    gmtime, gmtime_r, strftime, mktime, tzset_r, tzset, time, gettzinfo, systimes, month_lengths,
                    timelocal, tzvars, tzlock, tzcalc_limits, and strptime.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBCHAR_IN_IRAM
                bool "Put libc's characters related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: ctype_, toupper, tolower, toascii, strupr, bzero,
                    isalnum, isalpha, isascii, isblank, iscntrl, isdigit, isgraph, islower, isprint, ispunct,
                    isspace, and isupper.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBMEM_IN_IRAM
                bool "Put libc's memory related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: memccpy, memchr memmove, and memrchr.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBSTR_IN_IRAM
                bool "Put libc's string related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: strcasecmp, strcasestr, strchr, strcoll,
                    strcpy, strcspn, strdup, strdup_r, strlcat, strlcpy, strlen, strlwr, strncasecmp,
                    strncat, strncmp, strncpy, strndup, strndup_r, strrchr, strsep, strspn, strstr,
                    strtok_r, and strupr.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBRAND_IN_IRAM
                bool "Put libc's random related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: srand, rand, and rand_r.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBENV_IN_IRAM
                bool "Put libc's environment related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: environ, envlock, and getenv_r.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBFILE_IN_IRAM
                bool "Put libc's file related functions in IRAM"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: lock, isatty, fclose, open, close, creat, read,
                    rshift, sbrk, stdio, syssbrk, sysclose, sysopen, creat, sysread, syswrite, impure, fwalk,
                    and findfp.
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.

            config SPIRAM_CACHE_LIBMISC_IN_IRAM
                bool "Put libc's miscellaneous functions in IRAM, see help"
                depends on SPIRAM_CACHE_WORKAROUND
                default "y"
                help
                    The functions affected by this option are: raise and system
                    Putting these function in IRAM will allow them to be called when flash cache is disabled
                    but it will also reduce the available size of free IRAM for the user application.
        endmenu

        config SPIRAM_BANKSWITCH_ENABLE
            bool "Enable bank switching for >4MiB external RAM"
            default y
            depends on SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
            help
                The ESP32 only supports 4MiB of external RAM in its address space. The hardware does support larger
                memories, but these have to be bank-switched in and out of this address space. Enabling this allows you
                to reserve some MMU pages for this, which allows the use of the esp_himem api to manage these banks.

                #Note that this is limited to 62 banks, as esp_spiram_writeback_cache needs some kind of mapping of
                #some banks below that mark to work. We cannot at this moment guarantee this to exist when himem is
                #enabled.

                If spiram 2T mode is enabled, the size of 64Mbit psram will be changed as 32Mbit, so himem will be
                unusable.
        config SPIRAM_BANKSWITCH_RESERVE
            int "Amount of 32K pages to reserve for bank switching"
            depends on SPIRAM_BANKSWITCH_ENABLE
            default 8
            range 1 62
            help
                Select the amount of banks reserved for bank switching. Note that the amount of RAM allocatable with
                malloc/esp_heap_alloc_caps will decrease by 32K for each page reserved here.

                Note that this reservation is only actually done if your program actually uses the himem API. Without
                any himem calls, the reservation is not done and the original amount of memory will be available
                to malloc/esp_heap_alloc_caps.

        config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
            bool "Allow external memory as an argument to xTaskCreateStatic"
            default n
            depends on SPIRAM_USE_MALLOC
            help
                Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
                normally tasks cannot be safely run with their stack residing in external memory; for this reason
                xTaskCreate (and related task creaton functions) always allocate stack in internal memory and
                xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that
                needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no
                Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external
                memory.

        choice SPIRAM_OCCUPY_SPI_HOST
            prompt "SPI host to use for 32MBit PSRAM"
            default SPIRAM_OCCUPY_VSPI_HOST
            depends on SPIRAM_SPEED_80M
            help
                When both flash and PSRAM is working under 80MHz, and the PSRAM is of type 32MBit, one of the HSPI/VSPI
                host will be used to output the clock. Select which one to use here.

            config SPIRAM_OCCUPY_HSPI_HOST
                bool "HSPI host (SPI2)"
            config SPIRAM_OCCUPY_VSPI_HOST
                bool "VSPI host (SPI3)"
            config SPIRAM_OCCUPY_NO_HOST
                bool "Will not try to use any host, will abort if not able to use the PSRAM"

        endchoice

        menu "PSRAM clock and cs IO for ESP32-DOWD"

            config D0WD_PSRAM_CLK_IO
                int "PSRAM CLK IO number"
                depends on ESP32_SPIRAM_SUPPORT
                range 0 33
                default 17
                help
                    The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
                    1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

            config D0WD_PSRAM_CS_IO
                int "PSRAM CS IO number"
                depends on ESP32_SPIRAM_SUPPORT
                range 0 33
                default 16
                help
                    The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
                    1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
        endmenu

        menu "PSRAM clock and cs IO for ESP32-D2WD"

            config D2WD_PSRAM_CLK_IO
                int "PSRAM CLK IO number"
                depends on ESP32_SPIRAM_SUPPORT
                range 0 33
                default 9
                help
                    User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
                    so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

            config D2WD_PSRAM_CS_IO
                int "PSRAM CS IO number"
                depends on ESP32_SPIRAM_SUPPORT
                range 0 33
                default 10
                help
                    User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
                    so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
        endmenu

        menu "PSRAM clock and cs IO for ESP32-PICO"

            config PICO_PSRAM_CS_IO
                int "PSRAM CS IO number"
                depends on ESP32_SPIRAM_SUPPORT
                range 0 33
                default 10
                help
                    The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.

                    For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
                    IO.
                    For the reference hardware design, please refer to
                    https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf

        endmenu

        config SPIRAM_CUSTOM_SPIWP_SD3_PIN
            bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
            default y if SPIRAM_SPIWP_SD3_PIN != 7  # backwards compatibility, can remove in IDF 5
            default n
            help
                This setting is only used if the SPI flash pins have been overridden by setting the eFuses
                SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.

                When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
                ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
                mode, so a WP pin setting is necessary.

                If this config item is set to N (default), the correct WP pin will be automatically used for any
                Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
                to Y and specify the GPIO number connected to the WP pin.

                When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
                configured in the bootloader.

        config SPIRAM_SPIWP_SD3_PIN
            int "Custom SPI PSRAM WP(SD3) Pin"
            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT)
            #depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN  # backwards compatibility, can uncomment in IDF 5
            range 0 33
            default 7
            help
                The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored

                If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
                value to the GPIO number of the SPIRAM WP pin.

        config SPIRAM_2T_MODE
            bool "Enable SPI PSRAM 2T mode"
            depends on ESP32_SPIRAM_SUPPORT
            default "n"
            help
                Enable this option to fix single bit errors inside 64Mbit PSRAM.

                Some 64Mbit PSRAM chips have a hardware issue in the RAM which causes bit errors at multiple
                fixed bit positions.

                Note: If this option is enabled, the 64Mbit PSRAM chip will appear to be 32Mbit in size.
                Applications will not be affected unless the use the esp_himem APIs, which are not supported
                in 2T mode.

    endmenu # "SPI RAM config"

    config ESP32_MEMMAP_TRACEMEM
        bool
        default "n"

    config ESP32_MEMMAP_TRACEMEM_TWOBANKS
        bool
        default "n"

    config ESP32_TRAX
        bool "Use TRAX tracing feature"
        default "n"
        select ESP32_MEMMAP_TRACEMEM
        help
            The ESP32 contains a feature which allows you to trace the execution path the processor
            has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
            of memory that can't be used for general purposes anymore. Disable this if you do not know
            what this is.

    config ESP32_TRAX_TWOBANKS
        bool "Reserve memory for tracing both pro as well as app cpu execution"
        default "n"
        depends on ESP32_TRAX && !FREERTOS_UNICORE
        select ESP32_MEMMAP_TRACEMEM_TWOBANKS
        help
            The ESP32 contains a feature which allows you to trace the execution path the processor
            has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
            of memory that can't be used for general purposes anymore. Disable this if you do not know
            what this is.

            # Memory to reverse for trace, used in linker script
    config ESP32_TRACEMEM_RESERVE_DRAM
        hex
        default 0x8000 if ESP32_MEMMAP_TRACEMEM && ESP32_MEMMAP_TRACEMEM_TWOBANKS
        default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
        default 0x0

    config ESP32_DEEP_SLEEP_WAKEUP_DELAY
        int "Extra delay in deep sleep wake stub (in us)"
        default 2000
        range 0 5000
        help
            When ESP32 exits deep sleep, the CPU and the flash chip are powered on
            at the same time. CPU will run deep sleep stub first, and then
            proceed to load code from flash. Some flash chips need sufficient
            time to pass between power on and first read operation. By default,
            without any extra delay, this time is approximately 900us, although
            some flash chip types need more than that.

            By default extra delay is set to 2000us. When optimizing startup time
            for applications which require it, this value may be reduced.

            If you are seeing "flash read err, 1000" message printed to the
            console after deep sleep reset, try increasing this value.

    choice ESP32_XTAL_FREQ_SEL
        prompt "Main XTAL frequency"
        default ESP32_XTAL_FREQ_40
        help
            ESP32 currently supports the following XTAL frequencies:

            - 26 MHz
            - 40 MHz

            Startup code can automatically estimate XTAL frequency. This feature
            uses the internal 8MHz oscillator as a reference. Because the internal
            oscillator frequency is temperature dependent, it is not recommended
            to use automatic XTAL frequency detection in applications which need
            to work at high ambient temperatures and use high-temperature
            qualified chips and modules.
        config ESP32_XTAL_FREQ_40
            bool "40 MHz"
        config ESP32_XTAL_FREQ_26
            bool "26 MHz"
        config ESP32_XTAL_FREQ_AUTO
            bool "Autodetect"
    endchoice

    # Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
    config ESP32_XTAL_FREQ
        int
        default 0 if ESP32_XTAL_FREQ_AUTO
        default 40 if ESP32_XTAL_FREQ_40
        default 26 if ESP32_XTAL_FREQ_26

    config ESP32_DISABLE_BASIC_ROM_CONSOLE
        bool "Permanently disable BASIC ROM Console"
        default n
        help
            If set, the first time the app boots it will disable the BASIC ROM Console
            permanently (by burning an eFuse).

            Otherwise, the BASIC ROM Console starts on reset if no valid bootloader is
            read from the flash.

            (Enabling secure boot also disables the BASIC ROM Console by default.)

    config ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
        bool "App compatible with bootloaders before ESP-IDF v2.1"
        select ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
        default n
        help
            Bootloaders before ESP-IDF v2.1 did less initialisation of the
            system clock. This setting needs to be enabled to build an app
            which can be booted by these older bootloaders.

            If this setting is enabled, the app can be booted by any bootloader
            from IDF v1.0 up to the current version.

            If this setting is disabled, the app can only be booted by bootloaders
            from IDF v2.1 or newer.

            Enabling this setting adds approximately 1KB to the app's IRAM usage.

    config ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS
        bool "App compatible with bootloader and partition table before ESP-IDF v3.1"
        default n
        help
            Partition tables before ESP-IDF V3.1 do not contain an MD5 checksum
            field, and the bootloader before ESP-IDF v3.1 cannot read a partition
            table that contains an MD5 checksum field.

            Enable this option only if your app needs to boot on a bootloader and/or
            partition table that was generated from a version *before* ESP-IDF v3.1.

            If this option and Flash Encryption are enabled at the same time, and any
            data partitions in the partition table are marked Encrypted, then the
            partition encrypted flag should be manually verified in the app before accessing
            the partition (see CVE-2021-27926).

    config ESP32_APP_INIT_CLK
        bool
        default y if ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
        default y if APP_BUILD_TYPE_ELF_RAM

    config ESP32_RTCDATA_IN_FAST_MEM
        bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
        default n
        depends on FREERTOS_UNICORE
        help
            This option allows to place .rtc_data and .rtc_rodata sections into
            RTC fast memory segment to free the slow memory region for ULP programs.
            This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
            can be accessed only by PRO_CPU core.

    config ESP32_USE_FIXED_STATIC_RAM_SIZE
        bool "Use fixed static RAM size"
        default n
        help
            If this option is disabled, the DRAM part of the heap starts right after the .bss section,
            within the dram0_0 region. As a result, adding or removing some static variables
            will change the available heap size.

            If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
            where its length is set with ESP32_FIXED_STATIC_RAM_SIZE

    config ESP32_FIXED_STATIC_RAM_SIZE
        hex "Fixed Static RAM size"
        default 0x1E000
        range 0 0x2c200
        depends on ESP32_USE_FIXED_STATIC_RAM_SIZE
        help
            RAM size dedicated for static variables (.data & .bss sections).
            Please note that the actual length will be reduced by BTDM_RESERVE_DRAM if Bluetooth
            controller is enabled.

    config ESP32_DPORT_DIS_INTERRUPT_LVL
        int "Disable the interrupt level for the DPORT workarounds"
        default 5
        help
            To prevent interrupting DPORT workarounds,
            need to disable interrupt with a maximum used level in the system.

    config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
        bool "Enable IRAM as 8 bit accessible memory"
        depends on FREERTOS_UNICORE
        help
            If enabled, application can use IRAM as byte accessible region for storing data
            (Note: IRAM region cannot be used as task stack)

            This is possible due to handling of exceptions `LoadStoreError (3)` and `LoadStoreAlignmentError (9)`
            Each unaligned read/write access will incur a penalty of maximum of 167 CPU cycles.

endmenu  # ESP32-Specific