2018-10-24 11:17:56 +08:00
										 
									 
								 
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								Communication with ESP SDIO Slave
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								====================================
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								.. _esp_slave_init:
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								ESP SDIO slave initialization
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								------------------------------
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											2019-12-09 11:01:09 +08:00
										 
									 
								 
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								The host should initialize the {IDF_TARGET_NAME} SDIO slave according to the standard
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											2018-10-24 11:17:56 +08:00
										 
									 
								 
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								SDIO initialization process (Sector 3.1.2 of `SDIO Simplified
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								Specification <https://www.sdcard.org/downloads/pls/>`_). In this specification
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								and below, the SDIO slave is also called an (SD)IO card. All the
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								initialization CMD52 and CMD53 are sent to Func 0 (CIA region). Here is an
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								brief example on how to do this:
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								1. SDIO reset
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								    CMD52 (Write 0x6=0x8)
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								2. SD reset
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								    CMD0
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								3. Check whether IO card (optional)
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								    CMD8
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								4. Send SDIO op cond and wait for card ready
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								    CMD5 arg = 0x00000000
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								    CMD5 arg = 0x00ff8000 (according to the response above, poll until ready)
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								    **Example:**
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								        Arg of R4 after first CMD5 (arg=0x00000000) is 0xXXFFFF00.
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								        Keep sending CMD5 with arg=0x00FFFF00 until the R4 shows card ready (arg bit 31=1).
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								5. Set address
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								    CMD3
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								6. Select card
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								    CMD7 (arg address according to CMD3 response)
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								    **Example:**
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								        Arg of R6 after CMD3 is 0x0001xxxx.
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								        Arg of CMD7 should be 0x00010000.
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								7. Select 4-bit mode (optional)
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								    CMD52 (Write 0x07=0x02)
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								8. Enable func1
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								    CMD52 (Write 0x02=0x02)
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								9. Enable SDIO interrupt (required if interrupt line (DAT1) is used)
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								    CMD52 (Write 0x04=0x03)
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								10. Set Func0 blocksize (optional, default value is 512 (0x200))
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								     CMD52/53 (Read 0x10~0x11)
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								     CMD52/53 (Write 0x10=0x00)
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								     CMD52/53 (Write 0x11=0x02)
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								     CMD52/53 (Read 0x10~0x11, read to check the final value)
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								11. Set Func1 blocksize (optional, default value is 512 (0x200))
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								     CMD52/53 (Read 0x110~0x111)
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								     CMD52/53 (Write 0x110=0x00)
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								     CMD52/53 (Write 0x111=0x02)
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								     CMD52/53 (Read 0x110~0x111, read to check the final value)
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								.. _esp_slave_protocol_layer:
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											2017-12-04 20:05:09 +08:00
										 
									 
								 
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								ESP SDIO slave protocol
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											2018-10-24 11:17:56 +08:00
										 
									 
								 
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								-----------------------
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								The protocol is based on Function 1 access by CMD52 and CMD53, offering 3 services: (1) sending and receiving FIFO, (2) 52 8-bit R/W
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											2019-09-28 18:14:24 +08:00
										 
									 
								 
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								register shared by host and slave, (3) 8 general purpose interrupt sources from host to slave and 8 in the opposite direction.
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								There is a component `esp_serial_slave_link` implementing the logic of this protocol for
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								ESP32 master to communicate with the ESP32 slave. See :doc:`/api-reference/protocols/esp_serial_slave_link`.
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								The host should access the registers below as described to communicate with slave.
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								Slave register table
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								^^^^^^^^^^^^^^^^^^^^
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								32-bit
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								#######
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								- 0x044 (TOKEN_RDATA): in which bit 27-16 holds the receiving buffer number.
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								- 0x058 (INT_ST): holds the interrupt source bits from slave to host.
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								- 0x060 (PKT_LEN): holds the accumulated length (by byte) to be sent from slave to host.
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								- 0x0D4 (INT_CLR): write 1 to clear interrupt bits corresponding to INT_ST.
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								- 0x0DC (INT_ENA): mask bits for interrupts from slave to host.
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								8-bit
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								#####
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								Shared general purpose registers:
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								- 0x06C-0x077: R/W registers 0-11 shared by slave and host.
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								- 0x07A-0x07B: R/W registers 14-15 shared by slave and host.
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								- 0x07E-0x07F: R/W registers 18-19 shared by slave and host.
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								- 0x088-0x08B: R/W registers 24-27 shared by slave and host.
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								- 0x09C-0x0BB: R/W registers 32-63 shared by slave and host.
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								Interrupt Registers:
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								- 0x08D (SLAVE_INT): bits for host to interrupt slave. auto clear.
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								FIFO (sending and receiving)
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								############################
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								0x090 - 0x1F7FF are reserved for FIFOs.
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											2018-06-22 16:21:03 +08:00
										 
									 
								 
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								The address of CMD53 is related to the length requested to read from/write to
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								the slave in a single transfer:
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								    *requested length = 0x1F800-address*
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								The slave will respond with the length according to the length field in
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								CMD53, with the data longer than *requested length* filled with 0 (sending)
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								or discard (receiving).
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								.. note:: This includes both the block and the byte mode of CMD53.
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								    The function number should be set to 1, OP Code should be set to 1 (for CMD53).
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								    It is allowed to use CMD53 mode combination of block+byte to get higher
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								    effeciency when accessing the FIFO by arbitrary length. E.g. The block
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								    size is set to 512 by default, you can write/get 1031 bytes of data
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								    to/from the FIFO by:
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								    1. Send CMD53 in block mode, block count=2 (1024 bytes) to address
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								       0x1F3F9=0x1F800-**1031**.
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								    2. Then send CMD53 in byte mode, byte count=8 (or 7 if your controller
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								       supports that) to address 0x1F7F9=0x1F800-**7**.
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								Interrupts
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								^^^^^^^^^^
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								For the host interrupts, the slave raise the interrupt by pulling DAT1 line down at a proper time (level sensitive).
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								The host detect this and read the INT_ST register to see the source. Then the host can clear it by writing the INT_CLR
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								register and do something with the interrupt. The host can also mask unneeded sources by clearing the bits in INT_ENA
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								register corresponding to the sources. If all the sources are cleared (or masked), the DAT1 line goes inactive.
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								``sdio_slave_hostint_t`` (:doc:`sdio_slave`) shows the bit definition corresponding to host interrupt sources.
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								For the slave interrupts, the host send transfers to write the SLAVE_INT register. Once a bit is written from 0 to 1,
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								the slave hardware and driver will detect it and inform the app.
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								Receiving FIFO
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								^^^^^^^^^^^^^^
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								To write the receiving FIFO in the slave, host should work in the following steps:
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								1. Read the TOKEN1 field (bits 27-16) of TOKEN_RDATA (0x044) register. The buffer number remaining is TOKEN1 minus
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								   the number of buffers used by host.
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								2. Make sure the buffer number is sufficient (*recv_buffer_size* * *buffer_num* is greater than data to write, *recv_buffer_size*
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								   is pre-defined between the host and the slave before the communication starts). Or go back to step 1 until the buffer
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								   is enough.
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								3. Write to the FIFO address with CMD53. Note that the *requested length* should not be larger than calculated in step 2,
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								   and the FIFO address is related to *rquested length*.
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								4. Calculate used buffers, note that non-full buffer at the tail should be seen as one that is used.
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								Sending FIFO
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								^^^^^^^^^^^^
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								To read the sending FIFO in the slave, host should work in the following steps:
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								1. Wait for the interrupt line to be active (optional, low by default).
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								2. Read (poll) the interrupt bits in INT_ST register to see whether new packets exists.
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								3. If new packets are ready, reads the PKT_LEN reg. The data length to read from slave is PKT_LEN minuses the length
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								   that has been read from the host. If the PKT_LEN is not larger than used, wait and poll until the slave is ready and
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								   update the PKT_LEN.
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								4. Read from the FIFO with CMD53. Note that the *requested length* should not be larger than calculated in step3, and
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								   the FIFO address is related to *requested length*.
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								5. Recored read length.
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