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27 lines
1.0 KiB
Plaintext
27 lines
1.0 KiB
Plaintext
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menu "ESP-Driver:I3C Master Configurations"
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depends on SOC_I3C_MASTER_SUPPORTED
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config I3C_MASTER_ISR_CACHE_SAFE
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bool "I3C ISR Cache-Safe"
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select I3C_MASTER_ISR_HANDLER_IN_IRAM
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select GDMA_ISR_HANDLER_IN_IRAM if SOC_GDMA_SUPPORTED
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default n
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help
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Ensure the I3C interrupt is Cache-Safe by allowing the interrupt handler to be
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executable when the cache is disabled (e.g. SPI Flash write).
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config I3C_MASTER_ENABLE_DEBUG_LOG
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bool "Enable I3C debug log"
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default n
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help
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whether to enable the debug log message for I3C driver.
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Note that this option only controls the I3C driver log, will not affect other drivers.
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config I3C_MASTER_ISR_HANDLER_IN_IRAM
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bool "Place I3C master ISR handler into IRAM"
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select GDMA_CTRL_FUNC_IN_IRAM if SOC_GDMA_SUPPORTED
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default n
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help
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Place I3C master ISR handler into IRAM for better performance and fewer cache misses.
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endmenu # I3C Master Configurations
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