components/espcoredump/component.mk

COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_SRCDIRS := src
COMPONENT_PRIV_INCLUDEDIRS := include_core_dump
COMPONENT_ADD_LDFRAGMENTS += linker.lf

ifdef CONFIG_IDF_TARGET_ARCH_XTENSA
	COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/xtensa
endif

ifdef CONFIG_IDF_TARGET_ARCH_RISCV
	COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/riscv
endif
coredump: improvements refactoring Move existing core dump files into espcoredump component folder Add KConfig, linker.lf, make and CMakeList.txt for new component Existing functionality separated into core_dump_common, core_dump_flash, core_dump_uart Update test_core_dump.c and make files to link it as unit test Update according to review: Move target and RTOS related functionality into separated file (core_dump_port.c). 2019-01-29 15:49:56 +01:00			`COMPONENT_ADD_INCLUDEDIRS := include`
			`COMPONENT_SRCDIRS := src`
			`COMPONENT_PRIV_INCLUDEDIRS := include_core_dump`
Whitespace: Automated whitespace fixes (large commit) Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace) 2020-11-10 18:40:01 +11:00			`COMPONENT_ADD_LDFRAGMENTS += linker.lf`
espcoredump: code refactoring and add support for RISC-V implemetation This commit includes the refactoring of the core dump feature. Thanks to this refactoring, it is easier to integrate the support of RISC-V architecture for this feature. Fixes ESP-1758 2020-12-14 11:10:29 +08:00
			`ifdef CONFIG_IDF_TARGET_ARCH_XTENSA`
			`COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/xtensa`
			`endif`

			`ifdef CONFIG_IDF_TARGET_ARCH_RISCV`
			`COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/riscv`
			`endif`