2022-08-03 15:22:49 +02:00
										 
									 
								 
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								/*
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								 * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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								 *
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								 * SPDX-License-Identifier: Apache-2.0
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								 */
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											2019-09-26 00:22:36 +08:00
										 
									 
								 
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								#include "soc/interrupts.h"
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								const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
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								    [0] = "WIFI_MAC",
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								    [1] = "WIFI_NMI",
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								    [2] = "WIFI_BB",
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								    [3] = "BT_MAC",
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								    [4] = "BT_BB",
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								    [5] = "BT_BB_NMI",
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								    [6] = "RWBT",
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								    [7] = "RWBLE",
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								    [8] = "RWBT_NMI",
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								    [9] = "RWBLE_NMI",
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								    [10] = "SLC0",
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								    [11] = "SLC1",
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								    [12] = "UHCI0",
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								    [13] = "UHCI1",
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								    [14] = "TG0_T0_LEVEL",
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								    [15] = "TG0_T1_LEVEL",
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								    [16] = "TG0_WDT_LEVEL",
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								    [17] = "TG0_LACT_LEVEL",
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								    [18] = "TG1_T0_LEVEL",
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								    [19] = "TG1_T1_LEVEL",
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								    [20] = "TG1_WDT_LEVEL",
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								    [21] = "TG1_LACT_LEVEL",
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								    [22] = "GPIO",
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								    [23] = "GPIO_NMI",
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								    [24] = "FROM_CPU0",
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								    [25] = "FROM_CPU1",
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								    [26] = "FROM_CPU2",
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								    [27] = "FROM_CPU3",
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								    [28] = "SPI0",
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								    [29] = "SPI1",
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								    [30] = "SPI2",
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								    [31] = "SPI3",
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								    [32] = "I2S0",
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								    [33] = "I2S1",
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								    [34] = "UART0",
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								    [35] = "UART1",
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								    [36] = "UART2",
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								    [37] = "SDIO_HOST",
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								    [38] = "ETH_MAC",
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								    [39] = "PWM0",
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								    [40] = "PWM1",
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								    [41] = "RESERVED",
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								    [42] = "RESERVED",
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								    [43] = "LEDC",
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								    [44] = "EFUSE",
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								    [45] = "TWAI",
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								    [46] = "RTC_CORE",
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								    [47] = "RMT",
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								    [48] = "PCNT",
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								    [49] = "I2C_EXT0",
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								    [50] = "I2C_EXT1",
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								    [51] = "RSA",
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								    [52] = "SPI1_DMA",
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								    [53] = "SPI2_DMA",
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								    [54] = "SPI3_DMA",
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								    [55] = "WDT",
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								    [56] = "TIMER1",
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								    [57] = "TIMER2",
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								    [58] = "TG0_T0_EDGE",
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								    [59] = "TG0_T1_EDGE",
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								    [60] = "TG0_WDT_EDGE",
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								    [61] = "TG0_LACT_EDGE",
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								    [62] = "TG1_T0_EDGE",
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								    [63] = "TG1_T1_EDGE",
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								    [64] = "TG1_WDT_EDGE",
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								    [65] = "TG1_LACT_EDGE",
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								    [66] = "MMU_IA",
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								    [67] = "MPU_IA",
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								    [68] = "CACHE_IA",
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								};
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