2024-02-07 16:56:53 +08:00
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gdma_periph.h"
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#include "soc/gdma_reg.h"
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const gdma_signal_conn_t gdma_periph_signals = {
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.groups = {
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[0] = {
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.module = PERIPH_GDMA_MODULE,
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.pairs = {
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[0] = {
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.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
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},
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[1] = {
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.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
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},
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[2] = {
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.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
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}
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}
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}
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}
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};
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#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
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/* GDMA Channel (Group0, Pair0) Registers Context
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Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
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GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
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GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
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GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
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*/
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#define G0P0_RETENTION_REGS_CNT_0 13
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#define G0P0_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH0_REG
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#define G0P0_RETENTION_REGS_CNT_1 2
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#define G0P0_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG
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static const uint32_t g0p0_regs_map0[4] = {0x4C801001, 0x604C0060, 0, 0};
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static const uint32_t g0p0_regs_map1[4] = {0x3, 0, 0, 0};
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static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
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G0P0_RETENTION_REGS_CNT_0, 0, 0, \
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g0p0_regs_map0[0], g0p0_regs_map0[1], \
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g0p0_regs_map0[2], g0p0_regs_map0[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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2024-05-15 19:07:58 +08:00
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[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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2024-02-07 16:56:53 +08:00
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G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
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G0P0_RETENTION_REGS_CNT_1, 0, 0, \
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g0p0_regs_map1[0], g0p0_regs_map1[1], \
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g0p0_regs_map1[2], g0p0_regs_map1[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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};
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/* GDMA Channel (Group0, Pair1) Registers Context
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Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
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GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
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GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
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GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
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*/
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#define G0P1_RETENTION_REGS_CNT_0 13
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#define G0P1_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH1_REG
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#define G0P1_RETENTION_REGS_CNT_1 2
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#define G0P1_RETENTION_MAP_BASE_1 GDMA_BT_TX_SEL_REG
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static const uint32_t g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604};
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static const uint32_t g0p1_regs_map1[4] = {0x3, 0, 0, 0};
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static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
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G0P1_RETENTION_REGS_CNT_0, 0, 0, \
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g0p1_regs_map0[0], g0p1_regs_map0[1], \
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g0p1_regs_map0[2], g0p1_regs_map0[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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2024-05-15 19:07:58 +08:00
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[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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2024-02-07 16:56:53 +08:00
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G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
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G0P1_RETENTION_REGS_CNT_1, 0, 0, \
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g0p1_regs_map1[0], g0p1_regs_map1[1], \
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g0p1_regs_map1[2], g0p1_regs_map1[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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};
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/* GDMA Channel (Group0, Pair2) Registers Context
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Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
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GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
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GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
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GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
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*/
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#define G0P2_RETENTION_REGS_CNT_0 6
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#define G0P2_RETENTION_MAP_BASE_0 GDMA_IN_INT_ENA_CH2_REG
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#define G0P2_RETENTION_REGS_CNT_1 9
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#define G0P2_RETENTION_MAP_BASE_1 GDMA_IN_PRI_CH2_REG
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static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
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static const uint32_t g0p2_regs_map1[4] = {0xf026003, 0, 0, 0};
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static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
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G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
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G0P2_RETENTION_REGS_CNT_0, 0, 0, \
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g0p2_regs_map0[0], g0p2_regs_map0[1], \
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g0p2_regs_map0[2], g0p2_regs_map0[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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2024-05-15 19:07:58 +08:00
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[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
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2024-02-07 16:56:53 +08:00
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G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
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G0P2_RETENTION_REGS_CNT_1, 0, 0, \
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g0p2_regs_map1[0], g0p2_regs_map1[1], \
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g0p2_regs_map1[2], g0p2_regs_map1[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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};
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2024-04-23 20:11:32 +08:00
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const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
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2024-02-07 16:56:53 +08:00
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[0] = {
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[0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
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[1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
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[2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
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}
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};
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#endif
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