mirror of
https://github.com/espressif/esp-idf.git
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252 lines
11 KiB
C
252 lines
11 KiB
C
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/*
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* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*----------------------------------------------------------------------------------
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This file contains ESP32 and ESP32S2 Depricated ADC APIs and functions
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-----------------------------------------------------------------------------------*/
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#include "sdkconfig.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "driver/rtc_io.h"
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#include "hal/adc_hal.h"
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#include "hal/adc_ll.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal_conf.h"
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#ifdef CONFIG_PM_ENABLE
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#include "esp_pm.h"
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#endif
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#include "freertos/FreeRTOS.h"
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#include "driver/adc_i2s_legacy.h"
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#include "driver/adc_types_legacy.h"
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static __attribute__((unused)) const char *ADC_TAG = "ADC";
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#define ADC_CHECK_RET(fun_ret) ({ \
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if (fun_ret != ESP_OK) { \
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ESP_LOGE(ADC_TAG,"%s:%d\n",__FUNCTION__,__LINE__); \
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return ESP_FAIL; \
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} \
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})
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#define ADC_CHECK(a, str, ret_val) ({ \
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if (!(a)) { \
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ESP_LOGE(ADC_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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} \
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})
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#define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG)
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t adc_digi_arbiter_lock = NULL;
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#endif //CONFIG_PM_ENABLE
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#if CONFIG_IDF_TARGET_ESP32
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/*---------------------------------------------------------------
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ESP32 Depricated ADC APIs and functions
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---------------------------------------------------------------*/
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#define DIG_ADC_OUTPUT_FORMAT_DEFUALT (ADC_DIGI_FORMAT_12BIT)
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#define DIG_ADC_ATTEN_DEFUALT (ADC_ATTEN_DB_11)
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#define DIG_ADC_BIT_WIDTH_DEFUALT (3) //3 for ADC_WIDTH_BIT_12
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/**
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* @brief ADC digital controller (DMA mode) conversion rules setting.
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*/
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typedef struct {
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union {
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struct {
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uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements.
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0: measurement range 0 - 800mV,
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1: measurement range 0 - 1100mV,
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2: measurement range 0 - 1350mV,
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3: measurement range 0 - 2600mV. */
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uint8_t bit_width: 2; /*!< ADC resolution.
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- 0: 9 bit;
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- 1: 10 bit;
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- 2: 11 bit;
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- 3: 12 bit. */
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int8_t channel: 4; /*!< ADC channel index. */
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};
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uint8_t val; /*!<Raw data value */
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};
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} adc_digi_pattern_table_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format option.
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*/
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typedef enum {
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ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`). Note: For single convert mode. */
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ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`). Note: For multi or alter convert mode. */
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ADC_DIGI_FORMAT_MAX,
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} adc_digi_format_t;
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/**
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* Explanation of the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA outputs:
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*
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* +---------------------+--------+--------+--------+
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* | conv_mode | single | both | alter |
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* +---------------------+--------+--------+--------+
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* | trigger meas times | 1 | 1 | 1 |
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* +---------------------+--------+--------+--------+
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* | conv_limit_num | +1 | +1 | +1 |
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* | dma_eof_num | +1 | +2 | +1 |
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* | dma output (byte) | +2 | +4 | +2 |
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* +---------------------+--------+--------+--------+
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*/
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typedef struct {
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uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
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The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
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resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
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pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
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uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
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adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
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adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
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adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
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adc_digi_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_format_t``. */
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} adc_digi_config_t;
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/**
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* Set adc output 16-bit-data format from digital controller.
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*
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* @param data_sel 1: [15] unit, [14:11] channel, [10:0] data, 11-bit-width at most. Only work under `ADC_LL_DIGI_CONV_BOTH_UNIT` or `ADC_LL_DIGI_CONV_ALTER_UNIT` mode.
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* 0: [15:12] channel, [11:0] data, 12-bit-width at most. Only work under `ADC_LL_DIGI_CONV_ONLY_ADC1` or `ADC_LL_DIGI_CONV_ONLY_ADC2` mode
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* @note see `adc_ll_digi_pattern_table_t` for more detail of data bit width
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*/
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static inline void adc_ll_digi_set_output_format(bool data_sel)
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{
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SYSCON.saradc_ctrl.data_sar_sel = data_sel;
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}
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static inline void adc_ll_digi_prepare_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern)
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{
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uint32_t tab;
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uint8_t index = pattern_index / 4;
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uint8_t offset = (pattern_index % 4) * 8;
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if (adc_n == ADC_UNIT_1) {
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tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
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tab &= (~(0xFF000000 >> offset)); // clear old data
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tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
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SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back
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} else { // adc_n == ADC_UNIT_2
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tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value
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tab &= (~(0xFF000000 >> offset)); // clear old data
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tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
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SYSCON.saradc_sar2_patt_tab[index] = tab; // Write back
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}
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}
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static void adc_digi_controller_reg_set(const adc_digi_config_t *cfg)
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{
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/* On ESP32, only support ADC1 */
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switch (cfg->conv_mode) {
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case ADC_CONV_SINGLE_UNIT_1:
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adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC1);
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break;
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case ADC_CONV_SINGLE_UNIT_2:
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adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC2);
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break;
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case ADC_CONV_BOTH_UNIT:
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adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
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break;
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case ADC_CONV_ALTER_UNIT:
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adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ALTER_UNIT);
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break;
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default:
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abort();
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}
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
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adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
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if (cfg->adc1_pattern_len) {
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adc_ll_digi_clear_pattern_table(ADC_UNIT_1);
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, cfg->adc1_pattern_len);
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for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) {
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adc_ll_digi_prepare_pattern_table(ADC_UNIT_1, i, cfg->adc1_pattern[i]);
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}
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}
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}
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if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
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adc_ll_set_controller(ADC_UNIT_2, ADC_LL_CTRL_DIG);
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if (cfg->adc2_pattern_len) {
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adc_ll_digi_clear_pattern_table(ADC_UNIT_2);
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adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, cfg->adc2_pattern_len);
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for (uint32_t i = 0; i < cfg->adc2_pattern_len; i++) {
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adc_ll_digi_prepare_pattern_table(ADC_UNIT_2, i, cfg->adc2_pattern[i]);
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}
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}
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}
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adc_ll_digi_set_output_format(cfg->format);
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adc_ll_digi_convert_limit_enable(ADC_LL_DEFAULT_CONV_LIMIT_EN);
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adc_ll_digi_set_convert_limit_num(ADC_LL_DEFAULT_CONV_LIMIT_NUM);
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adc_ll_digi_set_data_source(ADC_I2S_DATA_SRC_ADC);
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}
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esp_err_t adc_set_i2s_data_source(adc_i2s_source_t src)
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{
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ADC_CHECK((src == ADC_I2S_DATA_SRC_IO_SIG || src == ADC_I2S_DATA_SRC_ADC), "ADC i2s data source error", ESP_ERR_INVALID_ARG);
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ADC_ENTER_CRITICAL();
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adc_ll_digi_set_data_source(src);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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extern esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel);
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esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
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{
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if (adc_unit == ADC_UNIT_1) {
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ADC_CHANNEL_CHECK(ADC_UNIT_1, channel);
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} else if (adc_unit == ADC_UNIT_2) {
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//ADC2 does not support DMA mode
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ADC_CHECK(false, "ADC2 not support DMA for now.", ESP_ERR_INVALID_ARG);
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ADC_CHANNEL_CHECK(ADC_UNIT_2, channel);
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}
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adc_digi_pattern_table_t adc1_pattern[1];
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adc_digi_pattern_table_t adc2_pattern[1];
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adc_digi_config_t dig_cfg = {
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.format = DIG_ADC_OUTPUT_FORMAT_DEFUALT,
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.conv_mode = ADC_CONV_SINGLE_UNIT_1,
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};
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if (adc_unit == ADC_UNIT_1) {
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adc1_pattern[0].atten = DIG_ADC_ATTEN_DEFUALT;
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adc1_pattern[0].bit_width = DIG_ADC_BIT_WIDTH_DEFUALT;
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adc1_pattern[0].channel = channel;
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dig_cfg.adc1_pattern_len = 1;
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dig_cfg.adc1_pattern = adc1_pattern;
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} else if (adc_unit == ADC_UNIT_2) {
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adc2_pattern[0].atten = DIG_ADC_ATTEN_DEFUALT;
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adc2_pattern[0].bit_width = DIG_ADC_BIT_WIDTH_DEFUALT;
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adc2_pattern[0].channel = channel;
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dig_cfg.adc2_pattern_len = 1;
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dig_cfg.adc2_pattern = adc2_pattern;
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}
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adc_common_gpio_init(adc_unit, channel);
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ADC_ENTER_CRITICAL();
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adc_ll_digi_set_fsm_time(ADC_HAL_FSM_RSTB_WAIT_DEFAULT, ADC_HAL_FSM_START_WAIT_DEFAULT,
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ADC_HAL_FSM_STANDBY_WAIT_DEFAULT);
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adc_ll_set_sample_cycle(ADC_HAL_SAMPLE_CYCLE_DEFAULT);
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adc_hal_pwdet_set_cct(ADC_HAL_PWDET_CCT_DEFAULT);
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adc_ll_digi_output_invert(ADC_UNIT_1, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_1));
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adc_ll_digi_output_invert(ADC_UNIT_2, ADC_HAL_DIGI_DATA_INVERT_DEFAULT(ADC_UNIT_2));
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adc_ll_digi_set_clk_div(ADC_HAL_DIGI_SAR_CLK_DIV_DEFAULT);
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adc_digi_controller_reg_set(&dig_cfg);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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#endif //#if CONFIG_IDF_TARGET_ESP32
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