mirror of
https://github.com/espressif/esp-idf.git
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81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "soc/interrupts.h"
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const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
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[0] = "WIFI_MAC",
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[1] = "WIFI_NMI",
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[2] = "WIFI_PWR",
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[3] = "WIFI_BB",
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[4] = "BT_MAC",
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[5] = "BT_BB",
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[6] = "BT_BB_NMI",
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[7] = "RWBT",
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[8] = "RWBLE",
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[9] = "RWBT_NMI",
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[10] = "RWBLE_NMI",
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[11] = "I2C",
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[12] = "SLC0",
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[13] = "SLC1",
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[14] = "APB_CTRL",
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[15] = "UHCI0",
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[16] = "GPIO",
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[17] = "GPIO_NMI",
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[18] = "SPI1",
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[19] = "SPI2",
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[20] = "I2S1",
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[21] = "UART0",
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[22] = "UART1",
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[23] = "LEDC",
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[24] = "EFUSE",
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[25] = "CAN",
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[26] = "USB",
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[27] = "RTC_CORE",
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[28] = "RMT",
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[29] = "I2C_EXT0",
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[30] = "TIMER1",
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[31] = "TIMER2",
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[32] = "TG0_T0_LEVEL",
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[33] = "TG0_WDT_LEVEL",
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[34] = "TG1_T0_LEVEL",
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[35] = "TG1_WDT_LEVEL",
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[36] = "CACHE_IA",
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[37] = "SYSTIMER_TARGET0_EDGE",
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[38] = "SYSTIMER_TARGET1_EDGE",
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[39] = "SYSTIMER_TARGET2_EDGE",
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[40] = "SPI_MEM_REJECT_CACHE",
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[41] = "ICACHE_PRELOAD0",
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[42] = "ICACHE_SYNC0",
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[43] = "APB_ADC",
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[44] = "DMA_CH0",
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[45] = "DMA_CH1",
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[46] = "DMA_CH2",
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[47] = "RSA",
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[48] = "AES",
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[49] = "SHA",
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[50] = "ETS_FROM_CPU_INTR0",
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[51] = "ETS_FROM_CPU_INTR1",
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[52] = "ETS_FROM_CPU_INTR2",
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[53] = "ETS_FROM_CPU_INTR3",
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[54] = "ETS_ASSIST_DEBUG",
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[55] = "ETS_DMA_APBPERI_PMS",
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[56] = "ETS_CORE0_IRAM0_PMS",
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[57] = "ETS_CORE0_DRAM0_PMS",
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[58] = "ETS_CORE0_PIF_PMS",
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[59] = "ETS_CORE0_PIF_PMS_SIZE",
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[60] = "ETS_BAK_PMS_VIOLATE",
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[61] = "ETS_CACHE_CORE0_ACS",
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};
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