mirror of
https://github.com/espressif/esp-idf.git
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72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
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/*
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* Copyright (c) 2001 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* simboard.h - Xtensa ISS "Board" specific definitions */
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#ifndef _INC_SIMBOARD_H_
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#define _INC_SIMBOARD_H_
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#include <xtensa/config/core.h>
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#include <xtensa/config/system.h>
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/*
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* Device addresses.
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*/
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/* System ROM: */
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#define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE
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#ifdef XSHAL_ROM_VADDR
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#define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR
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#endif
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#ifdef XSHAL_ROM_PADDR
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#define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR
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#endif
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/* System RAM: */
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#define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE
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#ifdef XSHAL_RAM_VADDR
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#define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR
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#endif
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#ifdef XSHAL_RAM_PADDR
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#define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR
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#endif
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/*
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* Things that depend on device addresses.
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*/
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#define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK
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#define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC
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#define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU
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#define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS
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#define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT
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#define XTBOARD_BUSINT_PIPE_REGIONS 0
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#define XTBOARD_BUSINT_SDRAM_REGIONS 0
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#endif /*_INC_SIMBOARD_H_*/
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