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										 |  |  | /*
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							|  |  |  |  * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * SPDX-License-Identifier: Apache-2.0 | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | #include "soc/gpio_periph.h"
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										 |  |  | #include "esp_attr.h"
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										 |  |  | const uint32_t GPIO_PIN_MUX_REG[] = { | 
					
						
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										 |  |  |     IO_MUX_GPIO0_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO1_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO2_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO3_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO4_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO5_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO6_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO7_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO8_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO9_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO10_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO11_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO12_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO13_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO14_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO15_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO16_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO17_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO18_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO19_REG, | 
					
						
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										 |  |  |     IO_MUX_GPIO20_REG, // This corresponding pin is only available on ESP32-PICO-V3 chip package
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										 |  |  |     IO_MUX_GPIO21_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO22_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO23_REG, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     IO_MUX_GPIO25_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO26_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO27_REG, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     IO_MUX_GPIO32_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO33_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO34_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO35_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO36_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO37_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO38_REG, | 
					
						
							|  |  |  |     IO_MUX_GPIO39_REG, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | DRAM_ATTR const uint8_t GPIO_PIN_MUX_REG_OFFSET[] = { | 
					
						
							|  |  |  |     0x44, | 
					
						
							|  |  |  |     0x88, | 
					
						
							|  |  |  |     0x40, | 
					
						
							|  |  |  |     0x84, | 
					
						
							|  |  |  |     0x48, | 
					
						
							|  |  |  |     0x6c, | 
					
						
							|  |  |  |     0x60, | 
					
						
							|  |  |  |     0x64, | 
					
						
							|  |  |  |     0x68, | 
					
						
							|  |  |  |     0x54, | 
					
						
							|  |  |  |     0x58, | 
					
						
							|  |  |  |     0x5c, | 
					
						
							|  |  |  |     0x34, | 
					
						
							|  |  |  |     0x38, | 
					
						
							|  |  |  |     0x30, | 
					
						
							|  |  |  |     0x3c, | 
					
						
							|  |  |  |     0x4c, | 
					
						
							|  |  |  |     0x50, | 
					
						
							|  |  |  |     0x70, | 
					
						
							|  |  |  |     0x74, | 
					
						
							|  |  |  |     0x78, | 
					
						
							|  |  |  |     0x7c, | 
					
						
							|  |  |  |     0x80, | 
					
						
							|  |  |  |     0x8c, | 
					
						
							|  |  |  |     0xFF, // 24
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							|  |  |  |     0x24, | 
					
						
							|  |  |  |     0x28, | 
					
						
							|  |  |  |     0x2c, | 
					
						
							|  |  |  |     0xFF, // 28
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							|  |  |  |     0xFF, // 29
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							|  |  |  |     0xFF, // 30
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							|  |  |  |     0xFF, // 31
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							|  |  |  |     0x1c, | 
					
						
							|  |  |  |     0x20, | 
					
						
							|  |  |  |     0x14, | 
					
						
							|  |  |  |     0x18, | 
					
						
							|  |  |  |     0x04, | 
					
						
							|  |  |  |     0x08, | 
					
						
							|  |  |  |     0x0c, | 
					
						
							|  |  |  |     0x10, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); | 
					
						
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							|  |  |  | const uint32_t GPIO_HOLD_MASK[] = { | 
					
						
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										 |  |  |     0, | 
					
						
							|  |  |  |     BIT(1), | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     BIT(0), | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     BIT(8), | 
					
						
							|  |  |  |     BIT(2), | 
					
						
							|  |  |  |     BIT(3), | 
					
						
							|  |  |  |     BIT(4), | 
					
						
							|  |  |  |     BIT(5), | 
					
						
							|  |  |  |     BIT(6), | 
					
						
							|  |  |  |     BIT(7), | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     BIT(9), | 
					
						
							|  |  |  |     BIT(10), | 
					
						
							|  |  |  |     BIT(11), | 
					
						
							|  |  |  |     BIT(12), | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     BIT(14), | 
					
						
							|  |  |  |     BIT(15), | 
					
						
							|  |  |  |     BIT(16), | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  |     0, | 
					
						
							|  |  |  | }; | 
					
						
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							|  |  |  | _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); |