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esp-idf/components/efuse/esp32/esp_efuse_table.csv

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efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
efuse: Add MAX_BLK_LEN define for changing len of field Added docs, improved efuse_table_gen.py, and minor fixes Checking the generated files for compliance with the coding scheme.
2018-12-12 15:50:31 +08:00
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
# | EFUSE_BLK2 | | | #
# | EFUSE_BLK3) | | | #
##########################################################################
efuse: Fix to pass CI tests
2018-12-18 22:42:10 +08:00
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
# !!!!!!!!!!! #
efuse: update the scheme of getting chip revision
2019-07-29 11:35:00 +08:00
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# Factory MAC address #
#######################
MAC_FACTORY, EFUSE_BLK0, 72, 8, Factory MAC addr [0]
, EFUSE_BLK0, 64, 8, Factory MAC addr [1]
, EFUSE_BLK0, 56, 8, Factory MAC addr [2]
, EFUSE_BLK0, 48, 8, Factory MAC addr [3]
, EFUSE_BLK0, 40, 8, Factory MAC addr [4]
, EFUSE_BLK0, 32, 8, Factory MAC addr [5]
MAC_FACTORY_CRC, EFUSE_BLK0, 80, 8, CRC8 for factory MAC address
# Custom MAC address #
######################
MAC_CUSTOM_CRC, EFUSE_BLK3, 0, 8, CRC8 for custom MAC address.
MAC_CUSTOM, EFUSE_BLK3, 8, 48, Custom MAC
MAC_CUSTOM_VER, EFUSE_BLK3, 184, 8, Custom MAC version
# Security boot #
#################
efuse: Add MAX_BLK_LEN define for changing len of field Added docs, improved efuse_table_gen.py, and minor fixes Checking the generated files for compliance with the coding scheme.
2018-12-12 15:50:31 +08:00
SECURE_BOOT_KEY, EFUSE_BLK2, 0, MAX_BLK_LEN, Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
ESP32 SecureBoot V2: eFuse write operations are updated to use the eFuse Manager APIs Closes IDF-2034 Closes https://github.com/espressif/esp-idf/issues/5771
2020-08-23 01:30:46 +05:30
ABS_DONE_0, EFUSE_BLK0, 196, 1, Secure boot V1 is enabled for bootloader image. EFUSE_RD_ABS_DONE_0
ABS_DONE_1, EFUSE_BLK0, 197, 1, Secure boot V2 is enabled for bootloader image. EFUSE_RD_ABS_DONE_1
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
# Flash encrypt #
#################
efuse: Add MAX_BLK_LEN define for changing len of field Added docs, improved efuse_table_gen.py, and minor fixes Checking the generated files for compliance with the coding scheme.
2018-12-12 15:50:31 +08:00
ENCRYPT_FLASH_KEY, EFUSE_BLK1, 0, MAX_BLK_LEN, Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
ENCRYPT_CONFIG, EFUSE_BLK0, 188, 4, Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M
efuse: update the scheme of getting chip revision
2019-07-29 11:35:00 +08:00
DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT.
DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT.
DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE.
efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field 8th bit is not used by hardware. As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894
2019-03-29 10:28:42 +11:00
FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT.
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
efuse: Add 'disable Download Mode' & ESP32-S2 'Secure Download Mode' functionality
2020-04-25 16:36:53 +10:00
# Misc Security #
DISABLE_JTAG, EFUSE_BLK0, 198, 1, Disable JTAG. EFUSE_RD_DISABLE_JTAG.
CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE.
UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, Disable UART download mode. Valid for ESP32 V3 and newer, only.
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
# Write protection #
####################
ESP32 SecureBoot V2: eFuse write operations are updated to use the eFuse Manager APIs Closes IDF-2034 Closes https://github.com/espressif/esp-idf/issues/5771
2020-08-23 01:30:46 +05:30
WR_DIS_EFUSE_RD_DISABLE,EFUSE_BLK0, 0, 1, Write protection for EFUSE_RD_DISABLE
efuse: Add 'disable Download Mode' & ESP32-S2 'Secure Download Mode' functionality
2020-04-25 16:36:53 +10:00
WR_DIS_FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, Flash encrypt. Write protection FLASH_CRYPT_CNT, UART_DOWNLOAD_DIS. EFUSE_WR_DIS_FLASH_CRYPT_CNT
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
WR_DIS_BLK1, EFUSE_BLK0, 7, 1, Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1
WR_DIS_BLK2, EFUSE_BLK0, 8, 1, Security boot. Write protection security key. EFUSE_WR_DIS_BLK2
WR_DIS_BLK3, EFUSE_BLK0, 9, 1, Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3
# Read protection #
###################
RD_DIS_BLK1, EFUSE_BLK0, 16, 1, Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1
efuse: update the scheme of getting chip revision
2019-07-29 11:35:00 +08:00
RD_DIS_BLK2, EFUSE_BLK0, 17, 1, Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
RD_DIS_BLK3, EFUSE_BLK0, 18, 1, Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3
# Chip info #
#############
CHIP_VER_DIS_APP_CPU, EFUSE_BLK0, 96, 1, EFUSE_RD_CHIP_VER_DIS_APP_CPU
CHIP_VER_DIS_BT, EFUSE_BLK0, 97, 1, EFUSE_RD_CHIP_VER_DIS_BT
efuse/esp32: Expands PKG_VER from 3 bit to 4 bits Closes: IDF-1919
2020-08-05 14:56:01 +08:00
CHIP_VER_PKG, EFUSE_BLK0, 105, 3, EFUSE_RD_CHIP_VER_PKG least significant bits
, EFUSE_BLK0, 98, 1, EFUSE_RD_CHIP_VER_PKG_4BIT most significant bit
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW
CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED
CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1
efuse: update the scheme of getting chip revision
2019-07-29 11:35:00 +08:00
CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2
efuse: Add API efuse Added support 3/4 coding scheme
2018-11-19 11:46:21 +08:00
XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG
SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH
SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE
#SDIO_DREFH, EFUSE_BLK0, 136, 2, EFUSE_RD_SDIO_DREFH
#SDIO_DREFM, EFUSE_BLK0, 138, 2, EFUSE_RD_SDIO_DREFM
#SDIO_DREFL, EFUSE_BLK0, 140, 2, EFUSE_RD_SDIO_DREFL
# esp_adc_cal #
###############
ADC_VREF_AND_SDIO_DREF, EFUSE_BLK0, 136, 6, EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1], SDIO_DREFM[2 3], SDIO_DREFL[4 5] )
ADC1_TP_LOW, EFUSE_BLK3, 96, 7, TP_REG EFUSE_RD_ADC1_TP_LOW
ADC2_TP_LOW, EFUSE_BLK3, 112, 7, TP_REG EFUSE_RD_ADC2_TP_LOW
ADC1_TP_HIGH, EFUSE_BLK3, 103, 9, TP_REG EFUSE_RD_ADC1_TP_HIGH
ADC2_TP_HIGH, EFUSE_BLK3, 119, 9, TP_REG EFUSE_RD_ADC2_TP_HIGH
efuse: Add support coding scheme to script Added support using BLK1 and BLK2 in custom table. Added change size key in BLK1 and BLK2 if coding scheme was changed.
2018-11-21 16:09:36 +08:00
# anti-rollback #
#################
SECURE_VERSION, EFUSE_BLK3, 128, 32, Secure version for anti-rollback
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