esp-idf/components/esp_hw_support/linker.lf

[mapping:esp_hw_support]
archive: libesp_hw_support.a
entries:
    cpu_util (noflash_text)
    if IDF_TARGET_ESP32S2 = y:
        regi2c_ctrl (noflash)
    rtc_clk (noflash)
    rtc_init:rtc_vddsdio_set_config (noflash)
    rtc_pm (noflash_text)
    rtc_sleep (noflash_text)
    rtc_time (noflash_text)
    if IDF_TARGET_ESP32C3 = n && IDF_TARGET_ESP32H2 = n && IDF_TARGET_ESP8684 = n:
        rtc_wdt (noflash_text)
    if IDF_TARGET_ESP32S3 = y:
        if SPIRAM_MODE_QUAD = y:
            spiram_psram (noflash)
        if SPIRAM_MODE_OCT = y:
            opiram_psram (noflash)
soc: move implementations to esp_hw_support 2020-09-25 15:23:52 +08:00			`[mapping:esp_hw_support]`
			`archive: libesp_hw_support.a`
			`entries:`
			`cpu_util (noflash_text)`
rtc: compile the regi2c_ctrl.c code to iram 2020-10-21 20:26:10 +08:00			`if IDF_TARGET_ESP32S2 = y:`
			`regi2c_ctrl (noflash)`
soc: move implementations to esp_hw_support 2020-09-25 15:23:52 +08:00			`rtc_clk (noflash)`
			`rtc_init:rtc_vddsdio_set_config (noflash)`
			`rtc_pm (noflash_text)`
			`rtc_sleep (noflash_text)`
			`rtc_time (noflash_text)`
ESP8684: add spi_flash, efuse, hw_support support 2021-11-06 17:23:21 +08:00			`if IDF_TARGET_ESP32C3 = n && IDF_TARGET_ESP32H2 = n && IDF_TARGET_ESP8684 = n:`
ci: enabled ldgen mapping check in ci 2020-11-12 23:17:17 +08:00			`rtc_wdt (noflash_text)`
psram: put opiram_psram and spiram_psram in internal ram External memory is accessed via SPI0. When modifying the SPI0 registers, should put the code in internal RAM. Otherwise when there is an ongoing SPI0 transaction, CPU changes the SPI0 registers. This is dangerous. Besides, modifying SPI0 registers may lead external memory to an unstable state. Therefore putting these code in internal RAM is necessary. 2021-09-27 10:41:07 +08:00			`if IDF_TARGET_ESP32S3 = y:`
			`if SPIRAM_MODE_QUAD = y:`
			`spiram_psram (noflash)`
			`if SPIRAM_MODE_OCT = y:`
			`opiram_psram (noflash)`