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# field_name , | efuse_block , | bit_start , | bit_count , |comment #
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# | (EFUSE_BLK0 | (0..255) | (1-256) | #
# | EFUSE_BLK1 | | | #
# | ...) | | | #
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##########################################################################
# !!!!!!!!!!! #
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# After editing this file , run the command manually "idf.py efuse-common-table"
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# this will generate new source files , next rebuild all the sources.
# !!!!!!!!!!! #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: 73787d3f5ae45b80abca925a7562120b
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WR_DIS , EFUSE_BLK0 , 0 , 32 , [] Disable programming of individual eFuses
WR_DIS.RD_DIS , EFUSE_BLK0 , 0 , 1 , [] wr_dis of RD_DIS
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WR_DIS.KM_RND_SWITCH_CYCLE , EFUSE_BLK0 , 1 , 1 , [] wr_dis of KM_RND_SWITCH_CYCLE
WR_DIS.KM_DEPLOY_ONLY_ONCE , EFUSE_BLK0 , 1 , 1 , [] wr_dis of KM_DEPLOY_ONLY_ONCE
WR_DIS.FORCE_USE_KEY_MANAGER_KEY , EFUSE_BLK0 , 1 , 1 , [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
WR_DIS.FORCE_DISABLE_SW_INIT_KEY , EFUSE_BLK0 , 1 , 1 , [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
WR_DIS.XTS_KEY_LENGTH_256 , EFUSE_BLK0 , 1 , 1 , [] wr_dis of XTS_KEY_LENGTH_256
WR_DIS.LOCK_KM_KEY , EFUSE_BLK0 , 1 , 1 , [] wr_dis of LOCK_KM_KEY
WR_DIS.KM_DISABLE_DEPLOY_MODE , EFUSE_BLK0 , 1 , 1 , [] wr_dis of KM_DISABLE_DEPLOY_MODE
WR_DIS.DIS_USB_JTAG , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_USB_JTAG
WR_DIS.DIS_FORCE_DOWNLOAD , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_FORCE_DOWNLOAD
WR_DIS.SPI_DOWNLOAD_MSPI_DIS , EFUSE_BLK0 , 2 , 1 , [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
WR_DIS.DIS_TWAI , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_TWAI
WR_DIS.JTAG_SEL_ENABLE , EFUSE_BLK0 , 2 , 1 , [] wr_dis of JTAG_SEL_ENABLE
WR_DIS.DIS_PAD_JTAG , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_PAD_JTAG
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.WDT_DELAY_SEL , EFUSE_BLK0 , 2 , 1 , [] wr_dis of WDT_DELAY_SEL
WR_DIS.HYS_EN_PAD , EFUSE_BLK0 , 2 , 1 , [] wr_dis of HYS_EN_PAD
WR_DIS.PXA0_TIEH_SEL_0 , EFUSE_BLK0 , 2 , 1 , [] wr_dis of PXA0_TIEH_SEL_0
WR_DIS.PXA0_TIEH_SEL_1 , EFUSE_BLK0 , 2 , 1 , [] wr_dis of PXA0_TIEH_SEL_1
WR_DIS.PXA0_TIEH_SEL_2 , EFUSE_BLK0 , 2 , 1 , [] wr_dis of PXA0_TIEH_SEL_2
WR_DIS.PXA0_TIEH_SEL_3 , EFUSE_BLK0 , 2 , 1 , [] wr_dis of PXA0_TIEH_SEL_3
WR_DIS.DIS_WDT , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_WDT
WR_DIS.DIS_SWD , EFUSE_BLK0 , 2 , 1 , [] wr_dis of DIS_SWD
WR_DIS.HP_PWR_SRC_SEL , EFUSE_BLK0 , 3 , 1 , [] wr_dis of HP_PWR_SRC_SEL
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WR_DIS.SPI_BOOT_CRYPT_CNT , EFUSE_BLK0 , 4 , 1 , [] wr_dis of SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0 , EFUSE_BLK0 , 5 , 1 , [] wr_dis of SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1 , EFUSE_BLK0 , 6 , 1 , [] wr_dis of SECURE_BOOT_KEY_REVOKE1
WR_DIS.SECURE_BOOT_KEY_REVOKE2 , EFUSE_BLK0 , 7 , 1 , [] wr_dis of SECURE_BOOT_KEY_REVOKE2
WR_DIS.KEY_PURPOSE_0 , EFUSE_BLK0 , 8 , 1 , [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
WR_DIS.KEY_PURPOSE_1 , EFUSE_BLK0 , 9 , 1 , [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
WR_DIS.KEY_PURPOSE_2 , EFUSE_BLK0 , 10 , 1 , [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
WR_DIS.KEY_PURPOSE_3 , EFUSE_BLK0 , 11 , 1 , [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
WR_DIS.KEY_PURPOSE_4 , EFUSE_BLK0 , 12 , 1 , [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
WR_DIS.KEY_PURPOSE_5 , EFUSE_BLK0 , 13 , 1 , [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
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WR_DIS.SEC_DPA_LEVEL , EFUSE_BLK0 , 14 , 1 , [] wr_dis of SEC_DPA_LEVEL
WR_DIS.CRYPT_DPA_ENABLE , EFUSE_BLK0 , 14 , 1 , [] wr_dis of CRYPT_DPA_ENABLE
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WR_DIS.SECURE_BOOT_EN , EFUSE_BLK0 , 15 , 1 , [] wr_dis of SECURE_BOOT_EN
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WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE , EFUSE_BLK0 , 16 , 1 , [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.ECDSA_ENABLE_SOFT_K , EFUSE_BLK0 , 17 , 1 , [] wr_dis of ECDSA_ENABLE_SOFT_K
WR_DIS.FLASH_TYPE , EFUSE_BLK0 , 18 , 1 , [] wr_dis of FLASH_TYPE
WR_DIS.FLASH_PAGE_SIZE , EFUSE_BLK0 , 18 , 1 , [] wr_dis of FLASH_PAGE_SIZE
WR_DIS.FLASH_ECC_EN , EFUSE_BLK0 , 18 , 1 , [] wr_dis of FLASH_ECC_EN
WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE , EFUSE_BLK0 , 18 , 1 , [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
WR_DIS.FLASH_TPUW , EFUSE_BLK0 , 18 , 1 , [] wr_dis of FLASH_TPUW
WR_DIS.DIS_DOWNLOAD_MODE , EFUSE_BLK0 , 18 , 1 , [] wr_dis of DIS_DOWNLOAD_MODE
WR_DIS.DIS_DIRECT_BOOT , EFUSE_BLK0 , 18 , 1 , [] wr_dis of DIS_DIRECT_BOOT
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT , EFUSE_BLK0 , 18 , 1 , [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE , EFUSE_BLK0 , 18 , 1 , [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
WR_DIS.ENABLE_SECURITY_DOWNLOAD , EFUSE_BLK0 , 18 , 1 , [] wr_dis of ENABLE_SECURITY_DOWNLOAD
WR_DIS.UART_PRINT_CONTROL , EFUSE_BLK0 , 18 , 1 , [] wr_dis of UART_PRINT_CONTROL
WR_DIS.FORCE_SEND_RESUME , EFUSE_BLK0 , 18 , 1 , [] wr_dis of FORCE_SEND_RESUME
WR_DIS.SECURE_VERSION , EFUSE_BLK0 , 18 , 1 , [] wr_dis of SECURE_VERSION
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE , EFUSE_BLK0 , 18 , 1 , [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
WR_DIS.KM_HUK_GEN_STATE , EFUSE_BLK0 , 19 , 1 , [] wr_dis of KM_HUK_GEN_STATE
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WR_DIS.BLK1 , EFUSE_BLK0 , 20 , 1 , [] wr_dis of BLOCK1
WR_DIS.MAC , EFUSE_BLK0 , 20 , 1 , [WR_DIS.MAC_FACTORY] wr_dis of MAC
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WR_DIS.WAFER_VERSION_MINOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of WAFER_VERSION_MINOR
WR_DIS.WAFER_VERSION_MAJOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of WAFER_VERSION_MAJOR
WR_DIS.DISABLE_WAFER_VERSION_MAJOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
WR_DIS.DISABLE_BLK_VERSION_MAJOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of DISABLE_BLK_VERSION_MAJOR
WR_DIS.BLK_VERSION_MINOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of BLK_VERSION_MINOR
WR_DIS.BLK_VERSION_MAJOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of BLK_VERSION_MAJOR
WR_DIS.PSRAM_CAP , EFUSE_BLK0 , 20 , 1 , [] wr_dis of PSRAM_CAP
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WR_DIS.TEMP , EFUSE_BLK0 , 20 , 1 , [] wr_dis of TEMP
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WR_DIS.PSRAM_VENDOR , EFUSE_BLK0 , 20 , 1 , [] wr_dis of PSRAM_VENDOR
WR_DIS.PKG_VERSION , EFUSE_BLK0 , 20 , 1 , [] wr_dis of PKG_VERSION
WR_DIS.SYS_DATA_PART1 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of BLOCK2
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WR_DIS.LDO_VO1_DREF , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO1_DREF
WR_DIS.LDO_VO2_DREF , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO2_DREF
WR_DIS.LDO_VO1_MUL , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO1_MUL
WR_DIS.LDO_VO2_MUL , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO2_MUL
WR_DIS.LDO_VO3_K , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO3_K
WR_DIS.LDO_VO3_VOS , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO3_VOS
WR_DIS.LDO_VO3_C , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO3_C
WR_DIS.LDO_VO4_K , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO4_K
WR_DIS.LDO_VO4_VOS , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO4_VOS
WR_DIS.LDO_VO4_C , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LDO_VO4_C
WR_DIS.ACTIVE_HP_DBIAS , EFUSE_BLK0 , 20 , 1 , [] wr_dis of ACTIVE_HP_DBIAS
WR_DIS.ACTIVE_LP_DBIAS , EFUSE_BLK0 , 20 , 1 , [] wr_dis of ACTIVE_LP_DBIAS
WR_DIS.LSLP_HP_DBIAS , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LSLP_HP_DBIAS
WR_DIS.DSLP_DBG , EFUSE_BLK0 , 20 , 1 , [] wr_dis of DSLP_DBG
WR_DIS.DSLP_LP_DBIAS , EFUSE_BLK0 , 20 , 1 , [] wr_dis of DSLP_LP_DBIAS
WR_DIS.LP_DCDC_DBIAS_VOL_GAP , EFUSE_BLK0 , 20 , 1 , [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
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WR_DIS.OPTIONAL_UNIQUE_ID , EFUSE_BLK0 , 21 , 1 , [] wr_dis of OPTIONAL_UNIQUE_ID
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WR_DIS.ADC1_AVE_INITCODE_ATTEN0 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
WR_DIS.ADC1_AVE_INITCODE_ATTEN1 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
WR_DIS.ADC1_AVE_INITCODE_ATTEN2 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
WR_DIS.ADC1_AVE_INITCODE_ATTEN3 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
WR_DIS.ADC2_AVE_INITCODE_ATTEN0 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
WR_DIS.ADC2_AVE_INITCODE_ATTEN1 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
WR_DIS.ADC2_AVE_INITCODE_ATTEN2 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
WR_DIS.ADC2_AVE_INITCODE_ATTEN3 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
WR_DIS.ADC1_HI_DOUT_ATTEN0 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_HI_DOUT_ATTEN0
WR_DIS.ADC1_HI_DOUT_ATTEN1 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_HI_DOUT_ATTEN1
WR_DIS.ADC1_HI_DOUT_ATTEN2 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_HI_DOUT_ATTEN2
WR_DIS.ADC1_HI_DOUT_ATTEN3 , EFUSE_BLK0 , 21 , 1 , [] wr_dis of ADC1_HI_DOUT_ATTEN3
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WR_DIS.BLOCK_USR_DATA , EFUSE_BLK0 , 22 , 1 , [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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WR_DIS.CUSTOM_MAC , EFUSE_BLK0 , 22 , 1 , [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
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WR_DIS.BLOCK_KEY0 , EFUSE_BLK0 , 23 , 1 , [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
WR_DIS.BLOCK_KEY1 , EFUSE_BLK0 , 24 , 1 , [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
WR_DIS.BLOCK_KEY2 , EFUSE_BLK0 , 25 , 1 , [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
WR_DIS.BLOCK_KEY3 , EFUSE_BLK0 , 26 , 1 , [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
WR_DIS.BLOCK_KEY4 , EFUSE_BLK0 , 27 , 1 , [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
WR_DIS.BLOCK_KEY5 , EFUSE_BLK0 , 28 , 1 , [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2 , EFUSE_BLK0 , 29 , 1 , [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
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WR_DIS.ADC2_HI_DOUT_ATTEN0 , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_HI_DOUT_ATTEN0
WR_DIS.ADC2_HI_DOUT_ATTEN1 , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_HI_DOUT_ATTEN1
WR_DIS.ADC2_HI_DOUT_ATTEN2 , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_HI_DOUT_ATTEN2
WR_DIS.ADC2_HI_DOUT_ATTEN3 , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_HI_DOUT_ATTEN3
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 29 , 1 , [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
WR_DIS.TEMPERATURE_SENSOR , EFUSE_BLK0 , 29 , 1 , [] wr_dis of TEMPERATURE_SENSOR
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WR_DIS.USB_DEVICE_EXCHG_PINS , EFUSE_BLK0 , 30 , 1 , [] wr_dis of USB_DEVICE_EXCHG_PINS
WR_DIS.USB_OTG11_EXCHG_PINS , EFUSE_BLK0 , 30 , 1 , [] wr_dis of USB_OTG11_EXCHG_PINS
WR_DIS.USB_PHY_SEL , EFUSE_BLK0 , 30 , 1 , [] wr_dis of USB_PHY_SEL
WR_DIS.SOFT_DIS_JTAG , EFUSE_BLK0 , 31 , 1 , [] wr_dis of SOFT_DIS_JTAG
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RD_DIS , EFUSE_BLK0 , 32 , 7 , [] Disable reading from BlOCK4-10
RD_DIS.BLOCK_KEY0 , EFUSE_BLK0 , 32 , 1 , [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
RD_DIS.BLOCK_KEY1 , EFUSE_BLK0 , 33 , 1 , [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
RD_DIS.BLOCK_KEY2 , EFUSE_BLK0 , 34 , 1 , [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
RD_DIS.BLOCK_KEY3 , EFUSE_BLK0 , 35 , 1 , [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
RD_DIS.BLOCK_KEY4 , EFUSE_BLK0 , 36 , 1 , [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
RD_DIS.BLOCK_KEY5 , EFUSE_BLK0 , 37 , 1 , [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
RD_DIS.BLOCK_SYS_DATA2 , EFUSE_BLK0 , 38 , 1 , [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
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RD_DIS.ADC2_HI_DOUT_ATTEN0 , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_HI_DOUT_ATTEN0
RD_DIS.ADC2_HI_DOUT_ATTEN1 , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_HI_DOUT_ATTEN1
RD_DIS.ADC2_HI_DOUT_ATTEN2 , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_HI_DOUT_ATTEN2
RD_DIS.ADC2_HI_DOUT_ATTEN3 , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_HI_DOUT_ATTEN3
RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF , EFUSE_BLK0 , 38 , 1 , [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
RD_DIS.TEMPERATURE_SENSOR , EFUSE_BLK0 , 38 , 1 , [] rd_dis of TEMPERATURE_SENSOR
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USB_DEVICE_EXCHG_PINS , EFUSE_BLK0 , 39 , 1 , [] Enable usb device exchange pins of D+ and D-
USB_OTG11_EXCHG_PINS , EFUSE_BLK0 , 40 , 1 , [] Enable usb otg11 exchange pins of D+ and D-
DIS_USB_JTAG , EFUSE_BLK0 , 41 , 1 , [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
POWERGLITCH_EN , EFUSE_BLK0 , 42 , 1 , [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
DIS_FORCE_DOWNLOAD , EFUSE_BLK0 , 44 , 1 , [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
SPI_DOWNLOAD_MSPI_DIS , EFUSE_BLK0 , 45 , 1 , [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
DIS_TWAI , EFUSE_BLK0 , 46 , 1 , [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
JTAG_SEL_ENABLE , EFUSE_BLK0 , 47 , 1 , [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
SOFT_DIS_JTAG , EFUSE_BLK0 , 48 , 3 , [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
DIS_PAD_JTAG , EFUSE_BLK0 , 51 , 1 , [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
DIS_DOWNLOAD_MANUAL_ENCRYPT , EFUSE_BLK0 , 52 , 1 , [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
USB_PHY_SEL , EFUSE_BLK0 , 57 , 1 , [] TBD
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KM_HUK_GEN_STATE , EFUSE_BLK0 , 58 , 9 , [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
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KM_RND_SWITCH_CYCLE , EFUSE_BLK0 , 67 , 2 , [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
KM_DEPLOY_ONLY_ONCE , EFUSE_BLK0 , 69 , 4 , [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
FORCE_USE_KEY_MANAGER_KEY , EFUSE_BLK0 , 73 , 4 , [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
FORCE_DISABLE_SW_INIT_KEY , EFUSE_BLK0 , 77 , 1 , [] Set this bit to disable software written init key; and force use efuse_init_key
XTS_KEY_LENGTH_256 , EFUSE_BLK0 , 78 , 1 , [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key
WDT_DELAY_SEL , EFUSE_BLK0 , 80 , 2 , [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
SPI_BOOT_CRYPT_CNT , EFUSE_BLK0 , 82 , 3 , [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
SECURE_BOOT_KEY_REVOKE0 , EFUSE_BLK0 , 85 , 1 , [] Revoke 1st secure boot key
SECURE_BOOT_KEY_REVOKE1 , EFUSE_BLK0 , 86 , 1 , [] Revoke 2nd secure boot key
SECURE_BOOT_KEY_REVOKE2 , EFUSE_BLK0 , 87 , 1 , [] Revoke 3rd secure boot key
KEY_PURPOSE_0 , EFUSE_BLK0 , 88 , 4 , [KEY0_PURPOSE] Represents the purpose of Key0
KEY_PURPOSE_1 , EFUSE_BLK0 , 92 , 4 , [KEY1_PURPOSE] Represents the purpose of Key1
KEY_PURPOSE_2 , EFUSE_BLK0 , 96 , 4 , [KEY2_PURPOSE] Represents the purpose of Key2
KEY_PURPOSE_3 , EFUSE_BLK0 , 100 , 4 , [KEY3_PURPOSE] Represents the purpose of Key3
KEY_PURPOSE_4 , EFUSE_BLK0 , 104 , 4 , [KEY4_PURPOSE] Represents the purpose of Key4
KEY_PURPOSE_5 , EFUSE_BLK0 , 108 , 4 , [KEY5_PURPOSE] Represents the purpose of Key5
SEC_DPA_LEVEL , EFUSE_BLK0 , 112 , 2 , [] Represents the spa secure level by configuring the clock random divide mode
ECDSA_ENABLE_SOFT_K , EFUSE_BLK0 , 114 , 1 , [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
CRYPT_DPA_ENABLE , EFUSE_BLK0 , 115 , 1 , [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
SECURE_BOOT_EN , EFUSE_BLK0 , 116 , 1 , [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
SECURE_BOOT_AGGRESSIVE_REVOKE , EFUSE_BLK0 , 117 , 1 , [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
FLASH_TYPE , EFUSE_BLK0 , 119 , 1 , [] The type of interfaced flash. 0: four data lines; 1: eight data lines
FLASH_PAGE_SIZE , EFUSE_BLK0 , 120 , 2 , [] Set flash page size
FLASH_ECC_EN , EFUSE_BLK0 , 122 , 1 , [] Set this bit to enable ecc for flash boot
DIS_USB_OTG_DOWNLOAD_MODE , EFUSE_BLK0 , 123 , 1 , [] Set this bit to disable download via USB-OTG
FLASH_TPUW , EFUSE_BLK0 , 124 , 4 , [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
DIS_DOWNLOAD_MODE , EFUSE_BLK0 , 128 , 1 , [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
DIS_DIRECT_BOOT , EFUSE_BLK0 , 129 , 1 , [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
DIS_USB_SERIAL_JTAG_ROM_PRINT , EFUSE_BLK0 , 130 , 1 , [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
LOCK_KM_KEY , EFUSE_BLK0 , 131 , 1 , [] TBD
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE , EFUSE_BLK0 , 132 , 1 , [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
ENABLE_SECURITY_DOWNLOAD , EFUSE_BLK0 , 133 , 1 , [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
UART_PRINT_CONTROL , EFUSE_BLK0 , 134 , 2 , [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing
FORCE_SEND_RESUME , EFUSE_BLK0 , 136 , 1 , [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
SECURE_VERSION , EFUSE_BLK0 , 137 , 16 , [] Represents the version used by ESP-IDF anti-rollback feature
SECURE_BOOT_DISABLE_FAST_WAKE , EFUSE_BLK0 , 153 , 1 , [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
HYS_EN_PAD , EFUSE_BLK0 , 154 , 1 , [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled
DCDC_VSET , EFUSE_BLK0 , 155 , 5 , [] Set the dcdc voltage default
PXA0_TIEH_SEL_0 , EFUSE_BLK0 , 160 , 2 , [] TBD
PXA0_TIEH_SEL_1 , EFUSE_BLK0 , 162 , 2 , [] TBD
PXA0_TIEH_SEL_2 , EFUSE_BLK0 , 164 , 2 , [] TBD
PXA0_TIEH_SEL_3 , EFUSE_BLK0 , 166 , 2 , [] TBD
KM_DISABLE_DEPLOY_MODE , EFUSE_BLK0 , 168 , 4 , [] TBD
HP_PWR_SRC_SEL , EFUSE_BLK0 , 178 , 1 , [] HP system power source select. 0:LDO. 1: DCDC
DCDC_VSET_EN , EFUSE_BLK0 , 179 , 1 , [] Select dcdc vset use efuse_dcdc_vset
DIS_WDT , EFUSE_BLK0 , 180 , 1 , [] Set this bit to disable watch dog
DIS_SWD , EFUSE_BLK0 , 181 , 1 , [] Set this bit to disable super-watchdog
MAC , EFUSE_BLK1 , 40 , 8 , [MAC_FACTORY] MAC address
, EFUSE_BLK1 , 32 , 8 , [MAC_FACTORY] MAC address
, EFUSE_BLK1 , 24 , 8 , [MAC_FACTORY] MAC address
, EFUSE_BLK1 , 16 , 8 , [MAC_FACTORY] MAC address
, EFUSE_BLK1 , 8 , 8 , [MAC_FACTORY] MAC address
, EFUSE_BLK1 , 0 , 8 , [MAC_FACTORY] MAC address
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WAFER_VERSION_MINOR , EFUSE_BLK1 , 64 , 4 , [] Minor chip version
WAFER_VERSION_MAJOR , EFUSE_BLK1 , 68 , 2 , [] Major chip version
DISABLE_WAFER_VERSION_MAJOR , EFUSE_BLK1 , 70 , 1 , [] Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR , EFUSE_BLK1 , 71 , 1 , [] Disables check of blk version major
BLK_VERSION_MINOR , EFUSE_BLK1 , 72 , 3 , [] BLK_VERSION_MINOR of BLOCK2
BLK_VERSION_MAJOR , EFUSE_BLK1 , 75 , 2 , [] BLK_VERSION_MAJOR of BLOCK2
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PSRAM_CAP , EFUSE_BLK1 , 77 , 3 , [] PSRAM capacity
TEMP , EFUSE_BLK1 , 80 , 2 , [] Operating temperature of the ESP chip
PSRAM_VENDOR , EFUSE_BLK1 , 82 , 2 , [] PSRAM vendor
PKG_VERSION , EFUSE_BLK1 , 84 , 3 , [] Package version
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LDO_VO1_DREF , EFUSE_BLK1 , 88 , 4 , [] Output VO1 parameter
LDO_VO2_DREF , EFUSE_BLK1 , 92 , 4 , [] Output VO2 parameter
LDO_VO1_MUL , EFUSE_BLK1 , 96 , 3 , [] Output VO1 parameter
LDO_VO2_MUL , EFUSE_BLK1 , 99 , 3 , [] Output VO2 parameter
LDO_VO3_K , EFUSE_BLK1 , 102 , 8 , [] Output VO3 calibration parameter
LDO_VO3_VOS , EFUSE_BLK1 , 110 , 6 , [] Output VO3 calibration parameter
LDO_VO3_C , EFUSE_BLK1 , 116 , 6 , [] Output VO3 calibration parameter
LDO_VO4_K , EFUSE_BLK1 , 122 , 8 , [] Output VO4 calibration parameter
LDO_VO4_VOS , EFUSE_BLK1 , 130 , 6 , [] Output VO4 calibration parameter
LDO_VO4_C , EFUSE_BLK1 , 136 , 6 , [] Output VO4 calibration parameter
ACTIVE_HP_DBIAS , EFUSE_BLK1 , 144 , 4 , [] Active HP DBIAS of fixed voltage
ACTIVE_LP_DBIAS , EFUSE_BLK1 , 148 , 4 , [] Active LP DBIAS of fixed voltage
LSLP_HP_DBIAS , EFUSE_BLK1 , 152 , 4 , [] LSLP HP DBIAS of fixed voltage
DSLP_DBG , EFUSE_BLK1 , 156 , 4 , [] DSLP BDG of fixed voltage
DSLP_LP_DBIAS , EFUSE_BLK1 , 160 , 5 , [] DSLP LP DBIAS of fixed voltage
LP_DCDC_DBIAS_VOL_GAP , EFUSE_BLK1 , 165 , 5 , [] DBIAS gap between LP and DCDC
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OPTIONAL_UNIQUE_ID , EFUSE_BLK2 , 0 , 128 , [] Optional unique 128-bit ID
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ADC1_AVE_INITCODE_ATTEN0 , EFUSE_BLK2 , 128 , 10 , [] Average initcode of ADC1 atten0
ADC1_AVE_INITCODE_ATTEN1 , EFUSE_BLK2 , 138 , 10 , [] Average initcode of ADC1 atten1
ADC1_AVE_INITCODE_ATTEN2 , EFUSE_BLK2 , 148 , 10 , [] Average initcode of ADC1 atten2
ADC1_AVE_INITCODE_ATTEN3 , EFUSE_BLK2 , 158 , 10 , [] Average initcode of ADC1 atten3
ADC2_AVE_INITCODE_ATTEN0 , EFUSE_BLK2 , 168 , 10 , [] Average initcode of ADC2 atten0
ADC2_AVE_INITCODE_ATTEN1 , EFUSE_BLK2 , 178 , 10 , [] Average initcode of ADC2 atten1
ADC2_AVE_INITCODE_ATTEN2 , EFUSE_BLK2 , 188 , 10 , [] Average initcode of ADC2 atten2
ADC2_AVE_INITCODE_ATTEN3 , EFUSE_BLK2 , 198 , 10 , [] Average initcode of ADC2 atten3
ADC1_HI_DOUT_ATTEN0 , EFUSE_BLK2 , 208 , 10 , [] HI_DOUT of ADC1 atten0
ADC1_HI_DOUT_ATTEN1 , EFUSE_BLK2 , 218 , 10 , [] HI_DOUT of ADC1 atten1
ADC1_HI_DOUT_ATTEN2 , EFUSE_BLK2 , 228 , 10 , [] HI_DOUT of ADC1 atten2
ADC1_HI_DOUT_ATTEN3 , EFUSE_BLK2 , 238 , 10 , [] HI_DOUT of ADC1 atten3
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USER_DATA , EFUSE_BLK3 , 0 , 256 , [BLOCK_USR_DATA] User data
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USER_DATA.MAC_CUSTOM , EFUSE_BLK3 , 200 , 48 , [MAC_CUSTOM CUSTOM_MAC] Custom MAC
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KEY0 , EFUSE_BLK4 , 0 , 256 , [BLOCK_KEY0] Key0 or user data
KEY1 , EFUSE_BLK5 , 0 , 256 , [BLOCK_KEY1] Key1 or user data
KEY2 , EFUSE_BLK6 , 0 , 256 , [BLOCK_KEY2] Key2 or user data
KEY3 , EFUSE_BLK7 , 0 , 256 , [BLOCK_KEY3] Key3 or user data
KEY4 , EFUSE_BLK8 , 0 , 256 , [BLOCK_KEY4] Key4 or user data
KEY5 , EFUSE_BLK9 , 0 , 256 , [BLOCK_KEY5] Key5 or user data
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ADC2_HI_DOUT_ATTEN0 , EFUSE_BLK10 , 0 , 10 , [] HI_DOUT of ADC2 atten0
ADC2_HI_DOUT_ATTEN1 , EFUSE_BLK10 , 10 , 10 , [] HI_DOUT of ADC2 atten1
ADC2_HI_DOUT_ATTEN2 , EFUSE_BLK10 , 20 , 10 , [] HI_DOUT of ADC2 atten2
ADC2_HI_DOUT_ATTEN3 , EFUSE_BLK10 , 30 , 10 , [] HI_DOUT of ADC2 atten3
ADC1_CH0_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 40 , 4 , [] Gap between ADC1_ch0 and average initcode
ADC1_CH1_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 44 , 4 , [] Gap between ADC1_ch1 and average initcode
ADC1_CH2_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 48 , 4 , [] Gap between ADC1_ch2 and average initcode
ADC1_CH3_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 52 , 4 , [] Gap between ADC1_ch3 and average initcode
ADC1_CH4_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 56 , 4 , [] Gap between ADC1_ch4 and average initcode
ADC1_CH5_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 60 , 4 , [] Gap between ADC1_ch5 and average initcode
ADC1_CH6_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 64 , 4 , [] Gap between ADC1_ch6 and average initcode
ADC1_CH7_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 68 , 4 , [] Gap between ADC1_ch7 and average initcode
ADC2_CH0_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 72 , 4 , [] Gap between ADC2_ch0 and average initcode
ADC2_CH1_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 76 , 4 , [] Gap between ADC2_ch1 and average initcode
ADC2_CH2_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 80 , 4 , [] Gap between ADC2_ch2 and average initcode
ADC2_CH3_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 84 , 4 , [] Gap between ADC2_ch3 and average initcode
ADC2_CH4_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 88 , 4 , [] Gap between ADC2_ch4 and average initcode
ADC2_CH5_ATTEN0_INITCODE_DIFF , EFUSE_BLK10 , 92 , 4 , [] Gap between ADC2_ch5 and average initcode
TEMPERATURE_SENSOR , EFUSE_BLK10 , 96 , 9 , [] Temperature calibration data
