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213 lines
7.4 KiB
C
213 lines
7.4 KiB
C
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/* xtruntime-core-state.h - core state save area (used eg. by PSO) */
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/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
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/*
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* Copyright (c) 2012-2013 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _XTOS_CORE_STATE_H_
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#define _XTOS_CORE_STATE_H_
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/* Import STRUCT_xxx macros for defining structures: */
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#include <xtensa/xtruntime-frames.h>
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#include <xtensa/config/core.h>
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#include <xtensa/config/tie.h>
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//#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only
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#define CORE_STATE_SIGNATURE 0xB1C5AFED // pattern that indicates state was saved
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/*
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* Save area for saving entire core state, such as across Power Shut-Off (PSO).
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*/
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STRUCT_BEGIN
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STRUCT_FIELD (long,4,CS_SA_,signature) // for checking whether state was saved
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STRUCT_FIELD (long,4,CS_SA_,restore_label)
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STRUCT_FIELD (long,4,CS_SA_,aftersave_label)
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STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS)
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#if XCHAL_HAVE_WINDOWED
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STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16) // save a max of 16 caller regs
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STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved) // flag to show if caller regs saved
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#endif
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#if XCHAL_HAVE_PSO_CDM
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STRUCT_FIELD (long,4,CS_SA_,pwrctl)
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#endif
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#if XCHAL_HAVE_WINDOWED
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STRUCT_FIELD (long,4,CS_SA_,windowbase)
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STRUCT_FIELD (long,4,CS_SA_,windowstart)
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#endif
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STRUCT_FIELD (long,4,CS_SA_,sar)
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#if XCHAL_HAVE_EXCEPTIONS
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STRUCT_FIELD (long,4,CS_SA_,epc1)
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STRUCT_FIELD (long,4,CS_SA_,ps)
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STRUCT_FIELD (long,4,CS_SA_,excsave1)
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# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
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STRUCT_FIELD (long,4,CS_SA_,depc)
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# endif
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#endif
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#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
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STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
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STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
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STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
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#endif
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#if XCHAL_HAVE_LOOPS
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STRUCT_FIELD (long,4,CS_SA_,lcount)
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STRUCT_FIELD (long,4,CS_SA_,lbeg)
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STRUCT_FIELD (long,4,CS_SA_,lend)
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#endif
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#if XCHAL_HAVE_ABSOLUTE_LITERALS
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STRUCT_FIELD (long,4,CS_SA_,litbase)
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#endif
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#if XCHAL_HAVE_VECBASE
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STRUCT_FIELD (long,4,CS_SA_,vecbase)
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#endif
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#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
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STRUCT_FIELD (long,4,CS_SA_,atomctl)
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#endif
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#if XCHAL_HAVE_PREFETCH
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STRUCT_FIELD (long,4,CS_SA_,prefctl)
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#endif
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#if XCHAL_USE_MEMCTL
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STRUCT_FIELD (long,4,CS_SA_,memctl)
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#endif
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#if XCHAL_HAVE_CCOUNT
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STRUCT_FIELD (long,4,CS_SA_,ccount)
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STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
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#endif
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#if XCHAL_HAVE_INTERRUPTS
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STRUCT_FIELD (long,4,CS_SA_,intenable)
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STRUCT_FIELD (long,4,CS_SA_,interrupt)
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#endif
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#if XCHAL_HAVE_DEBUG
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STRUCT_FIELD (long,4,CS_SA_,icount)
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STRUCT_FIELD (long,4,CS_SA_,icountlevel)
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STRUCT_FIELD (long,4,CS_SA_,debugcause)
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// DDR not saved
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# if XCHAL_NUM_DBREAK
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STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK)
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STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK)
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# endif
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# if XCHAL_NUM_IBREAK
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STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK)
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STRUCT_FIELD (long,4,CS_SA_,ibreakenable)
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# endif
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#endif
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#if XCHAL_NUM_MISC_REGS
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STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS)
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#endif
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#if XCHAL_HAVE_MEM_ECC_PARITY
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STRUCT_FIELD (long,4,CS_SA_,mepc)
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STRUCT_FIELD (long,4,CS_SA_,meps)
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STRUCT_FIELD (long,4,CS_SA_,mesave)
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STRUCT_FIELD (long,4,CS_SA_,mesr)
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STRUCT_FIELD (long,4,CS_SA_,mecr)
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STRUCT_FIELD (long,4,CS_SA_,mevaddr)
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#endif
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/* We put this ahead of TLB and other TIE state,
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to keep it within S32I/L32I offset range. */
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#if XCHAL_HAVE_CP
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STRUCT_FIELD (long,4,CS_SA_,cpenable)
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#endif
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/* TLB state */
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#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
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STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2)
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#endif
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#if XCHAL_HAVE_PTP_MMU
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/* Compute number of auto-refill (ARF) entries as max of I and D,
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to simplify TLB save logic. On the unusual configs with
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ITLB ARF != DTLB ARF entries, we'll just end up
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saving/restoring some extra entries redundantly. */
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# if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4
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# define ARF_ENTRIES 8
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# else
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# define ARF_ENTRIES 4
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# endif
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STRUCT_FIELD (long,4,CS_SA_,ptevaddr)
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STRUCT_FIELD (long,4,CS_SA_,rasid)
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STRUCT_FIELD (long,4,CS_SA_,dtlbcfg)
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STRUCT_FIELD (long,4,CS_SA_,itlbcfg)
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/*** WARNING: past this point, field offsets may be larger than S32I/L32I range ***/
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STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2)
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# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */
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STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
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# endif
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#endif
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/* TIE state */
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/* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN,
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because the offsets of all subsequent coprocessor save areas are relative
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to the NCP save area. */
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STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
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#if XCHAL_HAVE_CP
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STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
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STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE)
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//STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE)
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#endif
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STRUCT_END(XtosCoreState)
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// These are part of non-coprocessor state (ncp):
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#if XCHAL_HAVE_MAC16
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//STRUCT_FIELD (long,4,CS_SA_,acclo)
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//STRUCT_FIELD (long,4,CS_SA_,acchi)
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//STRUCT_AFIELD(long,4,CS_SA_,mr, 4)
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#endif
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#if XCHAL_HAVE_THREADPTR
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//STRUCT_FIELD (long,4,CS_SA_,threadptr)
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#endif
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#if XCHAL_HAVE_S32C1I
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//STRUCT_FIELD (long,4,CS_SA_,scompare1)
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#endif
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#if XCHAL_HAVE_BOOLEANS
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//STRUCT_FIELD (long,4,CS_SA_,br)
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#endif
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// Not saved:
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// EXCCAUSE ??
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// DEBUGCAUSE ??
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// EXCVADDR ??
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// DDR
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// INTERRUPT
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// ... locked cache lines ...
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#endif /* _XTOS_CORE_STATE_H_ */
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