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https://github.com/espressif/esp-idf.git
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70 lines
2.8 KiB
C
70 lines
2.8 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ROM_CACHE_H_
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#define _ROM_CACHE_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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//===========================================
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// function : cache_init
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// description: initialise cache mmu, mark all entries as invalid.
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// conditions:
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// Call Cache_Read_Disable() before calling this function.
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// inputs:
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// cpu_no is CPU number,0(PRO CPU) or 1(APP CPU),
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// output: NONE
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//===========================================
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void mmu_init(int cpu_no);
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//===========================================
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// function : cache_flash_mmu_set
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// description: Configure MMU to cache a flash region.
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// conditions:
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// Call this function to configure the flash cache before enabling it.
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// Check return value to verify MMU was set correctly.
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// inputs:
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// cpu_no is CPU number,0(PRO CPU) or 1(APP CPU),
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// pid is process identifier. Range 0~7
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// vaddr is "virtual" address in CPU address space. Can be IRam0, IRam1, IRom0 and DRom0 memory address.
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// Should be aligned by psize
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// paddr is "physical" address in flash controller's address space.
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// ie for 16M flash the range is 0x000000~0xFFFFFF. Should be aligned by psize
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// psize is page size of flash, in kilobytes. Can be 64, 32, 16.
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// num is number of pages to be set, valid range 0 ~ (flash size)/(page size)
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// output: error status
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// 0 : mmu set success
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// 1 : vaddr or paddr is not aligned
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// 2 : pid error
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// 3 : psize error
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// 4 : mmu table to be written is out of range
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// 5 : vaddr is out of range
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//===========================================
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unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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unsigned int cache_sram_mmu_set(int cpu_no, int pid,unsigned int vaddr, unsigned int paddr, int psize, int num);
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void Cache_Read_Init(int cpu_no);
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void Cache_Read_Disable(int cpu_no);
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void Cache_Read_Enable(int cpu_no);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_CACHE_H_ */
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