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								// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
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								//
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								// Licensed under the Apache License, Version 2.0 (the "License");
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								// you may not use this file except in compliance with the License.
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								// You may obtain a copy of the License at
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								//
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								//     http://www.apache.org/licenses/LICENSE-2.0
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								//
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								// Unless required by applicable law or agreed to in writing, software
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								// distributed under the License is distributed on an "AS IS" BASIS,
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								// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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								// See the License for the specific language governing permissions and
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								// limitations under the License.
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								#include <stdio.h>
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								#include <string.h>
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								#include "esp_sleep.h"
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								#include "soc/rtc_cntl_reg.h"
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								#include "soc/sens_reg.h"
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								#include "soc/rtc_periph.h"
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								#include "esp32s2/ulp.h"
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								#include "esp32s2/ulp_riscv.h"
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								#include "ulp_test_app.h"
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								#include "unity.h"
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								typedef enum{
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								    RISCV_READ_WRITE_TEST = 1,
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								    RISCV_DEEP_SLEEP_WAKEUP_TEST,
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								    RISCV_LIGHT_SLEEP_WAKEUP_TEST,
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								    RISCV_NO_COMMAND,
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								} riscv_test_commands_t;
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								typedef enum {
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								    RISCV_COMMAND_OK = 1,
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								    RISCV_COMMAND_NOK,
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								} riscv_test_command_reply_t;
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								#define XOR_MASK 0xDEADBEEF
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								extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_test_app_bin_start");
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								extern const uint8_t ulp_main_bin_end[]   asm("_binary_ulp_test_app_bin_end");
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								static bool  firmware_loaded = false;
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								static void load_and_start_ulp_firmware(void)
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								{
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								    if (!firmware_loaded) {
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								        TEST_ASSERT(ulp_riscv_load_binary(ulp_main_bin_start,
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								                            (ulp_main_bin_end - ulp_main_bin_start)) == ESP_OK);
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								        TEST_ASSERT(ulp_set_wakeup_period(0, 1000000) == ESP_OK);
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								        TEST_ASSERT(ulp_riscv_run() == ESP_OK);
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								        firmware_loaded = true;
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								    }
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								}
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								TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp][ignore]")
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								{
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								    const uint32_t test_data = 0x12345678;
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								    load_and_start_ulp_firmware();
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								    TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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								    ulp_riscv_test_data_in = test_data ^ XOR_MASK;
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								    ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
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								    TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
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								    TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
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								    TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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								    printf("data out: 0x%X, expected: 0x%X \n", ulp_riscv_test_data_out, test_data);
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								    TEST_ASSERT(test_data == ulp_riscv_test_data_out);
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								}
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								TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp][ignore]")
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								{
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								    load_and_start_ulp_firmware();
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								    TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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								    ulp_main_cpu_command = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
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								    TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
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								    TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
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								    TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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								}
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								TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset=SW_CPU_RESET][ignore]")
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								{
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								    load_and_start_ulp_firmware();
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								    TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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								    ulp_main_cpu_command = RISCV_DEEP_SLEEP_WAKEUP_TEST;
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								    esp_deep_sleep_start();
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								    UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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								}
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