From 002411b16947d165453915791b9edcdd50b019d5 Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Tue, 22 Nov 2022 23:17:03 +0300 Subject: [PATCH] riscv: Use 'li' instead of 'la' for loading peripheral reg address --- components/riscv/vectors.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/riscv/vectors.S b/components/riscv/vectors.S index 56d0a2c85f..4fdc951126 100644 --- a/components/riscv/vectors.S +++ b/components/riscv/vectors.S @@ -238,14 +238,14 @@ _interrupt_handler: csrr s2, mstatus /* Save the interrupt threshold level */ - la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG + li t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG lw s3, 0(t0) /* Increase interrupt threshold level */ li t2, 0x7fffffff and t1, s1, t2 /* t1 = mcause & mask */ slli t1, t1, 2 /* t1 = mcause * 4 */ - la t2, INTC_INT_PRIO_REG(0) + li t2, INTC_INT_PRIO_REG(0) add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */ lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */ addi t2, t2, 1 /* t2 = t2 +1 */ @@ -287,7 +287,7 @@ _interrupt_handler: /* MIE cleared. Nested interrupts are disabled */ /* restore the interrupt threshold level */ - la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG + li t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG sw s3, 0(t0) fence