diff --git a/components/hal/esp32c5/include/hal/lp_aon_ll.h b/components/hal/esp32c5/include/hal/lp_aon_ll.h index 62a9d630bc..66392768ba 100644 --- a/components/hal/esp32c5/include/hal/lp_aon_ll.h +++ b/components/hal/esp32c5/include/hal/lp_aon_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -85,54 +85,6 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp) } } -/** - * @brief Set the maximum number of linked lists supported by REGDMA - * @param count: the maximum number of regdma link - */ -static inline void lp_aon_ll_set_regdma_link_count(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, branch_link_length_aon, count); -} - -/** - * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop - * for some reason and the execution count exceeds this configured number, a timeout will be triggered. - * @param count: the maximum number of loop - */ -static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_work_tout_thres_aon, count); -} - -/** - * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing - * registers and gets stuck on the bus, a timeout will be triggered. - * @param count: the maximum number of time - */ -static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_backup_tout_thres_aon, count); -} - -/** - * @brief Set the regdma_link_addr - * @param addr: the addr of regdma_link - */ -static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr); -} - -static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count); -} - -static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/pau_ll.h b/components/hal/esp32c5/include/hal/pau_ll.h index 2a6de7d704..f6117925c3 100644 --- a/components/hal/esp32c5/include/hal/pau_ll.h +++ b/components/hal/esp32c5/include/hal/pau_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,8 +14,10 @@ #include "soc/pau_reg.h" #include "soc/pau_struct.h" #include "soc/pcr_struct.h" +#include "soc/lp_aon_struct.h" #include "hal/pau_types.h" #include "hal/assert.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -47,14 +49,9 @@ static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, dev->regdma_conf.to_mem = to_mem ? 1 : 0; } -static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) { - dev->regdma_conf.start = 1; -} - -static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) -{ - dev->regdma_conf.start = 0; + dev->regdma_conf.start = enable; } static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) @@ -107,14 +104,9 @@ static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) return dev->int_st.val; } -static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) { - dev->int_ena.done_int_ena = 1; -} - -static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) -{ - dev->int_ena.done_int_ena = 0; + dev->int_ena.done_int_ena = enable; } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) @@ -129,12 +121,61 @@ static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { - dev->int_clr.done_int_clr = 1; + dev->int_clr.val = 0x1; } static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { - dev->int_clr.error_int_clr = 1; + dev->int_clr.val = 0x2; +} + + +/** + * @brief Set the maximum number of linked lists supported by REGDMA + * @param count: the maximum number of regdma link + */ +static inline void pau_ll_set_regdma_link_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, branch_link_length_aon, count); +} + +/** + * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop + * for some reason and the execution count exceeds this configured number, a timeout will be triggered. + * @param count: the maximum number of loop + */ +static inline void pau_ll_set_regdma_link_loop_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_work_tout_thres_aon, count); +} + +/** + * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing + * registers and gets stuck on the bus, a timeout will be triggered. + * @param count: the maximum number of time + */ +static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_backup_tout_thres_aon, count); +} + +/** + * @brief Set the regdma_link_addr + * @param addr: the addr of regdma_link + */ +static inline void pau_ll_set_regdma_link_addr(uint32_t addr) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr); +} + +static inline void pau_ll_set_regdma_link_wait_retry_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count); +} + +static inline void pau_ll_set_regdma_link_wait_read_interval(int interval) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval); } #ifdef __cplusplus diff --git a/components/hal/esp32c5/pau_hal.c b/components/hal/esp32c5/pau_hal.c index da41160446..55460068c4 100644 --- a/components/hal/esp32c5/pau_hal.c +++ b/components/hal/esp32c5/pau_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,7 +12,7 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) { - lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); + pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); } void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) @@ -43,14 +43,14 @@ void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool back */ pau_ll_select_regdma_entry_link(hal->dev, 3); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } @@ -59,20 +59,20 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) { HAL_ASSERT(count > 0); - lp_aon_ll_set_regdma_link_count(count - 1); + pau_ll_set_regdma_link_count(count - 1); } #endif void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) { HAL_ASSERT(loop_num > 0 && time > 0); - lp_aon_ll_set_regdma_link_loop_threshold(loop_num); - lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); + pau_ll_set_regdma_link_loop_threshold(loop_num); + pau_ll_set_regdma_link_reg_access_tout_threshold(time); } void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) { HAL_ASSERT(count > 0 && interval > 0); - lp_aon_ll_set_regdma_link_wait_retry_count(count); - lp_aon_ll_set_regdma_link_wait_read_interval(interval); + pau_ll_set_regdma_link_wait_retry_count(count); + pau_ll_set_regdma_link_wait_read_interval(interval); } diff --git a/components/hal/esp32c6/include/hal/pau_ll.h b/components/hal/esp32c6/include/hal/pau_ll.h index 3a8878c83e..d8b36b90e2 100644 --- a/components/hal/esp32c6/include/hal/pau_ll.h +++ b/components/hal/esp32c6/include/hal/pau_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,14 +47,9 @@ static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, dev->regdma_conf.to_mem = to_mem ? 1 : 0; } -static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) { - dev->regdma_conf.start = 1; -} - -static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) -{ - dev->regdma_conf.start = 0; + dev->regdma_conf.start = enable; } static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) @@ -132,14 +127,9 @@ static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) return dev->int_st.val; } -static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) { - dev->int_ena.done_int_ena = 1; -} - -static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) -{ - dev->int_ena.done_int_ena = 0; + dev->int_ena.done_int_ena = enable; } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable) @@ -149,12 +139,12 @@ static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bo static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { - dev->int_clr.done_int_clr = 1; + dev->int_clr.val = 0x1; } static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { - dev->int_clr.error_int_clr = 1; + dev->int_clr.val = 0x2; } static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count) diff --git a/components/hal/esp32c6/pau_hal.c b/components/hal/esp32c6/pau_hal.c index 765e6e36e2..ac9e4a0759 100644 --- a/components/hal/esp32c6/pau_hal.c +++ b/components/hal/esp32c6/pau_hal.c @@ -46,14 +46,14 @@ void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool back */ pau_ll_select_regdma_entry_link(hal->dev, 3); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } diff --git a/components/hal/esp32c61/include/hal/pau_ll.h b/components/hal/esp32c61/include/hal/pau_ll.h index 6a19d22a7b..e68d17fce0 100644 --- a/components/hal/esp32c61/include/hal/pau_ll.h +++ b/components/hal/esp32c61/include/hal/pau_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,14 +47,9 @@ static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, dev->regdma_conf.to_mem = to_mem ? 1 : 0; } -static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) { - dev->regdma_conf.start = 1; -} - -static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) -{ - dev->regdma_conf.start = 0; + dev->regdma_conf.start = enable; } static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) @@ -132,14 +127,9 @@ static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) return dev->int_st.val; } -static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) { - dev->int_ena.done_int_ena = 1; -} - -static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) -{ - dev->int_ena.done_int_ena = 0; + dev->int_ena.done_int_ena = enable; } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable) @@ -149,12 +139,12 @@ static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bo static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { - dev->int_clr.done_int_clr = 1; + dev->int_clr.val = 0x1; } static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { - dev->int_clr.error_int_clr = 1; + dev->int_clr.val = 0x2; } static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count) diff --git a/components/hal/esp32c61/pau_hal.c b/components/hal/esp32c61/pau_hal.c index 335188cc5a..69e5323b99 100644 --- a/components/hal/esp32c61/pau_hal.c +++ b/components/hal/esp32c61/pau_hal.c @@ -46,14 +46,14 @@ void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool back */ pau_ll_select_regdma_entry_link(hal->dev, 3); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } diff --git a/components/hal/esp32h2/include/hal/pau_ll.h b/components/hal/esp32h2/include/hal/pau_ll.h index 7ce03f6d7b..355e17352e 100644 --- a/components/hal/esp32h2/include/hal/pau_ll.h +++ b/components/hal/esp32h2/include/hal/pau_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,14 +47,9 @@ static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_b dev->regdma_conf.to_mem = to_mem ? 1 : 0; } -static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) { - dev->regdma_conf.start = 1; -} - -static inline __attribute__((always_inline)) void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) -{ - dev->regdma_conf.start = 0; + dev->regdma_conf.start = enable; } static inline __attribute__((always_inline)) void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr) @@ -102,14 +97,9 @@ static inline __attribute__((always_inline)) uint32_t pau_ll_get_regdma_intr_sta return dev->int_st.val; } -static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) { - dev->int_ena.done_int_ena = 1; -} - -static inline __attribute__((always_inline)) void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) -{ - dev->int_ena.done_int_ena = 0; + dev->int_ena.done_int_ena = enable; } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable) @@ -119,12 +109,12 @@ static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bo static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { - dev->int_clr.done_int_clr = 1; + dev->int_clr.val = 0x1; } static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { - dev->int_clr.error_int_clr = 1; + dev->int_clr.val = 0x2; } static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count) diff --git a/components/hal/esp32h2/pau_hal.c b/components/hal/esp32h2/pau_hal.c index b123cd41af..03adbe1851 100644 --- a/components/hal/esp32h2/pau_hal.c +++ b/components/hal/esp32h2/pau_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -24,14 +24,14 @@ void IRAM_ATTR pau_hal_start_regdma_system_link(pau_hal_context_t *hal, bool bac pau_ll_select_regdma_entry_link(hal->dev, 0); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_system_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } @@ -64,14 +64,14 @@ void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool back */ pau_ll_select_regdma_entry_link(hal->dev, 3); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } diff --git a/components/hal/esp32h21/include/hal/lp_aon_ll.h b/components/hal/esp32h21/include/hal/lp_aon_ll.h index 64e8164180..ce7141f347 100644 --- a/components/hal/esp32h21/include/hal/lp_aon_ll.h +++ b/components/hal/esp32h21/include/hal/lp_aon_ll.h @@ -85,54 +85,6 @@ static inline void lp_aon_ll_inform_wakeup_type(bool dslp) } } -/** - * @brief Set the maximum number of linked lists supported by REGDMA - * @param count: the maximum number of regdma link - */ -static inline void lp_aon_ll_set_regdma_link_count(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); -} - -/** - * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop - * for some reason and the execution count exceeds this configured number, a timeout will be triggered. - * @param count: the maximum number of loop - */ -static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count); -} - -/** - * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing - * registers and gets stuck on the bus, a timeout will be triggered. - * @param count: the maximum number of time - */ -static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count); -} - -/** - * @brief Set the regdma_link_addr - * @param addr: the addr of regdma_link - */ -static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); -} - -static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count); -} - -static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval) -{ - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h21/include/hal/pau_ll.h b/components/hal/esp32h21/include/hal/pau_ll.h index d927070687..895cecfe99 100644 --- a/components/hal/esp32h21/include/hal/pau_ll.h +++ b/components/hal/esp32h21/include/hal/pau_ll.h @@ -14,8 +14,10 @@ #include "soc/pau_reg.h" #include "soc/pau_struct.h" #include "soc/pcr_struct.h" +#include "soc/lp_aon_struct.h" #include "hal/pau_types.h" #include "hal/assert.h" +#include "hal/misc.h" #ifdef __cplusplus extern "C" { @@ -47,14 +49,9 @@ static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, dev->regdma_conf.to_mem = to_mem ? 1 : 0; } -static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) { - dev->regdma_conf.start = 1; -} - -static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) -{ - dev->regdma_conf.start = 0; + dev->regdma_conf.start = enable; } static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) @@ -107,14 +104,9 @@ static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) return dev->int_st.val; } -static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) { - dev->int_ena.done_int_ena = 1; -} - -static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) -{ - dev->int_ena.done_int_ena = 0; + dev->int_ena.done_int_ena = enable; } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) @@ -129,12 +121,60 @@ static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { - dev->int_clr.done_int_clr = 1; + dev->int_clr.val = 0x1; } static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { - dev->int_clr.error_int_clr = 1; + dev->int_clr.val = 0x2; +} + +/** + * @brief Set the maximum number of linked lists supported by REGDMA + * @param count: the maximum number of regdma link + */ +static inline void pau_ll_set_regdma_link_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); +} + +/** + * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop + * for some reason and the execution count exceeds this configured number, a timeout will be triggered. + * @param count: the maximum number of loop + */ +static inline void pau_ll_set_regdma_link_loop_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count); +} + +/** + * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing + * registers and gets stuck on the bus, a timeout will be triggered. + * @param count: the maximum number of time + */ +static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count); +} + +/** + * @brief Set the regdma_link_addr + * @param addr: the addr of regdma_link + */ +static inline void pau_ll_set_regdma_link_addr(uint32_t addr) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); +} + +static inline void pau_ll_set_regdma_link_wait_retry_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count); +} + +static inline void pau_ll_set_regdma_link_wait_read_interval(int interval) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval); } #ifdef __cplusplus diff --git a/components/hal/esp32h21/pau_hal.c b/components/hal/esp32h21/pau_hal.c index 05da12e136..d5b28fa086 100644 --- a/components/hal/esp32h21/pau_hal.c +++ b/components/hal/esp32h21/pau_hal.c @@ -16,7 +16,7 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) { - lp_aon_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); + pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); } void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) @@ -47,14 +47,14 @@ void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool back */ pau_ll_select_regdma_entry_link(hal->dev, 3); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } @@ -63,20 +63,20 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) { HAL_ASSERT(count > 0); - lp_aon_ll_set_regdma_link_count(count - 1); + pau_ll_set_regdma_link_count(count - 1); } #endif void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) { HAL_ASSERT(loop_num > 0 && time > 0); - lp_aon_ll_set_regdma_link_loop_threshold(loop_num); - lp_aon_ll_set_regdma_link_reg_access_tout_threshold(time); + pau_ll_set_regdma_link_loop_threshold(loop_num); + pau_ll_set_regdma_link_reg_access_tout_threshold(time); } void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) { HAL_ASSERT(count > 0 && interval > 0); - lp_aon_ll_set_regdma_link_wait_retry_count(count); - lp_aon_ll_set_regdma_link_wait_read_interval(interval); + pau_ll_set_regdma_link_wait_retry_count(count); + pau_ll_set_regdma_link_wait_read_interval(interval); } diff --git a/components/hal/esp32h4/include/hal/gdma_ll.h b/components/hal/esp32h4/include/hal/gdma_ll.h index 5c7ca2ad77..ad24af8a45 100644 --- a/components/hal/esp32h4/include/hal/gdma_ll.h +++ b/components/hal/esp32h4/include/hal/gdma_ll.h @@ -25,13 +25,15 @@ static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) /** * @brief Reset the DMA module */ -static inline void gdma_ll_reset_register(int group_id) +static inline void _gdma_ll_reset_register(int group_id) { (void)group_id; PCR.gdma_conf.gdma_rst_en = 1; PCR.gdma_conf.gdma_rst_en = 0; } +#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__) + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h4/include/hal/lp_aon_ll.h b/components/hal/esp32h4/include/hal/lp_aon_ll.h new file mode 100644 index 0000000000..ec7bbcbd14 --- /dev/null +++ b/components/hal/esp32h4/include/hal/lp_aon_ll.h @@ -0,0 +1,106 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H4 LP_AON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/lp_aon_struct.h" +#include "hal/misc.h" +#include "esp32h4/rom/rtc.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get ext1 wakeup source status + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl1, aon_ext_wakeup_status); +} + +/** + * @brief Clear the ext1 wakeup source status + */ +static inline void lp_aon_ll_ext1_clear_wakeup_status(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl1, aon_ext_wakeup_status_clr, 1); +} + +/** + * @brief Set the wake-up LP_IO of the ext1 wake-up source + * @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7 + * @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level + * each bit's corresponding position is set to 0, the wakeup level will be low + * on the contrary, each bit's corresponding position is set to 1, the wakeup + * level will be high + */ +static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) +{ + uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); + wakeup_sel_mask |= io_mask; + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, wakeup_sel_mask); + + uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv); + wakeup_level_mask |= io_mask & level_mask; + wakeup_level_mask &= ~(io_mask & ~level_mask); + + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv, wakeup_level_mask); +} + +/** + * @brief Clear all ext1 wakup-source setting + */ +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, 0); +} + +/** + * @brief Get ext1 wakeup source setting + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); +} + + +/** + * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. + * Set the flag to inform + * @param true: deepsleep false: lightsleep + */ +static inline void lp_aon_ll_inform_wakeup_type(bool dslp) +{ + if (dslp) { + REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */ + + } else { + REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ + } +} + +/** + * @brief Set the maximum number of linked lists supported by REGDMA + * @param count: the maximum number of regdma link + */ +static inline void pau_ll_set_regdma_link_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/include/hal/pau_ll.h b/components/hal/esp32h4/include/hal/pau_ll.h new file mode 100644 index 0000000000..2aee1df282 --- /dev/null +++ b/components/hal/esp32h4/include/hal/pau_ll.h @@ -0,0 +1,218 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H4 PAU(Power Assist Unit) register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/pau_reg.h" +#include "soc/pau_struct.h" +#include "soc/pcr_struct.h" +#include "soc/lp_aon_struct.h" +#include "soc/lp_aon_reg.h" +#include "hal/pau_types.h" +#include "hal/assert.h" +#include "hal/misc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void pau_ll_enable_bus_clock(bool enable) +{ + if (enable) { + PCR.regdma_conf.regdma_clk_en = 1; + PCR.regdma_conf.regdma_rst_en = 0; + } else { + PCR.regdma_conf.regdma_clk_en = 0; + PCR.regdma_conf.regdma_rst_en = 1; + } +} + +static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) +{ + return LP_AON.backup_dma_cfg0.aon_regdma_error; +} + +static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) +{ + dev->regdma_conf.link_sel = link; +} + +static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem = to_mem ? 1 : 0; +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) +{ + dev->regdma_conf.start = enable; +} + +static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr) +{ + LP_AON.backup_dma_cfg2.aon_link_addr_aon = (uint32_t)link_addr; +} + +static inline void pau_ll_set_regdma_timeout_link_backup_wait(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_BACKUP_TOUT_THRES_AON, thres); +} + +static inline void pau_ll_set_regdma_timeout_read_interval(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG0_REG, LP_AON_READ_INTERVAL_AON, thres); +} + +static inline void pau_ll_set_regdma_timeout_burst_limit(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG0_REG, LP_AON_BURST_LIMIT_AON, thres); +} +static inline void pau_ll_set_regdma_timeout_max_link_work(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_WORK_TOUT_THRES_AON, thres); +} + +static inline void pau_ll_set_regdma_timeout_read_mode_try_time(pau_dev_t *dev, uint32_t thres) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_LINK_WAIT_TOUT_THRES_AON, thres); +} + +static inline void pau_ll_set_regdma_branch_max_link(pau_dev_t *dev, uint32_t max_link_len) +{ + REG_SET_FIELD(LP_AON_BACKUP_DMA_CFG1_REG, LP_AON_BRANCH_LINK_LENGTH_AON, max_link_len); +} + +static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) +{ + return dev->regdma_current_link_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) +{ + return dev->regdma_peri_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) +{ + return dev->regdma_mem_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) +{ + return dev->int_raw.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) +{ + return dev->int_st.val; +} + +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) +{ + dev->int_ena.done_int_ena = enable; +} + +static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable) +{ + dev->int_ena.error_int_ena = enable; +} + +static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) +{ + dev->int_clr.val = 0x1; +} + +static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) +{ + dev->int_clr.val = 0x2; +} + +static inline void pau_ll_arbiter_auto_retry_enable(pau_dev_t *dev, bool ena) +{ + dev->regdma_conf.sw_retry_en = ena; +} + +static inline void pau_ll_arbiter_fix_priority_enable(pau_dev_t *dev, bool ena) +{ + dev->regdma_conf.fix_pri_en = ena; +} + +/** + * arbiter result coding: + * 1: mac_req + * 2: pmu_req + * 3: sw_req + * 4: etm0_req + * 5: etm1_req + * 6: etm2_req + * 7: etm3_req +*/ +static inline uint32_t pau_ll_arbiter_get_start_result(pau_dev_t *dev) +{ + return dev->regdma_grant_result.grant_start_result; +} + +static inline uint32_t pau_ll_arbiter_get_done_result(pau_dev_t *dev) +{ + return dev->regdma_grant_result.grant_done_result; +} + +static inline void pau_ll_arbiter_clr_result_flag(pau_dev_t *dev) +{ + dev->regdma_grant_result.grant_result_clr = 1; +} + +static inline bool pau_ll_is_busy(pau_dev_t *dev) +{ + return dev->regdma_conf.paudma_busy; +} + +/** + * @brief Set the regdma_link_addr + * @param addr: the addr of regdma_link + */ +static inline void pau_ll_set_regdma_link_addr(uint32_t addr) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); +} + +/** + * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop + * for some reason and the execution count exceeds this configured number, a timeout will be triggered. + * @param count: the maximum number of loop + */ +static inline void pau_ll_set_regdma_link_loop_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count); +} + +/** + * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing + * registers and gets stuck on the bus, a timeout will be triggered. + * @param count: the maximum number of time + */ +static inline void pau_ll_set_regdma_link_reg_access_tout_threshold(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count); +} + +static inline void pau_ll_set_regdma_link_wait_retry_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count); +} + +static inline void pau_ll_set_regdma_link_wait_read_interval(int interval) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h4/pau_hal.c b/components/hal/esp32h4/pau_hal.c new file mode 100644 index 0000000000..e14160d601 --- /dev/null +++ b/components/hal/esp32h4/pau_hal.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for PAU (ESP32-H4 specific part) + +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/pau_hal.h" +#include "hal/pau_types.h" +#include "hal/lp_aon_ll.h" + +void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) +{ + pau_ll_set_regdma_link_addr((uint32_t)(*link_addr)[0]); +} + +void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + /* The link 3 of REGDMA is reserved, we use it as an extra linked list to + * provide backup and restore services for BLE, IEEE802.15.4 and possibly + * other modules. + * It is also used as software trigger REGDMA to backup and restore, and is + * used by the UT to test module driver retention function. + */ + pau_ll_select_regdma_entry_link(hal->dev, 3); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +#if SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE +void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) +{ + HAL_ASSERT(count > 0); + pau_ll_set_regdma_link_count(count - 1); +} +#endif + +void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) +{ + HAL_ASSERT(loop_num > 0 && time > 0); + pau_ll_set_regdma_link_loop_threshold(loop_num); + pau_ll_set_regdma_link_reg_access_tout_threshold(time); +} + +void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) +{ + HAL_ASSERT(count > 0 && interval > 0); + pau_ll_set_regdma_link_wait_retry_count(count); + pau_ll_set_regdma_link_wait_read_interval(interval); +} diff --git a/components/hal/esp32p4/include/hal/pau_ll.h b/components/hal/esp32p4/include/hal/pau_ll.h index a454a64db2..f2d5266b2c 100644 --- a/components/hal/esp32p4/include/hal/pau_ll.h +++ b/components/hal/esp32p4/include/hal/pau_ll.h @@ -55,14 +55,9 @@ static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, dev->regdma_conf.to_mem = to_mem ? 1 : 0; } -static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) { - dev->regdma_conf.start = 1; -} - -static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) -{ - dev->regdma_conf.start = 0; + dev->regdma_conf.start = enable; } static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) @@ -140,14 +135,9 @@ static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) return dev->int_st.val; } -static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) { - dev->int_ena.done_int_ena = 1; -} - -static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) -{ - dev->int_ena.done_int_ena = 0; + dev->int_ena.done_int_ena = enable; } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable) @@ -157,12 +147,12 @@ static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bo static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { - dev->int_clr.done_int_clr = 1; + dev->int_clr.val = 0x1; } static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { - dev->int_clr.error_int_clr = 1; + dev->int_clr.val = 0x2; } static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count) diff --git a/components/hal/esp32p4/pau_hal.c b/components/hal/esp32p4/pau_hal.c index ebf58c180f..963e6e7228 100644 --- a/components/hal/esp32p4/pau_hal.c +++ b/components/hal/esp32p4/pau_hal.c @@ -51,14 +51,14 @@ void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool back */ pau_ll_select_regdma_entry_link(hal->dev, 3); pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); - pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); } void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) { - pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); pau_ll_select_regdma_entry_link(hal->dev, 3); /* restore link select to default */ pau_ll_clear_regdma_backup_done_intr_state(hal->dev); } diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 658679fb7d..3ddec58754 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -43,6 +43,10 @@ config SOC_MODEM_CLOCK_SUPPORTED bool default y +config SOC_PAU_SUPPORTED + bool + default y + config SOC_WDT_SUPPORTED bool default y @@ -531,6 +535,14 @@ config SOC_PM_PAU_LINK_NUM int default 4 +config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE + bool + default y + +config SOC_PM_RETENTION_MODULE_NUM + int + default 32 + config SOC_MODEM_CLOCK_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32h4/include/soc/retention_periph_defs.h b/components/soc/esp32h4/include/soc/retention_periph_defs.h new file mode 100644 index 0000000000..dc5e35603f --- /dev/null +++ b/components/soc/esp32h4/include/soc/retention_periph_defs.h @@ -0,0 +1,93 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum periph_retention_module { + SLEEP_RETENTION_MODULE_MIN = 0, + SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ + /* clock module, which includes system and modem */ + SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, + /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, + * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ + SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + /* Timer Group by target*/ + SLEEP_RETENTION_MODULE_TG0_WDT = 4, + SLEEP_RETENTION_MODULE_TG1_WDT = 5, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + /* GDMA by channel */ + SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, + SLEEP_RETENTION_MODULE_GDMA_CH3 = 11, + SLEEP_RETENTION_MODULE_GDMA_CH4 = 12, + /* MISC Peripherals */ + SLEEP_RETENTION_MODULE_ADC = 13, + SLEEP_RETENTION_MODULE_I2C0 = 14, + SLEEP_RETENTION_MODULE_I2C1 = 15, + SLEEP_RETENTION_MODULE_RMT0 = 16, + SLEEP_RETENTION_MODULE_UART0 = 17, + SLEEP_RETENTION_MODULE_UART1 = 18, + SLEEP_RETENTION_MODULE_I2S0 = 19, + SLEEP_RETENTION_MODULE_ETM0 = 20, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 21, + SLEEP_RETENTION_MODULE_TWAI0 = 22, + SLEEP_RETENTION_MODULE_PARLIO0 = 23, + SLEEP_RETENTION_MODULE_GPSPI2 = 24, + SLEEP_RETENTION_MODULE_LEDC = 25, + SLEEP_RETENTION_MODULE_PCNT0 = 26, + SLEEP_RETENTION_MODULE_MCPWM0 = 27, + + /* Modem module, which includes BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_BLE_MAC = 28, + SLEEP_RETENTION_MODULE_BT_BB = 29, + SLEEP_RETENTION_MODULE_802154_MAC = 30, + + SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 +} periph_retention_module_t; + +#define is_top_domain_module(m) \ + ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH3) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH4) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_PCNT0) ? true \ + : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ + : false) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index b74aa68ab6..7cdd816143 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -69,7 +69,7 @@ // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32H4] IDF-12295 // #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256 // #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32H4] IDF-12286 -// #define SOC_PAU_SUPPORTED 1 +#define SOC_PAU_SUPPORTED 1 // #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12274 // #define SOC_LP_AON_SUPPORTED 1 // #define SOC_LP_PERIPHERALS_SUPPORTED 1 @@ -531,7 +531,9 @@ // #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) // #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1) -#define SOC_PM_PAU_LINK_NUM (4) +#define SOC_PM_PAU_LINK_NUM (4) +#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1) +#define SOC_PM_RETENTION_MODULE_NUM (32) /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ // #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) // TODO: [ESP32H4] IDF-12285 diff --git a/components/soc/esp32h4/wdt_periph.c b/components/soc/esp32h4/wdt_periph.c index 0a5961d41e..3d9932ed10 100644 --- a/components/soc/esp32h4/wdt_periph.c +++ b/components/soc/esp32h4/wdt_periph.c @@ -7,7 +7,7 @@ #include "soc/wdt_periph.h" #include "soc/soc_caps.h" -#if SOC_PAU_SUPPORTED +#if SOC_PAU_SUPPORTED && SOC_MWDT_SUPPORT_SLEEP_RETENTION #define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h index 5d3e940561..07885ae002 100644 --- a/components/soc/include/soc/regdma.h +++ b/components/soc/include/soc/regdma.h @@ -49,6 +49,7 @@ extern "C" { #define REGDMA_MODEM_BT_BB_LINK(_pri) ((0x15 << 8) | _pri) #define REGDMA_MODEM_IEEE802154_LINK(_pri) ((0x16 << 8) | _pri) #define REGDMA_GDMA_LINK(_pri) ((0x17 << 8) | _pri) +#define REGDMA_AHB_DMA_LINK(_pri) ((0x17 << 8) | _pri) #define REGDMA_I2C_LINK(_pri) ((0x18 << 8) | _pri) #define REGDMA_RMT_LINK(_pri) ((0x19 << 8) | _pri) #define REGDMA_TG0_WDT_LINK(_pri) ((0x1A << 8) | _pri)