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support BLE with 26M xtal for esp32c2

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This commit is contained in:
Shen Weilong
2022-07-12 21:10:58 +08:00
committed by shenweilong
parent b66be87f88
commit 028d071e84
5 changed files with 16 additions and 6 deletions
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components/bt/controller/esp32c2/bt.c
+7 -1
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@@ -571,12 +571,18 @@ void ble_rtc_clk_init(void)
// LP_TIMER_SEL_XTAL -> 1
// LP_TIMER_SEL_8M -> 0
// LP_TIMER_SEL_RTC_SLOW -> 0
// LP_TIMER_CLK_DIV_NUM -> 1250
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
// LP_TIMER_CLK_DIV_NUM -> 130
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#else
// LP_TIMER_CLK_DIV_NUM -> 250
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#endif // CONFIG_ESP32C2_XTAL_FREQ_26
// MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
// MODEM_CLKRST_ETM_CLK_SEL -> 0