From 95dbc746ed12f9c492c24379a4659670ddc88e71 Mon Sep 17 00:00:00 2001
From: Ivan Grokhotkov <ivan@espressif.com>
Date: Thu, 16 Jun 2022 15:28:21 +0200
Subject: [PATCH] esp_system: fix garbled UART output on startup on esp32s2

Closes https://github.com/espressif/esp-idf/issues/9168
---
 components/esp_system/port/soc/esp32s2/clk.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c
index 7d78470182..d11c43233e 100644
--- a/components/esp_system/port/soc/esp32s2/clk.c
+++ b/components/esp_system/port/soc/esp32s2/clk.c
@@ -81,6 +81,12 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
     rst_reas = rtc_get_reset_reason(0);
     if (rst_reas == POWERON_RESET) {
         cfg.cali_ocode = 1;
+        /* Ocode calibration will switch to XTAL frequency, need to wait for UART FIFO
+         * to be empty, to avoid garbled output.
+         */
+        if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
+            esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+        }
     }
     rtc_init(cfg);