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refactor(ulp_riscv): Modify ESP_EARLY_LOG to ESP_LOG and move it outside critical section

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Moved the error logs outside critical section for i2c communication errors
like READ fail, WRITE fail etc. in the ulp_riscv_i2c component

Also changed the error log API from ESP_EARLY_LOG to ESP_LOG, so we can support
tag based filtering and enabling/disabling of logs

Closes https://github.com/espressif/esp-idf/issues/17425
This commit is contained in:
Meet Patel
2025-08-18 14:21:29 +05:30
parent bf0c45e18d
commit 032e141150
1 changed files with 18 additions and 9 deletions
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27
components/ulp/ulp_riscv/ulp_riscv_i2c.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -321,6 +321,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
uint32_t i = 0; uint32_t i = 0;
uint32_t cmd_idx = 0; uint32_t cmd_idx = 0;
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
uint32_t status = 0;
if (size == 0) { if (size == 0) {
// Quietly return // Quietly return
@@ -379,10 +380,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
/* Clear the Rx data interrupt bit */ /* Clear the Rx data interrupt bit */
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR);
} else { } else {
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Read Failed!"); status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
uint32_t status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status);
break; break;
} }
@@ -390,6 +388,12 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
portEXIT_CRITICAL(&rtc_i2c_lock); portEXIT_CRITICAL(&rtc_i2c_lock);
if (ret != ESP_OK) {
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Read Failed!");
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
}
/* Clear the RTC I2C transmission bits */ /* Clear the RTC I2C transmission bits */
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE);
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START);
@@ -417,6 +421,7 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
uint32_t i = 0; uint32_t i = 0;
uint32_t cmd_idx = 0; uint32_t cmd_idx = 0;
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
uint32_t status = 0;
if (size == 0) { if (size == 0) {
// Quietly return // Quietly return
@@ -455,10 +460,7 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
/* Clear the Tx data interrupt bit */ /* Clear the Tx data interrupt bit */
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR);
} else { } else {
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Write Failed!"); status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
uint32_t status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status);
break; break;
} }
@@ -466,6 +468,13 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
portEXIT_CRITICAL(&rtc_i2c_lock); portEXIT_CRITICAL(&rtc_i2c_lock);
/* In case of error, print the status after critical section */
if (ret != ESP_OK) {
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Write Failed!");
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
}
/* Clear the RTC I2C transmission bits */ /* Clear the RTC I2C transmission bits */
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE);
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START);