Merge branch 'remove/remove_c5_beta3_support' into 'master'

remove(c5beta3): remove esp32c5 beta3 support

Closes IDF-9197

See merge request espressif/esp-idf!31412

.codespellrc

@@ -1,4 +1,4 @@
 [codespell]
 skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane
 write-changes = true

Kconfig

@@ -118,28 +118,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32c5"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
-
-    # TODO: IDF-9197
-    choice IDF_TARGET_ESP32C5_VERSION
-        prompt "ESP32-C5 version"
-        depends on IDF_TARGET_ESP32C5
-        default IDF_TARGET_ESP32C5_MP_VERSION
-        help
-            ESP32-C5 will support two versions for a period.
-            This option is for internal use only.
-            Select the one that matches your chip model.
-
-        config IDF_TARGET_ESP32C5_BETA3_VERSION
-            bool
-            prompt "ESP32-C5 beta3"
-            select ESPTOOLPY_NO_STUB
-
-        config IDF_TARGET_ESP32C5_MP_VERSION
-            bool
-            prompt "ESP32-C5 MP"
-            select ESPTOOLPY_NO_STUB
         select IDF_ENV_FPGA
-    endchoice
 
     config IDF_TARGET_ESP32P4
         bool
@@ -173,8 +152,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default 0x000D if IDF_TARGET_ESP32C6
         default 0x0010 if IDF_TARGET_ESP32H2
         default 0x0012 if IDF_TARGET_ESP32P4
-        default 0x0011 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_BETA3_VERSION  # TODO: IDF-9197
+        default 0x0017 if IDF_TARGET_ESP32C5
-        default 0x0017 if IDF_TARGET_ESP32C5 && IDF_TARGET_ESP32C5_MP_VERSION     # TODO: IDF-9197
         default 0x0014 if IDF_TARGET_ESP32C61
         default 0xFFFF
 

components/bootloader/subproject/main/CMakeLists.txt

@@ -1,13 +1,7 @@
 idf_component_register(SRCS "bootloader_start.c"
                     REQUIRES bootloader bootloader_support)
 
-if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+set(target_folder "${target}")
-    set(target_folder "esp32c5/beta3")
-elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
-    set(target_folder "esp32c5/mp")
-else()
-    set(target_folder "${target}")
-endif()
 
 idf_build_get_property(target IDF_TARGET)
 set(scripts "ld/${target_folder}/bootloader.ld")

components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld

@@ -1,310 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/** Simplified memory map for the bootloader.
- *  Make sure the bootloader can load into main memory without overwriting itself.
- *
- *  TODO: [ESP32C5] IDF-9358 Check this file whether need update for MP ROM
- *  ESP32-C5 ROM static data usage is as follows:
- *  - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
- *  - 0x4087ebc0 - 0x40880000: ROM .bss and .data (not easily reclaimable)
- *
- *  The 2nd stage bootloader can take space up to the end of ROM shared
- *  buffers area (0x4087cbc0).
- */
-
-/* We consider 0x4087cbc0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
- * and work out iram_seg and iram_loader_seg addresses from there, backwards.
- */
-
-/* These lengths can be adjusted, if necessary: */
-bootloader_usable_dram_end = 0x4087cbc0;
-bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
-bootloader_dram_seg_len = 0x5000;
-bootloader_iram_loader_seg_len = 0x7000;
-bootloader_iram_seg_len = 0x2200;
-
-/* Start of the lower region is determined by region size and the end of the higher region */
-bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
-bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
-bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
-bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
-
-MEMORY
-{
-  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
-  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
-  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
-}
-
-/* The app may use RAM for static allocations up to the start of iram_loader_seg.
- * If you have changed something above and this assert fails:
- * 1. Check what the new value of bootloader_iram_loader_seg start is.
- * 2. Update the value in this assert.
- * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
- */
-ASSERT(bootloader_iram_loader_seg_start == 0x4086EBC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
-
-/* Default entry point: */
-ENTRY(call_start_cpu0);
-
-SECTIONS
-{
-
-  .iram_loader.text :
-  {
-    . = ALIGN (16);
-    _loader_text_start = ABSOLUTE(.);
-    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
-    *liblog.a:(.literal .text .literal.* .text.*)
-    /* we use either libgcc or compiler-rt, so put similar entries for them here */
-    *libgcc.a:(.literal .text .literal.* .text.*)
-    *libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
-    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
-    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
-    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
-    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
-    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
-    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
-    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
-    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
-    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
-    *libefuse.a:*.*(.literal .text .literal.* .text.*)
-    *(.fini.literal)
-    *(.fini)
-    *(.gnu.version)
-    _loader_text_end = ABSOLUTE(.);
-  } > iram_loader_seg
-
-  .iram.text :
-  {
-    . = ALIGN (16);
-    *(.entry.text)
-    *(.init.literal)
-    *(.init)
-  } > iram_seg
-
-
-  /* Shared RAM */
-  .dram0.bss (NOLOAD) :
-  {
-    . = ALIGN (8);
-    _dram_start = ABSOLUTE(.);
-    _bss_start = ABSOLUTE(.);
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-  } > dram_seg
-
-  .dram0.bootdesc : ALIGN(0x10)
-  {
-    _data_start = ABSOLUTE(.);
-    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
-  } > dram_seg
-
-  .dram0.data :
-  {
-    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
-    *(.data)
-    *(.data.*)
-    *(.gnu.linkonce.d.*)
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.gnu.linkonce.s2.*)
-    *(.jcr)
-    _data_end = ABSOLUTE(.);
-  } > dram_seg
-
-  .dram0.rodata :
-  {
-    _rodata_start = ABSOLUTE(.);
-    *(.rodata)
-    *(.rodata.*)
-    *(.gnu.linkonce.r.*)
-    *(.rodata1)
-    *(.sdata2 .sdata2.* .srodata .srodata.*)
-    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
-    *(.xt_except_table)
-    *(.gcc_except_table)
-    *(.gnu.linkonce.e.*)
-    *(.gnu.version_r)
-    *(.eh_frame_hdr)
-    *(.eh_frame)
-    . = (. + 3) & ~ 3;
-    /* C++ constructor and destructor tables, properly ordered: */
-    __init_array_start = ABSOLUTE(.);
-    KEEP (*crtbegin.*(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    __init_array_end = ABSOLUTE(.);
-    KEEP (*crtbegin.*(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    /*  C++ exception handlers table:  */
-    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
-    *(.xt_except_desc)
-    *(.gnu.linkonce.h.*)
-    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
-    *(.xt_except_desc_end)
-    *(.dynamic)
-    *(.gnu.version_d)
-    _rodata_end = ABSOLUTE(.);
-    /* Literals are also RO data. */
-    _lit4_start = ABSOLUTE(.);
-    *(*.lit4)
-    *(.lit4.*)
-    *(.gnu.linkonce.lit4.*)
-    _lit4_end = ABSOLUTE(.);
-    . = ALIGN(4);
-    _dram_end = ABSOLUTE(.);
-  } > dram_seg
-
-  .iram.text :
-  {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.iram .iram.*) /* catch stray IRAM_ATTR */
-    *(.fini.literal)
-    *(.fini)
-    *(.gnu.version)
-
-    /** CPU will try to prefetch up to 16 bytes of
-      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
-      * safe access to up to 16 bytes after the last real instruction, add
-      * dummy bytes to ensure this
-      */
-    . += 16;
-
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-  } > iram_seg
-
-  .riscv.attributes 0: { *(.riscv.attributes) }
-
-  /* DWARF 1 */
-  .debug              0 : { *(.debug) }
-  .line               0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo      0 : { *(.debug_srcinfo) }
-  .debug_sfnames      0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges      0 : { *(.debug_aranges) }
-  .debug_pubnames     0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev       0 : { *(.debug_abbrev) }
-  .debug_line         0 : { *(.debug_line) }
-  .debug_frame        0 : { *(.debug_frame) }
-  .debug_str          0 : { *(.debug_str) }
-  .debug_loc          0 : { *(.debug_loc) }
-  .debug_macinfo      0 : { *(.debug_macinfo) }
-  .debug_pubtypes     0 : { *(.debug_pubtypes) }
-  /* DWARF 3 */
-  .debug_ranges       0 : { *(.debug_ranges) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames    0 : { *(.debug_weaknames) }
-  .debug_funcnames    0 : { *(.debug_funcnames) }
-  .debug_typenames    0 : { *(.debug_typenames) }
-  .debug_varnames     0 : { *(.debug_varnames) }
-  /* GNU DWARF 2 extensions */
-  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
-  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
-  /* DWARF 4 */
-  .debug_types        0 : { *(.debug_types) }
-  /* DWARF 5 */
-  .debug_addr         0 : { *(.debug_addr) }
-  .debug_line_str     0 : { *(.debug_line_str) }
-  .debug_loclists     0 : { *(.debug_loclists) }
-  .debug_macro        0 : { *(.debug_macro) }
-  .debug_names        0 : { *(.debug_names) }
-  .debug_rnglists     0 : { *(.debug_rnglists) }
-  .debug_str_offsets  0 : { *(.debug_str_offsets) }
-
-  .comment 0 : { *(.comment) }
-  .note.GNU-stack 0: { *(.note.GNU-stack) }
-
-  /**
-   * Discarding .rela.* sections results in the following mapping:
-   * .rela.text.* -> .text.*
-   * .rela.data.* -> .data.*
-   * And so forth...
-   */
-  /DISCARD/ : { *(.rela.*) }
-
-}
-
-
-/**
- *  Appendix: Memory Usage of ROM bootloader
- *
- * 0x4086b2b8 ------------------> _dram0_0_start
- *            |               |
- *            |               |
- *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
- *            |               |
- *            |               |
- * 0x4087cbc0 ------------------> __stack_sentry
- *            |               |
- *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
- *            |               |
- * 0x4087ebc0 ------------------> __stack (pro cpu)
- *            |               |
- *            |               |
- *            |               |   3. Shared memory only used in startup code or nonos/early boot*
- *            |               |      (can be freed when IDF runs)
- *            |               |
- *            |               |
- * 0x4087fb14 ------------------> _dram0_rtos_reserved_start
- *            |               |
- *            |               |
- *            |               |   4. Shared memory used in startup code and when IDF runs
- *            |               |
- *            |               |
- * 0x4087fefc ------------------> _dram0_rtos_reserved_end
- *            |               |
- * 0x4087ffb8 ------------------> _data_start_interface
- *            |               |
- *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
- *            |               |
- * 0x40880000 ------------------> _data_end_interface
- */

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c

@@ -14,11 +14,8 @@
 #include "esp32c5/rom/efuse.h"
 #include "soc/gpio_periph.h"
 #include "soc/io_mux_reg.h"
-// TODO: IDF-9197
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
 #include "esp_rom_efuse.h"
 #include "soc/efuse_reg.h"
-#endif
 #include "soc/spi_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/soc_caps.h"
@@ -207,19 +204,10 @@ static void bootloader_spi_flash_resume(void)
 
 esp_err_t bootloader_init_spi_flash(void)
 {
-// TODO: IDF-9197
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     // On ESP32C5, MSPI source clock's default HS divider leads to 120MHz, which is unusable before calibration
     // Therefore, before switching SOC_ROOT_CLK to HS, we need to set MSPI source clock HS divider to make it run at
     // 80MHz after the switch. PLL = 480MHz, so divider is 6.
     clk_ll_mspi_fast_set_hs_divider(6);
-#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    /* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
-       need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI，
-       and we need to check flash freq before restart as well */
-    clk_ll_mspi_fast_set_divider(1);
-    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
-#endif
 
     bootloader_init_flash_configure();
     bootloader_spi_flash_resume();

components/bootloader_support/include/esp_app_format.h

@@ -8,9 +8,6 @@
 #include <inttypes.h>
 #include "esp_assert.h"
 
-// TODO: IDF-9197
-#include "sdkconfig.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -28,11 +25,7 @@ typedef enum {
     ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
     ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
     ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
+    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 */
-    ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 beta3 (MPW)*/
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    ESP_CHIP_ID_ESP32C5 = 0x0017, /*!< chip ID: ESP32-C5 MP */
-#endif
     ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;
 

components/bootloader_support/src/bootloader_random_esp32c5.c

@@ -3,7 +3,6 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "sdkconfig.h"
 #include "soc/soc.h"
 #include "soc/pcr_reg.h"
 #include "soc/pmu_reg.h"
@@ -12,12 +11,12 @@
 
 void bootloader_random_enable(void)
 {
-// TODO: [ESP32C5] IDF-8626, IDF-9197
+// TODO: [ESP32C5] IDF-8626
     ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
 }
 
 void bootloader_random_disable(void)
 {
-// TODO: [ESP32C5] IDF-8626, IDF-9197
+// TODO: [ESP32C5] IDF-8626
     ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
 }

components/bootloader_support/test_apps/rtc_custom_section/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/driver/deprecated/pcnt_legacy.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,7 @@
 #include "hal/gpio_hal.h"
 #include "soc/pcnt_periph.h"
 #include "esp_rom_gpio.h"
+#include "esp_private/gpio.h"
 
 #define PCNT_CHANNEL_ERR_STR  "PCNT CHANNEL ERROR"
 #define PCNT_UNIT_ERR_STR  "PCNT UNIT ERROR"
@@ -86,14 +87,14 @@ static inline esp_err_t _pcnt_set_pin(pcnt_port_t pcnt_port, pcnt_unit_t unit, p
     PCNT_CHECK(GPIO_IS_VALID_GPIO(ctrl_io) || ctrl_io < 0, PCNT_GPIO_ERR_STR, ESP_ERR_INVALID_ARG);
 
     if (pulse_io >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[pulse_io], PIN_FUNC_GPIO);
+        gpio_func_sel(pulse_io, PIN_FUNC_GPIO);
         gpio_set_direction(pulse_io, GPIO_MODE_INPUT);
         gpio_set_pull_mode(pulse_io, GPIO_PULLUP_ONLY);
         esp_rom_gpio_connect_in_signal(pulse_io, pcnt_periph_signals.groups[pcnt_port].units[unit].channels[channel].pulse_sig, 0);
     }
 
     if (ctrl_io >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[ctrl_io], PIN_FUNC_GPIO);
+        gpio_func_sel(ctrl_io, PIN_FUNC_GPIO);
         gpio_set_direction(ctrl_io, GPIO_MODE_INPUT);
         gpio_set_pull_mode(ctrl_io, GPIO_PULLUP_ONLY);
         esp_rom_gpio_connect_in_signal(ctrl_io, pcnt_periph_signals.groups[pcnt_port].units[unit].channels[channel].control_sig, 0);

components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/driver/test_apps/legacy_mcpwm_driver/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |

components/driver/test_apps/legacy_pcnt_driver/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

components/driver/test_apps/legacy_rmt_driver/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/driver/test_apps/legacy_timer_driver/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/efuse/test_apps/README.md

@@ -1,3 +1,3 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
 

components/esp_driver_gptimer/test_apps/gptimer/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_i2s/test_apps/i2s/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md

@@ -1,3 +1,3 @@
-| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
 

components/esp_driver_ledc/src/ledc.c

@@ -22,6 +22,7 @@
 #include "esp_rom_sys.h"
 #include "clk_ctrl_os.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/gpio.h"
 #include "esp_memory_utils.h"
 
 static __attribute__((unused)) const char *LEDC_TAG = "ledc";
@@ -645,7 +646,7 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc
     LEDC_ARG_CHECK(ledc_channel < LEDC_CHANNEL_MAX, "ledc_channel");
     LEDC_ARG_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "gpio_num");
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
-    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
+    gpio_func_sel(gpio_num, PIN_FUNC_GPIO);
     gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
     esp_rom_gpio_connect_out_signal(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
     return ESP_OK;
@@ -709,7 +710,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
     ESP_LOGD(LEDC_TAG, "LEDC_PWM CHANNEL %"PRIu32"|GPIO %02u|Duty %04"PRIu32"|Time %"PRIu32,
              ledc_channel, gpio_num, duty, timer_select);
     /*set LEDC signal in gpio matrix*/
-    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
+    gpio_func_sel(gpio_num, PIN_FUNC_GPIO);
     gpio_set_level(gpio_num, output_invert);
     gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
     esp_rom_gpio_connect_out_signal(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, output_invert, 0);

components/esp_driver_ledc/test_apps/ledc/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c

@@ -14,6 +14,7 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "unity.h"
+#include "hal/gpio_ll.h"
 #include "soc/gpio_periph.h"
 #include "soc/io_mux_reg.h"
 #include "esp_system.h"
@@ -509,7 +510,7 @@ static void tear_testbench(void)
 static int wave_count(int last_time)
 {
     // The input ability of PULSE_IO is disabled after ledc driver install, so we need to re-enable it again
-    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[PULSE_IO]);
+    gpio_ll_input_enable(&GPIO, PULSE_IO);
     int test_counter = 0;
     TEST_ESP_OK(pcnt_unit_clear_count(pcnt_unit));
     TEST_ESP_OK(pcnt_unit_start(pcnt_unit));

components/esp_driver_mcpwm/test_apps/mcpwm/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_pcnt/test_apps/pulse_cnt/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_rmt/test_apps/rmt/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_sdspi/test_apps/sdspi/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_spi/test_apps/master/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_spi/test_apps/param/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_spi/test_apps/slave/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_spi/test_apps/slave_hd/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_uart/test_apps/rs485/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_uart/test_apps/uart/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_hw_support/CMakeLists.txt

@@ -153,13 +153,7 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "esp_clock_output.c")
     endif()
 
-    if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+    if(CONFIG_IDF_TARGET_ESP32C5)
-        list(REMOVE_ITEM srcs
-                "sleep_gpio.c"        # TODO: [ESP32C5] IDF-8638
-                "port/esp_clk_tree_common.c"    # TODO: [ESP32C5] IDF-8638
-            )
-    endif()
-    if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
         list(REMOVE_ITEM srcs
                 "sleep_modes.c"       # TODO: [ESP32C5] IDF-8638
                 "sleep_modem.c"       # TODO: [ESP32C5] IDF-8638
@@ -168,6 +162,7 @@ if(NOT BOOTLOADER_BUILD)
                 "port/esp_clk_tree_common.c"    # TODO: [ESP32C5] IDF-8638
             )
     endif()
+
     if(CONFIG_IDF_TARGET_ESP32C61)  # TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-9248
         list(REMOVE_ITEM srcs
                 "sleep_cpu.c"

components/esp_hw_support/include/esp_chip_info.h

@@ -27,13 +27,9 @@ typedef enum {
     CHIP_ESP32C2 = 12, //!< ESP32-C2
     CHIP_ESP32C6 = 13, //!< ESP32-C6
     CHIP_ESP32H2 = 16, //!< ESP32-H2
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION  // TODO: IDF-9197
-    CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 (MPW)
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    CHIP_ESP32C5 = 23, //!< ESP32-C5 MP
-#endif
     CHIP_ESP32P4 = 18, //!< ESP32-P4
     CHIP_ESP32C61= 20, //!< ESP32-C61
+    CHIP_ESP32C5 = 23, //!< ESP32-C5
     CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator
 } esp_chip_model_t;
 
@@ -66,7 +62,7 @@ void esp_chip_info(esp_chip_info_t* out_info);
  * @brief Cache lock bug exists or not
  *
  * @return
- *          - ture : bug exists
+ *          - true : bug exists
  *          - false : bug not exists
  */
 bool soc_has_cache_lock_bug(void);

components/esp_hw_support/port/esp32c5/CMakeLists.txt

@@ -1,20 +1,8 @@
-if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
+set(srcs "rtc_clk_init.c"
-    set(srcs "rtc_clk_init.c"
-        "rtc_clk.c"
-        "rtc_time.c"
-        "pmu_init.c"
-        "pmu_sleep.c"
-        "pmu_param.c"
-        "chip_info.c"
-    )
-endif()
-if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
-    set(srcs "rtc_clk_init.c"
     "rtc_time.c"
     "rtc_clk.c"
     "chip_info.c"
-    )
+)
-endif()
 
 
 if(NOT BOOTLOADER_BUILD)

components/esp_hw_support/port/esp32c5/Kconfig.rtc

@@ -1,13 +1,10 @@
 choice RTC_CLK_SRC
     prompt "RTC clock source"
-    # TODO: IDF-9197
+    default RTC_CLK_SRC_INT_RC
-    default RTC_CLK_SRC_INT_RC if IDF_TARGET_ESP32C5_MP_VERSION
-    default RTC_CLK_SRC_INT_RC32K if IDF_TARGET_ESP32C5_BETA3_VERSION
     help
         Choose which clock is used as RTC clock source.
 
     config RTC_CLK_SRC_INT_RC
-        depends on IDF_TARGET_ESP32C5_MP_VERSION
         bool "Internal 136kHz RC oscillator"
     config RTC_CLK_SRC_EXT_CRYS
         bool "External 32 kHz crystal"

components/esp_hw_support/port/esp32c5/Kconfig.xtal

@@ -1,6 +1,5 @@
 choice XTAL_FREQ
     prompt "Main XTAL frequency"
-    default XTAL_FREQ_48 if IDF_TARGET_ESP32C5_BETA3_VERSION
     default XTAL_FREQ_AUTO
     help
         This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target.
@@ -11,14 +10,7 @@ choice XTAL_FREQ
         the crystal frequency, and record to PCR_CLK_XTAL_FREQ register field.
 
     config XTAL_FREQ_AUTO
-        depends on IDF_TARGET_ESP32C5_MP_VERSION
         bool "Autodetect"
-    config XTAL_FREQ_40
-        depends on IDF_TARGET_ESP32C5_BETA3_VERSION
-        bool "40 MHz"
-    config XTAL_FREQ_48
-        depends on IDF_TARGET_ESP32C5_BETA3_VERSION
-        bool "48 MHz"
 endchoice
 
 # soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported
@@ -26,5 +18,3 @@ endchoice
 config XTAL_FREQ
     int
     default 0  if XTAL_FREQ_AUTO
-    default 40 if XTAL_FREQ_40
-    default 48 if XTAL_FREQ_48

components/esp_hw_support/port/esp32c5/clock_retention_init.c

@@ -12,11 +12,7 @@ static __attribute__((unused)) const char *TAG = "sleep_clock";
 
 esp_err_t sleep_clock_system_retention_init(void *arg)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#define N_REGS_PCR()    (((PCR_SRAM_POWER_CONF_1_REG - DR_REG_PCR_BASE) / 4) + 1)
-    #define N_REGS_PCR()    (((PCR_SRAM_POWER_CONF_1_REG - DR_REG_PCR_BASE) / 4) + 1)
-#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    #define N_REGS_PCR()    (((PCR_PWDET_SAR_CLK_CONF_REG - DR_REG_PCR_BASE) / 4) + 1)
-#endif
 
     const static sleep_retention_entries_config_t pcr_regs_retention[] = {
         [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* pcr */

components/esp_hw_support/port/esp32c5/cpu_region_protect.c

@@ -5,7 +5,6 @@
  */
 
 #include <stdint.h>
-#include "sdkconfig.h"
 #include "soc/soc.h"
 #include "esp_cpu.h"
 #include "esp_fault.h"
@@ -24,14 +23,6 @@
 #define CONDITIONAL_RWX         RWX
 #endif
 
-// TODO: IDF-9197
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-void esp_cpu_configure_region_protection(void)
-{
-    // TODO: [ESP32C5] IDF-8833
-}
-
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
 static void esp_cpu_configure_invalid_regions(void)
 {
     const unsigned PMA_NONE                            = PMA_L | PMA_EN;
@@ -220,4 +211,3 @@ void esp_cpu_configure_region_protection(void)
     PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
     _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
 }
-#endif  // CONFIG_IDF_TARGET_ESP32C5_MP_VERSION

components/esp_hw_support/port/esp32c5/esp_clk_tree.c

@@ -38,11 +38,6 @@ uint32_t *freq_value)
     case SOC_MOD_CLK_PLL_F240M:
         clk_src_freq = CLK_LL_PLL_240M_FREQ_MHZ * MHZ;
         break;
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    case SOC_MOD_CLK_RTC_FAST:
-        clk_src_freq = 20 * MHZ;
-        break;
-#endif
     case SOC_MOD_CLK_SPLL:
         clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ * MHZ;
         break;

components/esp_hw_support/port/esp32c5/include/soc/rtc.h

@@ -135,9 +135,7 @@ typedef enum {
     RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K,            //!< Internal 32kHz RC oscillator, as one type of 32k clock
     RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K,       //!< External 32kHz XTAL, as one type of 32k clock
     RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW,  //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     RTC_CAL_RC_FAST                                        //!< Internal 20MHz RC oscillator
-#endif
 } rtc_cal_sel_t;
 
 /**
@@ -187,17 +185,6 @@ void rtc_clk_init(rtc_clk_config_t cfg);
  */
 soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-/**
- * @brief Update XTAL frequency
- *
- * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
- * after startup.
- *
- * @param xtal_freq New frequency value
- */
-void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
-#endif
 
 /**
  * @brief Enable or disable 32 kHz XTAL oscillator

components/esp_hw_support/port/esp32c5/pmu_param.c

@@ -367,11 +367,7 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 # define PMU_SLOW_CLK_USE_EXT_XTAL  (0)
 #endif
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-#define PMU_LP_DEFAULT_XPD_RC32K (1)
-#else
 #define PMU_LP_DEFAULT_XPD_RC32K (0)
-#endif
 
 #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \

components/esp_hw_support/port/esp32c5/rtc_clk.c

@@ -9,7 +9,6 @@
 #include <stddef.h>
 #include <assert.h>
 #include <stdlib.h>
-#include "sdkconfig.h"
 #include "esp32c5/rom/rtc.h"
 #include "soc/rtc.h"
 #include "soc/soc_caps.h"
@@ -117,9 +116,7 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
 uint32_t rtc_clk_slow_freq_get_hz(void)
 {
     switch (rtc_clk_slow_src_get()) {
-#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
-#endif
     case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
     case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
     case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX;
@@ -175,9 +172,6 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
     /* WAIT CALIBRATION DONE */
     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    esp_rom_delay_us(10); // wait for true stop // TODO: check this
-#endif
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
     rtc_clk_enable_i2c_ana_master_clock(false);
@@ -191,39 +185,17 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
  */
 static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    /* Configure clk mspi fast to XTAL*/
-    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
-    clk_ll_mspi_fast_set_divider(1);
-
-    clk_ll_cpu_set_divider(div);
-    clk_ll_ahb_set_divider(div);
-    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
-    clk_ll_bus_update();
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     clk_ll_ahb_set_ls_divider(div);
     clk_ll_cpu_set_ls_divider(div);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
-#endif
     esp_rom_set_cpu_ticks_per_us(cpu_freq);
 }
 
 static void rtc_clk_cpu_freq_to_8m(void)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    /* Configure clk mspi fast to XTAL*/
-    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
-    clk_ll_mspi_fast_set_divider(1);
-
-    clk_ll_cpu_set_divider(1);
-    clk_ll_ahb_set_divider(1);
-    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
-    clk_ll_bus_update();
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     clk_ll_ahb_set_ls_divider(1);
     clk_ll_cpu_set_ls_divider(1);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
-#endif
     esp_rom_set_cpu_ticks_per_us(20);
 }
 
@@ -234,24 +206,9 @@ static void rtc_clk_cpu_freq_to_8m(void)
  */
 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    rtc_cpu_freq_config_t cfg;
-    rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &cfg);
-    // Set AHB always be 40MHz
-    clk_ll_ahb_set_divider(cfg.source_freq_mhz / 40);
-    clk_ll_cpu_set_divider(cfg.div);
-    clk_ll_cpu_set_src(cfg.source);
-    clk_ll_bus_update();
-    esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
-
-    /* Configure clk mspi fast to 80m*/
-    clk_ll_mspi_fast_set_divider(6);
-    clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_SPLL);
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
     clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
     esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
-#endif
 }
 
 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
@@ -262,16 +219,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
     uint32_t real_freq_mhz;
 
     uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION && (CONFIG_XTAL_FREQ == 48)
-    // To maintain APB_MAX (40MHz) while lowering CPU frequency when using a 48MHz XTAL, have to let CPU frequnecy be
-    // 40MHz with PLL_F160M or PLL_F240M clock source. This is a special case, has to handle separately.
-    if (freq_mhz == 40) {
-        real_freq_mhz = freq_mhz;
-        source = SOC_CPU_CLK_SRC_PLL_F160M;
-        source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
-        divider = CLK_LL_PLL_160M_FREQ_MHZ / freq_mhz;
-    } else
-#endif
     if (freq_mhz <= xtal_freq && freq_mhz != 0) {
         divider = xtal_freq / freq_mhz;
         real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
@@ -282,18 +229,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
 
         source_freq_mhz = xtal_freq;
         source = SOC_CPU_CLK_SRC_XTAL;
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    } else if (freq_mhz == 240) {
-        real_freq_mhz = freq_mhz;
-        source = SOC_CPU_CLK_SRC_PLL_F240M;
-        source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
-        divider = CLK_LL_PLL_240M_FREQ_MHZ / freq_mhz;
-    } else if (freq_mhz == 160 || freq_mhz == 80) { // TODO: 80MHz can be get from PLL_F240M or PLL_F160M, which is better?
-        real_freq_mhz = freq_mhz;
-        source = SOC_CPU_CLK_SRC_PLL_F160M;
-        source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
-        divider = CLK_LL_PLL_160M_FREQ_MHZ / freq_mhz;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     } else if (freq_mhz == 80) {
         real_freq_mhz = freq_mhz;
         source = SOC_CPU_CLK_SRC_PLL;
@@ -309,7 +244,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
         source = SOC_CPU_CLK_SRC_PLL;
         source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
         divider = 3;
-#endif
     } else {
         // unsupported frequency
         return false;
@@ -330,31 +264,6 @@ __attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id)
 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
 {
     soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
-        /* Configure clk mspi fast to 80m*/
-        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
-        if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) {
-            // We don't turn off the bbpll if some consumers depend on bbpll
-            rtc_clk_bbpll_disable();
-        }
-    } else if ((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) {
-        if ((old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) && (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M)) {
-            // PLL_F160M and PLL_F240M both derived from S(BB)PLL (480MHz)
-            rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START);
-            rtc_clk_bbpll_enable();
-            rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ);
-        }
-        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
-        rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
-    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
-        rtc_clk_cpu_freq_to_8m();
-        if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) {
-            // We don't turn off the bbpll if some consumers depend on bbpll
-            rtc_clk_bbpll_disable();
-        }
-    }
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     if (config->source == SOC_CPU_CLK_SRC_XTAL) {
         rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
         if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
@@ -376,7 +285,6 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
             rtc_clk_bbpll_disable();
         }
     }
-#endif
 }
 
 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
@@ -384,36 +292,18 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
     uint32_t source_freq_mhz;
     uint32_t freq_mhz;
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    uint32_t div = clk_ll_cpu_get_divider();        // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     uint32_t div = clk_ll_cpu_get_ls_divider();     // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
     uint32_t hs_div = clk_ll_cpu_get_hs_divider();
-#else
-    uint32_t div = 0;
-#endif
     switch (source) {
     case SOC_CPU_CLK_SRC_XTAL: {
         source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
         freq_mhz = source_freq_mhz / div;
         break;
     }
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    case SOC_CPU_CLK_SRC_PLL_F160M: {
-        source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
-        freq_mhz = source_freq_mhz / div;
-        break;
-    }
-    case SOC_CPU_CLK_SRC_PLL_F240M: {
-        source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
-        freq_mhz = source_freq_mhz / div;
-        break;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     case SOC_CPU_CLK_SRC_PLL: {
         source_freq_mhz = clk_ll_bbpll_get_freq_mhz();
         freq_mhz = source_freq_mhz / hs_div;
         break;
-#endif
     }
     case SOC_CPU_CLK_SRC_RC_FAST:
         source_freq_mhz = 20;
@@ -436,11 +326,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
     if (config->source == SOC_CPU_CLK_SRC_XTAL) {
         rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
     } else if (
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-               ((config->source == SOC_CPU_CLK_SRC_PLL_F160M) || (config->source == SOC_CPU_CLK_SRC_PLL_F240M)) &&
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
                config->source == SOC_CPU_CLK_SRC_PLL &&
-#endif
                s_cur_pll_freq == config->source_freq_mhz
     ) {
         rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
@@ -476,51 +362,17 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 
 soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
-    if (xtal_freq_mhz == 0) {
-        ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 48MHz");
-        return SOC_XTAL_FREQ_48M;
-    }
-    return (soc_xtal_freq_t)xtal_freq_mhz;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     uint32_t xtal_freq_mhz = clk_ll_xtal_get_freq_mhz();
     assert(xtal_freq_mhz == SOC_XTAL_FREQ_48M || xtal_freq_mhz == SOC_XTAL_FREQ_40M);
     return (soc_xtal_freq_t)xtal_freq_mhz;
-#endif
 }
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
-{
-    clk_ll_xtal_store_freq_mhz(xtal_freq);
-}
-#endif
-
 static uint32_t rtc_clk_ahb_freq_get(void)
 {
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
     uint32_t soc_root_freq_mhz;
     uint32_t divider;
     switch (source) {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    case SOC_CPU_CLK_SRC_XTAL:
-        soc_root_freq_mhz = rtc_clk_xtal_freq_get();
-        divider = clk_ll_ahb_get_divider();
-        break;
-    case SOC_CPU_CLK_SRC_PLL_F160M:
-        soc_root_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
-        divider = clk_ll_ahb_get_divider();
-        break;
-    case SOC_CPU_CLK_SRC_PLL_F240M:
-        soc_root_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
-        divider = clk_ll_ahb_get_divider();
-        break;
-    case SOC_CPU_CLK_SRC_RC_FAST:
-        soc_root_freq_mhz = 20;
-        divider = clk_ll_ahb_get_divider();
-        break;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
     case SOC_CPU_CLK_SRC_XTAL:
         soc_root_freq_mhz = rtc_clk_xtal_freq_get();
         divider = clk_ll_ahb_get_ls_divider();
@@ -533,7 +385,6 @@ static uint32_t rtc_clk_ahb_freq_get(void)
         soc_root_freq_mhz = 20;
         divider = clk_ll_ahb_get_ls_divider();
         break;
-#endif
     default:
         // Unknown SOC_ROOT clock source
         soc_root_freq_mhz = 0;

components/esp_hw_support/port/esp32c5/rtc_clk_init.c

@@ -84,13 +84,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
     clk_ll_rc_fast_tick_conf(); // TODO: IDF-8642 Unnecessary or not?
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
-    esp_rom_output_tx_wait_idle(0);
-    rtc_clk_xtal_freq_update(xtal_freq);
-#else
     // XTAL freq determined by efuse, and can be directly informed from register field PCR_CLK_XTAL_FREQ
-#endif
 
     /* Set CPU frequency */
     rtc_clk_cpu_freq_get_config(&old_config);

components/esp_hw_support/port/esp32c5/rtc_time.c

@@ -246,12 +246,8 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
 
 uint64_t rtc_time_get(void)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    return lp_timer_hal_get_cycle_count();
-#else
     ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet");
     return 0;
-#endif
 }
 
 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more

components/esp_hw_support/port/esp32c5/systimer.c

@@ -8,37 +8,6 @@
 #include "esp_private/systimer.h"
 #include "hal/clk_tree_ll.h"
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-#if CONFIG_XTAL_FREQ_40
-/**
- * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
- *        So the resolution of the systimer is 40MHz/2.5 = 16MHz.
- */
-
-uint64_t systimer_ticks_to_us(uint64_t ticks)
-{
-    return ticks / 16;
-}
-
-uint64_t systimer_us_to_ticks(uint64_t us)
-{
-    return us * 16;
-}
-#elif CONFIG_XTAL_FREQ_48
-uint64_t systimer_ticks_to_us(uint64_t ticks)
-{
-    return ticks * 5 / 96;
-}
-
-uint64_t systimer_us_to_ticks(uint64_t us)
-{
-    return us * 96 / 5;
-}
-#else
-#error "Unsupported XTAL frequency by systimer"
-#endif // CONFIG_XTAL_FREQ_xx
-
-#else // !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
 /**
  * @brief systimer's clock source is fixed to XTAL, the fixed fractional divider is changed according to
  * EFUSE_XTAL_48M_SEL. No matter 48MHz or 40MHz XTAL, the resolution of the systimer is always 16MHz.
@@ -53,4 +22,3 @@ uint64_t systimer_us_to_ticks(uint64_t us)
 {
     return us * 16;
 }
-#endif

components/esp_hw_support/sleep_modes.c

@@ -737,11 +737,7 @@ static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
     if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp)
 #endif
     {
-#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
         s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
-#else
-        s_config.fast_clk_cal_period = 0x8000;
-#endif
     }
 #endif
 }
@@ -1665,11 +1661,7 @@ bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
 #if SOC_RTCIO_PIN_COUNT > 0
     return RTC_GPIO_IS_VALID_GPIO(gpio_num);
 #else
-#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION    // TODO: IDF-9673
     return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
-#else
-    return true;
-#endif
 #endif
 }
 

components/esp_hw_support/test_apps/esp_hw_support_unity_tests/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_lcd/test_apps/spi_lcd/README.md

@@ -1,4 +1,4 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
 
 This test app is used to test LCDs with SPI interface.

components/esp_rom/CMakeLists.txt

@@ -1,13 +1,6 @@
 idf_build_get_property(target IDF_TARGET)
 
-# TODO: IDF-9197
+set(target_folder "${target}")
-if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
-    set(target_folder "esp32c5/beta3/esp32c5")
-elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
-    set(target_folder "esp32c5/mp/esp32c5")
-else()
-    set(target_folder "${target}")
-endif()
 
 set(include_dirs "include"
                  "include/${target_folder}"

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -3,10 +3,94 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
-if IDF_TARGET_ESP32C5_BETA3_VERSION
+config ESP_ROM_HAS_CRC_LE
-    source "$IDF_PATH/components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in"
+    bool
-endif
+    default y
 
-if IDF_TARGET_ESP32C5_MP_VERSION
+config ESP_ROM_HAS_CRC_BE
-    source "$IDF_PATH/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in"
+    bool
-endif
+    default y
+
+config ESP_ROM_HAS_JPEG_DECODE
+    bool
+    default y
+
+config ESP_ROM_UART_CLK_IS_XTAL
+    bool
+    default y
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default 3
+
+config ESP_ROM_HAS_RETARGETABLE_LOCKING
+    bool
+    default y
+
+config ESP_ROM_GET_CLK_FREQ
+    bool
+    default y
+
+config ESP_ROM_HAS_RVFPLIB
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_WDT
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_SYSTIMER
+    bool
+    default y
+
+config ESP_ROM_HAS_HEAP_TLSF
+    bool
+    default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y
+
+config ESP_ROM_WITHOUT_REGI2C
+    bool
+    default y
+
+config ESP_ROM_HAS_NEWLIB
+    bool
+    default y
+
+config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
+    bool
+    default y
+
+config ESP_ROM_WDT_INIT_PATCH
+    bool
+    default y
+
+config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
+    bool
+    default y
+
+config ESP_ROM_HAS_VERSION
+    bool
+    default y
+
+config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
+    bool
+    default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1
+
+config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
+    bool
+    default y
+
+config ESP_ROM_CLIC_INT_THRESH_PATCH
+    bool
+    default y

components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in

@@ -1,100 +0,0 @@
-#####################################################
-# This file is auto-generated from SoC caps
-# using gen_soc_caps_kconfig.py, do not edit manually
-#####################################################
-
-config ESP_ROM_HAS_CRC_LE
-    bool
-    default y
-
-config ESP_ROM_HAS_CRC_BE
-    bool
-    default y
-
-config ESP_ROM_HAS_JPEG_DECODE
-    bool
-    default y
-
-config ESP_ROM_UART_CLK_IS_XTAL
-    bool
-    default y
-
-config ESP_ROM_USB_SERIAL_DEVICE_NUM
-    int
-    default 3
-
-config ESP_ROM_HAS_RETARGETABLE_LOCKING
-    bool
-    default y
-
-config ESP_ROM_GET_CLK_FREQ
-    bool
-    default y
-
-config ESP_ROM_HAS_RVFPLIB
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_WDT
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_SYSTIMER
-    bool
-    default y
-
-config ESP_ROM_HAS_HEAP_TLSF
-    bool
-    default y
-
-config ESP_ROM_TLSF_CHECK_PATCH
-    bool
-    default y
-
-config ESP_ROM_MULTI_HEAP_WALK_PATCH
-    bool
-    default y
-
-config ESP_ROM_HAS_LAYOUT_TABLE
-    bool
-    default y
-
-config ESP_ROM_HAS_SPI_FLASH
-    bool
-    default y
-
-config ESP_ROM_WITHOUT_REGI2C
-    bool
-    default y
-
-config ESP_ROM_HAS_NEWLIB
-    bool
-    default y
-
-config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
-    bool
-    default y
-
-config ESP_ROM_WDT_INIT_PATCH
-    bool
-    default y
-
-config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
-    bool
-    default y
-
-config ESP_ROM_USB_OTG_NUM
-    int
-    default -1
-
-config ESP_ROM_HAS_VERSION
-    bool
-    default y
-
-config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
-    bool
-    default y
-
-config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
-    bool
-    default y

components/esp_rom/esp32c5/beta3/esp32c5/esp_rom_caps.h

@@ -1,32 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
-#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
-#define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
-#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
-#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
-#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
-#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
-#define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
-#define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
-#define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
-#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
-#define ESP_ROM_TLSF_CHECK_PATCH            (1) // ROM does not contain the patch of tlsf_check_pool()
-#define ESP_ROM_MULTI_HEAP_WALK_PATCH       (1) // ROM does not contain the patch of multi_heap_walk()
-#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
-#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver
-#define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs
-#define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
-#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
-#define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
-#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
-#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
-#define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
-#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.
-#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.heap.ld

@@ -1,81 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.heap.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group heap
- ***************************************/
-
-/* Functions */
-tlsf_create = 0x400003f8;
-tlsf_create_with_pool = 0x400003fc;
-tlsf_get_pool = 0x40000400;
-tlsf_add_pool = 0x40000404;
-tlsf_remove_pool = 0x40000408;
-tlsf_malloc = 0x4000040c;
-tlsf_memalign = 0x40000410;
-tlsf_memalign_offs = 0x40000414;
-tlsf_realloc = 0x40000418;
-tlsf_free = 0x4000041c;
-tlsf_block_size = 0x40000420;
-tlsf_size = 0x40000424;
-tlsf_align_size = 0x40000428;
-tlsf_block_size_min = 0x4000042c;
-tlsf_block_size_max = 0x40000430;
-tlsf_pool_overhead = 0x40000434;
-tlsf_alloc_overhead = 0x40000438;
-tlsf_walk_pool = 0x4000043c;
-tlsf_check = 0x40000440;
-tlsf_check_pool = 0x40000444;
-tlsf_poison_fill_pfunc_set = 0x40000448;
-tlsf_poison_check_pfunc_set = 0x4000044c;
-multi_heap_get_block_address_impl = 0x40000450;
-multi_heap_get_allocated_size_impl = 0x40000454;
-multi_heap_register_impl = 0x40000458;
-multi_heap_set_lock = 0x4000045c;
-multi_heap_os_funcs_init = 0x40000460;
-multi_heap_internal_lock = 0x40000464;
-multi_heap_internal_unlock = 0x40000468;
-multi_heap_get_first_block = 0x4000046c;
-multi_heap_get_next_block = 0x40000470;
-multi_heap_is_free = 0x40000474;
-multi_heap_malloc_impl = 0x40000478;
-multi_heap_free_impl = 0x4000047c;
-multi_heap_realloc_impl = 0x40000480;
-multi_heap_aligned_alloc_impl_offs = 0x40000484;
-multi_heap_aligned_alloc_impl = 0x40000488;
-multi_heap_check = 0x4000048c;
-multi_heap_dump = 0x40000490;
-multi_heap_free_size_impl = 0x40000494;
-multi_heap_minimum_free_size_impl = 0x40000498;
-multi_heap_get_info_impl = 0x4000049c;
-/* Data (.data, .bss, .rodata) */
-heap_tlsf_table_ptr = 0x4087ffd8;
-
-PROVIDE (multi_heap_malloc = multi_heap_malloc_impl);
-PROVIDE (multi_heap_free = multi_heap_free_impl);
-PROVIDE (multi_heap_realloc = multi_heap_realloc_impl);
-PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl);
-PROVIDE (multi_heap_register = multi_heap_register_impl);
-PROVIDE (multi_heap_get_info = multi_heap_get_info_impl);
-PROVIDE (multi_heap_free_size = multi_heap_free_size_impl);
-PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl);
-PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl);
-PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
-PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
-PROVIDE (multi_heap_check = multi_heap_check);
-PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
-PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
-PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
-PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.ld

@@ -1,542 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group common
- ***************************************/
-
-/* Functions */
-rtc_get_reset_reason = 0x40000018;
-rtc_get_wakeup_cause = 0x4000001c;
-pmu_enable_unhold_pads = 0x40000020;
-ets_printf = 0x40000024;
-ets_install_putc1 = 0x40000028;
-ets_install_putc2 = 0x4000002c;
-ets_install_uart_printf = 0x40000030;
-ets_install_usb_printf = 0x40000034;
-ets_get_printf_channel = 0x40000038;
-ets_delay_us = 0x4000003c;
-ets_get_cpu_frequency = 0x40000040;
-ets_update_cpu_frequency = 0x40000044;
-ets_install_lock = 0x40000048;
-UartRxString = 0x4000004c;
-UartGetCmdLn = 0x40000050;
-uart_tx_one_char = 0x40000054;
-uart_tx_one_char2 = 0x40000058;
-uart_tx_one_char3 = 0x4000005c;
-uart_rx_one_char = 0x40000060;
-uart_rx_one_char_block = 0x40000064;
-uart_rx_intr_handler = 0x40000068;
-uart_rx_readbuff = 0x4000006c;
-uartAttach = 0x40000070;
-uart_tx_flush = 0x40000074;
-uart_tx_wait_idle = 0x40000078;
-uart_div_modify = 0x4000007c;
-ets_write_char_uart = 0x40000080;
-uart_tx_switch = 0x40000084;
-uart_buff_switch = 0x40000088;
-roundup2 = 0x4000008c;
-multofup = 0x40000090;
-software_reset = 0x40000094;
-software_reset_cpu = 0x40000098;
-ets_clk_assist_debug_clock_enable = 0x4000009c;
-clear_super_wdt_reset_flag = 0x400000a0;
-disable_default_watchdog = 0x400000a4;
-esp_rom_set_rtc_wake_addr = 0x400000a8;
-esp_rom_get_rtc_wake_addr = 0x400000ac;
-send_packet = 0x400000b0;
-recv_packet = 0x400000b4;
-GetUartDevice = 0x400000b8;
-UartDwnLdProc = 0x400000bc;
-GetSecurityInfoProc = 0x400000c0;
-Uart_Init = 0x400000c4;
-ets_set_user_start = 0x400000c8;
-/* Data (.data, .bss, .rodata) */
-ets_rom_layout_p = 0x4004fffc;
-ets_ops_table_ptr = 0x4087fff8;
-g_saved_pc = 0x4087fffc;
-
-
-/***************************************
- Group miniz
- ***************************************/
-
-/* Functions */
-mz_adler32 = 0x400000cc;
-mz_free = 0x400000d0;
-tdefl_compress = 0x400000d4;
-tdefl_compress_buffer = 0x400000d8;
-tdefl_compress_mem_to_heap = 0x400000dc;
-tdefl_compress_mem_to_mem = 0x400000e0;
-tdefl_compress_mem_to_output = 0x400000e4;
-tdefl_get_adler32 = 0x400000e8;
-tdefl_get_prev_return_status = 0x400000ec;
-tdefl_init = 0x400000f0;
-tdefl_write_image_to_png_file_in_memory = 0x400000f4;
-tdefl_write_image_to_png_file_in_memory_ex = 0x400000f8;
-tinfl_decompress = 0x400000fc;
-tinfl_decompress_mem_to_callback = 0x40000100;
-tinfl_decompress_mem_to_heap = 0x40000104;
-tinfl_decompress_mem_to_mem = 0x40000108;
-
-
-/***************************************
- Group spiflash_legacy
- ***************************************/
-
-/* Functions */
-esp_rom_spiflash_wait_idle = 0x4000010c;
-esp_rom_spiflash_write_encrypted = 0x40000110;
-esp_rom_spiflash_write_encrypted_dest = 0x40000114;
-esp_rom_spiflash_write_encrypted_enable = 0x40000118;
-esp_rom_spiflash_write_encrypted_disable = 0x4000011c;
-esp_rom_spiflash_erase_chip = 0x40000120;
-_esp_rom_spiflash_erase_sector = 0x40000124;
-_esp_rom_spiflash_erase_block = 0x40000128;
-_esp_rom_spiflash_write = 0x4000012c;
-_esp_rom_spiflash_read = 0x40000130;
-_esp_rom_spiflash_unlock = 0x40000134;
-_SPIEraseArea = 0x40000138;
-_SPI_write_enable = 0x4000013c;
-esp_rom_spiflash_erase_sector = 0x40000140;
-esp_rom_spiflash_erase_block = 0x40000144;
-esp_rom_spiflash_write = 0x40000148;
-esp_rom_spiflash_read = 0x4000014c;
-esp_rom_spiflash_unlock = 0x40000150;
-SPIEraseArea = 0x40000154;
-SPI_write_enable = 0x40000158;
-esp_rom_spiflash_config_param = 0x4000015c;
-esp_rom_spiflash_read_user_cmd = 0x40000160;
-esp_rom_spiflash_select_qio_pins = 0x40000164;
-esp_rom_spi_flash_auto_sus_res = 0x40000168;
-esp_rom_spi_flash_send_resume = 0x4000016c;
-esp_rom_spi_flash_update_id = 0x40000170;
-esp_rom_spiflash_config_clk = 0x40000174;
-esp_rom_spiflash_config_readmode = 0x40000178;
-esp_rom_spiflash_read_status = 0x4000017c;
-esp_rom_spiflash_read_statushigh = 0x40000180;
-esp_rom_spiflash_write_status = 0x40000184;
-esp_rom_spiflash_write_disable = 0x40000188;
-spi_cache_mode_switch = 0x4000018c;
-spi_common_set_dummy_output = 0x40000190;
-spi_common_set_flash_cs_timing = 0x40000194;
-esp_rom_spi_set_address_bit_len = 0x40000198;
-SPILock = 0x4000019c;
-SPIMasterReadModeCnfig = 0x400001a0;
-SPI_Common_Command = 0x400001a4;
-SPI_WakeUp = 0x400001a8;
-SPI_block_erase = 0x400001ac;
-SPI_chip_erase = 0x400001b0;
-SPI_init = 0x400001b4;
-SPI_page_program = 0x400001b8;
-SPI_read_data = 0x400001bc;
-SPI_sector_erase = 0x400001c0;
-SelectSpiFunction = 0x400001c4;
-SetSpiDrvs = 0x400001c8;
-Wait_SPI_Idle = 0x400001cc;
-spi_dummy_len_fix = 0x400001d0;
-Disable_QMode = 0x400001d4;
-Enable_QMode = 0x400001d8;
-spi_flash_attach = 0x400001dc;
-spi_flash_get_chip_size = 0x400001e0;
-spi_flash_guard_set = 0x400001e4;
-spi_flash_guard_get = 0x400001e8;
-spi_flash_read_encrypted = 0x400001ec;
-/* Data (.data, .bss, .rodata) */
-rom_spiflash_legacy_funcs = 0x4087fff0;
-rom_spiflash_legacy_data = 0x4087ffec;
-g_flash_guard_ops = 0x4087fff4;
-
-
-/***************************************
- Group cache
- ***************************************/
-
-/* Functions */
-Cache_Get_ICache_Line_Size = 0x40000624;
-Cache_Get_Mode = 0x40000628;
-Cache_Address_Through_Cache = 0x4000062c;
-ROM_Boot_Cache_Init = 0x40000630;
-MMU_Set_Page_Mode = 0x40000634;
-MMU_Get_Page_Mode = 0x40000638;
-Cache_Invalidate_ICache_Items = 0x4000063c;
-Cache_Op_Addr = 0x40000640;
-Cache_Invalidate_Addr = 0x40000644;
-Cache_Invalidate_ICache_All = 0x40000648;
-Cache_Mask_All = 0x4000064c;
-Cache_UnMask_Dram0 = 0x40000650;
-Cache_Suspend_ICache_Autoload = 0x40000654;
-Cache_Resume_ICache_Autoload = 0x40000658;
-Cache_Start_ICache_Preload = 0x4000065c;
-Cache_ICache_Preload_Done = 0x40000660;
-Cache_End_ICache_Preload = 0x40000664;
-Cache_Config_ICache_Autoload = 0x40000668;
-Cache_Enable_ICache_Autoload = 0x4000066c;
-Cache_Disable_ICache_Autoload = 0x40000670;
-Cache_Enable_ICache_PreLock = 0x40000674;
-Cache_Disable_ICache_PreLock = 0x40000678;
-Cache_Lock_ICache_Items = 0x4000067c;
-Cache_Unlock_ICache_Items = 0x40000680;
-Cache_Lock_Addr = 0x40000684;
-Cache_Unlock_Addr = 0x40000688;
-Cache_Disable_ICache = 0x4000068c;
-Cache_Enable_ICache = 0x40000690;
-Cache_Suspend_ICache = 0x40000694;
-Cache_Resume_ICache = 0x40000698;
-Cache_Freeze_ICache_Enable = 0x4000069c;
-Cache_Freeze_ICache_Disable = 0x400006a0;
-Cache_Set_IDROM_MMU_Size = 0x400006a4;
-Cache_Get_IROM_MMU_End = 0x400006a8;
-Cache_Get_DROM_MMU_End = 0x400006ac;
-Cache_MMU_Init = 0x400006b0;
-Cache_MSPI_MMU_Set = 0x400006b4;
-Cache_MSPI_MMU_Set_Secure = 0x400006b8;
-Cache_Travel_Tag_Memory = 0x400006bc;
-Cache_Get_Virtual_Addr = 0x400006c0;
-/* Data (.data, .bss, .rodata) */
-rom_cache_op_cb = 0x4087ffcc;
-rom_cache_internal_table_ptr = 0x4087ffc8;
-
-
-/***************************************
- Group clock
- ***************************************/
-
-/* Functions */
-ets_clk_get_xtal_freq = 0x400006c4;
-ets_clk_get_cpu_freq = 0x400006c8;
-
-
-/***************************************
- Group gpio
- ***************************************/
-
-/* Functions */
-gpio_set_output_level = 0x400006cc;
-gpio_get_input_level = 0x400006d0;
-gpio_matrix_in = 0x400006d4;
-gpio_matrix_out = 0x400006d8;
-gpio_bypass_matrix_in = 0x400006dc;
-gpio_output_disable = 0x400006e0;
-gpio_output_enable = 0x400006e4;
-gpio_pad_input_disable = 0x400006e8;
-gpio_pad_input_enable = 0x400006ec;
-gpio_pad_pulldown = 0x400006f0;
-gpio_pad_pullup = 0x400006f4;
-gpio_pad_select_gpio = 0x400006f8;
-gpio_pad_set_drv = 0x400006fc;
-gpio_pad_unhold = 0x40000700;
-gpio_pad_hold = 0x40000704;
-
-
-/***************************************
- Group interrupts
- ***************************************/
-
-/* Functions */
-esprv_intc_int_set_priority = 0x40000708;
-esprv_intc_int_set_threshold = 0x4000070c;
-esprv_intc_int_enable = 0x40000710;
-esprv_intc_int_disable = 0x40000714;
-esprv_intc_int_set_type = 0x40000718;
-PROVIDE( intr_handler_set = 0x4000071c );
-intr_matrix_set = 0x40000720;
-ets_intr_lock = 0x40000724;
-ets_intr_unlock = 0x40000728;
-ets_isr_attach = 0x4000072c;
-ets_isr_mask = 0x40000730;
-ets_isr_unmask = 0x40000734;
-
-
-/***************************************
- Group crypto
- ***************************************/
-
-/* Functions */
-md5_vector = 0x40000738;
-MD5Init = 0x4000073c;
-MD5Update = 0x40000740;
-MD5Final = 0x40000744;
-crc32_le = 0x40000748;
-crc16_le = 0x4000074c;
-crc8_le = 0x40000750;
-crc32_be = 0x40000754;
-crc16_be = 0x40000758;
-crc8_be = 0x4000075c;
-esp_crc8 = 0x40000760;
-ets_sha_enable = 0x40000764;
-ets_sha_disable = 0x40000768;
-ets_sha_get_state = 0x4000076c;
-ets_sha_init = 0x40000770;
-ets_sha_process = 0x40000774;
-ets_sha_starts = 0x40000778;
-ets_sha_update = 0x4000077c;
-ets_sha_finish = 0x40000780;
-ets_sha_clone = 0x40000784;
-ets_hmac_enable = 0x40000788;
-ets_hmac_disable = 0x4000078c;
-ets_hmac_calculate_message = 0x40000790;
-ets_hmac_calculate_downstream = 0x40000794;
-ets_hmac_invalidate_downstream = 0x40000798;
-ets_jtag_enable_temporarily = 0x4000079c;
-ets_aes_enable = 0x400007a0;
-ets_aes_disable = 0x400007a4;
-ets_aes_setkey = 0x400007a8;
-ets_aes_block = 0x400007ac;
-ets_aes_setkey_dec = 0x400007b0;
-ets_aes_setkey_enc = 0x400007b4;
-ets_bigint_enable = 0x400007b8;
-ets_bigint_disable = 0x400007bc;
-ets_bigint_multiply = 0x400007c0;
-ets_bigint_modmult = 0x400007c4;
-ets_bigint_modexp = 0x400007c8;
-ets_bigint_wait_finish = 0x400007cc;
-ets_bigint_getz = 0x400007d0;
-ets_ds_enable = 0x400007d4;
-ets_ds_disable = 0x400007d8;
-ets_ds_start_sign = 0x400007dc;
-ets_ds_is_busy = 0x400007e0;
-ets_ds_finish_sign = 0x400007e4;
-ets_ds_encrypt_params = 0x400007e8;
-ets_mgf1_sha256 = 0x400007ec;
-/* Data (.data, .bss, .rodata) */
-crc32_le_table_ptr = 0x4004fff8;
-crc16_le_table_ptr = 0x4004fff4;
-crc8_le_table_ptr = 0x4004fff0;
-crc32_be_table_ptr = 0x4004ffec;
-crc16_be_table_ptr = 0x4004ffe8;
-crc8_be_table_ptr = 0x4004ffe4;
-
-
-/***************************************
- Group efuse
- ***************************************/
-
-/* Functions */
-ets_efuse_read = 0x400007f0;
-ets_efuse_program = 0x400007f4;
-ets_efuse_clear_program_registers = 0x400007f8;
-ets_efuse_write_key = 0x400007fc;
-ets_efuse_get_read_register_address = 0x40000800;
-ets_efuse_get_key_purpose = 0x40000804;
-ets_efuse_key_block_unused = 0x40000808;
-ets_efuse_find_unused_key_block = 0x4000080c;
-ets_efuse_rs_calculate = 0x40000810;
-ets_efuse_count_unused_key_blocks = 0x40000814;
-ets_efuse_secure_boot_enabled = 0x40000818;
-ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000081c;
-ets_efuse_cache_encryption_enabled = 0x40000820;
-ets_efuse_download_modes_disabled = 0x40000824;
-ets_efuse_find_purpose = 0x40000828;
-ets_efuse_force_send_resume = 0x4000082c;
-ets_efuse_get_flash_delay_us = 0x40000830;
-ets_efuse_get_uart_print_control = 0x40000834;
-ets_efuse_direct_boot_mode_disabled = 0x40000838;
-ets_efuse_security_download_modes_enabled = 0x4000083c;
-ets_efuse_jtag_disabled = 0x40000840;
-ets_efuse_usb_print_is_disabled = 0x40000844;
-ets_efuse_usb_download_mode_disabled = 0x40000848;
-ets_efuse_usb_device_disabled = 0x4000084c;
-ets_efuse_secure_boot_fast_wake_enabled = 0x40000850;
-
-
-/***************************************
- Group secureboot
- ***************************************/
-
-/* Functions */
-ets_emsa_pss_verify = 0x40000854;
-ets_rsa_pss_verify = 0x40000858;
-ets_ecdsa_verify = 0x4000085c;
-ets_secure_boot_verify_bootloader_with_keys = 0x40000860;
-ets_secure_boot_verify_signature = 0x40000864;
-ets_secure_boot_read_key_digests = 0x40000868;
-ets_secure_boot_revoke_public_key_digest = 0x4000086c;
-
-
-/***************************************
- Group usb_device_uart
- ***************************************/
-
-/* Functions */
-usb_serial_device_rx_one_char = 0x40000a6c;
-usb_serial_device_rx_one_char_block = 0x40000a70;
-usb_serial_device_tx_flush = 0x40000a74;
-usb_serial_device_tx_one_char = 0x40000a78;
-
-
-/***************************************
- Group usb_dwcotg_uart
- ***************************************/
-
-/* Functions */
-Uart_Init_USB = 0x40000a7c;
-usb_serial_otg_rx_one_char = 0x40000a80;
-usb_serial_otg_rx_one_char_block = 0x40000a84;
-usb_serial_otg_tx_flush = 0x40000a88;
-usb_serial_otg_tx_one_char = 0x40000a8c;
-/* Data (.data, .bss, .rodata) */
-uart_acm_dev = 0x4087ffc4;
-
-
-/***************************************
- Group usb_dwcotg_module
- ***************************************/
-
-/* Functions */
-cdc_acm_class_handle_req = 0x40000a90;
-cdc_acm_init = 0x40000a94;
-cdc_acm_fifo_fill = 0x40000a98;
-cdc_acm_rx_fifo_cnt = 0x40000a9c;
-cdc_acm_fifo_read = 0x40000aa0;
-cdc_acm_irq_tx_enable = 0x40000aa4;
-cdc_acm_irq_tx_disable = 0x40000aa8;
-cdc_acm_irq_state_enable = 0x40000aac;
-cdc_acm_irq_state_disable = 0x40000ab0;
-cdc_acm_irq_tx_ready = 0x40000ab4;
-cdc_acm_irq_rx_enable = 0x40000ab8;
-cdc_acm_irq_rx_disable = 0x40000abc;
-cdc_acm_irq_rx_ready = 0x40000ac0;
-cdc_acm_irq_is_pending = 0x40000ac4;
-cdc_acm_irq_callback_set = 0x40000ac8;
-cdc_acm_line_ctrl_set = 0x40000acc;
-cdc_acm_line_ctrl_get = 0x40000ad0;
-cdc_acm_poll_out = 0x40000ad4;
-chip_usb_dw_did_persist = 0x40000ad8;
-chip_usb_dw_init = 0x40000adc;
-chip_usb_detach = 0x40000ae0;
-chip_usb_dw_prepare_persist = 0x40000ae4;
-chip_usb_get_persist_flags = 0x40000ae8;
-chip_usb_set_persist_flags = 0x40000aec;
-cpio_start = 0x40000af0;
-cpio_feed = 0x40000af4;
-cpio_done = 0x40000af8;
-cpio_destroy = 0x40000afc;
-dfu_flash_init = 0x40000b00;
-dfu_flash_erase = 0x40000b04;
-dfu_flash_program = 0x40000b08;
-dfu_flash_read = 0x40000b0c;
-dfu_flash_attach = 0x40000b10;
-dfu_cpio_callback = 0x40000b14;
-dfu_updater_get_err = 0x40000b18;
-dfu_updater_clear_err = 0x40000b1c;
-dfu_updater_enable = 0x40000b20;
-dfu_updater_begin = 0x40000b24;
-dfu_updater_feed = 0x40000b28;
-dfu_updater_end = 0x40000b2c;
-dfu_updater_set_raw_addr = 0x40000b30;
-dfu_updater_flash_read = 0x40000b34;
-usb_dc_prepare_persist = 0x40000b38;
-usb_dw_isr_handler = 0x40000b3c;
-usb_dc_attach = 0x40000b40;
-usb_dc_detach = 0x40000b44;
-usb_dc_reset = 0x40000b48;
-usb_dc_set_address = 0x40000b4c;
-usb_dc_ep_check_cap = 0x40000b50;
-usb_dc_ep_configure = 0x40000b54;
-usb_dc_ep_set_stall = 0x40000b58;
-usb_dc_ep_clear_stall = 0x40000b5c;
-usb_dc_ep_halt = 0x40000b60;
-usb_dc_ep_is_stalled = 0x40000b64;
-usb_dc_ep_enable = 0x40000b68;
-usb_dc_ep_disable = 0x40000b6c;
-usb_dc_ep_flush = 0x40000b70;
-usb_dc_ep_write_would_block = 0x40000b74;
-usb_dc_ep_write = 0x40000b78;
-usb_dc_ep_read_wait = 0x40000b7c;
-usb_dc_ep_read_continue = 0x40000b80;
-usb_dc_ep_read = 0x40000b84;
-usb_dc_ep_set_callback = 0x40000b88;
-usb_dc_set_status_callback = 0x40000b8c;
-usb_dc_ep_mps = 0x40000b90;
-usb_dc_check_poll_for_interrupts = 0x40000b94;
-mac_addr_to_serial_str_desc = 0x40000b98;
-usb_set_current_descriptor = 0x40000b9c;
-usb_get_descriptor = 0x40000ba0;
-usb_dev_resume = 0x40000ba4;
-usb_dev_get_configuration = 0x40000ba8;
-usb_set_config = 0x40000bac;
-usb_deconfig = 0x40000bb0;
-usb_enable = 0x40000bb4;
-usb_disable = 0x40000bb8;
-usb_write_would_block = 0x40000bbc;
-usb_write = 0x40000bc0;
-usb_read = 0x40000bc4;
-usb_ep_set_stall = 0x40000bc8;
-usb_ep_clear_stall = 0x40000bcc;
-usb_ep_read_wait = 0x40000bd0;
-usb_ep_read_continue = 0x40000bd4;
-usb_transfer_ep_callback = 0x40000bd8;
-usb_transfer = 0x40000bdc;
-usb_cancel_transfer = 0x40000be0;
-usb_transfer_sync = 0x40000be4;
-usb_dfu_set_detach_cb = 0x40000be8;
-dfu_class_handle_req = 0x40000bec;
-dfu_status_cb = 0x40000bf0;
-dfu_custom_handle_req = 0x40000bf4;
-usb_dfu_init = 0x40000bf8;
-usb_dfu_force_detach = 0x40000bfc;
-usb_dev_deinit = 0x40000c00;
-usb_dw_ctrl_deinit = 0x40000c04;
-/* Data (.data, .bss, .rodata) */
-s_usb_osglue = 0x4087ffb8;
-
-
-/***************************************
- Group lldesc
- ***************************************/
-
-/* Functions */
-lldesc_build_chain = 0x40000c08;
-
-
-/***************************************
- Group sip
- ***************************************/
-
-/* Functions */
-sip_after_tx_complete = 0x40000c0c;
-sip_alloc_to_host_evt = 0x40000c10;
-sip_download_begin = 0x40000c14;
-sip_get_ptr = 0x40000c18;
-sip_get_state = 0x40000c1c;
-sip_init_attach = 0x40000c20;
-sip_install_rx_ctrl_cb = 0x40000c24;
-sip_install_rx_data_cb = 0x40000c28;
-sip_is_active = 0x40000c2c;
-sip_post_init = 0x40000c30;
-sip_reclaim_from_host_cmd = 0x40000c34;
-sip_reclaim_tx_data_pkt = 0x40000c38;
-sip_send = 0x40000c3c;
-sip_to_host_chain_append = 0x40000c40;
-sip_to_host_evt_send_done = 0x40000c44;
-
-
-/***************************************
- Group slc
- ***************************************/
-
-/* Functions */
-slc_add_credits = 0x40000c48;
-slc_enable = 0x40000c4c;
-slc_from_host_chain_fetch = 0x40000c50;
-slc_from_host_chain_recycle = 0x40000c54;
-slc_has_pkt_to_host = 0x40000c58;
-slc_init_attach = 0x40000c5c;
-slc_init_credit = 0x40000c60;
-slc_reattach = 0x40000c64;
-slc_send_to_host_chain = 0x40000c68;
-slc_set_host_io_max_window = 0x40000c6c;
-slc_to_host_chain_recycle = 0x40000c70;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.libgcc.ld

@@ -1,119 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.libgcc.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group libgccsf
- ***************************************/
-
-/* Functions */
-__addsf3 = 0x40000870;
-__divsf3 = 0x40000874;
-__eqsf2 = 0x40000878;
-__fixsfsi = 0x4000087c;
-__floatsisf = 0x40000880;
-__floatunsisf = 0x40000884;
-__gesf2 = 0x40000888;
-__gtsf2 = 0x4000088c;
-__lesf2 = 0x40000890;
-__ltsf2 = 0x40000894;
-__mulsf3 = 0x40000898;
-__negsf2 = 0x4000089c;
-__nesf2 = 0x400008a0;
-__powisf2 = 0x400008a4;
-__subsf3 = 0x400008a8;
-__truncdfsf2 = 0x400008ac;
-__unordsf2 = 0x400008b0;
-
-
-/***************************************
- Group libgccdf
- ***************************************/
-
-/* Functions */
-__absvdi2 = 0x400008b4;
-__absvsi2 = 0x400008b8;
-__adddf3 = 0x400008bc;
-__addvdi3 = 0x400008c0;
-__addvsi3 = 0x400008c4;
-__ashldi3 = 0x400008c8;
-__ashrdi3 = 0x400008cc;
-__bswapdi2 = 0x400008d0;
-__bswapsi2 = 0x400008d4;
-__clear_cache = 0x400008d8;
-__clrsbdi2 = 0x400008dc;
-__clrsbsi2 = 0x400008e0;
-__clzdi2 = 0x400008e4;
-__clzsi2 = 0x400008e8;
-__cmpdi2 = 0x400008ec;
-__ctzdi2 = 0x400008f0;
-__ctzsi2 = 0x400008f4;
-__divdc3 = 0x400008f8;
-__divdf3 = 0x400008fc;
-__divdi3 = 0x40000900;
-__divsc3 = 0x40000904;
-__divsi3 = 0x40000908;
-__eqdf2 = 0x4000090c;
-__extendsfdf2 = 0x40000910;
-__ffsdi2 = 0x40000914;
-__ffssi2 = 0x40000918;
-__fixdfdi = 0x4000091c;
-__fixdfsi = 0x40000920;
-__fixsfdi = 0x40000924;
-__fixunsdfsi = 0x40000928;
-__fixunssfdi = 0x4000092c;
-__fixunssfsi = 0x40000930;
-__floatdidf = 0x40000934;
-__floatdisf = 0x40000938;
-__floatsidf = 0x4000093c;
-__floatundidf = 0x40000940;
-__floatundisf = 0x40000944;
-__floatunsidf = 0x40000948;
-__gcc_bcmp = 0x4000094c;
-__gedf2 = 0x40000950;
-__gtdf2 = 0x40000954;
-__ledf2 = 0x40000958;
-__lshrdi3 = 0x4000095c;
-__ltdf2 = 0x40000960;
-__moddi3 = 0x40000964;
-__modsi3 = 0x40000968;
-__muldc3 = 0x4000096c;
-__muldf3 = 0x40000970;
-__muldi3 = 0x40000974;
-__mulsc3 = 0x40000978;
-__mulsi3 = 0x4000097c;
-__mulvdi3 = 0x40000980;
-__mulvsi3 = 0x40000984;
-__nedf2 = 0x40000988;
-__negdf2 = 0x4000098c;
-__negdi2 = 0x40000990;
-__negvdi2 = 0x40000994;
-__negvsi2 = 0x40000998;
-__paritysi2 = 0x4000099c;
-__popcountdi2 = 0x400009a0;
-__popcountsi2 = 0x400009a4;
-__powidf2 = 0x400009a8;
-__subdf3 = 0x400009ac;
-__subvdi3 = 0x400009b0;
-__subvsi3 = 0x400009b4;
-__ucmpdi2 = 0x400009b8;
-__udivdi3 = 0x400009bc;
-__udivmoddi4 = 0x400009c0;
-__udivsi3 = 0x400009c4;
-__udiv_w_sdiv = 0x400009c8;
-__umoddi3 = 0x400009cc;
-__umodsi3 = 0x400009d0;
-__unorddf2 = 0x400009d4;
-__extenddftf2 = 0x400009d8;
-__trunctfdf2 = 0x400009dc;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib-normal.ld

@@ -1,41 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group newlib_normal_format
- ***************************************/
-
-/* Functions */
-__sprint_r = 0x400005d0;
-_fiprintf_r = 0x400005d4;
-_fprintf_r = 0x400005d8;
-_vfiprintf_r = 0x400005dc;
-_vfprintf_r = 0x400005e0;
-fiprintf = 0x400005e4;
-fprintf = 0x400005e8;
-printf = 0x400005ec;
-vfiprintf = 0x400005f0;
-vfprintf = 0x400005f4;
-asprintf = 0x400005f8;
-sprintf = 0x400005fc;
-snprintf = 0x40000600;
-siprintf = 0x40000604;
-sniprintf = 0x40000608;
-vprintf = 0x4000060c;
-viprintf = 0x40000610;
-vsnprintf = 0x40000614;
-vsniprintf = 0x40000618;
-sscanf = 0x4000061c;
-siscanf = 0x40000620;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib.ld

@@ -1,99 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.newlib.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group newlib
- ***************************************/
-
-/* Functions */
-esp_rom_newlib_init_common_mutexes = 0x400004a0;
-memset = 0x400004a4;
-memcpy = 0x400004a8;
-memmove = 0x400004ac;
-memcmp = 0x400004b0;
-strcpy = 0x400004b4;
-strncpy = 0x400004b8;
-strcmp = 0x400004bc;
-strncmp = 0x400004c0;
-strlen = 0x400004c4;
-strstr = 0x400004c8;
-bzero = 0x400004cc;
-_isatty_r = 0x400004d0;
-sbrk = 0x400004d4;
-isalnum = 0x400004d8;
-isalpha = 0x400004dc;
-isascii = 0x400004e0;
-isblank = 0x400004e4;
-iscntrl = 0x400004e8;
-isdigit = 0x400004ec;
-islower = 0x400004f0;
-isgraph = 0x400004f4;
-isprint = 0x400004f8;
-ispunct = 0x400004fc;
-isspace = 0x40000500;
-isupper = 0x40000504;
-toupper = 0x40000508;
-tolower = 0x4000050c;
-toascii = 0x40000510;
-memccpy = 0x40000514;
-memchr = 0x40000518;
-memrchr = 0x4000051c;
-strcasecmp = 0x40000520;
-strcasestr = 0x40000524;
-strcat = 0x40000528;
-strdup = 0x4000052c;
-strchr = 0x40000530;
-strcspn = 0x40000534;
-strcoll = 0x40000538;
-strlcat = 0x4000053c;
-strlcpy = 0x40000540;
-strlwr = 0x40000544;
-strncasecmp = 0x40000548;
-strncat = 0x4000054c;
-strndup = 0x40000550;
-strnlen = 0x40000554;
-strrchr = 0x40000558;
-strsep = 0x4000055c;
-strspn = 0x40000560;
-strtok_r = 0x40000564;
-strupr = 0x40000568;
-longjmp = 0x4000056c;
-setjmp = 0x40000570;
-abs = 0x40000574;
-div = 0x40000578;
-labs = 0x4000057c;
-ldiv = 0x40000580;
-qsort = 0x40000584;
-rand_r = 0x40000588;
-rand = 0x4000058c;
-srand = 0x40000590;
-utoa = 0x40000594;
-itoa = 0x40000598;
-atoi = 0x4000059c;
-atol = 0x400005a0;
-strtol = 0x400005a4;
-strtoul = 0x400005a8;
-fflush = 0x400005ac;
-_fflush_r = 0x400005b0;
-_fwalk = 0x400005b4;
-_fwalk_reent = 0x400005b8;
-__smakebuf_r = 0x400005bc;
-__swhatbuf_r = 0x400005c0;
-__swbuf_r = 0x400005c4;
-__swbuf = 0x400005c8;
-__swsetup_r = 0x400005cc;
-/* Data (.data, .bss, .rodata) */
-syscall_table_ptr = 0x4087ffd4;
-_global_impure_ptr = 0x4087ffd0;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.rvfp.ld

@@ -1,125 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.rvfp.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group rvfplibsf
- ***************************************/
-
-/* Functions */
-__addsf3 = 0x400009e0;
-__eqsf2 = 0x400009e4;
-__extendsfdf2 = 0x400009e8;
-__fixsfsi = 0x400009ec;
-__fixunssfsi = 0x400009f0;
-__floatdisf = 0x400009f4;
-__floatsisf = 0x400009f8;
-__floatundisf = 0x400009fc;
-__floatunsisf = 0x40000a00;
-__gesf2 = 0x40000a04;
-__gtsf2 = 0x40000a08;
-__lesf2 = 0x40000a0c;
-__ltsf2 = 0x40000a10;
-__mulsf3 = 0x40000a14;
-__nesf2 = 0x40000a18;
-__subsf3 = 0x40000a1c;
-__truncdfsf2 = 0x40000a20;
-
-
-/***************************************
- Group rvfplibdf
- ***************************************/
-
-/* Functions */
-__adddf3 = 0x40000a24;
-__eqdf2 = 0x40000a28;
-__fixdfdi = 0x40000a2c;
-__fixdfsi = 0x40000a30;
-__fixsfdi = 0x40000a34;
-__fixunsdfsi = 0x40000a38;
-__fixunssfdi = 0x40000a3c;
-__floatdidf = 0x40000a40;
-__floatsidf = 0x40000a44;
-__floatundidf = 0x40000a48;
-__floatunsidf = 0x40000a4c;
-__gedf2 = 0x40000a50;
-__gtdf2 = 0x40000a54;
-__ledf2 = 0x40000a58;
-__ltdf2 = 0x40000a5c;
-__muldf3 = 0x40000a60;
-__nedf2 = 0x40000a64;
-__subdf3 = 0x40000a68;
-
-/***************************************
- Group libgcc
-***************************************/
-
-/* Functions */
-__divsf3 = 0x40000874;
-__negsf2 = 0x4000089c;
-__powisf2 = 0x400008a4;
-__unordsf2 = 0x400008b0;
-__absvdi2 = 0x400008b4;
-__absvsi2 = 0x400008b8;
-__addvdi3 = 0x400008c0;
-__addvsi3 = 0x400008c4;
-__ashldi3 = 0x400008c8;
-__ashrdi3 = 0x400008cc;
-__bswapdi2 = 0x400008d0;
-__bswapsi2 = 0x400008d4;
-__clear_cache = 0x400008d8;
-__clrsbdi2 = 0x400008dc;
-__clrsbsi2 = 0x400008e0;
-__clzdi2 = 0x400008e4;
-__clzsi2 = 0x400008e8;
-__cmpdi2 = 0x400008ec;
-__ctzdi2 = 0x400008f0;
-__ctzsi2 = 0x400008f4;
-__divdc3 = 0x400008f8;
-__divdf3 = 0x400008fc;
-__divdi3 = 0x40000900;
-__divsc3 = 0x40000904;
-__divsi3 = 0x40000908;
-__ffsdi2 = 0x40000914;
-__ffssi2 = 0x40000918;
-__gcc_bcmp = 0x4000094c;
-__lshrdi3 = 0x4000095c;
-__moddi3 = 0x40000964;
-__modsi3 = 0x40000968;
-__muldc3 = 0x4000096c;
-__muldi3 = 0x40000974;
-__mulsc3 = 0x40000978;
-__mulsi3 = 0x4000097c;
-__mulvdi3 = 0x40000980;
-__mulvsi3 = 0x40000984;
-__negdf2 = 0x4000098c;
-__negdi2 = 0x40000990;
-__negvdi2 = 0x40000994;
-__negvsi2 = 0x40000998;
-__paritysi2 = 0x4000099c;
-__popcountdi2 = 0x400009a0;
-__popcountsi2 = 0x400009a4;
-__powidf2 = 0x400009a8;
-__subvdi3 = 0x400009b0;
-__subvsi3 = 0x400009b4;
-__ucmpdi2 = 0x400009b8;
-__udivdi3 = 0x400009bc;
-__udivmoddi4 = 0x400009c0;
-__udivsi3 = 0x400009c4;
-__udiv_w_sdiv = 0x400009c8;
-__umoddi3 = 0x400009cc;
-__umodsi3 = 0x400009d0;
-__unorddf2 = 0x400009d4;
-__extenddftf2 = 0x400009d8;
-__trunctfdf2 = 0x400009dc;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.spiflash.ld

@@ -1,165 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM function interface esp32c5.rom.spiflash.ld for esp32c5
- *
- *
- * Generated from ./target/esp32c5/interface-esp32c5.yml md5sum 2476337377df636dda217b0b3c1a63db
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
-/***************************************
- Group spi_flash_cache
- ***************************************/
-
-/* Functions */
-spi_flash_disable_cache = 0x400001f0;
-spi_flash_restore_cache = 0x400001f4;
-spi_flash_cache_enabled = 0x400001f8;
-spi_flash_enable_cache = 0x400001fc;
-esp_enable_cache_flash_wrap = 0x40000200;
-
-
-/***************************************
- Group spi_flash_mmap
- ***************************************/
-
-/* Functions */
-spi_flash_mmap_os_func_set = 0x40000204;
-spi_flash_mmap_page_num_init = 0x40000208;
-spi_flash_mmap = 0x4000020c;
-spi_flash_mmap_pages = 0x40000210;
-spi_flash_munmap = 0x40000214;
-spi_flash_mmap_dump = 0x40000218;
-spi_flash_check_and_flush_cache = 0x4000021c;
-spi_flash_mmap_get_free_pages = 0x40000220;
-spi_flash_cache2phys = 0x40000224;
-spi_flash_phys2cache = 0x40000228;
-
-
-/***************************************
- Group esp_flash
- ***************************************/
-
-/* Functions */
-esp_flash_chip_driver_initialized = 0x4000022c;
-esp_flash_read_id = 0x40000230;
-esp_flash_get_size = 0x40000234;
-esp_flash_erase_chip = 0x40000238;
-esp_flash_erase_region = 0x4000023c;
-esp_flash_get_chip_write_protect = 0x40000240;
-esp_flash_set_chip_write_protect = 0x40000244;
-esp_flash_get_protectable_regions = 0x40000248;
-esp_flash_get_protected_region = 0x4000024c;
-esp_flash_set_protected_region = 0x40000250;
-esp_flash_read = 0x40000254;
-esp_flash_write = 0x40000258;
-esp_flash_write_encrypted = 0x4000025c;
-esp_flash_read_encrypted = 0x40000260;
-esp_flash_get_io_mode = 0x40000264;
-esp_flash_set_io_mode = 0x40000268;
-spi_flash_boot_attach = 0x4000026c;
-esp_flash_read_chip_id = 0x40000270;
-detect_spi_flash_chip = 0x40000274;
-esp_flash_suspend_cmd_init = 0x40000278;
-/* Data (.data, .bss, .rodata) */
-esp_flash_default_chip = 0x4087ffe8;
-esp_flash_api_funcs = 0x4087ffe4;
-
-
-/***************************************
- Group spi_flash_chips
- ***************************************/
-
-/* Functions */
-spi_flash_chip_generic_probe = 0x4000027c;
-spi_flash_chip_generic_detect_size = 0x40000280;
-spi_flash_chip_generic_write = 0x40000284;
-spi_flash_chip_generic_write_encrypted = 0x40000288;
-spi_flash_chip_generic_set_write_protect = 0x4000028c;
-spi_flash_common_write_status_16b_wrsr = 0x40000290;
-spi_flash_chip_generic_reset = 0x40000294;
-spi_flash_chip_generic_erase_chip = 0x40000298;
-spi_flash_chip_generic_erase_sector = 0x4000029c;
-spi_flash_chip_generic_erase_block = 0x400002a0;
-spi_flash_chip_generic_page_program = 0x400002a4;
-spi_flash_chip_generic_get_write_protect = 0x400002a8;
-spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400002ac;
-spi_flash_chip_generic_read_reg = 0x400002b0;
-spi_flash_chip_generic_yield = 0x400002b4;
-spi_flash_generic_wait_host_idle = 0x400002b8;
-spi_flash_chip_generic_wait_idle = 0x400002bc;
-spi_flash_chip_generic_config_host_io_mode = 0x400002c0;
-spi_flash_chip_generic_read = 0x400002c4;
-spi_flash_common_read_status_8b_rdsr2 = 0x400002c8;
-spi_flash_chip_generic_get_io_mode = 0x400002cc;
-spi_flash_common_read_status_8b_rdsr = 0x400002d0;
-spi_flash_common_write_status_8b_wrsr = 0x400002d4;
-spi_flash_common_write_status_8b_wrsr2 = 0x400002d8;
-spi_flash_common_set_io_mode = 0x400002dc;
-spi_flash_chip_generic_set_io_mode = 0x400002e0;
-spi_flash_chip_generic_read_unique_id = 0x400002e4;
-spi_flash_chip_generic_get_caps = 0x400002e8;
-spi_flash_chip_generic_suspend_cmd_conf = 0x400002ec;
-spi_flash_chip_gd_get_io_mode = 0x400002f0;
-spi_flash_chip_gd_probe = 0x400002f4;
-spi_flash_chip_gd_set_io_mode = 0x400002f8;
-/* Data (.data, .bss, .rodata) */
-spi_flash_chip_generic_config_data = 0x4087ffe0;
-spi_flash_encryption = 0x4087ffdc;
-
-
-/***************************************
- Group memspi_host
- ***************************************/
-
-/* Functions */
-memspi_host_read_id_hs = 0x400002fc;
-memspi_host_read_status_hs = 0x40000300;
-memspi_host_flush_cache = 0x40000304;
-memspi_host_erase_chip = 0x40000308;
-memspi_host_erase_sector = 0x4000030c;
-memspi_host_erase_block = 0x40000310;
-memspi_host_program_page = 0x40000314;
-memspi_host_read = 0x40000318;
-memspi_host_set_write_protect = 0x4000031c;
-memspi_host_set_max_read_len = 0x40000320;
-memspi_host_read_data_slicer = 0x40000324;
-memspi_host_write_data_slicer = 0x40000328;
-
-
-/***************************************
- Group hal_spiflash
- ***************************************/
-
-/* Functions */
-spi_flash_hal_poll_cmd_done = 0x4000032c;
-spi_flash_hal_device_config = 0x40000330;
-spi_flash_hal_configure_host_io_mode = 0x40000334;
-spi_flash_hal_common_command = 0x40000338;
-spi_flash_hal_read = 0x4000033c;
-spi_flash_hal_erase_chip = 0x40000340;
-spi_flash_hal_erase_sector = 0x40000344;
-spi_flash_hal_erase_block = 0x40000348;
-spi_flash_hal_program_page = 0x4000034c;
-spi_flash_hal_set_write_protect = 0x40000350;
-spi_flash_hal_host_idle = 0x40000354;
-spi_flash_hal_check_status = 0x40000358;
-spi_flash_hal_setup_read_suspend = 0x4000035c;
-spi_flash_hal_setup_auto_suspend_mode = 0x40000360;
-spi_flash_hal_setup_auto_resume_mode = 0x40000364;
-spi_flash_hal_disable_auto_suspend_mode = 0x40000368;
-spi_flash_hal_disable_auto_resume_mode = 0x4000036c;
-spi_flash_hal_resume = 0x40000370;
-spi_flash_hal_suspend = 0x40000374;
-spi_flash_encryption_hal_enable = 0x40000378;
-spi_flash_encryption_hal_disable = 0x4000037c;
-spi_flash_encryption_hal_prepare = 0x40000380;
-spi_flash_encryption_hal_done = 0x40000384;
-spi_flash_encryption_hal_destroy = 0x40000388;
-spi_flash_encryption_hal_check = 0x4000038c;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.systimer.ld

@@ -1,27 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-/***************************************
- Group hal_systimer
- ***************************************/
-
-/* Functions */
-systimer_hal_init = 0x400003bc;
-systimer_hal_deinit = 0x400003c0;
-systimer_hal_set_tick_rate_ops = 0x400003c4;
-systimer_hal_get_counter_value = 0x400003c8;
-systimer_hal_get_time = 0x400003cc;
-systimer_hal_set_alarm_target = 0x400003d0;
-systimer_hal_set_alarm_period = 0x400003d4;
-systimer_hal_get_alarm_value = 0x400003d8;
-systimer_hal_enable_alarm_int = 0x400003dc;
-systimer_hal_on_apb_freq_update = 0x400003e0;
-systimer_hal_counter_value_advance = 0x400003e4;
-systimer_hal_enable_counter = 0x400003e8;
-systimer_hal_select_alarm_mode = 0x400003ec;
-systimer_hal_connect_alarm_counter = 0x400003f0;
-systimer_hal_counter_can_stall_by_cpu = 0x400003f4;

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.wdt.ld

@@ -1,22 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/***************************************
- Group hal_wdt
- ***************************************/
-
-/* Functions */
-wdt_hal_init = 0x40000390;
-wdt_hal_deinit = 0x40000394;
-wdt_hal_config_stage = 0x40000398;
-wdt_hal_write_protect_disable = 0x4000039c;
-wdt_hal_write_protect_enable = 0x400003a0;
-wdt_hal_enable = 0x400003a4;
-wdt_hal_disable = 0x400003a8;
-wdt_hal_handle_intr = 0x400003ac;
-wdt_hal_feed = 0x400003b0;
-wdt_hal_set_flashboot_en = 0x400003b4;
-wdt_hal_is_enabled = 0x400003b8;

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -6,12 +6,26 @@
 
 #pragma once
 
-#include "sdkconfig.h"
+#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
-
+#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
-// TODO: IDF-9197 This file is created to glob the version specific soc_caps correctly
+#define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
-
+#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
-#include "beta3/esp32c5/esp_rom_caps.h"   // recursive, condition: IDF_TARGET_ESP32C5_BETA3_VERSION
+#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
-#include "mp/esp32c5/esp_rom_caps.h"      // recursive, condition: IDF_TARGET_ESP32C5_MP_VERSION
+#define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
-#endif
+#define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
+#define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
+#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
+#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
+#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver
+#define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs       TODO: IDF-10110 need refactor
+#define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
+#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
+#define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
+#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
+#define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
+#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.
+#define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
+#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
+#define ESP_ROM_CLIC_INT_THRESH_PATCH       (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF

components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in

@@ -1,88 +0,0 @@
-#####################################################
-# This file is auto-generated from SoC caps
-# using gen_soc_caps_kconfig.py, do not edit manually
-#####################################################
-
-config ESP_ROM_HAS_CRC_LE
-    bool
-    default y
-
-config ESP_ROM_HAS_CRC_BE
-    bool
-    default y
-
-config ESP_ROM_HAS_JPEG_DECODE
-    bool
-    default y
-
-config ESP_ROM_UART_CLK_IS_XTAL
-    bool
-    default y
-
-config ESP_ROM_USB_SERIAL_DEVICE_NUM
-    int
-    default 3
-
-config ESP_ROM_HAS_RETARGETABLE_LOCKING
-    bool
-    default y
-
-config ESP_ROM_GET_CLK_FREQ
-    bool
-    default y
-
-config ESP_ROM_HAS_RVFPLIB
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_WDT
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_SYSTIMER
-    bool
-    default y
-
-config ESP_ROM_HAS_HEAP_TLSF
-    bool
-    default y
-
-config ESP_ROM_HAS_LAYOUT_TABLE
-    bool
-    default y
-
-config ESP_ROM_HAS_SPI_FLASH
-    bool
-    default y
-
-config ESP_ROM_WITHOUT_REGI2C
-    bool
-    default y
-
-config ESP_ROM_HAS_NEWLIB
-    bool
-    default y
-
-config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
-    bool
-    default y
-
-config ESP_ROM_WDT_INIT_PATCH
-    bool
-    default y
-
-config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
-    bool
-    default y
-
-config ESP_ROM_HAS_VERSION
-    bool
-    default y
-
-config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
-    bool
-    default y
-
-config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
-    bool
-    default y

components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h

@@ -1,29 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
-#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
-#define ESP_ROM_HAS_JPEG_DECODE             (1) // ROM has JPEG decode library
-#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
-#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
-#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
-#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
-#define ESP_ROM_HAS_RVFPLIB                 (1) // ROM has the rvfplib
-#define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
-#define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
-#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
-#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
-#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver
-#define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has no regi2c APIs       TODO: IDF-10110 need refactor
-#define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
-#define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
-#define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
-#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
-#define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
-#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.
-#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)

components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.api.ld

@@ -1,65 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/** ROM APIs
- */
-
-PROVIDE ( esp_rom_crc32_le = crc32_le );
-PROVIDE ( esp_rom_crc16_le = crc16_le );
-PROVIDE ( esp_rom_crc8_le  = crc8_le );
-PROVIDE ( esp_rom_crc32_be = crc32_be );
-PROVIDE ( esp_rom_crc16_be = crc16_be );
-PROVIDE ( esp_rom_crc8_be  = crc8_be );
-
-PROVIDE ( esp_rom_gpio_pad_select_gpio    = gpio_pad_select_gpio );
-PROVIDE ( esp_rom_gpio_pad_pullup_only    = gpio_pad_pullup );
-PROVIDE ( esp_rom_gpio_pad_set_drv        = gpio_pad_set_drv );
-PROVIDE ( esp_rom_gpio_pad_unhold         = gpio_pad_unhold );
-PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
-PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
-
-PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
-PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
-
-PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );
-PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char2 );
-PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
-PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
-PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
-PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
-PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
-
-PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
-PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
-PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
-PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
-PROVIDE ( esp_rom_output_rx_string      = UartRxString );
-PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
-PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
-
-PROVIDE ( esp_rom_md5_init   = MD5Init );
-PROVIDE ( esp_rom_md5_update = MD5Update );
-PROVIDE ( esp_rom_md5_final  = MD5Final );
-
-PROVIDE ( esp_rom_software_reset_system = software_reset );
-PROVIDE ( esp_rom_software_reset_cpu    = software_reset_cpu );
-
-PROVIDE ( esp_rom_printf   = ets_printf );
-PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
-PROVIDE ( esp_rom_delay_us = ets_delay_us );
-PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
-PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
-PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
-PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
-
-PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
-PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
-PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable );
-PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
-
-PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
-PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
-PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
-PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );

components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.version.ld

@@ -1,13 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/* ROM version variables for esp32c5
- *
- * These addresses should be compatible with any ROM version for this chip.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-_rom_chip_id = 0x40000010;
-_rom_eco_version = 0x40000014;

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/aes.h

@@ -1,46 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_AES_H_
-#define _ROM_AES_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define AES_BLOCK_SIZE 16
-
-enum AES_TYPE {
-    AES_ENC,
-    AES_DEC,
-};
-
-enum AES_BITS {
-    AES128,
-    AES192,
-    AES256
-};
-
-void ets_aes_enable(void);
-
-void ets_aes_disable(void);
-
-int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits);
-
-int ets_aes_setkey_enc(const void *key, enum AES_BITS bits);
-
-int ets_aes_setkey_dec(const void *key, enum AES_BITS bits);
-
-void ets_aes_block(const void *input, void *output);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_AES_H_ */

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/bigint.h

@@ -1,35 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_BIGINT_H_
-#define _ROM_BIGINT_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void ets_bigint_enable(void);
-
-void ets_bigint_disable(void);
-
-int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words);
-
-int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words);
-
-int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words);
-
-void ets_bigint_wait_finish(void);
-
-int ets_bigint_getz(uint32_t *z, uint32_t len_words);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_BIGINT_H_ */

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/cache.h

@@ -1,609 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "esp_bit_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup cache_apis, cache operation related apis
-  * @brief cache apis
-  */
-
-/** @addtogroup cache_apis
-  * @{
-  */
-#define MIN_ICACHE_SIZE                 16384
-#define MAX_ICACHE_SIZE                 16384
-#define MIN_ICACHE_WAYS                 8
-#define MAX_ICACHE_WAYS                 8
-#define MAX_CACHE_WAYS                  8
-#define MIN_CACHE_LINE_SIZE             32
-#define TAG_SIZE                        4
-#define MIN_ICACHE_BANK_NUM             1
-#define MAX_ICACHE_BANK_NUM             1
-#define CACHE_MEMORY_BANK_NUM           1
-#define CACHE_MEMORY_IBANK_SIZE         0x4000
-
-#define MAX_ITAG_BANK_ITEMS             (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
-#define MAX_ITAG_BLOCK_ITEMS            (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
-#define MAX_ITAG_BANK_SIZE              (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
-#define MAX_ITAG_BLOCK_SIZE             (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
-
-typedef enum {
-    CACHE_SIZE_HALF = 0,                /*!< 8KB for icache and dcache */
-    CACHE_SIZE_FULL = 1,                /*!< 16KB for icache and dcache */
-} cache_size_t;
-
-typedef enum {
-    CACHE_4WAYS_ASSOC = 0,              /*!< 4 way associated cache */
-    CACHE_8WAYS_ASSOC = 1,              /*!< 8 way associated cache */
-} cache_ways_t;
-
-typedef enum {
-    CACHE_LINE_SIZE_16B = 0,            /*!< 16 Byte cache line size */
-    CACHE_LINE_SIZE_32B = 1,            /*!< 32 Byte cache line size */
-    CACHE_LINE_SIZE_64B = 2,            /*!< 64 Byte cache line size */
-} cache_line_size_t;
-
-typedef enum {
-    CACHE_AUTOLOAD_POSITIVE = 0,        /*!< cache autoload step is positive */
-    CACHE_AUTOLOAD_NEGATIVE = 1,        /*!< cache autoload step is negative */
-} cache_autoload_order_t;
-
-#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
-
-typedef enum {
-    CACHE_AUTOLOAD_MISS_TRIGGER = 0,    /*!< autoload only triggered by cache miss */
-    CACHE_AUTOLOAD_HIT_TRIGGER  = 1,    /*!< autoload only triggered by cache hit */
-    CACHE_AUTOLOAD_BOTH_TRIGGER = 2,    /*!< autoload triggered both by cache miss and hit */
-} cache_autoload_trigger_t;
-
-typedef enum {
-    CACHE_FREEZE_ACK_BUSY = 0,          /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
-    CACHE_FREEZE_ACK_ERROR  = 1,        /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
-} cache_freeze_mode_t;
-
-typedef enum {
-    MMU_PAGE_MODE_64KB = 0,
-    MMU_PAGE_MODE_32KB = 1,
-    MMU_PAGE_MODE_16KB = 2,
-    MMU_PAGE_MODE_8KB = 3,
-    MMU_PAGE_MODE_INVALID,
-} mmu_page_mode_t;
-
-struct cache_mode {
-    uint32_t cache_size;                /*!< cache size in byte */
-    uint16_t cache_line_size;           /*!< cache line size in byte */
-    uint8_t cache_ways;                 /*!< cache ways, always 4 */
-    uint8_t ibus;                     /*!< the cache index, 0 for dcache, 1 for icache */
-};
-
-struct icache_tag_item {
-    uint32_t valid:1;                   /*!< the tag item is valid or not */
-    uint32_t lock:1;                    /*!< the cache line is locked or not */
-    uint32_t fifo_cnt:3;                /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
-    uint32_t tag:13;                    /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
-    uint32_t reserved:14;
-};
-
-struct autoload_config {
-    uint8_t order;                      /*!< autoload step is positive or negative */
-    uint8_t trigger;                    /*!< autoload trigger */
-    uint8_t ena0;                       /*!< autoload region0 enable */
-    uint8_t ena1;                       /*!< autoload region1 enable */
-    uint32_t addr0;                     /*!< autoload region0 start address */
-    uint32_t size0;                     /*!< autoload region0 size */
-    uint32_t addr1;                     /*!< autoload region1 start address */
-    uint32_t size1;                     /*!< autoload region1 size */
-};
-
-struct tag_group_info {
-    struct cache_mode mode;                         /*!< cache and cache mode */
-    uint32_t filter_addr;                           /*!< the address that used to generate the struct */
-    uint32_t vaddr_offset;                          /*!< virtual address offset of the cache ways */
-    uint32_t tag_addr[MAX_CACHE_WAYS];              /*!< tag memory address, only [0~mode.ways-1] is valid to use */
-    uint32_t cache_memory_offset[MAX_CACHE_WAYS];   /*!< cache memory address, only [0~mode.ways-1] is valid to use */
-};
-
-struct lock_config {
-    uint32_t addr;                                  /*!< manual lock address*/
-    uint16_t size;                                  /*!< manual lock size*/
-    uint16_t group;                                 /*!< manual lock group, 0 or 1*/
-};
-
-struct cache_internal_stub_table {
-    uint32_t (* icache_line_size)(void);
-    uint32_t (* icache_addr)(uint32_t addr);
-    uint32_t (* dcache_addr)(uint32_t addr);
-    void (* invalidate_icache_items)(uint32_t addr, uint32_t items);
-    void (* lock_icache_items)(uint32_t addr, uint32_t items);
-    void (* unlock_icache_items)(uint32_t addr, uint32_t items);
-    uint32_t (* suspend_icache_autoload)(void);
-    void (* resume_icache_autoload)(uint32_t autoload);
-    void (* freeze_icache_enable)(cache_freeze_mode_t mode);
-    void (* freeze_icache_disable)(void);
-    int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t));
-};
-
-/* Defined in the interface file, default value is rom_default_cache_internal_table */
-extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
-
-typedef void (* cache_op_start)(void);
-typedef void (* cache_op_end)(void);
-
-typedef struct {
-    cache_op_start start;
-    cache_op_end end;
-} cache_op_cb_t;
-
-/* Defined in the interface file, default value is NULL */
-extern const cache_op_cb_t* rom_cache_op_cb;
-
-#define ESP_ROM_ERR_INVALID_ARG         1
-#define MMU_SET_ADDR_ALIGNED_ERROR      2
-#define MMU_SET_PASE_SIZE_ERROR         3
-#define MMU_SET_VADDR_OUT_RANGE         4
-
-#define CACHE_OP_ICACHE_Y               1
-#define CACHE_OP_ICACHE_N               0
-
-/**
-  * @brief Initialise cache mmu, mark all entries as invalid.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void Cache_MMU_Init(void);
-
-/**
-  * @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus.
-  *
-  * @param None
-  *
-  * @return None
-  */
-void ROM_Boot_Cache_Init(void);
-
-/**
-  * @brief Set ICache mmu mapping.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t senitive : Config this page should apply flash encryption or not
-  *
-  * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
-  *                 esp32c5, external memory is always flash
-  *
-  * @param  uint32_t vaddr : virtual address in CPU address space.
-  *                              Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
-  *                              Should be aligned by psize.
-  *
-  * @param  uint32_t paddr : physical address in external memory.
-  *                              Should be aligned by psize.
-  *
-  * @param  uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
-  *
-  * @param  uint32_t num : pages to be set.
-  *
-  * @param  uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
-  *
-  * @return uint32_t: error status
-  *                   0 : mmu set success
-  *                   2 : vaddr or paddr is not aligned
-  *                   3 : psize error
-  *                   4 : vaddr is out of range
-  */
-int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,  uint32_t psize, uint32_t num, uint32_t fixed);
-
-/**
-  * @brief Set DCache mmu mapping.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
-  *                 esp32c5, external memory is always flash
-  *
-  * @param  uint32_t vaddr : virtual address in CPU address space.
-  *                              Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
-  *                              Should be aligned by psize.
-  *
-  * @param  uint32_t paddr : physical address in external memory.
-  *                              Should be aligned by psize.
-  *
-  * @param  uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
-  *
-  * @param  uint32_t num : pages to be set.
-
-  * @param  uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
-  *
-  * @return uint32_t: error status
-  *                   0 : mmu set success
-  *                   2 : vaddr or paddr is not aligned
-  *                   3 : psize error
-  *                   4 : vaddr is out of range
-  */
-int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
-
-
-/**
-  * @brief Get cache mode of ICache or DCache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
-  *
-  * return none
-  */
-void Cache_Get_Mode(struct cache_mode * mode);
-
-/**
-  * @brief Set cache page mode.
-  *
-  * @param mmu_page_mode_t
-  *
-  * @return None
-  */
-void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode);
-
-/**
-  * @brief Get cache page mode.
-  *
-  * @param None
-  *
-  * @return page mode
-  */
-mmu_page_mode_t MMU_Get_Page_Mode(void);
-
-/**
-  * @brief Invalidate the cache items for ICache.
-  *        Operation will be done CACHE_LINE_SIZE aligned.
-  *        If the region is not in ICache addr room, nothing will be done.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  uint32_t addr: start address to invalidate
-  *
-  * @param  uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
-  *
-  * @return None
-  */
-void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items);
-
-/**
-  * @brief Invalidate the Cache items in the region from ICache or DCache.
-  *        If the region is not in Cache addr room, nothing will be done.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  uint32_t addr : invalidated region start address.
-  *
-  * @param  uint32_t size : invalidated region size.
-  *
-  * @return 0 for success
-  *         1 for invalid argument
-  */
-int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
-
-/**
-  * @brief Invalidate all cache items in ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void Cache_Invalidate_ICache_All(void);
-
-/**
-  * @brief Mask all buses through ICache and DCache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void Cache_Mask_All(void);
-
-/**
-  * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  None
-  *
-  * @return uint32_t : 0 for ICache not auto preload before suspend.
-  */
-uint32_t Cache_Suspend_ICache_Autoload(void);
-
-/**
-  * @brief Resume ICache auto preload operation after some ICache operations.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t autoload : 0 for ICache not auto preload before suspend.
-  *
-  * @return None.
-  */
-void Cache_Resume_ICache_Autoload(uint32_t autoload);
-
-/**
-  * @brief Start an ICache manual preload, will suspend auto preload of ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t addr : start address of the preload region.
-  *
-  * @param uint32_t size : size of the preload region, should not exceed the size of ICache.
-  *
-  * @param uint32_t order : the preload order, 0 for positive, other for negative
-  *
-  * @return uint32_t : 0 for ICache not auto preload before manual preload.
-  */
-uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order);
-
-/**
-  * @brief Return if the ICache manual preload done.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  None
-  *
-  * @return uint32_t : 0 for ICache manual preload not done.
-  */
-uint32_t Cache_ICache_Preload_Done(void);
-
-/**
-  * @brief End the ICache manual preload to resume auto preload of ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
-  *
-  * @return None
-  */
-void Cache_End_ICache_Preload(uint32_t autoload);
-
-/**
-  * @brief Config autoload parameters of ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param struct autoload_config * config : autoload parameters.
-  *
-  * @return None
-  */
-void Cache_Config_ICache_Autoload(const struct autoload_config * config);
-
-/**
-  * @brief Enable auto preload for ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param None
-  *
-  * @return None
-  */
-void Cache_Enable_ICache_Autoload(void);
-
-/**
-  * @brief Disable auto preload for ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param None
-  *
-  * @return None
-  */
-void Cache_Disable_ICache_Autoload(void);
-
-/**
-  * @brief Config a group of prelock parameters of ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param struct lock_config * config : a group of lock parameters.
-  *
-  * @return None
-  */
-
-void Cache_Enable_ICache_PreLock(const struct lock_config *config);
-
-/**
-  * @brief Disable a group of prelock parameters for ICache.
-  *        However, the locked data will not be released.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint16_t group : 0 for group0, 1 for group1.
-  *
-  * @return None
-  */
-void Cache_Disable_ICache_PreLock(uint16_t group);
-
-/**
-  * @brief Lock the cache items for ICache.
-  *        Operation will be done CACHE_LINE_SIZE aligned.
-  *        If the region is not in ICache addr room, nothing will be done.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  uint32_t addr: start address to lock
-  *
-  * @param  uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
-  *
-  * @return None
-  */
-void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items);
-
-/**
-  * @brief Unlock the cache items for ICache.
-  *        Operation will be done CACHE_LINE_SIZE aligned.
-  *        If the region is not in ICache addr room, nothing will be done.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  uint32_t addr: start address to unlock
-  *
-  * @param  uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
-  *
-  * @return None
-  */
-void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items);
-
-/**
-  * @brief Lock the cache items in tag memory for ICache or DCache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t addr : start address of lock region.
-  *
-  * @param uint32_t size : size of lock region.
-  *
-  * @return 0 for success
-  *         1 for invalid argument
-  */
-int Cache_Lock_Addr(uint32_t addr, uint32_t size);
-
-/**
-  * @brief Unlock the cache items in tag memory for ICache or DCache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param uint32_t addr : start address of unlock region.
-  *
-  * @param uint32_t size : size of unlock region.
-  *
-  * @return 0 for success
-  *         1 for invalid argument
-  */
-int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
-
-/**
-  * @brief Disable ICache access for the cpu.
-  *        This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
-  *        Please do not call this function in your SDK application.
-  *
-  * @return uint32_t : auto preload enabled before
-  */
-uint32_t Cache_Disable_ICache(void);
-
-/**
-  * @brief Enable ICache access for the cpu.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  uint32_t autoload : ICache will preload then.
-  *
-  * @return None
-  */
-void Cache_Enable_ICache(uint32_t autoload);
-
-/**
-  * @brief Suspend ICache access for the cpu.
-  *        The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
-  *        Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  None
-  *
-  * @return uint32_t : auto preload enabled before
-  */
-uint32_t Cache_Suspend_ICache(void);
-
-/**
-  * @brief Resume ICache access for the cpu.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  uint32_t autoload : ICache will preload then.
-  *
-  * @return None
-  */
-void Cache_Resume_ICache(uint32_t autoload);
-
-/**
-  * @brief Get ICache cache line size
-  *
-  * @param  None
-  *
-  * @return uint32_t: 16, 32, 64 Byte
-  */
-uint32_t Cache_Get_ICache_Line_Size(void);
-
-/**
-  * @brief Enable freeze for ICache.
-  *        Any miss request will be rejected, including cpu miss and preload/autoload miss.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
-  *
-  * @return None
-  */
-void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
-
-/**
-  * @brief Disable freeze for ICache.
-  *        Please do not call this function in your SDK application.
-  *
-  * @return None
-  */
-void Cache_Freeze_ICache_Disable(void);
-
-/**
-  * @brief Travel tag memory to run a call back function.
-  *        ICache and DCache are suspend when doing this.
-  *        The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  struct cache_mode * mode : the cache to check and the cache mode.
-  *
-  * @param  uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
-  *                                0 for do not filter, all cache lines will be returned.
-  *
-  * @param  void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
-  *
-  * @return None
-  */
-void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
-
-/**
-  * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
-  *
-  * @param  uint32_t tag : the tag part fo a tag item, 12-14 bits.
-  *
-  * @param  uint32_t addr_offset : the virtual address offset of the cache ways.
-  *
-  * @return uint32_t : the virtual address.
-  */
-uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
-
-/**
-  * @}
-  */
-
-/**
-  * @brief Get the cache MMU IROM end address.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  void
-  *
-  * @return uint32_t : the word value of the address.
-  */
-uint32_t Cache_Get_IROM_MMU_End(void);
-
-/**
-  * @brief Get the cache MMU DROM end address.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  void
-  *
-  * @return uint32_t : the word value of the address.
-  */
-uint32_t Cache_Get_DROM_MMU_End(void);
-
-/**
- * @brief Configure cache MMU page size according to instruction and rodata size
- *
- * @param irom_size The instruction cache MMU page size
- * @param drom_size The rodata data cache MMU page size
- */
-void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
-
-#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
-    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
-
-#ifdef __cplusplus
-}
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/crc.h

@@ -1,119 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ROM_CRC_H
-#define ROM_CRC_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup crc_apis, uart configuration and communication related apis
-  * @brief crc apis
-  */
-
-/** @addtogroup crc_apis
-  * @{
-  */
-
-
-/* Standard CRC8/16/32 algorithms. */
-// CRC-8        x8+x2+x1+1              0x07
-// CRC16-CCITT  x16+x12+x5+1   1021   ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
-// CRC32:
-//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
-//If your buf is not continuous, you can use the first result to be the second parameter.
-
-/**
-  * @brief Crc32 value that is in little endian.
-  *
-  * @param  uint32_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief Crc32 value that is in big endian.
-  *
-  * @param  uint32_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief Crc16 value that is in little endian.
-  *
-  * @param  uint16_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief Crc16 value that is in big endian.
-  *
-  * @param  uint16_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief Crc8 value that is in little endian.
-  *
-  * @param  uint8_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief Crc8 value that is in big endian.
-  *
-  * @param  uint32_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/digital_signature.h

@@ -1,142 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define ETS_DS_MAX_BITS 3072
-
-#define ETS_DS_IV_LEN 16
-
-/* Length of parameter 'C' stored in flash (not including IV)
-
-   Comprises encrypted Y, M, rinv, md (32), mprime (4), length (4), padding (8)
-
-   Note that if ETS_DS_MAX_BITS<4096, 'C' needs to be split up when writing to hardware
-*/
-#define ETS_DS_C_LEN ((ETS_DS_MAX_BITS * 3 / 8) + 32 + 8 + 8)
-
-/* Encrypted ETS data. Recommended to store in flash in this format.
- */
-typedef struct {
-    /* RSA LENGTH register parameters
-     * (number of words in RSA key & operands, minus one).
-     *
-     *
-     * This value must match the length field encrypted and stored in 'c',
-     * or invalid results will be returned. (The DS peripheral will
-     * always use the value in 'c', not this value, so an attacker can't
-     * alter the DS peripheral results this way, it will just truncate or
-     * extend the message and the resulting signature in software.)
-     */
-    unsigned rsa_length;
-
-    /* IV value used to encrypt 'c' */
-    uint8_t iv[ETS_DS_IV_LEN];
-
-    /* Encrypted Digital Signature parameters. Result of AES-CBC encryption
-       of plaintext values. Includes an encrypted message digest.
-    */
-    uint8_t c[ETS_DS_C_LEN];
-} ets_ds_data_t;
-
-typedef enum {
-    ETS_DS_OK,
-    ETS_DS_INVALID_PARAM,   /* Supplied parameters are invalid */
-    ETS_DS_INVALID_KEY,     /* HMAC peripheral failed to supply key */
-    ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */
-    ETS_DS_INVALID_DIGEST,  /* 'c' decrypted with invalid digest */
-} ets_ds_result_t;
-
-void ets_ds_enable(void);
-
-void ets_ds_disable(void);
-
-
-/*
- * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral
- *
- * - @param message Pointer to message (or padded digest) containing the message to sign. Should be
- *   (data->rsa_length + 1)*4 bytes long.  @param data Pointer to DS data. Can be a pointer to data
- *   in flash.
- *
- * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling
- * this function, and is responsible for calling ets_ds_finish_sign() and then
- * ets_hmac_invalidate_downstream() afterwards.
- *
- * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid,
- * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly.
- */
-ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data);
-
-
-/*
- * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign()
- *
- * A result of false indicates that a call to ets_ds_finish_sign() will not block.
- *
- * Only valid if ets_ds_enable() has been called.
- */
-bool ets_ds_is_busy(void);
-
-
-/* @brief Finish signing a message using the Digital Signature peripheral
- *
- * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until
- * peripheral is no longer busy.
- *
- * - @param signature Pointer to buffer to contain the signature. Should be
- *   (data->rsa_length + 1)*4 bytes long.
- * - @param data Should match the 'data' parameter passed to ets_ds_start_sign()
- *
- * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid,
- * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the
- * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a
- * digest is produced anyhow.)
- */
-ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data);
-
-
-/* Plaintext parameters used by Digital Signature.
-
-   Not used for signing with DS peripheral, but can be encrypted
-   in-device by calling ets_ds_encrypt_params()
-*/
-typedef struct {
-    uint32_t Y[ETS_DS_MAX_BITS / 32];
-    uint32_t M[ETS_DS_MAX_BITS / 32];
-    uint32_t Rb[ETS_DS_MAX_BITS / 32];
-    uint32_t M_prime;
-    uint32_t length;
-} ets_ds_p_data_t;
-
-typedef enum {
-    ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */
-    ETS_DS_KEY_AES,  /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */
-} ets_ds_key_t;
-
-/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral
- *
- * @param data Output buffer to store encrypted data, suitable for later use generating signatures.
- * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time.
- * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored.
- * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased.
- * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral)
- *
- * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters.
- */
-ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type);
-
-
-#ifdef __cplusplus
-}
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/ecdsa.h

@@ -1,26 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
-
-typedef enum {
-    ECDSA_CURVE_P192 = 1,
-    ECDSA_CURVE_P256 = 2
-} ECDSA_CURVE;
-
-int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest);
-
-#ifdef __cplusplus
-}
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/efuse.h

@@ -1,283 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_EFUSE_H_
-#define _ROM_EFUSE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stddef.h>
-#include <stdbool.h>
-
-/** \defgroup efuse_APIs efuse APIs
-  * @brief     ESP32 efuse read/write APIs
-  * @attention
-  *
-  */
-
-/** @addtogroup efuse_APIs
-  * @{
-  */
-
-typedef enum {
-    ETS_EFUSE_KEY_PURPOSE_USER = 0,
-    ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
-    ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
-    ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
-    ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
-    ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
-    ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
-    ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
-    ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
-    ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
-    ETS_EFUSE_KEY_PURPOSE_MAX,
-} ets_efuse_purpose_t;
-
-typedef enum {
-    ETS_EFUSE_BLOCK0 = 0,
-    ETS_EFUSE_MAC_SPI_SYS_0 = 1,
-    ETS_EFUSE_BLOCK_SYS_DATA = 2,
-    ETS_EFUSE_BLOCK_USR_DATA = 3,
-    ETS_EFUSE_BLOCK_KEY0 = 4,
-    ETS_EFUSE_BLOCK_KEY1 = 5,
-    ETS_EFUSE_BLOCK_KEY2 = 6,
-    ETS_EFUSE_BLOCK_KEY3 = 7,
-    ETS_EFUSE_BLOCK_KEY4 = 8,
-    ETS_EFUSE_BLOCK_KEY5 = 9,
-    ETS_EFUSE_BLOCK_KEY6 = 10,
-    ETS_EFUSE_BLOCK_MAX,
-} ets_efuse_block_t;
-
-/**
-  * @brief  Efuse read operation: copies data from physical efuses to efuse read registers.
-  *
-  * @param  null
-  *
-  * @return : 0 if success, others if apb clock is not accepted
-  */
-int ets_efuse_read(void);
-
-/**
-  * @brief  Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
-  *
-  * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
-  *
-  * @return : 0 if success, others if apb clock is not accepted
-  */
-int ets_efuse_program(ets_efuse_block_t block);
-
-/**
- * @brief Set all Efuse program registers to zero.
- *
- * Call this before writing new data to the program registers.
- */
-void ets_efuse_clear_program_registers(void);
-
-/**
- * @brief Program a block of key data to an efuse block
- *
- * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
- * @param purpose Purpose to set for this key. Purpose must be already unset.
- * @param data Pointer to data to write.
- * @param data_len Length of data to write.
- *
- * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
- */
-int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
-
-
-/* @brief Return the address of a particular efuse block's first read register
- *
- * @param block Index of efuse block to look up
- *
- * @return 0 if block is invalid, otherwise a numeric read register address
- * of the first word in the block.
- */
-uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
-
-/**
- * @brief Return the current purpose set for an efuse key block
- *
- * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
- */
-ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
-
-/**
- * @brief Find a key block with the particular purpose set
- *
- * @param purpose Purpose to search for.
- * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
- * @return true if found, false if not found. If false, value at key_block pointer is unchanged.
- */
-bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
-
-/**
- * Return true if the key block is unused, false otherwise.
- *
- * An unused key block is all zero content, not read or write protected,
- * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
- *
- * @param key_block key block to check.
- *
- * @return true if key block is unused, false if key block or used
- * or the specified block index is not a key block.
- */
-bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
-
-
-/**
- * @brief Search for an unused key block and return the first one found.
- *
- * See @ref ets_efuse_key_block_unused for a description of an unused key block.
- *
- * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
- */
-ets_efuse_block_t ets_efuse_find_unused_key_block(void);
-
-/**
- * @brief Return the number of unused efuse key blocks (0-6)
- */
-unsigned ets_efuse_count_unused_key_blocks(void);
-
-/**
- * @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
- *
- * @param data Pointer to data buffer (length 32 bytes)
- * @param rs_values Pointer to write encoded data to (length 12 bytes)
- */
-void ets_efuse_rs_calculate(const void *data, void *rs_values);
-
-/**
-  * @brief  Read if download mode disabled from Efuse
-  *
-  * @return
-  * - true for efuse disable download mode.
-  * - false for efuse doesn't disable download mode.
-  */
-bool ets_efuse_download_modes_disabled(void);
-
-/**
-  * @brief  Read if uart print control value from Efuse
-  *
-  * @return
-  * - 0 for uart force print.
-  * - 1 for uart print when GPIO8 is low when digital reset.
-  *   2 for uart print when GPIO8 is high when digital reset.
-  *   3 for uart force slient
-  */
-uint32_t ets_efuse_get_uart_print_control(void);
-
-/**
-  * @brief  Read if usb download mode disabled from Efuse
-  *
-  * (Also returns true if security download mode is enabled, as this mode
-  * disables USB download.)
-  *
-  * @return
-  * - true for efuse disable usb download mode.
-  * - false for efuse doesn't disable usb download mode.
-  */
-bool ets_efuse_usb_download_mode_disabled(void);
-
-/**
-  * @brief  Read if security download modes enabled from Efuse
-  *
-  * @return
-  * - true for efuse enable security download mode.
-  * - false for efuse doesn't enable security download mode.
-  */
-bool ets_efuse_security_download_modes_enabled(void);
-
-/**
- * @brief Return true if secure boot is enabled in EFuse
- */
-bool ets_efuse_secure_boot_enabled(void);
-
-/**
- * @brief Return true if secure boot aggressive revoke is enabled in EFuse
- */
-bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
-
-/**
- * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse
- */
-bool ets_efuse_cache_encryption_enabled(void);
-
-/**
- * @brief Return true if EFuse indicates to send a flash resume command.
- */
-bool ets_efuse_force_send_resume(void);
-
-/**
-  * @brief  return the time in us ROM boot need wait flash to power on from Efuse
-  *
-  * @return
-  * - uint32_t the time in us.
-  */
-uint32_t ets_efuse_get_flash_delay_us(void);
-
-#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
-#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
-
-#define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
-#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
-#define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
-
-#define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
-#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
-#define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
-
-#define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
-#define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
-#define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
-
-#define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
-#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
-#define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
-
-
-#define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
-#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
-#define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
-
-/**
- * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
- * the JTAG_CTRL registers.
- *
- * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
- *
- * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
- *
- * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
- * @param key_block Index of a key block containing the source for this key.
- *
- * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
- */
-int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
-
-/**
-  * @brief  A crc8 algorithm used for MAC addresses in efuse
-  *
-  * @param  unsigned char const *p : Pointer to original data.
-  *
-  * @param  unsigned int len : Data length in byte.
-  *
-  * @return unsigned char: Crc value.
-  */
-unsigned char esp_crc8(unsigned char const *p, unsigned int len);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_EFUSE_H_ */

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/ets_sys.h

@@ -1,432 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_ETS_SYS_H_
-#define _ROM_ETS_SYS_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup ets_sys_apis, ets system related apis
-  * @brief ets system apis
-  */
-
-/** @addtogroup ets_sys_apis
-  * @{
-  */
-
-/************************************************************************
-  *                                NOTE
-  *   Many functions in this header files can't be run in FreeRTOS.
-  *   Please see the comment of the Functions.
-  *   There are also some functions that doesn't work on FreeRTOS
-  *   without listed in the header, such as:
-  *   xtos functions start with "_xtos_" in ld file.
-  *
-  ***********************************************************************
-  */
-
-/** \defgroup ets_apis, Espressif Task Scheduler related apis
-  * @brief ets apis
-  */
-
-/** @addtogroup ets_apis
-  * @{
-  */
-
-typedef enum {
-    ETS_OK     = 0, /**< return successful in ets*/
-    ETS_FAILED = 1, /**< return failed in ets*/
-    ETS_PENDING = 2,
-    ETS_BUSY = 3,
-    ETS_CANCEL = 4,
-} ETS_STATUS;
-
-typedef ETS_STATUS ets_status_t;
-
-typedef uint32_t ETSSignal;
-typedef uint32_t ETSParam;
-
-typedef struct ETSEventTag ETSEvent;    /**< Event transmit/receive in ets*/
-
-struct ETSEventTag {
-    ETSSignal sig;  /**< Event signal, in same task, different Event with different signal*/
-    ETSParam  par;  /**< Event parameter, sometimes without usage, then will be set as 0*/
-};
-
-typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processer*/
-typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
-
-
-
-
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_boot_apis, Boot routing related apis
-  * @brief ets boot apis
-  */
-
-/** @addtogroup ets_apis
-  * @{
-  */
-
-extern const char *const exc_cause_table[40];   ///**< excption cause that defined by the core.*/
-
-/**
-  * @brief  Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
-  *         When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
-  *
-  * @param  uint32_t start : the PRO Entry code address value in uint32_t
-  *
-  * @return None
-  */
-void ets_set_user_start(uint32_t start);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_printf_apis, ets_printf related apis used in ets
-  * @brief ets printf apis
-  */
-
-/** @addtogroup ets_printf_apis
-  * @{
-  */
-
-/**
-  * @brief  Printf the strings to uart or other devices, similar with printf, simple than printf.
-  *         Can not print float point data format, or longlong data format.
-  *         So we maybe only use this in ROM.
-  *
-  * @param  const char *fmt : See printf.
-  *
-  * @param  ... : See printf.
-  *
-  * @return int : the length printed to the output device.
-  */
-int ets_printf(const char *fmt, ...);
-
-/**
-  * @brief Get the uart channel of ets_printf(uart_tx_one_char).
-  *
-  * @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
-  */
-uint8_t ets_get_printf_channel(void);
-
-/**
-  * @brief  Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
-  *         Can not print float point data format, or longlong data format
-  *
-  * @param  char c : char to output.
-  *
-  * @return None
-  */
-void ets_write_char_uart(char c);
-
-/**
-  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
-  *         To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
-  *
-  * @param  void (*)(char) p: Output function to install.
-  *
-  * @return None
-  */
-void ets_install_putc1(void (*p)(char c));
-
-/**
-  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
-  *         To install putc2, which is defaulted installed as NULL.
-  *
-  * @param  void (*)(char) p: Output function to install.
-  *
-  * @return None
-  */
-void ets_install_putc2(void (*p)(char c));
-
-/**
-  * @brief  Install putc1 as ets_write_char_uart.
-  *         In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_install_uart_printf(void);
-
-#define ETS_PRINTF(...) ets_printf(...)
-
-#define ETS_ASSERT(v) do { \
-    if (!(v)) {             \
-        ets_printf("%s %u \n", __FILE__, __LINE__); \
-        while (1) {};   \
-    }                   \
-} while (0);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_timer_apis, ets_timer related apis used in ets
-  * @brief ets timer apis
-  */
-
-/** @addtogroup ets_timer_apis
-  * @{
-  */
-typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
-
-typedef struct _ETSTIMER_ {
-    struct _ETSTIMER_    *timer_next;   /**< timer linker*/
-    uint32_t              timer_expire; /**< abstruct time when timer expire*/
-    uint32_t              timer_period; /**< timer period, 0 means timer is not periodic repeated*/
-    ETSTimerFunc         *timer_func;   /**< timer handler*/
-    void                 *timer_arg;    /**< timer handler argument*/
-} ETSTimer;
-
-/**
-  * @brief  Init ets timer, this timer range is 640 us to 429496 ms
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_timer_init(void);
-
-/**
-  * @brief  In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_timer_deinit(void);
-
-/**
-  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @param  uint32_t tmout : Timer value in ms, range is 1 to 429496.
-  *
-  * @param  bool repeat : Timer is periodic repeated.
-  *
-  * @return None
-  */
-void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
-
-/**
-  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @param  uint32_t tmout : Timer value in us, range is 1 to 429496729.
-  *
-  * @param  bool repeat : Timer is periodic repeated.
-  *
-  * @return None
-  */
-void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
-
-/**
-  * @brief  Disarm an ets timer.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @return None
-  */
-void ets_timer_disarm(ETSTimer *timer);
-
-/**
-  * @brief  Set timer callback and argument.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @param  ETSTimerFunc *pfunction : Timer callback.
-  *
-  * @param  void *parg : Timer callback argument.
-  *
-  * @return None
-  */
-void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
-
-/**
-  * @brief  Unset timer callback and argument to NULL.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @return None
-  */
-void ets_timer_done(ETSTimer *ptimer);
-
-/**
-  * @brief  CPU do while loop for some time.
-  *         In FreeRTOS task, please call FreeRTOS apis.
-  *
-  * @param  uint32_t us : Delay time in us.
-  *
-  * @return None
-  */
-void ets_delay_us(uint32_t us);
-
-/**
-  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
-  *         Call this function when CPU frequency is changed.
-  *
-  * @param  uint32_t ticks_per_us : CPU ticks per us.
-  *
-  * @return None
-  */
-void ets_update_cpu_frequency(uint32_t ticks_per_us);
-
-
-
-/**
-  * @brief  Get the real CPU ticks per us to the ets.
-  *         This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
-  *
-  * @param  None
-  *
-  * @return uint32_t : CPU ticks per us record in ets.
-  */
-uint32_t ets_get_cpu_frequency(void);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_intr_apis, ets interrupt configure related apis
-  * @brief ets intr apis
-  */
-
-/** @addtogroup ets_intr_apis
-  * @{
-  */
-
-typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
-
-/**
-  * @brief  Attach a interrupt handler to a CPU interrupt number.
-  *         This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  int i : CPU interrupt number.
-  *
-  * @param  ets_isr_t func : Interrupt handler.
-  *
-  * @param  void *arg : argument of the handler.
-  *
-  * @return None
-  */
-void ets_isr_attach(int i, ets_isr_t func, void *arg);
-
-/**
-  * @brief  Mask the interrupts which show in mask bits.
-  *         This function equals to _xtos_ints_off(mask).
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
-  *
-  * @return None
-  */
-void ets_isr_mask(uint32_t mask);
-
-/**
-  * @brief  Unmask the interrupts which show in mask bits.
-  *         This function equals to _xtos_ints_on(mask).
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
-  *
-  * @return None
-  */
-void ets_isr_unmask(uint32_t unmask);
-
-/**
-  * @brief  Lock the interrupt to level 2.
-  *         This function direct set the CPU registers.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_intr_lock(void);
-
-/**
-  * @brief  Unlock the interrupt to level 0.
-  *         This function direct set the CPU registers.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_intr_unlock(void);
-
-
-/**
-  * @brief  Attach an CPU interrupt to a hardware source.
-  *         We have 4 steps to use an interrupt:
-  *         1.Attach hardware interrupt source to CPU.  intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
-  *         2.Set interrupt handler.                    xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
-  *         3.Enable interrupt for CPU.                 xt_ints_on(1 << ETS_WMAC_INUM);
-  *         4.Enable interrupt in the module.
-  *
-  * @param  int cpu_no : The CPU which the interrupt number belongs.
-  *
-  * @param  uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
-  *
-  * @param  uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
-  *
-  * @return None
-  */
-void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
-
-/**
-  * @}
-  */
-
-#ifndef MAC2STR
-#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
-#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
-#endif
-
-#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
-
-#ifdef ESP_PLATFORM
-// Remove in IDF v6.0 (IDF-7044)
-typedef enum {
-    OK = 0,
-    FAIL,
-    PENDING,
-    BUSY,
-    CANCEL,
-} STATUS __attribute__((deprecated("Use ETS_STATUS instead")));
-#endif
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_ETS_SYS_H_ */

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/hmac.h

@@ -1,55 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_HMAC_H_
-#define _ROM_HMAC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdlib.h>
-#include "efuse.h"
-
-void ets_hmac_enable(void);
-
-void ets_hmac_disable(void);
-
-/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP)
-   to digest a message.
-*/
-int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac);
-
-/* Calculate a downstream HMAC message to temporarily enable JTAG, or
-   to generate a Digital Signature data decryption key.
-
-   - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
-     or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
-
-   - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6.
-     This efuse block must have the corresponding purpose set in "purpose", or
-     ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL.
-
-   The result of this HMAC calculation is only made available "downstream" to the
-   corresponding hardware module, and cannot be accessed by software.
-*/
-int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose);
-
-/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream().
- *
- * - purpose must match a previous call to ets_hmac_calculate_downstream().
- *
- * After this function is called, the corresponding internal operation (JTAG or DS) will no longer
- * have access to the generated key.
- */
-int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _ROM_HMAC_H_

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/libc_stubs.h

@@ -1,83 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _ROM_LIBC_STUBS_H_
-#define _ROM_LIBC_STUBS_H_
-
-#include <sys/lock.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <time.h>
-#include <reent.h>
-#include <errno.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-ESP32-C5 ROM code contains implementations of some of C library functions.
-Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
-implementation defined in the following struct.
-
-The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to
-set the address
-
-So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
-application must allocate syscall table structure for each CPU being used, and populate it with pointers
-to actual implementations of corresponding syscalls.
-*/
-
-struct syscall_stub_table {
-    struct _reent *(*__getreent)(void);
-    void *(*_malloc_r)(struct _reent *r, size_t);
-    void (*_free_r)(struct _reent *r, void *);
-    void *(*_realloc_r)(struct _reent *r, void *, size_t);
-    void *(*_calloc_r)(struct _reent *r, size_t, size_t);
-    void (*_abort)(void);
-    int (*_system_r)(struct _reent *r, const char *);
-    int (*_rename_r)(struct _reent *r, const char *, const char *);
-    clock_t (*_times_r)(struct _reent *r, struct tms *);
-    int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
-    void (*_raise_r)(struct _reent *r);
-    int (*_unlink_r)(struct _reent *r, const char *);
-    int (*_link_r)(struct _reent *r, const char *, const char *);
-    int (*_stat_r)(struct _reent *r, const char *, struct stat *);
-    int (*_fstat_r)(struct _reent *r, int, struct stat *);
-    void *(*_sbrk_r)(struct _reent *r, ptrdiff_t);
-    int (*_getpid_r)(struct _reent *r);
-    int (*_kill_r)(struct _reent *r, int, int);
-    void (*_exit_r)(struct _reent *r, int);
-    int (*_close_r)(struct _reent *r, int);
-    int (*_open_r)(struct _reent *r, const char *, int, int);
-    int (*_write_r)(struct _reent *r, int, const void *, int);
-    int (*_lseek_r)(struct _reent *r, int, int, int);
-    int (*_read_r)(struct _reent *r, int, void *, int);
-    void (*_retarget_lock_init)(_LOCK_T *lock);
-    void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
-    void (*_retarget_lock_close)(_LOCK_T lock);
-    void (*_retarget_lock_close_recursive)(_LOCK_T lock);
-    void (*_retarget_lock_acquire)(_LOCK_T lock);
-    void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
-    int (*_retarget_lock_try_acquire)(_LOCK_T lock);
-    int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
-    void (*_retarget_lock_release)(_LOCK_T lock);
-    void (*_retarget_lock_release_recursive)(_LOCK_T lock);
-    int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap);
-    int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
-    void (*__assert_func) (const char *file, int line, const char *func, const char *failedexpr) __attribute__((__noreturn__));
-    void (*__sinit) (struct _reent *r);
-    void (*_cleanup_r) (struct _reent *r);
-};
-
-extern struct syscall_stub_table *syscall_table_ptr;
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif /* _ROM_LIBC_STUBS_H_ */

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/lldesc.h

@@ -1,139 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_LLDESC_H_
-#define _ROM_LLDESC_H_
-
-#include <stdint.h>
-
-#include "sys/queue.h"
-#include "esp_rom_lldesc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define LLDESC_TX_MBLK_SIZE                 268 /* */
-#define LLDESC_RX_SMBLK_SIZE                64  /* small block size, for small mgmt frame */
-#define LLDESC_RX_MBLK_SIZE                 524 /* rx is large sinec we want to contain mgmt frame in one block*/
-#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE    64  /* it is a small buffer which is a cycle link*/
-#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE      256 /*for ampdu entry*/
-#ifdef ESP_MAC_5
-#define LLDESC_TX_MBLK_NUM                  116  /* 64K / 256 */
-#define LLDESC_RX_MBLK_NUM                  82 /* 64K / 512 MAX 172*/
-#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM     4
-#define LLDESC_RX_AMPDU_LEN_MLBK_NUM       12
-#else
-#ifdef SBUF_RXTX
-#define LLDESC_TX_MBLK_NUM_MAX    (2 * 48) /* 23K / 260 - 8 */
-#define LLDESC_RX_MBLK_NUM_MAX    (2 * 48) /* 23K / 524 */
-#define LLDESC_TX_MBLK_NUM_MIN    (2 * 16) /* 23K / 260 - 8 */
-#define LLDESC_RX_MBLK_NUM_MIN    (2 * 16) /* 23K / 524 */
-#endif
-#define LLDESC_TX_MBLK_NUM      10      //(2 * 32) /* 23K / 260 - 8 */
-
-#ifdef IEEE80211_RX_AMPDU
-#define LLDESC_RX_MBLK_NUM      30
-#else
-#define LLDESC_RX_MBLK_NUM      10
-#endif /*IEEE80211_RX_AMPDU*/
-
-#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM  4
-#define LLDESC_RX_AMPDU_LEN_MLBK_NUM    8
-#endif /* !ESP_MAC_5 */
-
-typedef struct tx_ampdu_entry_s {
-    uint32_t sub_len  : 12,
-             dili_num : 7,
-             : 1,
-             null_byte: 2,
-             data     : 1,
-             enc      : 1,
-             seq      : 8;
-} tx_ampdu_entry_t;
-
-typedef struct lldesc_chain_s {
-    lldesc_t *head;
-    lldesc_t *tail;
-} lldesc_chain_t;
-
-#ifdef SBUF_RXTX
-enum sbuf_mask_s  {
-    SBUF_MOVE_NO = 0,
-    SBUF_MOVE_TX2RX,
-    SBUF_MOVE_RX2TX,
-} ;
-
-#define SBUF_MOVE_STEP 8
-#endif
-#define LLDESC_SIZE  sizeof(struct lldesc_s)
-
-/* SLC Descriptor  */
-#define LLDESC_OWNER_MASK                  0x80000000
-#define LLDESC_OWNER_SHIFT                         31
-#define LLDESC_SW_OWNED                             0
-#define LLDESC_HW_OWNED                             1
-
-#define LLDESC_EOF_MASK                    0x40000000
-#define LLDESC_EOF_SHIFT                           30
-
-#define LLDESC_SOSF_MASK                   0x20000000
-#define LLDESC_SOSF_SHIFT                          29
-
-#define LLDESC_LENGTH_MASK                 0x00fff000
-#define LLDESC_LENGTH_SHIFT                        12
-
-#define LLDESC_SIZE_MASK                   0x00000fff
-#define LLDESC_SIZE_SHIFT                           0
-
-#define LLDESC_ADDR_MASK                    0x000fffff
-
-void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
-                        lldesc_t **head,
-#ifdef TO_HOST_RESTART
-                        lldesc_t **one_before_tail,
-#endif
-                        lldesc_t **tail);
-
-static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
-{
-    lldesc_t *ds = head;
-    uint32_t len = 0;
-
-    while (ds) {
-        len += ds->length;
-        ds = STAILQ_NEXT(ds, qe);
-    }
-
-    return len;
-}
-
-static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
-{
-    ds->owner  = owner;
-    ds->eof    = eof;
-    ds->sosf   = sosf;
-    ds->length = len;
-}
-
-#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len)        do { \
-        (_desc)->owner  = (_owner); \
-        (_desc)->eof    = (_eof);   \
-        (_desc)->sosf   = (_sosf);  \
-        (_desc)->length = (_len);   \
-} while(0)
-
-#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
-
-#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
-
-#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_LLDESC_H_ */

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/miniz.h

@@ -1,8 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead"
-#include "../../../../miniz.h"

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rom_layout.h

@@ -1,102 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SUPPORT_BTDM            0
-#define SUPPORT_BTBB            0
-#define SUPPORT_WIFI            1
-#define SUPPORT_USB_DWCOTG      0
-#define SUPPORT_COEXIST         1
-#define SUPPORT_MBEDTLS         0
-
-/* Structure and functions for returning ROM global layout
- *
- * This is for address symbols defined in the linker script, which may change during ECOs.
- */
-typedef struct {
-    void *dram0_stack_shared_mem_start;
-    void *dram0_rtos_reserved_start;
-    void *stack_sentry;
-    void *stack;
-
-#if SUPPORT_BTDM
-    void *data_start_btdm;
-    void *data_end_btdm;
-    void *bss_start_btdm;
-    void *bss_end_btdm;
-    void *data_start_btdm_rom;
-    void *data_start_interface_btdm;
-    void *data_end_interface_btdm;
-    void *bss_start_interface_btdm;
-    void *bss_end_interface_btdm;
-#endif
-
-#if SUPPORT_BTBB
-    void *dram_start_btbbrom;
-    void *dram_end_btbbrom;
-#endif
-
-#if SUPPORT_BTDM || SUPPORT_WIFI
-    void *dram_start_phyrom;
-    void *dram_end_phyrom;
-#endif
-
-#if SUPPORT_WIFI
-    void *dram_start_net80211;
-    void *dram_end_net80211;
-    void *data_start_interface_net80211;
-    void *data_end_interface_net80211;
-    void *bss_start_interface_net80211;
-    void *bss_end_interface_net80211;
-    void *dram_start_pp;
-    void *dram_end_pp;
-    void *data_start_interface_pp;
-    void *data_end_interface_pp;
-    void *bss_start_interface_pp;
-    void *bss_end_interface_pp;
-#endif
-
-#if SUPPORT_COEXIST
-    void *dram_start_coexist;
-    void *dram_end_coexist;
-    void *data_start_interface_coexist;
-    void *data_end_interface_coexist;
-    void *bss_start_interface_coexist;
-    void *bss_end_interface_coexist;
-#endif
-
-#if SUPPORT_MBEDTLS
-    void *dram_start_mbedtls_rom;
-    void *dram_end_mbedtls_rom;
-#endif
-
-#if SUPPORT_USB_DWCOTG
-    void *dram_start_usb_dwcotg_rom;
-    void *dram_end_usb_dwcotg_rom;
-#else
-    //Two reserved members are defined here, so the structure will not be broken,
-    //please keep in mind that there is no memory can be released between
-    //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom.
-    void *dram_start_usb_reserved_rom;
-    void *dram_end_usb_reserved_rom;
-#endif
-
-    void *dram_start_uart_rom;
-    void *dram_end_uart_rom;
-} ets_rom_layout_t;
-
-extern const ets_rom_layout_t *const ets_rom_layout_p;
-
-#ifdef __cplusplus
-}
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rsa_pss.h

@@ -1,38 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ROM_RSA_PSS_H_
-#define _ROM_RSA_PSS_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ETS_SIG_LEN 384 /* Bytes */
-#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
-
-typedef struct {
-    uint8_t n[384]; /* Public key modulus */
-    uint32_t e;     /* Public key exponent */
-    uint8_t rinv[384];
-    uint32_t mdash;
-} ets_rsa_pubkey_t;
-
-bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
-
-void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
-
-bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h

@@ -1,256 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "esp_assert.h"
-
-#include "soc/soc.h"
-#include "soc/lp_aon_reg.h"
-#include "soc/reset_reasons.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup rtc_apis, rtc registers and memory related apis
-  * @brief rtc apis
-  */
-
-/** @addtogroup rtc_apis
-  * @{
-  */
-
-/**************************************************************************************
-  *                                       Note:                                       *
-  *       Some Rtc memory and registers are used, in ROM or in internal library.      *
-  *          Please do not use reserved or used rtc memory or registers.              *
-  *                                                                                   *
-  *************************************************************************************
-  *                          LP  Memory & Store Register usage
-  *************************************************************************************
-  *     rtc memory addr         type    size            usage
-  *     0x3f421000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
-  *     0x3f421000+SIZE_CP      Slow    8192-SIZE_CP
-  *
-  *     0x3ff80000(0x40070000)  Fast    8192            deep sleep entry code
-  *
-  *************************************************************************************
-  *     RTC store registers     usage
-  *     LP_AON_STORE0_REG       Reserved
-  *     LP_AON_STORE1_REG       RTC_SLOW_CLK calibration value
-  *     LP_AON_STORE2_REG       Boot time, low word
-  *     LP_AON_STORE3_REG       Boot time, high word
-  *     LP_AON_STORE4_REG       External XTAL frequency
-  *     LP_AON_STORE5_REG       FAST_RTC_MEMORY_LENGTH
-  *     LP_AON_STORE6_REG       FAST_RTC_MEMORY_ENTRY
-  *     LP_AON_STORE7_REG       FAST_RTC_MEMORY_CRC
-  *     LP_AON_STORE8_REG       Store light sleep wake stub addr
-  *     LP_AON_STORE9_REG       Store the sleep mode at bit[0]  (0:light sleep 1:deep sleep)
-  *************************************************************************************
-  */
-
-#define RTC_SLOW_CLK_CAL_REG                LP_AON_STORE1_REG
-#define RTC_BOOT_TIME_LOW_REG               LP_AON_STORE2_REG
-#define RTC_BOOT_TIME_HIGH_REG              LP_AON_STORE3_REG
-#define RTC_XTAL_FREQ_REG                   LP_AON_STORE4_REG
-#define RTC_ENTRY_LENGTH_REG                LP_AON_STORE5_REG
-#define RTC_ENTRY_ADDR_REG                  LP_AON_STORE6_REG
-#define RTC_RESET_CAUSE_REG                 LP_AON_STORE6_REG
-#define RTC_MEMORY_CRC_REG                  LP_AON_STORE7_REG
-#define RTC_SLEEP_WAKE_STUB_ADDR_REG        LP_AON_STORE8_REG
-#define RTC_SLEEP_MODE_REG                  LP_AON_STORE8_REG
-
-#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
-
-typedef enum {
-    AWAKE = 0,             //<CPU ON
-    LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
-    DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
-} SLEEP_MODE;
-
-typedef enum {
-    NO_MEAN                = 0,
-    POWERON_RESET          = 1,   /**<1,  Power on reset*/
-    RTC_SW_HPSYS_RESET     = 3,   /**<3,  Software reset hp system*/
-    SLEEP_WAKEUP           = 5,   /**<5,  Deep Sleep reset hp system*/
-    TG0_WDT_HPSYS_RESET    = 7,   /**<7,  Timer Group0 Watch dog reset hp system*/
-    TG1_WDT_HPSYS_RESET    = 8,   /**<8,  Timer Group1 Watch dog reset hp system*/
-    RTC_WDT_HPSYS_RESET    = 9,   /**<9,  RTC Watch dog Reset hp system*/
-    TG0_WDT_CPU_RESET      = 11,  /**<11, Time Group0 reset CPU*/
-    SW_CPU_RESET           = 12,  /**<12, Software reset CPU*/
-    RTC_WDT_CPU_RESET      = 13,  /**<13, RTC Watch dog reset CPU*/
-    RTC_BOD_SYS_RESET      = 15,  /**<15, System reset when the vdd voltage is not stable*/
-    RTC_WDT_SYS_RESET      = 16,  /**<16, RTC Watch dog reset system*/
-    TG1_WDT_CPU_RESET      = 17,  /**<17, Time Group1 reset CPU*/
-    RTC_SWDT_SYS_RESET     = 18,  /**<18, super watchdog reset system*/
-    EFUSE_HPSYS_RESET      = 20,  /**<20, efuse reset hp system*/
-    USB_UART_HPSYS_RESET   = 21,  /**<21, usb uart reset hp system*/
-    USB_JTAG_HPSYS_RESET   = 22,  /**<22, usb jtag reset hp system*/
-    JTAG_CPU_RESET         = 24,  /**<24, jtag reset CPU*/
-    RTC_PWR_GLITCH_RESET   = 25,  /**<25, RTC power glitch reset system*/
-    CPU_LOCKUP_RESET       = 26,  /**<26, cpu lockup reset*/
-} RESET_REASON;
-
-// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
-ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_HPSYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_HPSYS_RESET != RESET_REASON_CORE_SW");
-ESP_STATIC_ASSERT((soc_reset_reason_t)SLEEP_WAKEUP == RESET_REASON_CORE_DEEP_SLEEP, "SLEEP_WAKEUP != RESET_REASON_CORE_DEEP_SLEEP");
-ESP_STATIC_ASSERT((soc_reset_reason_t)TG0_WDT_HPSYS_RESET == RESET_REASON_CORE_MWDT0, "TG0_WDT_HPSYS_RESET != RESET_REASON_CORE_MWDT0");
-ESP_STATIC_ASSERT((soc_reset_reason_t)TG1_WDT_HPSYS_RESET == RESET_REASON_CORE_MWDT1, "TG1_WDT_HPSYS_RESET != RESET_REASON_CORE_MWDT1");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_HPSYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTC_WDT_HPSYS_RESET != RESET_REASON_CORE_RTC_WDT");
-ESP_STATIC_ASSERT((soc_reset_reason_t)TG0_WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0_WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
-ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTC_WDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_BOD_SYS_RESET == RESET_REASON_SYS_BROWN_OUT, "RTC_BOD_SYS_RESET != RESET_REASON_SYS_BROWN_OUT");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_SYS_RESET == RESET_REASON_SYS_RTC_WDT, "RTC_WDT_SYS_RESET != RESET_REASON_SYS_RTC_WDT");
-ESP_STATIC_ASSERT((soc_reset_reason_t)TG1_WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1_WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SWDT_SYS_RESET == RESET_REASON_SYS_SUPER_WDT, "RTC_SWDT_SYS_RESET != RESET_REASON_SYS_SUPER_WDT");
-ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_HPSYS_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_HPSYS_RESET != RESET_REASON_CORE_EFUSE_CRC");
-ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_HPSYS_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_HPSYS_RESET != RESET_REASON_CORE_USB_UART");
-ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_HPSYS_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_HPSYS_RESET != RESET_REASON_CORE_USB_JTAG");
-ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_CPU_RESET == RESET_REASON_CPU0_JTAG, "JTAG_CPU_RESET != RESET_REASON_CPU0_JTAG");
-ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_PWR_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "RTC_PWR_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
-ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU0_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU0_LOCKUP");
-
-typedef enum {
-    NO_SLEEP        = 0,
-    EXT_EVENT0_TRIG = BIT0,
-    EXT_EVENT1_TRIG = BIT1,
-    GPIO_TRIG       = BIT2,
-    TIMER_EXPIRE    = BIT3,
-    SDIO_TRIG       = BIT4,
-    MAC_TRIG        = BIT5,
-    UART0_TRIG      = BIT6,
-    UART1_TRIG      = BIT7,
-    TOUCH_TRIG      = BIT8,
-    SAR_TRIG        = BIT9,
-    BT_TRIG         = BIT10,
-    RISCV_TRIG      = BIT11,
-    XTAL_DEAD_TRIG  = BIT12,
-    RISCV_TRAP_TRIG = BIT13,
-    USB_TRIG        = BIT14
-} WAKEUP_REASON;
-
-typedef enum {
-    DISEN_WAKEUP       = NO_SLEEP,
-    EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
-    EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
-    GPIO_TRIG_EN       = GPIO_TRIG,
-    TIMER_EXPIRE_EN    = TIMER_EXPIRE,
-    SDIO_TRIG_EN       = SDIO_TRIG,
-    MAC_TRIG_EN        = MAC_TRIG,
-    UART0_TRIG_EN      = UART0_TRIG,
-    UART1_TRIG_EN      = UART1_TRIG,
-    TOUCH_TRIG_EN      = TOUCH_TRIG,
-    SAR_TRIG_EN        = SAR_TRIG,
-    BT_TRIG_EN         = BT_TRIG,
-    RISCV_TRIG_EN      = RISCV_TRIG,
-    XTAL_DEAD_TRIG_EN  = XTAL_DEAD_TRIG,
-    RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
-    USB_TRIG_EN        = USB_TRIG
-} WAKEUP_ENABLE;
-
-/**
-  * @brief  Get the reset reason for CPU.
-  *
-  * @param  int cpu_no : CPU no.
-  *
-  * @return RESET_REASON
-  */
-RESET_REASON rtc_get_reset_reason(int cpu_no);
-
-/**
-  * @brief  Get the wakeup cause for CPU.
-  *
-  * @param  int cpu_no : CPU no.
-  *
-  * @return WAKEUP_REASON
-  */
-WAKEUP_REASON rtc_get_wakeup_cause(void);
-
-typedef void (* esp_rom_wake_func_t)(void);
-
-/**
-  * @brief Read stored RTC wake function address
-  *
-  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
-  * valid means that both stored stub length and stored wake function address are four-byte aligned non-zero values
-  * and the crc check passes
-  *
-  * @param  None
-  *
-  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
-  */
-esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
-
-/**
-  * @brief Store new RTC wake function address
-  *
-  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
-  * memory is calculated and stored also.
-  *
-  * @param entry_addr Address of function. should be 4-bytes aligned otherwise it will not start from the stub after wake from deepsleep，
-  *                   if NULL length will be ignored and all registers are cleared to 0.
-  *
-  * @param length length of function in RTC fast memory. should be less than RTC Fast memory size and aligned to 4-bytes.
-  *               otherwise all registers are cleared to 0.
-  *
-  * @return None
-  */
-void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
-
-/**
-  * @brief Suppress ROM log by setting specific RTC control register.
-  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-static inline void rtc_suppress_rom_log(void)
-{
-    /* To disable logging in the ROM, only the least significant bit of the register is used,
-     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
-     * you need to write to this register in the same format.
-     * Namely, the upper 16 bits and lower should be the same.
-     */
-    REG_SET_BIT(LP_AON_STORE4_REG, RTC_DISABLE_ROM_LOG);
-}
-
-/**
-  * @brief Software Reset digital core.
-  *
-  * It is not recommended to use this function in esp-idf, use
-  * esp_restart() instead.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void software_reset(void);
-
-/**
-  * @brief Software Reset digital core.
-  *
-  * It is not recommended to use this function in esp-idf, use
-  * esp_restart() instead.
-  *
-  * @param  int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
-  *
-  * @return None
-  */
-void software_reset_cpu(int cpu_no);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/secure_boot.h

@@ -1,133 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ets_sys.h"
-#include "ecdsa.h"
-#include "rsa_pss.h"
-#include "esp_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT
-
-typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
-typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
-typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
-
-/* Anti-FI measure: use full words for success/fail, instead of
-   0/non-zero
-*/
-typedef enum {
-    SB_SUCCESS = 0x3A5A5AA5,
-    SB_FAILED = 0x7533885E,
-} ets_secure_boot_status_t;
-
-/* Verify bootloader image (reconfigures cache to map),
-   with key digests provided as parameters.)
-
-   Can be used to verify secure boot status before enabling
-   secure boot permanently.
-
-   If stage_load parameter is true, bootloader is copied into staging
-   buffer in RAM at the same time.
-
-   If result is SB_SUCCESS, the "simple hash" of the bootloader is
-   copied into verified_hash.
-*/
-ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
-
-/* Read key digests from efuse. Any revoked/missing digests will be
-   marked as NULL
-*/
-ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
-
-/* Verify supplied signature against supplied digest, using
-   supplied trusted key digests.
-
-   Doesn't reconfigure cache or any other hardware access except for RSA peripheral.
-
-   If result is SB_SUCCESS, the image_digest value is copied into verified_digest.
-*/
-ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
-
-/* Revoke a public key digest in efuse.
-   @param index Digest to revoke. Must be 0, 1 or 2.
- */
-void ets_secure_boot_revoke_public_key_digest(int index);
-
-#define CRC_SIGN_BLOCK_LEN 1196
-#define SIG_BLOCK_PADDING 4096
-#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
-
-/* Secure Boot V2 signature block
-
-   (Up to 3 in a signature sector are appended to the image)
- */
-#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME
-
-struct ets_secure_boot_sig_block {
-    uint8_t magic_byte;
-    uint8_t version;
-    uint8_t _reserved1;
-    uint8_t _reserved2;
-    uint8_t image_digest[32];
-    ets_rsa_pubkey_t key;
-    uint8_t signature[384];
-    uint32_t block_crc;
-    uint8_t _padding[16];
-};
-
-#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME
-
-struct __attribute((packed)) ets_secure_boot_sig_block {
-    uint8_t magic_byte;
-    uint8_t version;
-    uint8_t _reserved1;
-    uint8_t _reserved2;
-    uint8_t image_digest[32];
-    struct {
-        struct {
-            uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */
-            uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */
-        } key;
-        uint8_t signature[64]; /* r followed by s (both little-endian) */
-        uint8_t padding[1031];
-    } ecdsa;
-    uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */
-    uint8_t _padding[16];
-};
-#endif
-
-ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
-
-#define SECURE_BOOT_NUM_BLOCKS 3
-
-/* V2 Secure boot signature sector (up to 3 blocks) */
-struct ets_secure_boot_signature {
-    ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
-    uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
-};
-
-ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
-
-#define MAX_KEY_DIGESTS 3
-
-struct ets_secure_boot_key_digests {
-    const void *key_digests[MAX_KEY_DIGESTS];
-    bool allow_key_revoke;
-};
-
-#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */
-
-#ifdef __cplusplus
-}
-#endif

components/esp_rom/include/esp32c5/beta3/esp32c5/rom/sha.h

@@ -1,53 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _ROM_SHA_H_
-#define _ROM_SHA_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "ets_sys.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    SHA1 = 0,
-    SHA2_224,
-    SHA2_256,
-    SHA_TYPE_MAX
-} SHA_TYPE;
-
-typedef struct SHAContext {
-    bool start;
-    bool in_hardware;               // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
-    SHA_TYPE type;
-    uint32_t state[16];             // For SHA1/SHA224/SHA256, used 8, other used 16
-    unsigned char buffer[128];      // For SHA1/SHA224/SHA256, used 64, other used 128
-    uint32_t total_bits[4];
-} SHA_CTX;
-
-void ets_sha_enable(void);
-
-void ets_sha_disable(void);
-
-ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
-
-ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
-
-void ets_sha_get_state(SHA_CTX *ctx);
-
-void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
-
-void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
-
-ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_SHA_H_ */