diff --git a/components/soc/esp32s2beta/include/soc/soc.h b/components/soc/esp32s2beta/include/soc/soc.h
index 31702827b9..d643518719 100644
--- a/components/soc/esp32s2beta/include/soc/soc.h
+++ b/components/soc/esp32s2beta/include/soc/soc.h
@@ -57,7 +57,7 @@
 
 #define PRO_CPU_NUM (0)
 
-#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
 
 #define DR_REG_SYSTEM_BASE                      0x3f4c0000
 #define DR_REG_SENSITIVE_BASE                   0x3f4c1000
diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c
index 02bf28d2f1..73e7ed3728 100644
--- a/components/soc/esp32s2beta/soc_memory_layout.c
+++ b/components/soc/esp32s2beta/soc_memory_layout.c
@@ -67,7 +67,7 @@ Because of requirements in the coalescing code which merges adjacent regions, th
 from low to high start address.
 */
 const soc_memory_region_t soc_memory_regions[] = {
-#ifdef CONFIG_SPIRAM_SUPPORT
+#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
     { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
 #if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
     { SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available