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Merge branch 'refactor/ulp_riscv_i2c_logs_v5.4' into 'release/v5.4'

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refactor(ulp_riscv): Modify i2c read/write API for better logging and return error code (v5.4)

See merge request espressif/esp-idf!41674
This commit is contained in:
Marius Vikhammer
2025-09-16 13:33:44 +08:00
parent d7228f798e 1b5138e37e
commit 05534d2686
4 changed files with 53 additions and 24 deletions
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8
components/ulp/ulp_riscv/include/ulp_riscv_i2c.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -114,8 +114,9 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr);
* *
* @param data_rd Buffer to hold data to be read * @param data_rd Buffer to hold data to be read
* @param size Size of data to be read in bytes * @param size Size of data to be read in bytes
* @return esp_err_t ESP_OK when successful
*/ */
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size); esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
/** /**
* @brief Write to I2C slave device * @brief Write to I2C slave device
@@ -124,8 +125,9 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
* *
* @param data_wr Buffer which holds the data to be written * @param data_wr Buffer which holds the data to be written
* @param size Size of data to be written in bytes * @param size Size of data to be written in bytes
* @return esp_err_t ESP_OK when successful
*/ */
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size); esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size);
/** /**
* @brief Initialize and configure the RTC I2C for use by ULP RISC-V * @brief Initialize and configure the RTC I2C for use by ULP RISC-V

9
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_i2c_ulp_core.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -12,6 +12,7 @@ extern "C" {
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
#include "esp_err.h"
/** /**
* @brief Set the I2C slave device address * @brief Set the I2C slave device address
@@ -34,8 +35,9 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr);
* *
* @param data_rd Buffer to hold data to be read * @param data_rd Buffer to hold data to be read
* @param size Size of data to be read in bytes * @param size Size of data to be read in bytes
* @return esp_err_t ESP_OK when successful
*/ */
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size); esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
/** /**
* @brief Write to I2C slave device * @brief Write to I2C slave device
@@ -44,8 +46,9 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
* *
* @param data_wr Buffer which holds the data to be written * @param data_wr Buffer which holds the data to be written
* @param size Size of data to be written in bytes * @param size Size of data to be written in bytes
* @return esp_err_t ESP_OK when successful
*/ */
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size); esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size);
#ifdef __cplusplus #ifdef __cplusplus
} }

19
components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c
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@@ -1,8 +1,9 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include "esp_err.h"
#include "ulp_riscv_i2c_ulp_core.h" #include "ulp_riscv_i2c_ulp_core.h"
#include "ulp_riscv_utils.h" #include "ulp_riscv_utils.h"
#include "soc/rtc_i2c_reg.h" #include "soc/rtc_i2c_reg.h"
@@ -131,14 +132,15 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr)
* | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | | * | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
* |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------| * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------|
*/ */
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size) esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
{ {
uint32_t i = 0; uint32_t i = 0;
uint32_t cmd_idx = 0; uint32_t cmd_idx = 0;
esp_err_t ret = ESP_OK;
if (size == 0) { if (size == 0) {
// Quietly return // Quietly return
return; return ESP_ERR_INVALID_ARG;
} }
// Workaround for IDF-9145 // Workaround for IDF-9145
@@ -197,6 +199,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
} else { } else {
/* Error in transaction */ /* Error in transaction */
CLEAR_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, READ_PERI_REG(RTC_I2C_INT_ST_REG)); CLEAR_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, READ_PERI_REG(RTC_I2C_INT_ST_REG));
ret = ESP_ERR_INVALID_RESPONSE;
break; break;
} }
} }
@@ -207,6 +210,8 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
// Workaround for IDF-9145 // Workaround for IDF-9145
ULP_RISCV_EXIT_CRITICAL(); ULP_RISCV_EXIT_CRITICAL();
return ret;
} }
/* /*
@@ -226,14 +231,15 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
* | Slave | | | ACK | | ACK | | ACK | | ACK | | * | Slave | | | ACK | | ACK | | ACK | | ACK | |
* |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------|
*/ */
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size) esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size)
{ {
uint32_t i = 0; uint32_t i = 0;
uint32_t cmd_idx = 0; uint32_t cmd_idx = 0;
esp_err_t ret = ESP_OK;
if (size == 0) { if (size == 0) {
// Quietly return // Quietly return
return; return ESP_ERR_INVALID_ARG;
} }
// Workaround for IDF-9145 // Workaround for IDF-9145
@@ -271,6 +277,7 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR);
} else { } else {
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, READ_PERI_REG(RTC_I2C_INT_ST_REG)); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, READ_PERI_REG(RTC_I2C_INT_ST_REG));
ret = ESP_ERR_INVALID_RESPONSE;
break; break;
} }
} }
@@ -281,4 +288,6 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
// Workaround for IDF-9145 // Workaround for IDF-9145
ULP_RISCV_EXIT_CRITICAL(); ULP_RISCV_EXIT_CRITICAL();
return ret;
} }

41
components/ulp/ulp_riscv/ulp_riscv_i2c.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -316,15 +316,16 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr)
* | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | | * | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
* |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------| * |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------|
*/ */
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size) esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
{ {
uint32_t i = 0; uint32_t i = 0;
uint32_t cmd_idx = 0; uint32_t cmd_idx = 0;
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
uint32_t status = 0;
if (size == 0) { if (size == 0) {
// Quietly return // Quietly return
return; return ESP_ERR_INVALID_ARG;
} }
/* By default, RTC I2C controller is hard wired to use CMD2 register onwards for read operations */ /* By default, RTC I2C controller is hard wired to use CMD2 register onwards for read operations */
@@ -379,20 +380,26 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
/* Clear the Rx data interrupt bit */ /* Clear the Rx data interrupt bit */
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_RX_DATA_INT_CLR);
} else { } else {
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Read Failed!"); status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
uint32_t status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status);
ret = ESP_ERR_INVALID_RESPONSE;
break; break;
} }
} }
portEXIT_CRITICAL(&rtc_i2c_lock); portEXIT_CRITICAL(&rtc_i2c_lock);
if (ret != ESP_OK) {
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Read Failed!");
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
}
/* Clear the RTC I2C transmission bits */ /* Clear the RTC I2C transmission bits */
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE);
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START);
return ret;
} }
/* /*
@@ -412,15 +419,16 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
* | Slave | | | ACK | | ACK | | ACK | | ACK | | * | Slave | | | ACK | | ACK | | ACK | | ACK | |
* |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------| * |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------|
*/ */
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size) esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size)
{ {
uint32_t i = 0; uint32_t i = 0;
uint32_t cmd_idx = 0; uint32_t cmd_idx = 0;
esp_err_t ret = ESP_OK; esp_err_t ret = ESP_OK;
uint32_t status = 0;
if (size == 0) { if (size == 0) {
// Quietly return // Quietly return
return; return ESP_ERR_INVALID_ARG;
} }
/* By default, RTC I2C controller is hard wired to use CMD0 and CMD1 registers for write operations */ /* By default, RTC I2C controller is hard wired to use CMD0 and CMD1 registers for write operations */
@@ -455,20 +463,27 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
/* Clear the Tx data interrupt bit */ /* Clear the Tx data interrupt bit */
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR);
} else { } else {
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Write Failed!"); status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
uint32_t status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_EARLY_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status); SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status);
ret = ESP_ERR_INVALID_RESPONSE;
break; break;
} }
} }
portEXIT_CRITICAL(&rtc_i2c_lock); portEXIT_CRITICAL(&rtc_i2c_lock);
/* In case of error, print the status after critical section */
if (ret != ESP_OK) {
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: Write Failed!");
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Interrupt Raw Reg 0x%"PRIx32"", status);
ESP_LOGE(RTCI2C_TAG, "ulp_riscv_i2c: RTC I2C Status Reg 0x%"PRIx32"", READ_PERI_REG(RTC_I2C_STATUS_REG));
}
/* Clear the RTC I2C transmission bits */ /* Clear the RTC I2C transmission bits */
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE);
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START); CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START);
return ret;
} }
esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg) esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg)