espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-04 21:24:32 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/esp32s3_libhal' into 'master'

Browse Source 
xtensa: update libhal and configuration headers for esp32s3

Closes FV-201

See merge request espressif/esp-idf!14126
This commit is contained in:
Jiang Jiang Jian
2021-06-30 07:38:45 +00:00
parent d2bd0a4cbd 969904cba6
commit 063f5089ed
9 changed files with 1375 additions and 1346 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
components/xtensa/esp32s3/include/xtensa/config/core-isa.h
View File

@@ -7,7 +7,7 @@
/* Xtensa processor core configuration information. /* Xtensa processor core configuration information.
Copyright (c) 1999-2020 Tensilica Inc. Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the
@@ -194,7 +194,8 @@
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ #define XCHAL_DATA_WIDTH 16 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */ #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
(1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ #define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */ /* In T1050, applies to selected core load and store instructions (see ISA): */
@@ -205,15 +206,17 @@
#define XCHAL_SW_VERSION 1200012 /* sw version of this header */ #define XCHAL_SW_VERSION 1200012 /* sw version of this header */
#define XCHAL_CORE_ID "LX7_ESP32_S3" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */ #define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x00088EF1 /* 22-bit sw build ID */ #define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
/* /*
* These definitions describe the hardware targeted by this software. * These definitions describe the hardware targeted by this software.
*/ */
#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/ #define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x23088EF1 /* ConfigID lo 32 bits*/ #define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */ #define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ #define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */ #define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
@@ -353,9 +356,10 @@
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero) */ #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */ /* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x000637FF #define XCHAL_INTLEVEL1_MASK 0x000637FF
@@ -410,7 +414,8 @@
#define XCHAL_INT31_LEVEL 5 #define XCHAL_INT31_LEVEL 5
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */ #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */ /* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
@@ -541,7 +546,10 @@
EXCEPTIONS and VECTORS EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 == XEA1 (old) 2 == XEA2 (new) 0 == XEAX (extern) or TX */ #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) or TX */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
@@ -644,7 +652,9 @@
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 5 are set, it's a custom TLB configuration. */ /* If none of the above last 5 are set, it's a custom TLB configuration. */

5
components/xtensa/esp32s3/include/xtensa/config/core-matmap.h
View File

@@ -22,7 +22,7 @@
* XCHAL_HW_VERSION_MINOR * XCHAL_HW_VERSION_MINOR
*/ */
/* Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Tensilica Inc. /* Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the
@@ -315,4 +315,7 @@
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 #define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ #endif /*XTENSA_CONFIG_CORE_MATMAP_H*/

2
components/xtensa/esp32s3/include/xtensa/config/defs.h
View File

@@ -1,6 +1,6 @@
/* Definitions for Xtensa instructions, types, and protos. */ /* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=15127; Build=0x86d67; Copyright (c) 2003-2004 Tensilica Inc. /* Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the

2
components/xtensa/esp32s3/include/xtensa/config/specreg.h
View File

@@ -4,7 +4,7 @@
/* $Id: //depot/rel/Foxhill/dot.12/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ /* $Id: //depot/rel/Foxhill/dot.12/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
/* Customer ID=15127; Build=0x86d67; Copyright (c) 1998-2002 Tensilica Inc. /* Customer ID=15128; Build=0x90f1f; Copyright (c) 1998-2002 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the

2
components/xtensa/esp32s3/include/xtensa/config/system.h
View File

@@ -10,7 +10,7 @@
* core-specific but system independent. * core-specific but system independent.
*/ */
/* Customer ID=15127; Build=0x86d67; Copyright (c) 2000-2010 Tensilica Inc. /* Customer ID=15128; Build=0x90f1f; Copyright (c) 2000-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the

276
components/xtensa/esp32s3/include/xtensa/config/tie-asm.h
View File

@@ -8,7 +8,7 @@
macros, etc.) for this specific Xtensa processor's TIE extensions macros, etc.) for this specific Xtensa processor's TIE extensions
and options. It is customized to this Xtensa processor configuration. and options. It is customized to this Xtensa processor configuration.
Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Cadence Design Systems Inc. Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the
@@ -53,7 +53,7 @@
| ((abi) & XTHAL_SAS_ANYABI) ) | ((abi) & XTHAL_SAS_ANYABI) )
/* /*
* Macro to store all non-coprocessor (extra) custom TIE and optional state * Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers). * (not including zero-overhead loop registers).
* Required parameters: * Required parameters:
@@ -73,13 +73,13 @@
* category is selected here that is not in <select>, space for * category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any store. * the corresponding registers is skipped without doing any store.
*/ */
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler: // Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4 xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 // threadptr option rur.THREADPTR \at1 // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_ + 0 s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4 xchal_sa_align \ptr, 0, 1016, 4, 4
@@ -89,9 +89,9 @@
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4 xchal_sa_align \ptr, 0, 1012, 4, 4
rsr.ACCLO \at1 // MAC16 option rsr.ACCLO \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_ + 0 s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.ACCHI \at1 // MAC16 option rsr.ACCHI \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_ + 4 s32i \at1, \ptr, .Lxchal_ofs_+4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4 xchal_sa_align \ptr, 0, 1012, 4, 4
@@ -101,32 +101,22 @@
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4 xchal_sa_align \ptr, 0, 996, 4, 4
rsr.BR \at1 // boolean option rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_ + 0 s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.SCOMPARE1 \at1 // conditional store option rsr.SCOMPARE1 \at1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_ + 4 s32i \at1, \ptr, .Lxchal_ofs_+4
rsr.M0 \at1 // MAC16 option rsr.M0 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_ + 8 s32i \at1, \ptr, .Lxchal_ofs_+8
rsr.M1 \at1 // MAC16 option rsr.M1 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_ + 12 s32i \at1, \ptr, .Lxchal_ofs_+12
rsr.M2 \at1 // MAC16 option rsr.M2 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_ + 16 s32i \at1, \ptr, .Lxchal_ofs_+16
rsr.M3 \at1 // MAC16 option rsr.M3 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_ + 20 s32i \at1, \ptr, .Lxchal_ofs_+20
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4 xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif .endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.SAR_BYTE \at1 // ureg 13
s32i \at1, \ptr, .Lxchal_ofs_ + 0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm // xchal_ncp_store .endm // xchal_ncp_store
/* /*
@@ -149,12 +139,12 @@
* category is selected here that is not in <select>, space for * category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any load. * the corresponding registers is skipped without doing any load.
*/ */
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler: // Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4 xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0 l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 // threadptr option wur.THREADPTR \at1 // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
@@ -164,9 +154,9 @@
// Optional caller-saved registers used by default by the compiler: // Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4 xchal_sa_align \ptr, 0, 1012, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0 l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_ + 4 l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
@@ -176,33 +166,23 @@
// Optional caller-saved registers not used by default by the compiler: // Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4 xchal_sa_align \ptr, 0, 996, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0 l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.BR \at1 // boolean option wsr.BR \at1 // boolean option
l32i \at1, \ptr, .Lxchal_ofs_ + 4 l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.SCOMPARE1 \at1 // conditional store option wsr.SCOMPARE1 \at1 // conditional store option
l32i \at1, \ptr, .Lxchal_ofs_ + 8 l32i \at1, \ptr, .Lxchal_ofs_+8
wsr.M0 \at1 // MAC16 option wsr.M0 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_ + 12 l32i \at1, \ptr, .Lxchal_ofs_+12
wsr.M1 \at1 // MAC16 option wsr.M1 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_ + 16 l32i \at1, \ptr, .Lxchal_ofs_+16
wsr.M2 \at1 // MAC16 option wsr.M2 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_ + 20 l32i \at1, \ptr, .Lxchal_ofs_+20
wsr.M3 \at1 // MAC16 option wsr.M3 \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4 xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif .endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0
wur.SAR_BYTE \at1 // ureg 13
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm // xchal_ncp_load .endm // xchal_ncp_load
@@ -218,31 +198,31 @@
* Optional parameters are the same as for xchal_ncp_store. * Optional parameters are the same as for xchal_ncp_store.
*/ */
#define xchal_cp_FPU_store xchal_cp0_store #define xchal_cp_FPU_store xchal_cp0_store
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler: // Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4 xchal_sa_align \ptr, 0, 948, 4, 4
rur.FCR \at1 // ureg 232 rur.FCR \at1 // ureg 232
s32i \at1, \ptr, .Lxchal_ofs_ + 0 s32i \at1, \ptr, .Lxchal_ofs_+0
rur.FSR \at1 // ureg 233 rur.FSR \at1 // ureg 233
s32i \at1, \ptr, .Lxchal_ofs_ + 4 s32i \at1, \ptr, .Lxchal_ofs_+4
ssi f0, \ptr, .Lxchal_ofs_ + 8 ssi f0, \ptr, .Lxchal_ofs_+8
ssi f1, \ptr, .Lxchal_ofs_ + 12 ssi f1, \ptr, .Lxchal_ofs_+12
ssi f2, \ptr, .Lxchal_ofs_ + 16 ssi f2, \ptr, .Lxchal_ofs_+16
ssi f3, \ptr, .Lxchal_ofs_ + 20 ssi f3, \ptr, .Lxchal_ofs_+20
ssi f4, \ptr, .Lxchal_ofs_ + 24 ssi f4, \ptr, .Lxchal_ofs_+24
ssi f5, \ptr, .Lxchal_ofs_ + 28 ssi f5, \ptr, .Lxchal_ofs_+28
ssi f6, \ptr, .Lxchal_ofs_ + 32 ssi f6, \ptr, .Lxchal_ofs_+32
ssi f7, \ptr, .Lxchal_ofs_ + 36 ssi f7, \ptr, .Lxchal_ofs_+36
ssi f8, \ptr, .Lxchal_ofs_ + 40 ssi f8, \ptr, .Lxchal_ofs_+40
ssi f9, \ptr, .Lxchal_ofs_ + 44 ssi f9, \ptr, .Lxchal_ofs_+44
ssi f10, \ptr, .Lxchal_ofs_ + 48 ssi f10, \ptr, .Lxchal_ofs_+48
ssi f11, \ptr, .Lxchal_ofs_ + 52 ssi f11, \ptr, .Lxchal_ofs_+52
ssi f12, \ptr, .Lxchal_ofs_ + 56 ssi f12, \ptr, .Lxchal_ofs_+56
ssi f13, \ptr, .Lxchal_ofs_ + 60 ssi f13, \ptr, .Lxchal_ofs_+60
ssi f14, \ptr, .Lxchal_ofs_ + 64 ssi f14, \ptr, .Lxchal_ofs_+64
ssi f15, \ptr, .Lxchal_ofs_ + 68 ssi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4 xchal_sa_align \ptr, 0, 948, 4, 4
@@ -260,31 +240,31 @@
* Optional parameters are the same as for xchal_ncp_load. * Optional parameters are the same as for xchal_ncp_load.
*/ */
#define xchal_cp_FPU_load xchal_cp0_load #define xchal_cp_FPU_load xchal_cp0_load
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler: // Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4 xchal_sa_align \ptr, 0, 948, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0 l32i \at1, \ptr, .Lxchal_ofs_+0
wur.FCR \at1 // ureg 232 wur.FCR \at1 // ureg 232
l32i \at1, \ptr, .Lxchal_ofs_ + 4 l32i \at1, \ptr, .Lxchal_ofs_+4
wur.FSR \at1 // ureg 233 wur.FSR \at1 // ureg 233
lsi f0, \ptr, .Lxchal_ofs_ + 8 lsi f0, \ptr, .Lxchal_ofs_+8
lsi f1, \ptr, .Lxchal_ofs_ + 12 lsi f1, \ptr, .Lxchal_ofs_+12
lsi f2, \ptr, .Lxchal_ofs_ + 16 lsi f2, \ptr, .Lxchal_ofs_+16
lsi f3, \ptr, .Lxchal_ofs_ + 20 lsi f3, \ptr, .Lxchal_ofs_+20
lsi f4, \ptr, .Lxchal_ofs_ + 24 lsi f4, \ptr, .Lxchal_ofs_+24
lsi f5, \ptr, .Lxchal_ofs_ + 28 lsi f5, \ptr, .Lxchal_ofs_+28
lsi f6, \ptr, .Lxchal_ofs_ + 32 lsi f6, \ptr, .Lxchal_ofs_+32
lsi f7, \ptr, .Lxchal_ofs_ + 36 lsi f7, \ptr, .Lxchal_ofs_+36
lsi f8, \ptr, .Lxchal_ofs_ + 40 lsi f8, \ptr, .Lxchal_ofs_+40
lsi f9, \ptr, .Lxchal_ofs_ + 44 lsi f9, \ptr, .Lxchal_ofs_+44
lsi f10, \ptr, .Lxchal_ofs_ + 48 lsi f10, \ptr, .Lxchal_ofs_+48
lsi f11, \ptr, .Lxchal_ofs_ + 52 lsi f11, \ptr, .Lxchal_ofs_+52
lsi f12, \ptr, .Lxchal_ofs_ + 56 lsi f12, \ptr, .Lxchal_ofs_+56
lsi f13, \ptr, .Lxchal_ofs_ + 60 lsi f13, \ptr, .Lxchal_ofs_+60
lsi f14, \ptr, .Lxchal_ofs_ + 64 lsi f14, \ptr, .Lxchal_ofs_+64
lsi f15, \ptr, .Lxchal_ofs_ + 68 lsi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4 xchal_sa_align \ptr, 0, 948, 4, 4
@@ -303,47 +283,61 @@
* Optional parameters are the same as for xchal_ncp_store. * Optional parameters are the same as for xchal_ncp_store.
*/ */
#define xchal_cp_cop_ai_store xchal_cp3_store #define xchal_cp_cop_ai_store xchal_cp3_store
.macro xchal_cp3_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 .macro xchal_cp3_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler: // Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 0, 16, 16 xchal_sa_align \ptr, 0, 0, 16, 16
rur.ACCX_0 \at1 // ureg 0 rur.ACCX_0 \at1 // ureg 0
s32i \at1, \ptr, .Lxchal_ofs_ + 0 s32i \at1, \ptr, .Lxchal_ofs_+0
rur.ACCX_1 \at1 // ureg 1 rur.ACCX_1 \at1 // ureg 1
s32i \at1, \ptr, .Lxchal_ofs_ + 4 s32i \at1, \ptr, .Lxchal_ofs_+4
rur.QACC_H_0 \at1 // ureg 2 rur.QACC_H_0 \at1 // ureg 2
s32i \at1, \ptr, .Lxchal_ofs_ + 8 s32i \at1, \ptr, .Lxchal_ofs_+8
rur.QACC_H_1 \at1 // ureg 3 rur.QACC_H_1 \at1 // ureg 3
s32i \at1, \ptr, .Lxchal_ofs_ + 12 s32i \at1, \ptr, .Lxchal_ofs_+12
rur.QACC_H_2 \at1 // ureg 4 rur.QACC_H_2 \at1 // ureg 4
s32i \at1, \ptr, .Lxchal_ofs_ + 16 s32i \at1, \ptr, .Lxchal_ofs_+16
rur.QACC_H_3 \at1 // ureg 5 rur.QACC_H_3 \at1 // ureg 5
s32i \at1, \ptr, .Lxchal_ofs_ + 20 s32i \at1, \ptr, .Lxchal_ofs_+20
rur.QACC_H_4 \at1 // ureg 6 rur.QACC_H_4 \at1 // ureg 6
s32i \at1, \ptr, .Lxchal_ofs_ + 24 s32i \at1, \ptr, .Lxchal_ofs_+24
rur.QACC_L_0 \at1 // ureg 7 rur.QACC_L_0 \at1 // ureg 7
s32i \at1, \ptr, .Lxchal_ofs_ + 28 s32i \at1, \ptr, .Lxchal_ofs_+28
rur.QACC_L_1 \at1 // ureg 8 rur.QACC_L_1 \at1 // ureg 8
s32i \at1, \ptr, .Lxchal_ofs_ + 32 s32i \at1, \ptr, .Lxchal_ofs_+32
rur.QACC_L_2 \at1 // ureg 9 rur.QACC_L_2 \at1 // ureg 9
s32i \at1, \ptr, .Lxchal_ofs_ + 36 s32i \at1, \ptr, .Lxchal_ofs_+36
rur.QACC_L_3 \at1 // ureg 10 rur.QACC_L_3 \at1 // ureg 10
s32i \at1, \ptr, .Lxchal_ofs_ + 40 s32i \at1, \ptr, .Lxchal_ofs_+40
rur.QACC_L_4 \at1 // ureg 11 rur.QACC_L_4 \at1 // ureg 11
s32i \at1, \ptr, .Lxchal_ofs_ + 44 s32i \at1, \ptr, .Lxchal_ofs_+44
st.qr q0, \ptr, .Lxchal_ofs_ + 48 rur.SAR_BYTE \at1 // ureg 13
st.qr q1, \ptr, .Lxchal_ofs_ + 64 s32i \at1, \ptr, .Lxchal_ofs_+48
st.qr q2, \ptr, .Lxchal_ofs_ + 80 rur.FFT_BIT_WIDTH \at1 // ureg 14
st.qr q3, \ptr, .Lxchal_ofs_ + 96 s32i \at1, \ptr, .Lxchal_ofs_+52
st.qr q4, \ptr, .Lxchal_ofs_ + 112 rur.UA_STATE_0 \at1 // ureg 15
s32i \at1, \ptr, .Lxchal_ofs_+56
rur.UA_STATE_1 \at1 // ureg 16
s32i \at1, \ptr, .Lxchal_ofs_+60
rur.UA_STATE_2 \at1 // ureg 17
s32i \at1, \ptr, .Lxchal_ofs_+64
rur.UA_STATE_3 \at1 // ureg 18
s32i \at1, \ptr, .Lxchal_ofs_+68
st.qr q0, \ptr, .Lxchal_ofs_+80
st.qr q1, \ptr, .Lxchal_ofs_+96
st.qr q2, \ptr, .Lxchal_ofs_+112
addi \ptr, \ptr, 128 addi \ptr, \ptr, 128
st.qr q5, \ptr, .Lxchal_ofs_ + 0 st.qr q3, \ptr, .Lxchal_ofs_+0
st.qr q4, \ptr, .Lxchal_ofs_+16
st.qr q5, \ptr, .Lxchal_ofs_+32
st.qr q6, \ptr, .Lxchal_ofs_+48
st.qr q7, \ptr, .Lxchal_ofs_+64
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16 .set .Lxchal_ofs_, .Lxchal_ofs_ + 80
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 0, 16, 16 xchal_sa_align \ptr, 0, 0, 16, 16
.set .Lxchal_ofs_, .Lxchal_ofs_ + 144 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208
.endif .endif
.endm // xchal_cp3_store .endm // xchal_cp3_store
@@ -357,47 +351,61 @@
* Optional parameters are the same as for xchal_ncp_load. * Optional parameters are the same as for xchal_ncp_load.
*/ */
#define xchal_cp_cop_ai_load xchal_cp3_load #define xchal_cp_cop_ai_load xchal_cp3_load
.macro xchal_cp3_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 .macro xchal_cp3_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler: // Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 0, 16, 16 xchal_sa_align \ptr, 0, 0, 16, 16
l32i \at1, \ptr, .Lxchal_ofs_ + 0 l32i \at1, \ptr, .Lxchal_ofs_+0
wur.ACCX_0 \at1 // ureg 0 wur.ACCX_0 \at1 // ureg 0
l32i \at1, \ptr, .Lxchal_ofs_ + 4 l32i \at1, \ptr, .Lxchal_ofs_+4
wur.ACCX_1 \at1 // ureg 1 wur.ACCX_1 \at1 // ureg 1
l32i \at1, \ptr, .Lxchal_ofs_ + 8 l32i \at1, \ptr, .Lxchal_ofs_+8
wur.QACC_H_0 \at1 // ureg 2 wur.QACC_H_0 \at1 // ureg 2
l32i \at1, \ptr, .Lxchal_ofs_ + 12 l32i \at1, \ptr, .Lxchal_ofs_+12
wur.QACC_H_1 \at1 // ureg 3 wur.QACC_H_1 \at1 // ureg 3
l32i \at1, \ptr, .Lxchal_ofs_ + 16 l32i \at1, \ptr, .Lxchal_ofs_+16
wur.QACC_H_2 \at1 // ureg 4 wur.QACC_H_2 \at1 // ureg 4
l32i \at1, \ptr, .Lxchal_ofs_ + 20 l32i \at1, \ptr, .Lxchal_ofs_+20
wur.QACC_H_3 \at1 // ureg 5 wur.QACC_H_3 \at1 // ureg 5
l32i \at1, \ptr, .Lxchal_ofs_ + 24 l32i \at1, \ptr, .Lxchal_ofs_+24
wur.QACC_H_4 \at1 // ureg 6 wur.QACC_H_4 \at1 // ureg 6
l32i \at1, \ptr, .Lxchal_ofs_ + 28 l32i \at1, \ptr, .Lxchal_ofs_+28
wur.QACC_L_0 \at1 // ureg 7 wur.QACC_L_0 \at1 // ureg 7
l32i \at1, \ptr, .Lxchal_ofs_ + 32 l32i \at1, \ptr, .Lxchal_ofs_+32
wur.QACC_L_1 \at1 // ureg 8 wur.QACC_L_1 \at1 // ureg 8
l32i \at1, \ptr, .Lxchal_ofs_ + 36 l32i \at1, \ptr, .Lxchal_ofs_+36
wur.QACC_L_2 \at1 // ureg 9 wur.QACC_L_2 \at1 // ureg 9
l32i \at1, \ptr, .Lxchal_ofs_ + 40 l32i \at1, \ptr, .Lxchal_ofs_+40
wur.QACC_L_3 \at1 // ureg 10 wur.QACC_L_3 \at1 // ureg 10
l32i \at1, \ptr, .Lxchal_ofs_ + 44 l32i \at1, \ptr, .Lxchal_ofs_+44
wur.QACC_L_4 \at1 // ureg 11 wur.QACC_L_4 \at1 // ureg 11
ld.qr q0, \ptr, .Lxchal_ofs_ + 48 l32i \at1, \ptr, .Lxchal_ofs_+48
ld.qr q1, \ptr, .Lxchal_ofs_ + 64 wur.SAR_BYTE \at1 // ureg 13
ld.qr q2, \ptr, .Lxchal_ofs_ + 80 l32i \at1, \ptr, .Lxchal_ofs_+52
ld.qr q3, \ptr, .Lxchal_ofs_ + 96 wur.FFT_BIT_WIDTH \at1 // ureg 14
ld.qr q4, \ptr, .Lxchal_ofs_ + 112 l32i \at1, \ptr, .Lxchal_ofs_+56
wur.UA_STATE_0 \at1 // ureg 15
l32i \at1, \ptr, .Lxchal_ofs_+60
wur.UA_STATE_1 \at1 // ureg 16
l32i \at1, \ptr, .Lxchal_ofs_+64
wur.UA_STATE_2 \at1 // ureg 17
l32i \at1, \ptr, .Lxchal_ofs_+68
wur.UA_STATE_3 \at1 // ureg 18
ld.qr q0, \ptr, .Lxchal_ofs_+80
ld.qr q1, \ptr, .Lxchal_ofs_+96
ld.qr q2, \ptr, .Lxchal_ofs_+112
addi \ptr, \ptr, 128 addi \ptr, \ptr, 128
ld.qr q5, \ptr, .Lxchal_ofs_ + 0 ld.qr q3, \ptr, .Lxchal_ofs_+0
ld.qr q4, \ptr, .Lxchal_ofs_+16
ld.qr q5, \ptr, .Lxchal_ofs_+32
ld.qr q6, \ptr, .Lxchal_ofs_+48
ld.qr q7, \ptr, .Lxchal_ofs_+64
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16 .set .Lxchal_ofs_, .Lxchal_ofs_ + 80
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 0, 16, 16 xchal_sa_align \ptr, 0, 0, 16, 16
.set .Lxchal_ofs_, .Lxchal_ofs_ + 144 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208
.endif .endif
.endm // xchal_cp3_load .endm // xchal_cp3_load
@@ -405,17 +413,17 @@
#define XCHAL_SA_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */ /* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/ #endif /*_XTENSA_CORE_TIE_ASM_H*/

43
components/xtensa/esp32s3/include/xtensa/config/tie.h
View File

@@ -8,7 +8,7 @@
that extend basic Xtensa core functionality. It is customized to this that extend basic Xtensa core functionality. It is customized to this
Xtensa processor configuration. Xtensa processor configuration.
Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Cadence Design Systems Inc. Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the a copy of this software and associated documentation files (the
@@ -45,7 +45,7 @@
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ #define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
#define XCHAL_CP3_NAME "cop_ai" #define XCHAL_CP3_NAME "cop_ai"
#define XCHAL_CP3_IDENT cop_ai #define XCHAL_CP3_IDENT cop_ai
#define XCHAL_CP3_SA_SIZE 144 /* size of state save area */ #define XCHAL_CP3_SA_SIZE 208 /* size of state save area */
#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */ #define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */ #define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
@@ -64,11 +64,11 @@
#define XCHAL_CP7_SA_ALIGN 1 #define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */ /* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 40 #define XCHAL_NCP_SA_SIZE 36
#define XCHAL_NCP_SA_ALIGN 4 #define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */ /* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 272 /* with 16-byte align padding */ #define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */ #define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
/* /*
@@ -111,7 +111,7 @@
* ...what you want to expand... * ...what you want to expand...
*/ */
#define XCHAL_NCP_SA_NUM 10 #define XCHAL_NCP_SA_NUM 9
#define XCHAL_NCP_SA_LIST(s) \ #define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
@@ -121,8 +121,7 @@
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 5,0,0,0)
#define XCHAL_CP0_SA_NUM 18 #define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \ #define XCHAL_CP0_SA_LIST(s) \
@@ -151,7 +150,7 @@
#define XCHAL_CP2_SA_NUM 0 #define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */ #define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 18 #define XCHAL_CP3_SA_NUM 26
#define XCHAL_CP3_SA_LIST(s) \ #define XCHAL_CP3_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \
@@ -165,12 +164,20 @@
XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \ XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \ XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0)
#define XCHAL_CP4_SA_NUM 0 #define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */ #define XCHAL_CP4_SA_LIST(s) /* empty */
@@ -185,16 +192,16 @@
#define XCHAL_CP7_SA_LIST(s) /* empty */ #define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ /* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
/* Byte length of instruction from its first byte, per FLIX. */ /* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \ #define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
#endif /*_XTENSA_CORE_TIE_H*/ #endif /*_XTENSA_CORE_TIE_H*/

BIN
components/xtensa/esp32s3/libxt_hal.a
View File

Binary file not shown.

1
tools/unit-test-app/sdkconfig.defaults
View File

@@ -26,3 +26,4 @@ CONFIG_SPIRAM_BANKSWITCH_ENABLE=n
CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y
CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=n CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=n
CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=3000