mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-04 21:24:32 +02:00
Merge branch 'bugfix/esp32s3_libhal' into 'master'
xtensa: update libhal and configuration headers for esp32s3 Closes FV-201 See merge request espressif/esp-idf!14126
This commit is contained in:
@@ -7,7 +7,7 @@
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2020 Tensilica Inc.
|
||||
Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@@ -194,7 +194,8 @@
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
@@ -205,15 +206,17 @@
|
||||
|
||||
#define XCHAL_SW_VERSION 1200012 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "LX7_ESP32_S3" /* alphanum core name (CoreID) set in the Xtensa Processor Generator */
|
||||
#define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x00088EF1 /* 22-bit sw build ID */
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x23088EF1 /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
|
||||
@@ -353,7 +356,8 @@
|
||||
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero) */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
@@ -410,7 +414,8 @@
|
||||
#define XCHAL_INT31_LEVEL 5
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
@@ -541,7 +546,10 @@
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture number: 1 == XEA1 (old) 2 == XEA2 (new) 0 == XEAX (extern) or TX */
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
@@ -644,7 +652,9 @@
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
|
@@ -22,7 +22,7 @@
|
||||
* XCHAL_HW_VERSION_MINOR
|
||||
*/
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@@ -315,4 +315,7 @@
|
||||
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
|
||||
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
|
||||
|
@@ -1,6 +1,6 @@
|
||||
/* Definitions for Xtensa instructions, types, and protos. */
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 2003-2004 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2004 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
@@ -4,7 +4,7 @@
|
||||
|
||||
/* $Id: //depot/rel/Foxhill/dot.12/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
@@ -10,7 +10,7 @@
|
||||
* core-specific but system independent.
|
||||
*/
|
||||
|
||||
/* Customer ID=15127; Build=0x86d67; Copyright (c) 2000-2010 Tensilica Inc.
|
||||
/* Customer ID=15128; Build=0x90f1f; Copyright (c) 2000-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
@@ -8,7 +8,7 @@
|
||||
macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
and options. It is customized to this Xtensa processor configuration.
|
||||
|
||||
Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Cadence Design Systems Inc.
|
||||
Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@@ -117,16 +117,6 @@
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
rur.SAR_BYTE \at1 // ureg 13
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/*
|
||||
@@ -193,16 +183,6 @@
|
||||
xchal_sa_align \ptr, 0, 996, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
|
||||
.endif
|
||||
// Custom caller-saved registers not used by default by the compiler:
|
||||
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur.SAR_BYTE \at1 // ureg 13
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 1016, 4, 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
@@ -332,18 +312,32 @@
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+40
|
||||
rur.QACC_L_4 \at1 // ureg 11
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+44
|
||||
st.qr q0, \ptr, .Lxchal_ofs_ + 48
|
||||
st.qr q1, \ptr, .Lxchal_ofs_ + 64
|
||||
st.qr q2, \ptr, .Lxchal_ofs_ + 80
|
||||
st.qr q3, \ptr, .Lxchal_ofs_ + 96
|
||||
st.qr q4, \ptr, .Lxchal_ofs_ + 112
|
||||
rur.SAR_BYTE \at1 // ureg 13
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+48
|
||||
rur.FFT_BIT_WIDTH \at1 // ureg 14
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+52
|
||||
rur.UA_STATE_0 \at1 // ureg 15
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+56
|
||||
rur.UA_STATE_1 \at1 // ureg 16
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+60
|
||||
rur.UA_STATE_2 \at1 // ureg 17
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+64
|
||||
rur.UA_STATE_3 \at1 // ureg 18
|
||||
s32i \at1, \ptr, .Lxchal_ofs_+68
|
||||
st.qr q0, \ptr, .Lxchal_ofs_+80
|
||||
st.qr q1, \ptr, .Lxchal_ofs_+96
|
||||
st.qr q2, \ptr, .Lxchal_ofs_+112
|
||||
addi \ptr, \ptr, 128
|
||||
st.qr q5, \ptr, .Lxchal_ofs_ + 0
|
||||
st.qr q3, \ptr, .Lxchal_ofs_+0
|
||||
st.qr q4, \ptr, .Lxchal_ofs_+16
|
||||
st.qr q5, \ptr, .Lxchal_ofs_+32
|
||||
st.qr q6, \ptr, .Lxchal_ofs_+48
|
||||
st.qr q7, \ptr, .Lxchal_ofs_+64
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 80
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 144
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 208
|
||||
.endif
|
||||
.endm // xchal_cp3_store
|
||||
|
||||
@@ -386,18 +380,32 @@
|
||||
wur.QACC_L_3 \at1 // ureg 10
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+44
|
||||
wur.QACC_L_4 \at1 // ureg 11
|
||||
ld.qr q0, \ptr, .Lxchal_ofs_ + 48
|
||||
ld.qr q1, \ptr, .Lxchal_ofs_ + 64
|
||||
ld.qr q2, \ptr, .Lxchal_ofs_ + 80
|
||||
ld.qr q3, \ptr, .Lxchal_ofs_ + 96
|
||||
ld.qr q4, \ptr, .Lxchal_ofs_ + 112
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+48
|
||||
wur.SAR_BYTE \at1 // ureg 13
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+52
|
||||
wur.FFT_BIT_WIDTH \at1 // ureg 14
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+56
|
||||
wur.UA_STATE_0 \at1 // ureg 15
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+60
|
||||
wur.UA_STATE_1 \at1 // ureg 16
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+64
|
||||
wur.UA_STATE_2 \at1 // ureg 17
|
||||
l32i \at1, \ptr, .Lxchal_ofs_+68
|
||||
wur.UA_STATE_3 \at1 // ureg 18
|
||||
ld.qr q0, \ptr, .Lxchal_ofs_+80
|
||||
ld.qr q1, \ptr, .Lxchal_ofs_+96
|
||||
ld.qr q2, \ptr, .Lxchal_ofs_+112
|
||||
addi \ptr, \ptr, 128
|
||||
ld.qr q5, \ptr, .Lxchal_ofs_ + 0
|
||||
ld.qr q3, \ptr, .Lxchal_ofs_+0
|
||||
ld.qr q4, \ptr, .Lxchal_ofs_+16
|
||||
ld.qr q5, \ptr, .Lxchal_ofs_+32
|
||||
ld.qr q6, \ptr, .Lxchal_ofs_+48
|
||||
ld.qr q7, \ptr, .Lxchal_ofs_+64
|
||||
.set .Lxchal_pofs_, .Lxchal_pofs_ + 128
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 80
|
||||
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
|
||||
xchal_sa_align \ptr, 0, 0, 16, 16
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 144
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 208
|
||||
.endif
|
||||
.endm // xchal_cp3_load
|
||||
|
||||
|
@@ -8,7 +8,7 @@
|
||||
that extend basic Xtensa core functionality. It is customized to this
|
||||
Xtensa processor configuration.
|
||||
|
||||
Customer ID=15127; Build=0x86d67; Copyright (c) 1999-2020 Cadence Design Systems Inc.
|
||||
Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Cadence Design Systems Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
@@ -45,7 +45,7 @@
|
||||
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
|
||||
#define XCHAL_CP3_NAME "cop_ai"
|
||||
#define XCHAL_CP3_IDENT cop_ai
|
||||
#define XCHAL_CP3_SA_SIZE 144 /* size of state save area */
|
||||
#define XCHAL_CP3_SA_SIZE 208 /* size of state save area */
|
||||
#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
|
||||
|
||||
@@ -64,11 +64,11 @@
|
||||
#define XCHAL_CP7_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 40
|
||||
#define XCHAL_NCP_SA_SIZE 36
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 272 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
@@ -111,7 +111,7 @@
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 10
|
||||
#define XCHAL_NCP_SA_NUM 9
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
@@ -121,8 +121,7 @@
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 5,0,0,0)
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 18
|
||||
#define XCHAL_CP0_SA_LIST(s) \
|
||||
@@ -151,7 +150,7 @@
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 18
|
||||
#define XCHAL_CP3_SA_NUM 26
|
||||
#define XCHAL_CP3_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \
|
||||
@@ -165,12 +164,20 @@
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0)
|
||||
XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0)
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
@@ -185,16 +192,16 @@
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
|
||||
/* Byte length of instruction from its first byte, per FLIX. */
|
||||
#define XCHAL_BYTE0_FORMAT_LENGTHS \
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,3
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
|
||||
3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
|
Binary file not shown.
@@ -26,3 +26,4 @@ CONFIG_SPIRAM_BANKSWITCH_ENABLE=n
|
||||
CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
|
||||
CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y
|
||||
CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=n
|
||||
CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=3000
|
||||
|
Reference in New Issue
Block a user