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Merge branch 'fix/fix_bad_dslp_param_after_lightsleep_v5.3' into 'release/v5.3'

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fix(esp_hw_support): Fixed the issue that light sleep destroyed the parameters of subsequent deep sleep (v5.3)

See merge request espressif/esp-idf!37303
This commit is contained in:
Jiang Jiang Jian
2025-02-28 11:36:21 +08:00
parent d05db91535 f72d3ea516
commit 064f63d2a0
11 changed files with 40 additions and 37 deletions
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7
components/esp_hw_support/port/esp32/include/soc/rtc.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -245,7 +245,7 @@ void rtc_clk_apll_enable(bool enable);
* *
* @return * @return
* - 0 Failed * - 0 Failed
* - else Sucess * - else Success
*/ */
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2); uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);
@@ -564,8 +564,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
* used in lightsleep mode. * used in lightsleep mode.
* *
* @param slowclk_period re-calibrated slow clock period * @param slowclk_period re-calibrated slow clock period
* @param dslp true if initialize for deepsleep request
*/ */
void rtc_sleep_low_init(uint32_t slowclk_period); void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup #define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup #define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

10
components/esp_hw_support/port/esp32/rtc_sleep.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -235,12 +235,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
{ {
// set 5 PWC state machine times to fit in main state machine time // set 5 PWC state machine times to fit in main state machine time
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
} }
/* Read back 'reject' status when waking from light or deep sleep */ /* Read back 'reject' status when waking from light or deep sleep */

3
components/esp_hw_support/port/esp32c2/include/soc/rtc.h
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@@ -597,8 +597,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
* used in lightsleep mode. * used in lightsleep mode.
* *
* @param slowclk_period re-calibrated slow clock period * @param slowclk_period re-calibrated slow clock period
* @param dslp true if initialize for deepsleep request
*/ */
void rtc_sleep_low_init(uint32_t slowclk_period); void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup #define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup #define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup

10
components/esp_hw_support/port/esp32c2/rtc_sleep.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -193,12 +193,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
{ {
// set 5 PWC state machine times to fit in main state machine time // set 5 PWC state machine times to fit in main state machine time
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
} }
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu); static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

3
components/esp_hw_support/port/esp32c3/include/soc/rtc.h
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@@ -643,8 +643,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
* used in lightsleep mode. * used in lightsleep mode.
* *
* @param slowclk_period re-calibrated slow clock period * @param slowclk_period re-calibrated slow clock period
* @param dslp true if initialize for deepsleep request
*/ */
void rtc_sleep_low_init(uint32_t slowclk_period); void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup #define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup #define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup

10
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -244,12 +244,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
{ {
// set 5 PWC state machine times to fit in main state machine time // set 5 PWC state machine times to fit in main state machine time
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
} }
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu); static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

7
components/esp_hw_support/port/esp32s2/include/soc/rtc.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -331,7 +331,7 @@ void rtc_clk_apll_enable(bool enable);
* *
* @return * @return
* - 0 Failed * - 0 Failed
* - else Sucess * - else Success
*/ */
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2); uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);
@@ -668,8 +668,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
* used in lightsleep mode. * used in lightsleep mode.
* *
* @param slowclk_period re-calibrated slow clock period * @param slowclk_period re-calibrated slow clock period
* @param dslp true if initialize for deepsleep request
*/ */
void rtc_sleep_low_init(uint32_t slowclk_period); void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup #define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup #define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

10
components/esp_hw_support/port/esp32s2/rtc_sleep.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -249,11 +249,11 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
{ {
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
} }
/* Read back 'reject' status when waking from light or deep sleep */ /* Read back 'reject' status when waking from light or deep sleep */

3
components/esp_hw_support/port/esp32s3/include/soc/rtc.h
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@@ -654,8 +654,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
* used in lightsleep mode. * used in lightsleep mode.
* *
* @param slowclk_period re-calibrated slow clock period * @param slowclk_period re-calibrated slow clock period
* @param dslp true if initialize for deepsleep request
*/ */
void rtc_sleep_low_init(uint32_t slowclk_period); void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup #define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup #define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

10
components/esp_hw_support/port/esp32s3/rtc_sleep.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -256,12 +256,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
{ {
// set 5 PWC state machine times to fit in main state machine time // set 5 PWC state machine times to fit in main state machine time
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
} }
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu); static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

4
components/esp_hw_support/sleep_modes.c
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@@ -958,9 +958,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
rtc_sleep_init(config); rtc_sleep_init(config);
// Set state machine time for light sleep // Set state machine time for light sleep
if (!deep_sleep) { rtc_sleep_low_init(s_config.rtc_clk_cal_period, deep_sleep);
rtc_sleep_low_init(s_config.rtc_clk_cal_period);
}
#endif #endif
// Configure timer wakeup // Configure timer wakeup