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ota: fix ota with flash encryption

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This commit is contained in:
Cao Sen Miao
2021-02-19 11:50:27 +08:00
committed by Cao Senmiao
parent f80f4cbf2d
commit 068dfcf1ba
5 changed files with 13 additions and 9 deletions
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2
components/spi_flash/esp32/flash_ops_esp32.c
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@ -32,6 +32,7 @@ static inline void IRAM_ATTR spi_flash_guard_end(void)
} }
} }
extern void IRAM_ATTR flash_rom_init(void);
esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size) esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
{ {
const uint8_t *ssrc = (const uint8_t *)src; const uint8_t *ssrc = (const uint8_t *)src;
@ -73,6 +74,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
} }
spi_flash_guard_start(); spi_flash_guard_start();
flash_rom_init();
rc = esp_rom_spiflash_write_encrypted(row_addr, (uint32_t *)encrypt_buf, 32); rc = esp_rom_spiflash_write_encrypted(row_addr, (uint32_t *)encrypt_buf, 32);
spi_flash_guard_end(); spi_flash_guard_end();
if (rc != ESP_ROM_SPIFLASH_RESULT_OK) { if (rc != ESP_ROM_SPIFLASH_RESULT_OK) {

2
components/spi_flash/esp32s2/flash_ops_esp32s2.c
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@ -29,6 +29,7 @@ static const char *TAG = "spiflash_s2";
#define SPICACHE SPIMEM0 #define SPICACHE SPIMEM0
#define SPIFLASH SPIMEM1 #define SPIFLASH SPIMEM1
extern void IRAM_ATTR flash_rom_init(void);
esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size) esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
{ {
const spi_flash_guard_funcs_t *ops = spi_flash_guard_get(); const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
@ -68,6 +69,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
if (ops && ops->start) { if (ops && ops->start) {
ops->start(); ops->start();
} }
flash_rom_init();
rc = SPI_Encrypt_Write(dest_addr, src, size); rc = SPI_Encrypt_Write(dest_addr, src, size);
if (ops && ops->end) { if (ops && ops->end) {
ops->end(); ops->end();

14
components/spi_flash/flash_ops.c
View File

@ -462,13 +462,13 @@ out:
} }
#endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL #endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL
#if !CONFIG_SPI_FLASH_USE_LEGACY_IMPL #ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode); extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv); extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
static void IRAM_ATTR flash_rom_init(void) extern uint8_t g_rom_spiflash_dummy_len_plus[];
void IRAM_ATTR flash_rom_init(void)
{ {
uint32_t freqdiv = 0; uint32_t freqdiv = 0;
esp_rom_spiflash_read_mode_t read_mode;
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
uint32_t dummy_bit = 0; uint32_t dummy_bit = 0;
@ -493,6 +493,8 @@ static void IRAM_ATTR flash_rom_init(void)
freqdiv = 4; freqdiv = 4;
#endif #endif
#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
esp_rom_spiflash_read_mode_t read_mode;
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO #if CONFIG_ESPTOOLPY_FLASHMODE_QIO
read_mode = ESP_ROM_SPIFLASH_QIO_MODE; read_mode = ESP_ROM_SPIFLASH_QIO_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT #elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT
@ -502,6 +504,7 @@ static void IRAM_ATTR flash_rom_init(void)
#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT #elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
read_mode = ESP_ROM_SPIFLASH_DOUT_MODE; read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
#endif #endif
#endif //!CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
g_rom_spiflash_dummy_len_plus[1] = dummy_bit; g_rom_spiflash_dummy_len_plus[1] = dummy_bit;
@ -512,11 +515,10 @@ static void IRAM_ATTR flash_rom_init(void)
#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32 #if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
spi_common_set_dummy_output(read_mode); spi_common_set_dummy_output(read_mode);
#endif //!CONFIG_IDF_TARGET_ESP32S2 #endif //!CONFIG_IDF_TARGET_ESP32S2
esp_rom_spiflash_config_readmode(read_mode);
esp_rom_spiflash_config_clk(freqdiv, 1); esp_rom_spiflash_config_clk(freqdiv, 1);
} }
#else #else
static void IRAM_ATTR flash_rom_init(void) void IRAM_ATTR flash_rom_init(void)
{ {
return; return;
} }
@ -525,7 +527,6 @@ static void IRAM_ATTR flash_rom_init(void)
esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size) esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size)
{ {
esp_err_t err = ESP_OK; esp_err_t err = ESP_OK;
flash_rom_init();
CHECK_WRITE_ADDRESS(dest_addr, size); CHECK_WRITE_ADDRESS(dest_addr, size);
if ((dest_addr % 16) != 0) { if ((dest_addr % 16) != 0) {
return ESP_ERR_INVALID_ARG; return ESP_ERR_INVALID_ARG;
@ -769,7 +770,6 @@ out:
esp_err_t IRAM_ATTR spi_flash_read_encrypted(size_t src, void *dstv, size_t size) esp_err_t IRAM_ATTR spi_flash_read_encrypted(size_t src, void *dstv, size_t size)
{ {
flash_rom_init();
if (src + size > g_rom_flashchip.chip_size) { if (src + size > g_rom_flashchip.chip_size) {
return ESP_ERR_INVALID_SIZE; return ESP_ERR_INVALID_SIZE;
} }

2
tools/ci/config/target-test.yml
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@ -485,7 +485,7 @@ UT_020:
- psram - psram
UT_021: UT_021:
extends: .unit_test_32_template extends: .unit_test_template
parallel: 2 parallel: 2
tags: tags:
- ESP32_IDF - ESP32_IDF

2
tools/unit-test-app/configs/psram_3
View File

@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32" CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=driver freertos sdmmc TEST_COMPONENTS=driver
CONFIG_ESP32_SPIRAM_SUPPORT=y CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y CONFIG_SPIRAM_OCCUPY_NO_HOST=y