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ulp-riscv: enable ULP-RISCV ADC example for esp32s2

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ADC can now be used from the ULP-RISCV on S2 after the RTC power parameters were
fixed in a624d8d061

Closes https://github.com/espressif/esp-idf/issues/11052
Closes https://github.com/espressif/esp-idf/issues/11040
This commit is contained in:
Marius Vikhammer
2023-04-11 12:59:20 +08:00
parent ef4b1b7704
commit 07471019ef
2 changed files with 3 additions and 3 deletions
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2
examples/system/.build-test-rules.yml
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@@ -154,7 +154,7 @@ examples/system/ulp_fsm/ulp_adc:
examples/system/ulp_riscv/adc: examples/system/ulp_riscv/adc:
enable: enable:
- if: IDF_TARGET in ["esp32s3"] - if: IDF_TARGET in ["esp32s2", "esp32s3"]
temporary: true temporary: true
reason: the other targets are not tested yet reason: the other targets are not tested yet

4
examples/system/ulp_riscv/adc/README.md
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-S3 | | Supported Targets | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | | ----------------- | -------- | -------- |
# ULP-RISC-V ADC Example # ULP-RISC-V ADC Example