From 741e89cbaa1421f15ec87b5e05a1677476ec2970 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Wed, 23 Nov 2022 00:39:25 +0800 Subject: [PATCH] esp_hw_support: Removes efuse dependency --- .../efuse/esp32s2/esp_efuse_rtc_table.c | 5 +- components/esp_hw_support/CMakeLists.txt | 1 + .../esp_hw_support/port/esp32/rtc_clk_init.c | 1 - .../port/esp32c2/rtc_clk_init.c | 1 - .../esp_hw_support/port/esp32c2/rtc_init.c | 40 ++++------- .../esp_hw_support/port/esp32c2/rtc_sleep.c | 1 - .../port/esp32c3/rtc_clk_init.c | 1 - .../esp_hw_support/port/esp32c3/rtc_init.c | 42 +++--------- .../port/esp32c6/rtc_clk_init.c | 1 - .../port/esp32h4/rtc_clk_init.c | 1 - .../esp_hw_support/port/esp32h4/rtc_init.c | 3 - .../esp_hw_support/port/esp32h4/rtc_sleep.c | 1 - .../port/esp32s2/rtc_clk_init.c | 1 - .../esp_hw_support/port/esp32s2/rtc_init.c | 16 ++--- .../esp_hw_support/port/esp32s3/rtc_init.c | 52 +++------------ components/esp_hw_support/rtc_wdt.c | 1 - components/esp_psram/CMakeLists.txt | 2 +- .../esp_psram/esp32/esp_psram_impl_quad.c | 3 +- components/hal/esp32c2/include/hal/efuse_ll.h | 66 +++++++++++++++++++ components/hal/esp32c3/include/hal/efuse_ll.h | 36 ++++++++++ components/hal/esp32s2/include/hal/efuse_ll.h | 8 +++ components/hal/esp32s3/include/hal/efuse_ll.h | 36 ++++++++++ .../soc/esp32c2/include/soc/efuse_struct.h | 46 ++++++------- .../soc/esp32c3/include/soc/efuse_struct.h | 21 ++++-- .../soc/esp32s2/include/soc/efuse_struct.h | 6 +- .../soc/esp32s3/include/soc/efuse_struct.h | 27 ++++++-- 26 files changed, 249 insertions(+), 170 deletions(-) diff --git a/components/efuse/esp32s2/esp_efuse_rtc_table.c b/components/efuse/esp32s2/esp_efuse_rtc_table.c index 7df7f45436..f24a56407c 100644 --- a/components/efuse/esp32s2/esp_efuse_rtc_table.c +++ b/components/efuse/esp32s2/esp_efuse_rtc_table.c @@ -10,6 +10,7 @@ #include "esp_efuse_table.h" #include "esp_log.h" #include "hal/adc_types.h" +#include "hal/efuse_ll.h" #include "soc/soc_caps.h" #define RTC_TBL_LOG_TAG "efuse_rtc_table" @@ -90,9 +91,7 @@ static const efuse_map_info_t adc_efuse_raw_map[] = { int esp_efuse_rtc_table_read_calib_version(void) { - uint32_t result = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &result, 3); - return result; + return efuse_ll_get_blk_version_minor(); } int esp_efuse_rtc_table_get_tag(int version, int adc_num, int atten, int extra_params) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 3de2a18299..6eb8cb8656 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -1,6 +1,7 @@ idf_build_get_property(target IDF_TARGET) set(requires soc) +# only esp_hw_support/adc_share_hw_ctrl.c requires efuse component set(priv_requires efuse spi_flash bootloader_support) set(srcs "cpu.c" "esp_memory_utils.c") diff --git a/components/esp_hw_support/port/esp32/rtc_clk_init.c b/components/esp_hw_support/port/esp32/rtc_clk_init.c index 821ecda345..63017c2cce 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32/rtc_clk_init.c @@ -14,7 +14,6 @@ #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/sens_periph.h" -#include "soc/efuse_periph.h" #include "hal/clk_tree_ll.h" #include "hal/regi2c_ctrl_ll.h" #include "esp_hw_log.h" diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk_init.c b/components/esp_hw_support/port/esp32c2/rtc_clk_init.c index c0ad3f4dce..8b5a185a93 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk_init.c @@ -13,7 +13,6 @@ #include "esp32c2/rom/uart.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" -#include "soc/efuse_periph.h" #include "hal/regi2c_ctrl_ll.h" #include "esp_hw_log.h" #include "esp_cpu.h" diff --git a/components/esp_hw_support/port/esp32c2/rtc_init.c b/components/esp_hw_support/port/esp32c2/rtc_init.c index e8ec002a09..b55769a5d6 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_init.c @@ -9,18 +9,16 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/efuse_periph.h" #include "soc/gpio_reg.h" #include "soc/spi_mem_reg.h" #include "soc/extmem_reg.h" #include "soc/system_reg.h" #include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" #include "regi2c_ctrl.h" #include "soc/regi2c_dig_reg.h" #include "soc/regi2c_lp_bias.h" #include "esp_hw_log.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" #ifndef BOOTLOADER_BUILD #include "esp_private/sar_periph_ctrl.h" #endif @@ -144,11 +142,7 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) static void set_ocode_by_efuse(int ocode_scheme_ver) { assert(ocode_scheme_ver == 1); - // use efuse ocode. - signed int ocode = 0; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, ESP_EFUSE_OCODE[0]->bit_count); - assert(err == ESP_OK); - (void) err; + signed int ocode = efuse_ll_get_ocode(); //recover efuse data ocode = ((ocode & BIT(6)) != 0)? -(ocode & 0x3f): ocode; @@ -211,13 +205,7 @@ static void calibrate_ocode(void) static uint32_t get_dig_dbias_by_efuse(uint8_t dbias_scheme_ver) { assert(dbias_scheme_ver == 1); - uint32_t dig_dbias = 26; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count); - if (err != ESP_OK) { - dig_dbias = 26; - ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); - } - return dig_dbias; + return efuse_ll_get_dig_dbias_hvt(); } uint32_t get_rtc_dbias_by_efuse(uint8_t dbias_scheme_ver, uint32_t dig_dbias) @@ -226,20 +214,14 @@ uint32_t get_rtc_dbias_by_efuse(uint8_t dbias_scheme_ver, uint32_t dig_dbias) uint32_t rtc_dbias = 31; //read efuse data - signed int dig_slp_dbias2 = 0, dig_slp_dbias26 = 0, dig_act_dbias26 = 0, dig_act_step = 0, rtc_slp_dbias29 = 0, rtc_slp_dbias31 = 0, rtc_act_dbias31 = 0, rtc_act_dbias13 = 0; - esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_SLP_DBIAS2, &dig_slp_dbias2, ESP_EFUSE_DIG_LDO_SLP_DBIAS2[0]->bit_count); - esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_SLP_DBIAS26, &dig_slp_dbias26, ESP_EFUSE_DIG_LDO_SLP_DBIAS26[0]->bit_count); - esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_ACT_DBIAS26, &dig_act_dbias26, ESP_EFUSE_DIG_LDO_ACT_DBIAS26[0]->bit_count); - esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_ACT_STEPD10, &dig_act_step, ESP_EFUSE_DIG_LDO_ACT_STEPD10[0]->bit_count); - esp_err_t err4 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_SLP_DBIAS29, &rtc_slp_dbias29, ESP_EFUSE_RTC_LDO_SLP_DBIAS29[0]->bit_count); - esp_err_t err5 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_SLP_DBIAS31, &rtc_slp_dbias31, ESP_EFUSE_RTC_LDO_SLP_DBIAS31[0]->bit_count); - esp_err_t err6 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_ACT_DBIAS31, &rtc_act_dbias31, ESP_EFUSE_RTC_LDO_ACT_DBIAS31[0]->bit_count); - esp_err_t err7 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_ACT_DBIAS13, &rtc_act_dbias13, ESP_EFUSE_RTC_LDO_ACT_DBIAS13[0]->bit_count); - - if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK) | (err4 != ESP_OK) | (err5 != ESP_OK) | (err6 != ESP_OK) | (err7 != ESP_OK)) { - ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_dbias value: %d\n", rtc_dbias); - return rtc_dbias; - } + signed int dig_slp_dbias2 = efuse_ll_get_dig_ldo_slp_dbias2(); + signed int dig_slp_dbias26 = efuse_ll_get_dig_ldo_slp_dbias26(); + signed int dig_act_dbias26 = efuse_ll_get_dig_ldo_act_dbias26(); + signed int dig_act_step = efuse_ll_get_dig_ldo_act_stepd10(); + signed int rtc_slp_dbias29 = efuse_ll_get_rtc_ldo_slp_dbias29(); + signed int rtc_slp_dbias31 = efuse_ll_get_rtc_ldo_slp_dbias31(); + signed int rtc_act_dbias31 = efuse_ll_get_rtc_ldo_act_dbias31(); + signed int rtc_act_dbias13 = efuse_ll_get_rtc_ldo_act_dbias13(); //recover dig&rtc parameter dig_slp_dbias2 = ((dig_slp_dbias2 & BIT(6)) != 0)? -(dig_slp_dbias2 & 0x3f): dig_slp_dbias2; diff --git a/components/esp_hw_support/port/esp32c2/rtc_sleep.c b/components/esp_hw_support/port/esp32c2/rtc_sleep.c index 50ccd67bc7..1934b87c13 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c2/rtc_sleep.c @@ -20,7 +20,6 @@ #include "regi2c_ctrl.h" #include "soc/regi2c_lp_bias.h" #include "soc/regi2c_dig_reg.h" -#include "esp_efuse.h" /** * Configure whether certain peripherals are powered down in deep sleep diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c index f2757fc10b..5b28bd787d 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c @@ -13,7 +13,6 @@ #include "esp32c3/rom/uart.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" -#include "soc/efuse_periph.h" #include "hal/regi2c_ctrl_ll.h" #include "esp_hw_log.h" #include "esp_cpu.h" diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 8d0cd1a1e1..4692562138 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -9,18 +9,16 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/efuse_periph.h" #include "soc/gpio_reg.h" #include "soc/spi_mem_reg.h" #include "soc/extmem_reg.h" #include "soc/system_reg.h" #include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" #include "regi2c_ctrl.h" #include "soc/regi2c_dig_reg.h" #include "soc/regi2c_lp_bias.h" #include "esp_hw_log.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" #ifndef BOOTLOADER_BUILD #include "esp_private/sar_periph_ctrl.h" #endif @@ -55,12 +53,7 @@ void rtc_init(rtc_config_t cfg) REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles); if (cfg.cali_ocode) { - uint32_t rtc_calib_version = 0; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366 - if (err != ESP_OK) { - rtc_calib_version = 0; - ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version); - } + uint32_t rtc_calib_version = efuse_ll_get_blk_version_major(); // IDF-5366 if (rtc_calib_version == 1) { set_ocode_by_efuse(rtc_calib_version); } else { @@ -207,11 +200,7 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) static void set_ocode_by_efuse(int calib_version) { assert(calib_version == 1); - // use efuse ocode. - uint32_t ocode; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8); - assert(err == ESP_OK); - (void) err; + uint32_t ocode = efuse_ll_get_ocode(); REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); } @@ -268,32 +257,17 @@ static void calibrate_ocode(void) static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version) { assert(chip_version >= 3); - uint32_t dig_dbias = 28; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5); - if (err != ESP_OK) { - dig_dbias = 28; - ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); - } - return dig_dbias; + return efuse_ll_get_dig_dbias_hvt(); } uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias) { assert(chip_version >= 3); uint32_t rtc_dbias = 0; - signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0; - esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7); - esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7); - esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8); - esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8); - if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) { - k_rtc_ldo = 0; - k_dig_ldo = 0; - v_rtc_bias20 = 0; - v_dig_bias20 = 0; - ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20); - } - + signed int k_rtc_ldo = efuse_ll_get_k_rtc_ldo(); + signed int k_dig_ldo = efuse_ll_get_k_dig_ldo(); + signed int v_rtc_bias20 = efuse_ll_get_v_rtc_dbias20(); + signed int v_dig_bias20 = efuse_ll_get_v_dig_dbias20(); k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo; k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20; diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c index 73a950930f..807cf9fd39 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk_init.c @@ -12,7 +12,6 @@ #include "esp32c6/rom/rtc.h" #include "esp32c6/rom/uart.h" #include "soc/rtc.h" -#include "soc/efuse_periph.h" #include "esp_cpu.h" #include "hal/regi2c_ctrl_ll.h" #include "esp_hw_log.h" diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk_init.c b/components/esp_hw_support/port/esp32h4/rtc_clk_init.c index 26ad1c0ed3..f46cfe7e8e 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32h4/rtc_clk_init.c @@ -16,7 +16,6 @@ #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/rtc_cntl_reg.h" -#include "soc/efuse_periph.h" #include "esp_hw_log.h" #include "esp_cpu.h" #include "sdkconfig.h" diff --git a/components/esp_hw_support/port/esp32h4/rtc_init.c b/components/esp_hw_support/port/esp32h4/rtc_init.c index 126e1e05db..04867ab772 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_init.c +++ b/components/esp_hw_support/port/esp32h4/rtc_init.c @@ -9,15 +9,12 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/efuse_periph.h" #include "soc/gpio_reg.h" #include "soc/spi_mem_reg.h" #include "soc/extmem_reg.h" #include "soc/system_reg.h" #include "soc/syscon_reg.h" #include "regi2c_ctrl.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" #include "i2c_pmu.h" #include "soc/clkrst_reg.h" #ifndef BOOTLOADER_BUILD diff --git a/components/esp_hw_support/port/esp32h4/rtc_sleep.c b/components/esp_hw_support/port/esp32h4/rtc_sleep.c index df09677777..4ea3a706fc 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32h4/rtc_sleep.c @@ -21,7 +21,6 @@ #include "regi2c_ctrl.h" #include "soc/regi2c_bias.h" #include "soc/regi2c_ulp.h" -#include "esp_efuse.h" #include "i2c_pmu.h" #include "esp_hw_log.h" #include "esp_rom_uart.h" diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk_init.c b/components/esp_hw_support/port/esp32s2/rtc_clk_init.c index c1d87a474e..00c66edaa6 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_clk_init.c @@ -13,7 +13,6 @@ #include "soc/rtc.h" #include "soc/rtc_periph.h" #include "soc/sens_periph.h" -#include "soc/efuse_periph.h" #include "soc/syscon_reg.h" #include "hal/regi2c_ctrl_ll.h" #include "esp_hw_log.h" diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index 18437d7a09..a4c401a5ef 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -9,15 +9,14 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/dport_reg.h" -#include "soc/efuse_periph.h" #include "soc/gpio_reg.h" #include "soc/spi_mem_reg.h" #include "soc/extmem_reg.h" #include "soc/regi2c_ulp.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" #include "regi2c_ctrl.h" #include "esp_hw_log.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" #ifndef BOOTLOADER_BUILD #include "esp_private/sar_periph_ctrl.h" #endif @@ -154,8 +153,7 @@ void rtc_init(rtc_config_t cfg) #if !CONFIG_IDF_ENV_FPGA if (cfg.cali_ocode) { - uint32_t rtc_calib_version = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366 + uint32_t rtc_calib_version = efuse_ll_get_blk_version_minor(); // IDF-5366 if (rtc_calib_version == 2) { set_ocode_by_efuse(rtc_calib_version); } else { @@ -222,13 +220,7 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) static void set_ocode_by_efuse(int calib_version) { assert(calib_version == 2); - // use efuse ocode. - uint32_t ocode1 = 0; - uint32_t ocode2 = 0; - uint32_t ocode; - esp_efuse_read_block(2, &ocode1, 16*8, 4); - esp_efuse_read_block(2, &ocode2, 18*8, 3); - ocode = (ocode2 << 4) + ocode1; + uint32_t ocode = efuse_ll_get_ocode(); if (ocode >> 6) { ocode = 93 - (ocode ^ (1 << 6)); } else { diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index 864047748d..0840dcec95 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -21,10 +21,9 @@ #include "esp_hw_log.h" #include "esp_err.h" #include "esp_attr.h" -#include "esp_efuse.h" -#include "esp_efuse_table.h" #include "esp_private/spi_flash_os.h" #include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" #ifndef BOOTLOADER_BUILD #include "esp_private/sar_periph_ctrl.h" #endif @@ -83,13 +82,7 @@ void rtc_init(rtc_config_t cfg) REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT); if (cfg.cali_ocode) { - uint32_t blk_ver_major = 0; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366 - if (err != ESP_OK) { - blk_ver_major = 0; - ESP_HW_LOGW(TAG, "efuse read fail, set default blk_ver_major: %d\n", blk_ver_major); - } - + uint32_t blk_ver_major = efuse_ll_get_blk_version_major(); // IDF-5366 //default blk_ver_major will fallback to using the self-calibration way for OCode bool ocode_efuse_cali = (blk_ver_major == 1); if (ocode_efuse_cali) { @@ -246,10 +239,7 @@ static void set_ocode_by_efuse(int calib_version) { assert(calib_version == 1); // use efuse ocode. - uint32_t ocode; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8); - assert(err == ESP_OK); - (void) err; + uint32_t ocode = efuse_ll_get_ocode(); REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); } @@ -326,32 +316,17 @@ static void calibrate_ocode(void) static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver) { assert(pvt_scheme_ver == 1); - uint32_t dig_dbias = 28; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count); - if (err != ESP_OK) { - dig_dbias = 28; - ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); - } - return dig_dbias; + return efuse_ll_get_dig_dbias_hvt(); } static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbias) { assert(pvt_scheme_ver == 1); uint32_t rtc_dbias = 0; - signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0; - esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, ESP_EFUSE_K_RTC_LDO[0]->bit_count); - esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count); - esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, ESP_EFUSE_V_RTC_DBIAS20[0]->bit_count); - esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count); - if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) { - k_rtc_ldo = 0; - k_dig_ldo = 0; - v_rtc_bias20 = 0; - v_dig_bias20 = 0; - ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20); - } - + signed int k_rtc_ldo = efuse_ll_get_k_rtc_ldo(); + signed int k_dig_ldo = efuse_ll_get_k_dig_ldo(); + signed int v_rtc_bias20 = efuse_ll_get_v_rtc_dbias20(); + signed int v_dig_bias20 = efuse_ll_get_v_dig_dbias20(); k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): (uint8_t)k_rtc_ldo; k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20; @@ -375,15 +350,8 @@ static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbia static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver) { assert(pvt_scheme_ver == 1); - signed int k_dig_ldo = 0, v_dig_bias20 = 0; - esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count); - esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count); - if ((err0 != ESP_OK) | (err1 != ESP_OK)) { - k_dig_ldo = 0; - v_dig_bias20 = 0; - ESP_HW_LOGW(TAG, "efuse read fail, k_dig_ldo: %d, v_dig_bias20: %d\n", k_dig_ldo, v_dig_bias20); - } - + signed int k_dig_ldo = efuse_ll_get_k_dig_ldo(); + signed int v_dig_bias20 = efuse_ll_get_v_dig_dbias20(); k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; diff --git a/components/esp_hw_support/rtc_wdt.c b/components/esp_hw_support/rtc_wdt.c index 33b82d4015..d1074073fb 100644 --- a/components/esp_hw_support/rtc_wdt.c +++ b/components/esp_hw_support/rtc_wdt.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/efuse_periph.h" #include "rtc_wdt.h" #include "soc/rtc.h" #include "hal/efuse_ll.h" diff --git a/components/esp_psram/CMakeLists.txt b/components/esp_psram/CMakeLists.txt index 0fe5d6a60c..8fafa87a04 100644 --- a/components/esp_psram/CMakeLists.txt +++ b/components/esp_psram/CMakeLists.txt @@ -2,7 +2,7 @@ idf_build_get_property(target IDF_TARGET) set(includes "include") -set(priv_requires efuse heap spi_flash) +set(priv_requires heap spi_flash) if(${target} STREQUAL "esp32") list(APPEND priv_requires bootloader_support) # [refactor-todo]: requires "driver" for `spicommon_periph_claim` diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index 160d009515..e74ef58584 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -15,7 +15,6 @@ #include "esp_err.h" #include "esp_types.h" #include "esp_log.h" -#include "esp_efuse.h" #include "../esp_psram_impl.h" #include "esp32/rom/spi_flash.h" #include "esp32/rom/cache.h" @@ -823,7 +822,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra { psram_cache_speed_t mode = PSRAM_SPEED; psram_io_t psram_io={0}; - uint32_t pkg_ver = esp_efuse_get_pkg_ver(); + uint32_t pkg_ver = efuse_ll_get_chip_ver_pkg(); if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) { ESP_EARLY_LOGI(TAG, "This chip is ESP32-D2WD"); rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config(); diff --git a/components/hal/esp32c2/include/hal/efuse_ll.h b/components/hal/esp32c2/include/hal/efuse_ll.h index 9847ab3f85..fe3a0d8217 100644 --- a/components/hal/esp32c2/include/hal/efuse_ll.h +++ b/components/hal/esp32c2/include/hal/efuse_ll.h @@ -82,6 +82,72 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return EFUSE.rd_blk2_data1.pkg_version; } +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) +{ + // OCODE, EFUSE_BLK2, 62, 7, OCode + return (EFUSE.rd_blk2_data2.ocode_hi << 2) + EFUSE.rd_blk2_data1.ocode_low; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void) +{ + // DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, BLOCK2 digital dbias when hvt + return EFUSE.rd_blk2_data3.dig_dbias_hvt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_slp_dbias2(void) +{ + // DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, BLOCK2 DIG_LDO_DBG0_DBIAS2 + return EFUSE.rd_blk2_data3.dig_ldo_slp_dbias2; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_slp_dbias26(void) +{ + // DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, BLOCK2 DIG_LDO_DBG0_DBIAS26 + return EFUSE.rd_blk2_data3.dig_ldo_slp_dbias26; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_dbias26(void) +{ + // DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26 + return (EFUSE.rd_blk2_data4.dig_ldo_act_dbias26_hi << 3) + EFUSE.rd_blk2_data3.dig_ldo_act_dbias26_low; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_ldo_act_stepd10(void) +{ + // DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, BLOCK2 DIG_LDO_ACT_STEPD10 + return EFUSE.rd_blk2_data4.dig_ldo_act_stepd10; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_slp_dbias13(void) +{ + // RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, BLOCK2 DIG_LDO_SLP_DBIAS13 + return EFUSE.rd_blk2_data4.rtc_ldo_slp_dbias13; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_slp_dbias29(void) +{ + // RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, BLOCK2 DIG_LDO_SLP_DBIAS29 + return EFUSE.rd_blk2_data4.rtc_ldo_slp_dbias29; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_slp_dbias31(void) +{ + // RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, BLOCK2 DIG_LDO_SLP_DBIAS31 + return EFUSE.rd_blk2_data4.rtc_ldo_slp_dbias31; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias31(void) +{ + // RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31 + return (EFUSE.rd_blk2_data5.rtc_ldo_act_dbias31_hi << 3) + EFUSE.rd_blk2_data4.rtc_ldo_act_dbias31_low; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_rtc_ldo_act_dbias13(void) +{ + // RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, BLOCK2 DIG_LDO_ACT_DBIAS13 + return EFUSE.rd_blk2_data5.rtc_ldo_act_dbias13; +} + /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) diff --git a/components/hal/esp32c3/include/hal/efuse_ll.h b/components/hal/esp32c3/include/hal/efuse_ll.h index 6274fe7e67..ee1deaf1ea 100644 --- a/components/hal/esp32c3/include/hal/efuse_ll.h +++ b/components/hal/esp32c3/include/hal/efuse_ll.h @@ -87,6 +87,42 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return EFUSE.rd_mac_spi_sys_3.pkg_version; } +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) +{ + // EFUSE_BLK2, 140, 8, ADC OCode + return EFUSE.rd_sys_part1_data4.ocode; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_rtc_ldo(void) +{ + // EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO + return EFUSE.rd_mac_spi_sys_4.k_rtc_ldo; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_dig_ldo(void) +{ + // EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO + return EFUSE.rd_mac_spi_sys_4.k_dig_ldo; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20(void) +{ + // EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20 + return EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void) +{ + // EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 + return (EFUSE.rd_mac_spi_sys_5.v_dig_dbias20_hi << 3) + EFUSE.rd_mac_spi_sys_4.v_dig_dbias20_low; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void) +{ + // EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt + return EFUSE.rd_mac_spi_sys_5.dig_dbias_hvt; +} + /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) diff --git a/components/hal/esp32s2/include/hal/efuse_ll.h b/components/hal/esp32s2/include/hal/efuse_ll.h index 1d67e4f126..147bde79bf 100644 --- a/components/hal/esp32s2/include/hal/efuse_ll.h +++ b/components/hal/esp32s2/include/hal/efuse_ll.h @@ -112,6 +112,14 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(vo return EFUSE.rd_repeat_data0.sdio_drefh; } +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) +{ + // OCODE1, BLOCK2, 128, 4, (#4 reg, pos 0) + // OCODE2, BLOCK2, 144, 3, (#4 reg, pos 16) + // OCODE = (ocode2 << 4) + ocode1 + return (EFUSE.rd_sys_data4.ocode_hi << 4) + EFUSE.rd_sys_data4.ocode_low; +} + /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) diff --git a/components/hal/esp32s3/include/hal/efuse_ll.h b/components/hal/esp32s3/include/hal/efuse_ll.h index 07e17f9c3f..7e2b6bb789 100644 --- a/components/hal/esp32s3/include/hal/efuse_ll.h +++ b/components/hal/esp32s3/include/hal/efuse_ll.h @@ -87,6 +87,42 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg( return 0; } +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) +{ + // EFUSE_BLK2, 141, 8, ADC OCode + return EFUSE.rd_sys_part1_data4.ocode; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_rtc_ldo(void) +{ + // EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO + return EFUSE.rd_mac_spi_sys_4.k_rtc_ldo; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_dig_ldo(void) +{ + // EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO + return EFUSE.rd_mac_spi_sys_4.k_dig_ldo; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20(void) +{ + // EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 + return (EFUSE.rd_mac_spi_sys_5.v_rtc_dbias20_hi << 5) + EFUSE.rd_mac_spi_sys_4.v_rtc_dbias20_low; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void) +{ + // EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20 + return EFUSE.rd_mac_spi_sys_5.v_dig_dbias20; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void) +{ + // EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt + return EFUSE.rd_mac_spi_sys_5.dig_dbias_hvt; +} + /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) diff --git a/components/soc/esp32c2/include/soc/efuse_struct.h b/components/soc/esp32c2/include/soc/efuse_struct.h index fb5ecf86d7..c8de3d9991 100644 --- a/components/soc/esp32c2/include/soc/efuse_struct.h +++ b/components/soc/esp32c2/include/soc/efuse_struct.h @@ -342,10 +342,10 @@ typedef union { * Store blk 2 efuse version major. */ uint32_t blk_version_major:2; - /** reserve1 : RO; bitpos: [31:30]; default: 0; - * Store reserve1. + /** ocode_lo : RO; bitpos: [31:30]; + * Store ocode. */ - uint32_t reserve1:2; + uint32_t ocode_low:2; }; uint32_t val; } efuse_rd_blk2_data1_reg_t; @@ -355,10 +355,14 @@ typedef union { */ typedef union { struct { - /** ldo_vol_bias_config_high : RO; bitpos: [26:0]; default: 0; - * Store the bit [3:29] of ido configuration parameters. + /** ocode_hi : RO; bitpos: [4:0]; + * Store ocode. */ - uint32_t ldo_vol_bias_config_high:27; + uint32_t ocode_hi:5; + /** ldo_vol_bias_config_high : RO; bitpos: [26:5]; default: 0; + * ido configuration parameters. + */ + uint32_t ldo_vol_bias_config_high:22; /** pvt_low : RO; bitpos: [31:27]; default: 0; * Store the bit [0:4] of pvt. */ @@ -372,14 +376,11 @@ typedef union { */ typedef union { struct { - /** pvt_high : RO; bitpos: [9:0]; default: 0; - * Store the bit [5:14] of pvt. - */ - uint32_t pvt_high:10; - /** adc_calibration_0 : RO; bitpos: [31:10]; default: 0; - * Store the bit [0:21] of ADC calibration data. - */ - uint32_t adc_calibration_0:22; + uint32_t reserved1:9; + uint32_t dig_dbias_hvt:5; + uint32_t dig_ldo_slp_dbias2:7; + uint32_t dig_ldo_slp_dbias26:8; + uint32_t dig_ldo_act_dbias26_low:3; }; uint32_t val; } efuse_rd_blk2_data3_reg_t; @@ -389,10 +390,12 @@ typedef union { */ typedef union { struct { - /** adc_calibration_1 : RO; bitpos: [31:0]; default: 0; - * Store the bit [22:53] of ADC calibration data. - */ - uint32_t adc_calibration_1:32; + uint32_t dig_ldo_act_dbias26_hi:3; + uint32_t dig_ldo_act_stepd10:4; + uint32_t rtc_ldo_slp_dbias13:7; + uint32_t rtc_ldo_slp_dbias29:9; + uint32_t rtc_ldo_slp_dbias31:6; + uint32_t rtc_ldo_act_dbias31_low:3; }; uint32_t val; } efuse_rd_blk2_data4_reg_t; @@ -402,10 +405,9 @@ typedef union { */ typedef union { struct { - /** adc_calibration_2 : RO; bitpos: [31:0]; default: 0; - * Store the bit [54:85] of ADC calibration data. - */ - uint32_t adc_calibration_2:32; + uint32_t rtc_ldo_act_dbias31_hi:3; + uint32_t rtc_ldo_act_dbias13:8; + uint32_t reserved2:21; }; uint32_t val; } efuse_rd_blk2_data5_reg_t; diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index cb67150035..230064321e 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -192,10 +192,21 @@ typedef volatile struct efuse_dev_s { }; uint32_t val; } rd_mac_spi_sys_3; - uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ union { struct { - uint32_t reserved1: 23; + uint32_t reserved1: 7; + uint32_t k_rtc_ldo: 7; + uint32_t k_dig_ldo: 7; + uint32_t v_rtc_dbias20: 8; + uint32_t v_dig_dbias20_low: 3; + }; + uint32_t val; + } rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ + union { + struct { + uint32_t v_dig_dbias20_hi: 5; + uint32_t dig_dbias_hvt: 5; + uint32_t reserved1: 13; uint32_t wafer_version_minor_high: 1; uint32_t wafer_version_major: 2; uint32_t reserved2: 6; @@ -208,8 +219,10 @@ typedef volatile struct efuse_dev_s { uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/ union { struct { - uint32_t blk_version_major : 2; - uint32_t reserved1: 30; + uint32_t blk_version_major: 2; + uint32_t reserved1: 10; + uint32_t ocode: 8; + uint32_t reserved2: 12; }; uint32_t val; } rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ diff --git a/components/soc/esp32s2/include/soc/efuse_struct.h b/components/soc/esp32s2/include/soc/efuse_struct.h index c2ffcbd2c3..705c47a412 100644 --- a/components/soc/esp32s2/include/soc/efuse_struct.h +++ b/components/soc/esp32s2/include/soc/efuse_struct.h @@ -228,9 +228,11 @@ typedef volatile struct efuse_dev_s { uint32_t rd_sys_data3; /**/ union { struct { - uint32_t reserved1: 4; + uint32_t ocode_low: 4; uint32_t blk_version_minor : 3; - uint32_t reserved2: 25; + uint32_t reserved1: 9; + uint32_t ocode_hi: 3; + uint32_t reserved2: 13; }; uint32_t val; } rd_sys_data4; /**/ diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index 4ad916e67a..78d797a3d1 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -138,13 +138,24 @@ typedef volatile struct efuse_dev_s { }; uint32_t val; } rd_mac_spi_sys_3; - uint32_t rd_mac_spi_sys_4; union { struct { - uint32_t reserved1: 23; - uint32_t wafer_version_minor_high: 1; - uint32_t wafer_version_major: 2; - uint32_t reserved2: 6; + uint32_t reserved1: 13; + uint32_t k_rtc_ldo: 7; + uint32_t k_dig_ldo: 7; + uint32_t v_rtc_dbias20_low: 5; + }; + uint32_t val; + } rd_mac_spi_sys_4; + union { + struct { + uint32_t v_rtc_dbias20_hi: 3; + uint32_t v_dig_dbias20: 8; + uint32_t dig_dbias_hvt: 5; + uint32_t reserved1: 7; + uint32_t wafer_version_minor_high: 1; + uint32_t wafer_version_major: 2; + uint32_t reserved2: 6; }; uint32_t val; } rd_mac_spi_sys_5; @@ -154,8 +165,10 @@ typedef volatile struct efuse_dev_s { uint32_t rd_sys_part1_data3; union { struct { - uint32_t blk_version_major : 2; - uint32_t reserved1: 30; + uint32_t blk_version_major: 2; + uint32_t reserved1: 11; + uint32_t ocode: 8; /*ADC OCode*/ + uint32_t reserved2: 11; }; uint32_t val; } rd_sys_part1_data4;