diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index c0b06e45c9..4b7445ba06 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include "soc/uart_periph.h"
 #include "soc/uart_channel.h"
 #include "soc/io_mux_reg.h"
-#include "soc/gpio_periph.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/rtc.h"
 #include "hal/gpio_ll.h"
@@ -27,9 +26,20 @@
 #include "esp_rom_sys.h"
 #include "esp_rom_caps.h"
 
+static void __attribute__((unused)) release_default_console_io(void)
+{
+    // Default console is UART0 with TX and RX on their IOMUX pins
+    gpio_ll_output_disable(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM);
+    esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(UART_NUM_0, SOC_UART_RX_PIN_IDX), 0);
+}
+
 #ifdef CONFIG_ESP_CONSOLE_NONE
 void bootloader_console_init(void)
 {
+    // Wait for UART FIFO to be empty.
+    esp_rom_output_tx_wait_idle(0);
+    release_default_console_io();
+
     esp_rom_install_channel_putc(1, NULL);
     esp_rom_install_channel_putc(2, NULL);
 }
@@ -60,9 +70,7 @@ void bootloader_console_init(void)
     if (uart_num != 0 ||
             uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM ||
             uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) {
-        // Change default UART pins back to GPIOs
-        gpio_ll_func_sel(&GPIO, UART_NUM_0_RXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO);
-        gpio_ll_func_sel(&GPIO, UART_NUM_0_TXD_DIRECT_GPIO_NUM, PIN_FUNC_GPIO);
+        release_default_console_io();
         // Route GPIO signals to/from pins
         const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX);
         const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX);
@@ -102,6 +110,10 @@ static char s_usb_cdc_buf[ESP_ROM_CDC_ACM_WORK_BUF_MIN];
 
 void bootloader_console_init(void)
 {
+    // Wait for UART FIFO to be empty.
+    esp_rom_output_tx_wait_idle(0);
+    release_default_console_io();
+
 #ifdef CONFIG_IDF_TARGET_ESP32S2
     /* ESP32-S2 specific patch to set the correct serial number in the descriptor.
      * Later chips don't need this.
@@ -121,6 +133,10 @@ void bootloader_console_init(void)
 #ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
 void bootloader_console_init(void)
 {
+    // Wait for UART FIFO to be empty.
+    esp_rom_output_tx_wait_idle(0);
+    release_default_console_io();
+
     esp_rom_output_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM);
 
     /* Switch console channel to avoid output on UART and allow  */
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 81bc60017a..b921f4e1cf 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -98,6 +98,7 @@
 #include "hal/cache_ll.h"
 #include "hal/efuse_ll.h"
 #include "hal/uart_ll.h"
+#include "soc/uart_pins.h"
 #include "hal/cpu_utility_ll.h"
 #include "soc/periph_defs.h"
 #include "esp_cpu.h"
@@ -761,6 +762,13 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
 
     _uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, clock_hz);
 #endif
+    int console_uart_tx_pin = U0TXD_GPIO_NUM;
+    int console_uart_rx_pin = U0RXD_GPIO_NUM;
+#if CONFIG_ESP_CONSOLE_UART_CUSTOM
+    console_uart_tx_pin = (CONFIG_ESP_CONSOLE_UART_TX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_TX_GPIO : U0TXD_GPIO_NUM;
+    console_uart_rx_pin = (CONFIG_ESP_CONSOLE_UART_RX_GPIO >= 0) ? CONFIG_ESP_CONSOLE_UART_RX_GPIO : U0RXD_GPIO_NUM;
+#endif
+    ESP_EARLY_LOGI(TAG, "GPIO %d and %d are used as console UART I/O pins", console_uart_rx_pin, console_uart_tx_pin);
 #endif
 
 #if SOC_DEEP_SLEEP_SUPPORTED