diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c
index 2850d9dfb4..332e436d9d 100644
--- a/components/esp_hw_support/port/pau_regdma.c
+++ b/components/esp_hw_support/port/pau_regdma.c
@@ -15,6 +15,9 @@
 #include "esp_private/esp_pau.h"
 #include "esp_private/periph_ctrl.h"
 
+#define PAU_REGDMA_LINK_WAIT_RETRY_COUNT    (1000)
+#define PAU_REGDMA_LINK_WAIT_READ_INTERNAL  (32)
+
 static __attribute__((unused)) const char *TAG = "pau_regdma";
 
 typedef struct {
@@ -32,6 +35,7 @@ pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void)
     if (pau_hal.dev == NULL) {
         pau_hal.dev = &PAU;
         pau_hal_enable_bus_clock(true);
+        pau_hal_set_regdma_wait_timeout(&pau_hal, PAU_REGDMA_LINK_WAIT_RETRY_COUNT, PAU_REGDMA_LINK_WAIT_READ_INTERNAL);
 #if SOC_PAU_IN_TOP_DOMAIN
         pau_hal_lp_sys_initialize();
 #endif
diff --git a/components/hal/esp32c6/include/hal/pau_ll.h b/components/hal/esp32c6/include/hal/pau_ll.h
index f47c7e9746..3a8878c83e 100644
--- a/components/hal/esp32c6/include/hal/pau_ll.h
+++ b/components/hal/esp32c6/include/hal/pau_ll.h
@@ -157,6 +157,16 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
     dev->int_clr.error_int_clr = 1;
 }
 
+static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
+{
+    dev->regdma_bkp_conf.link_tout_thres = count;
+}
+
+static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
+{
+    dev->regdma_bkp_conf.read_interval = interval;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c6/pau_hal.c b/components/hal/esp32c6/pau_hal.c
index cc39004bae..8634d6173a 100644
--- a/components/hal/esp32c6/pau_hal.c
+++ b/components/hal/esp32c6/pau_hal.c
@@ -54,3 +54,10 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
     pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
 }
+
+void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
+{
+    HAL_ASSERT(count > 0 && interval > 0);
+    pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
+    pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
+}
diff --git a/components/hal/esp32h2/include/hal/pau_ll.h b/components/hal/esp32h2/include/hal/pau_ll.h
index d0c4d1bcef..7ce03f6d7b 100644
--- a/components/hal/esp32h2/include/hal/pau_ll.h
+++ b/components/hal/esp32h2/include/hal/pau_ll.h
@@ -127,6 +127,16 @@ static inline __attribute__((always_inline)) void pau_ll_clear_regdma_backup_err
     dev->int_clr.error_int_clr = 1;
 }
 
+static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
+{
+    dev->regdma_bkp_conf.link_tout_thres = count;
+}
+
+static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
+{
+    dev->regdma_bkp_conf.read_interval = interval;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32h2/pau_hal.c b/components/hal/esp32h2/pau_hal.c
index 6eeaaef002..0cbc01ca80 100644
--- a/components/hal/esp32h2/pau_hal.c
+++ b/components/hal/esp32h2/pau_hal.c
@@ -41,3 +41,10 @@ void IRAM_ATTR pau_hal_regdma_clock_configure(pau_hal_context_t *hal, bool enabl
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.regdma_conf, regdma_rst_en, !enable);
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.regdma_conf, regdma_clk_en, enable);
 }
+
+void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
+{
+    HAL_ASSERT(count > 0 && interval > 0);
+    pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
+    pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
+}
diff --git a/components/hal/esp32p4/include/hal/pau_ll.h b/components/hal/esp32p4/include/hal/pau_ll.h
index 0753735eed..edd8007e84 100644
--- a/components/hal/esp32p4/include/hal/pau_ll.h
+++ b/components/hal/esp32p4/include/hal/pau_ll.h
@@ -158,6 +158,16 @@ static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
     dev->int_clr.error_int_clr = 1;
 }
 
+static inline void pau_ll_set_regdma_link_wait_retry_count(pau_dev_t *dev, int count)
+{
+    dev->regdma_bkp_conf.link_tout_thres = count;
+}
+
+static inline void pau_ll_set_regdma_link_wait_read_interval(pau_dev_t *dev, int interval)
+{
+    dev->regdma_bkp_conf.read_interval = interval;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/pau_hal.c b/components/hal/esp32p4/pau_hal.c
index 2852d99a92..fd13b18d53 100644
--- a/components/hal/esp32p4/pau_hal.c
+++ b/components/hal/esp32p4/pau_hal.c
@@ -63,6 +63,13 @@ void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
     pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
 }
 
+void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval)
+{
+    HAL_ASSERT(count > 0 && interval > 0);
+    pau_ll_set_regdma_link_wait_retry_count(hal->dev, count);
+    pau_ll_set_regdma_link_wait_read_interval(hal->dev, interval);
+}
+
 #if SOC_PAU_IN_TOP_DOMAIN
 void IRAM_ATTR pau_hal_lp_sys_initialize(void)
 {
diff --git a/components/hal/include/hal/pau_hal.h b/components/hal/include/hal/pau_hal.h
index e95ed32698..7ed90918fa 100644
--- a/components/hal/include/hal/pau_hal.h
+++ b/components/hal/include/hal/pau_hal.h
@@ -118,6 +118,15 @@ void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal);
 void pau_hal_regdma_clock_configure(pau_hal_context_t *hal, bool enable);
 #endif
 
+/**
+ * @brief Set regdma link wait timeout, include wait retry count and register read interval
+ *
+ * @param hal           regdma hal context
+ * @param count         the maximum number of regdma wait retry count
+ * @param interval      the interval of regdma wait link to read register
+ */
+void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval);
+
 #if SOC_PAU_IN_TOP_DOMAIN
 /**
  * If PAU is in TOP power domain, configuration will be lost after sleep, it is necessary