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docs: Implement comments

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Zhang Shuxian
2024-07-02 10:53:36 +08:00
parent 6cfd5967e0
commit 08eecfee22
10 changed files with 66 additions and 47 deletions
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docs/en/api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
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@@ -19,7 +19,7 @@ The SPI0/1 bus is shared between the instruction & data cache (for firmware exec
.. only:: SOC_SPIRAM_XIP_SUPPORTED
On {IDF_TARGET_NAME}, the config options :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` (disabled by default) and :ref:`CONFIG_SPIRAM_RODATA` (disabled by default) allow the cache to read/write PSRAM concurrently with SPI1 operations. See :ref:`xip_from_psram` for more details.
On {IDF_TARGET_NAME}, the config options :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` (disabled by default) allows the cache to read/write PSRAM concurrently with SPI1 operations. See :ref:`xip_from_psram` for more details.
If these options are disabled, the caches must be disabled while reading/writing/erasing operations. There are some constraints using driver on the SPI1 bus, see :ref:`impact_disabled_cache`. These constraints will cause more IRAM/DRAM usages.
@@ -40,7 +40,7 @@ Under this condition, all CPUs should always execute code and access data from i
.. note::
When :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and :ref:`CONFIG_SPIRAM_RODATA` are both enabled, these APIs will not disable the caches.
When :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM` is enabled, these APIs will not disable the caches.
.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES