diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index b833b50a6e..858634b4b9 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -66,7 +66,9 @@ endif() if(IDF_TARGET STREQUAL "esp32c3") list(APPEND srcs "gdma.c" "spi_slave_hd.c" - "esp32c3/adc.c") + "esp32c3/adc.c" + "esp32c3/adc2_init_cal.c" + "esp32c3/rtc_tempsensor.c") endif() idf_component_register(SRCS "${srcs}" diff --git a/components/driver/adc_common.c b/components/driver/adc_common.c index 0f5809961d..3c2400185d 100644 --- a/components/driver/adc_common.c +++ b/components/driver/adc_common.c @@ -31,7 +31,6 @@ #include "hal/adc_types.h" #include "hal/adc_hal.h" -#if !CONFIG_IDF_TARGET_ESP32C3 #include "hal/dac_hal.h" #include "hal/adc_hal_conf.h" @@ -121,7 +120,7 @@ static esp_pm_lock_handle_t s_adc2_arbiter_lock; ADC Common ---------------------------------------------------------------*/ -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 static uint32_t get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan) { adc_atten_t atten = adc_hal_get_atten(adc_n, chan); @@ -372,7 +371,7 @@ int adc1_get_raw(adc1_channel_t channel) adc1_rtc_mode_acquire(); adc_power_acquire(); -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // Get calibration value before going into critical section uint32_t cal_val = get_calibration_offset(ADC_NUM_1, channel); #endif @@ -382,7 +381,7 @@ int adc1_get_raw(adc1_channel_t channel) adc_hal_hall_disable(); //Disable other peripherals. adc_hal_amp_disable(); //Currently the LNA is not open, close it by default. #endif -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 adc_hal_set_calibration_param(ADC_NUM_1, cal_val); #endif adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC); //Set controller @@ -528,7 +527,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * adc_power_acquire(); //in critical section with whole rtc module -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // Get calibration value before going into critical section uint32_t cal_val = get_calibration_offset(ADC_NUM_2, channel); #endif @@ -544,7 +543,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * adc2_dac_disable(channel); //disable other peripherals #endif adc2_config_width(width_bit); // in critical section with whole rtc module. because the PWDET use the same registers, place it here. -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 adc_hal_set_calibration_param(ADC_NUM_2, cal_val); #endif adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);// set controller @@ -629,5 +628,3 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio) adc_gpio_init(ADC_UNIT_2, ch); return ESP_OK; } - -#endif // !CONFIG_IDF_TARGET_ESP32C3 diff --git a/components/driver/esp32c3/adc.c b/components/driver/esp32c3/adc.c index 5e9748cd82..628bb2f642 100644 --- a/components/driver/esp32c3/adc.c +++ b/components/driver/esp32c3/adc.c @@ -31,6 +31,7 @@ #include "hal/adc_types.h" #include "hal/adc_hal.h" #include "hal/dma_types.h" +#include "esp32c3/esp_efuse_rtc_calib.h" #define ADC_CHECK_RET(fun_ret) ({ \ if (fun_ret != ESP_OK) { \ @@ -89,13 +90,16 @@ typedef struct adc_digi_context_t { RingbufHandle_t ringbuf_hdl; //RX ringbuffer handler bool ringbuf_overflow_flag; //1: ringbuffer overflow bool driver_start_flag; //1: driver is started; 0: driver is stoped + bool use_adc1; //1: ADC unit1 will be used; 0: ADC unit1 won't be used. bool use_adc2; //1: ADC unit2 will be used; 0: ADC unit2 won't be used. This determines whether to acquire sar_adc2_mutex lock or not. + adc_atten_t adc1_atten; //Attenuation for ADC1. On this chip each ADC can only support one attenuation. + adc_atten_t adc2_atten; //Attenuation for ADC2. On this chip each ADC can only support one attenuation. adc_digi_config_t digi_controller_config; //Digital Controller Configuration } adc_digi_context_t; -static const char* ADC_DMA_TAG = "ADC_DMA:"; static adc_digi_context_t *s_adc_digi_ctx = NULL; +static uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan, adc_atten_t atten); /*--------------------------------------------------------------- ADC Continuous Read Mode (via DMA) @@ -238,6 +242,7 @@ static IRAM_ATTR void adc_dma_intr(void *arg) s_adc_digi_ctx->hal_dma_config.desc_cnt = 0; //start next turns of dma operation + adc_hal_digi_dma_multi_descriptor(&s_adc_digi_ctx->hal_dma_config, s_adc_digi_ctx->rx_dma_buf, s_adc_digi_ctx->bytes_between_intr, s_adc_digi_ctx->hal_dma_config.desc_max_num); adc_hal_digi_rxdma_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config); } @@ -264,6 +269,16 @@ esp_err_t adc_digi_start(void) adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); adc_hal_init(); + + if (s_adc_digi_ctx->use_adc1) { + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc1_atten); + adc_hal_set_calibration_param(ADC_NUM_1, cal_val); + } + if (s_adc_digi_ctx->use_adc2) { + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc2_atten); + adc_hal_set_calibration_param(ADC_NUM_2, cal_val); + } + adc_hal_arbiter_config(&config); adc_hal_digi_init(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config); adc_hal_digi_controller_config(&s_adc_digi_ctx->digi_controller_config); @@ -277,11 +292,13 @@ esp_err_t adc_digi_start(void) //enable in suc eof intr adc_hal_digi_ena_intr(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config, IN_SUC_EOF_BIT); - //start DMA - adc_hal_digi_rxdma_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config); + //start ADC adc_hal_digi_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config); + //start DMA + adc_hal_digi_rxdma_start(&s_adc_digi_ctx->hal_dma, &s_adc_digi_ctx->hal_dma_config); + return ESP_OK; } @@ -326,7 +343,7 @@ esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_l data = xRingbufferReceiveUpTo(s_adc_digi_ctx->ringbuf_hdl, &size, ticks_to_wait, length_max); if (!data) { - ESP_LOGW(ADC_DMA_TAG, "No data, increase timeout or reduce conv_num_each_intr"); + ESP_LOGV(ADC_TAG, "No data, increase timeout or reduce conv_num_each_intr"); ret = ESP_ERR_TIMEOUT; *out_length = 0; return ret; @@ -340,6 +357,7 @@ esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_l if (s_adc_digi_ctx->ringbuf_overflow_flag) { ret = ESP_ERR_INVALID_STATE; } + return ret; } @@ -363,6 +381,7 @@ esp_err_t adc_digi_deinitialize(void) s_adc_digi_ctx->ringbuf_hdl = NULL; } + free(s_adc_digi_ctx->rx_dma_buf); free(s_adc_digi_ctx->hal_dma_config.rx_desc); free(s_adc_digi_ctx->digi_controller_config.adc_pattern); free(s_adc_digi_ctx); @@ -382,8 +401,8 @@ static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuat esp_err_t adc1_config_width(adc_bits_width_t width_bit) { - //On ESP32C3, the data width is always 13-bits. - if (width_bit != ADC_WIDTH_BIT_13) { + //On ESP32C3, the data width is always 12-bits. + if (width_bit != ADC_WIDTH_BIT_12) { return ESP_ERR_INVALID_ARG; } @@ -404,40 +423,42 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten) int adc1_get_raw(adc1_channel_t channel) { - int result = 0; + int raw_out = 0; adc_digi_config_t dig_cfg = { .conv_limit_en = 0, .conv_limit_num = 250, - .interval = 40, - .dig_clk.use_apll = 0, - .dig_clk.div_num = 1, - .dig_clk.div_a = 0, - .dig_clk.div_b = 1, + .sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH, }; ADC_DIGI_LOCK_ACQUIRE(); + periph_module_enable(PERIPH_SARADC_MODULE); + + adc_atten_t atten = s_atten1_single[channel]; + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, channel, atten); + adc_hal_set_calibration_param(ADC_NUM_1, cal_val); + adc_hal_digi_controller_config(&dig_cfg); adc_hal_intr_clear(ADC_EVENT_ADC1_DONE); - adc_hal_onetime_channel(ADC_NUM_1, channel); - adc_hal_set_onetime_atten(s_atten1_single[channel]); + adc_hal_set_onetime_atten(atten); - adc_hal_adc1_onetime_sample_enable(true); //Trigger single read. + adc_hal_adc1_onetime_sample_enable(true); adc_hal_onetime_start(&dig_cfg); while (!adc_hal_intr_get_raw(ADC_EVENT_ADC1_DONE)); adc_hal_intr_clear(ADC_EVENT_ADC1_DONE); adc_hal_adc1_onetime_sample_enable(false); - result = adc_hal_adc1_read(); + adc_hal_single_read(ADC_NUM_1, &raw_out); adc_hal_digi_deinit(); + periph_module_disable(PERIPH_SARADC_MODULE); ADC_DIGI_LOCK_RELEASE(); - return result; + return raw_out; } esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) @@ -454,41 +475,46 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten) esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out) { - //On ESP32C3, the data width is always 13-bits. - if (width_bit != ADC_WIDTH_BIT_13) { + //On ESP32C3, the data width is always 12-bits. + if (width_bit != ADC_WIDTH_BIT_12) { return ESP_ERR_INVALID_ARG; } + esp_err_t ret = ESP_OK; adc_digi_config_t dig_cfg = { .conv_limit_en = 0, .conv_limit_num = 250, - .interval = 40, - .dig_clk.use_apll = 0, - .dig_clk.div_num = 1, - .dig_clk.div_a = 0, - .dig_clk.div_b = 1, + .sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH, }; SAC_ADC2_LOCK_ACQUIRE(); ADC_DIGI_LOCK_ACQUIRE(); + periph_module_enable(PERIPH_SARADC_MODULE); + + adc_atten_t atten = s_atten2_single[channel]; + uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten); + adc_hal_set_calibration_param(ADC_NUM_2, cal_val); adc_hal_digi_controller_config(&dig_cfg); adc_hal_intr_clear(ADC_EVENT_ADC2_DONE); - adc_hal_onetime_channel(ADC_NUM_2, channel); - adc_hal_set_onetime_atten(s_atten2_single[channel]); + adc_hal_set_onetime_atten(atten); - adc_hal_adc2_onetime_sample_enable(true); //Trigger single read. + adc_hal_adc2_onetime_sample_enable(true); adc_hal_onetime_start(&dig_cfg); while (!adc_hal_intr_get_raw(ADC_EVENT_ADC2_DONE)); adc_hal_intr_clear(ADC_EVENT_ADC2_DONE); adc_hal_adc2_onetime_sample_enable(false); - *raw_out = adc_hal_adc2_read(); + ret = adc_hal_single_read(ADC_NUM_2, raw_out); + if (ret != ESP_OK) { + return ret; + } adc_hal_digi_deinit(); + periph_module_disable(PERIPH_SARADC_MODULE); ADC_DIGI_LOCK_RELEASE(); SAC_ADC2_LOCK_RELEASE(); @@ -505,20 +531,38 @@ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config) if (!s_adc_digi_ctx) { return ESP_ERR_INVALID_STATE; } + ADC_CHECK(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, "ADC sampling frequency out of range", ESP_ERR_INVALID_ARG); s_adc_digi_ctx->digi_controller_config.conv_limit_en = config->conv_limit_en; s_adc_digi_ctx->digi_controller_config.conv_limit_num = config->conv_limit_num; s_adc_digi_ctx->digi_controller_config.adc_pattern_len = config->adc_pattern_len; - s_adc_digi_ctx->digi_controller_config.interval = config->interval; - s_adc_digi_ctx->digi_controller_config.dig_clk = config-> dig_clk; - s_adc_digi_ctx->digi_controller_config.dma_eof_num = config->dma_eof_num; + s_adc_digi_ctx->digi_controller_config.sample_freq_hz = config->sample_freq_hz; memcpy(s_adc_digi_ctx->digi_controller_config.adc_pattern, config->adc_pattern, config->adc_pattern_len * sizeof(adc_digi_pattern_table_t)); - //See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver + const int atten_uninitialised = 999; + s_adc_digi_ctx->adc1_atten = atten_uninitialised; + s_adc_digi_ctx->adc2_atten = atten_uninitialised; + s_adc_digi_ctx->use_adc1 = 0; s_adc_digi_ctx->use_adc2 = 0; for (int i = 0; i < config->adc_pattern_len; i++) { - if (config->adc_pattern->unit == ADC_NUM_2) { + const adc_digi_pattern_table_t* pat = &config->adc_pattern[i]; + if (pat->unit == ADC_NUM_1) { + s_adc_digi_ctx->use_adc1 = 1; + + if (s_adc_digi_ctx->adc1_atten == atten_uninitialised) { + s_adc_digi_ctx->adc1_atten = pat->atten; + } else if (s_adc_digi_ctx->adc1_atten != pat->atten) { + return ESP_ERR_INVALID_ARG; + } + } else if (pat->unit == ADC_NUM_2) { + //See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver s_adc_digi_ctx->use_adc2 = 1; + + if (s_adc_digi_ctx->adc2_atten == atten_uninitialised) { + s_adc_digi_ctx->adc2_atten = pat->atten; + } else if (s_adc_digi_ctx->adc2_atten != pat->atten) { + return ESP_ERR_INVALID_ARG; + } } } @@ -547,12 +591,12 @@ esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config) * @note For ADC1, Controller access is mutually exclusive. * * @param adc_unit ADC unit. - * @param ctrl ADC controller, Refer to `adc_ll_controller_t`. + * @param ctrl ADC controller, Refer to `adc_controller_t`. * * @return * - ESP_OK Success */ -esp_err_t adc_set_controller(adc_unit_t adc_unit, adc_ll_controller_t ctrl) +esp_err_t adc_set_controller(adc_unit_t adc_unit, adc_controller_t ctrl) { adc_arbiter_t config = {0}; adc_arbiter_t cfg = ADC_ARBITER_CONFIG_DEFAULT(); @@ -611,34 +655,34 @@ esp_err_t adc_digi_reset(void) esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx) { - abort(); // TODO ESP32-C3 IDF-2528 + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_reset(idx); + ADC_EXIT_CRITICAL(); + return ESP_OK; } esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config) { - abort(); // TODO ESP32-C3 IDF-2528 + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_set_factor(idx, config); + ADC_EXIT_CRITICAL(); + return ESP_OK; } esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config) { - abort(); // TODO ESP32-C3 IDF-2528 + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_get_factor(idx, config); + ADC_EXIT_CRITICAL(); + return ESP_OK; } esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable) { - abort(); // TODO ESP32-C3 IDF-2528 -} - -/** - * @brief Get the filtered data of adc digital controller filter. For debug. - * The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API. - * - * @param idx Filter index. - * @return Filtered data. if <0, the read data invalid. - */ -int adc_digi_filter_read_data(adc_digi_filter_idx_t idx) -{ - abort(); // TODO ESP32-C3 IDF-2528 + ADC_ENTER_CRITICAL(); + adc_hal_digi_filter_enable(idx, enable); + ADC_EXIT_CRITICAL(); + return ESP_OK; } /**************************************/ @@ -648,23 +692,16 @@ int adc_digi_filter_read_data(adc_digi_filter_idx_t idx) esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config) { ADC_ENTER_CRITICAL(); - if (idx == ADC_DIGI_MONITOR_IDX0) { - adc_hal_digi_monitor_config(ADC_NUM_1, config); - } else if (idx == ADC_DIGI_MONITOR_IDX1) { - adc_hal_digi_monitor_config(ADC_NUM_2, config); - } + adc_hal_digi_monitor_config(idx, config); ADC_EXIT_CRITICAL(); return ESP_OK; } esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable) { + ADC_ENTER_CRITICAL(); - if (idx == ADC_DIGI_MONITOR_IDX0) { - adc_hal_digi_monitor_enable(ADC_NUM_1, enable); - } else if (idx == ADC_DIGI_MONITOR_IDX1) { - adc_hal_digi_monitor_enable(ADC_NUM_2, enable); - } + adc_hal_digi_monitor_enable(idx, enable); ADC_EXIT_CRITICAL(); return ESP_OK; } @@ -756,3 +793,40 @@ esp_err_t adc_digi_isr_deregister(void) /*--------------------------------------------------------------- RTC controller setting ---------------------------------------------------------------*/ + +static uint16_t s_adc_cali_param[ADC_ATTEN_MAX] = {}; + +//NOTE: according to calibration version, different types of lock may be taken during the process: +// 1. Semaphore when reading efuse +// 2. Lock (Spinlock, or Mutex) if we actually do ADC calibration in the future +//This function shoudn't be called inside critical section or ISR +static uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + const bool no_cal = false; + if (s_adc_cali_param[atten]) { + return (uint32_t)s_adc_cali_param[atten]; + } + + if (no_cal) { + return 0; //indicating failure + } + + // check if we can fetch the values from eFuse. + int version = esp_efuse_rtc_calib_get_ver(); + assert(version == 1); + uint32_t init_code = esp_efuse_rtc_calib_get_init_code(version, atten); + + ESP_LOGD(ADC_TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n, atten, init_code); + s_adc_cali_param[atten] = init_code; + return init_code; +} + +// Internal function to calibrate PWDET for WiFi +esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) +{ + uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten); + ADC_ENTER_CRITICAL(); + adc_hal_set_calibration_param(adc_n, cal_val); + ADC_EXIT_CRITICAL(); + return ESP_OK; +} diff --git a/components/driver/esp32c3/adc2_init_cal.c b/components/driver/esp32c3/adc2_init_cal.c new file mode 100644 index 0000000000..944d8fa46f --- /dev/null +++ b/components/driver/esp32c3/adc2_init_cal.c @@ -0,0 +1,39 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* This file is used to get `adc2_init_code_calibration` executed before the APP when the ADC2 is used by Wi-Fi or other drivers. +The linker will link constructor (adc2_init_code_calibration) only when any sections inside the same file (adc2_cal_include) is used. +Don't put any other code into this file. */ + +#include "adc2_wifi_private.h" +#include "hal/adc_hal.h" +#include "esp_private/adc_cali.h" + +/** + * @brief Set initial code to ADC2 after calibration. ADC2 RTC and ADC2 PWDET controller share the initial code. + * This API be called in before `app_main()`. + */ +static __attribute__((constructor)) void adc2_init_code_calibration(void) +{ + const adc_ll_num_t adc_n = ADC_NUM_2; + const adc_atten_t atten = ADC_ATTEN_DB_11; + const adc_channel_t channel = 0; + adc_cal_offset(adc_n, channel, atten); +} + +/** Don't call `adc2_cal_include` in user code. */ +void adc2_cal_include(void) +{ + /* When this empty function is called, the `adc2_init_code_calibration` constructor will be linked and executed before the app.*/ +} diff --git a/components/driver/esp32c3/include/driver/temp_sensor.h b/components/driver/esp32c3/include/driver/temp_sensor.h new file mode 100644 index 0000000000..2eccefcf0f --- /dev/null +++ b/components/driver/esp32c3/include/driver/temp_sensor.h @@ -0,0 +1,99 @@ +// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + TSENS_DAC_L0 = 0, /*!< offset = -2, measure range: 50℃ ~ 125℃, error < 3℃. */ + TSENS_DAC_L1, /*!< offset = -1, measure range: 20℃ ~ 100℃, error < 2℃. */ + TSENS_DAC_L2, /*!< offset = 0, measure range:-10℃ ~ 80℃, error < 1℃. */ + TSENS_DAC_L3, /*!< offset = 1, measure range:-30℃ ~ 50℃, error < 2℃. */ + TSENS_DAC_L4, /*!< offset = 2, measure range:-40℃ ~ 20℃, error < 3℃. */ + TSENS_DAC_MAX, + TSENS_DAC_DEFAULT = TSENS_DAC_L2, +} temp_sensor_dac_offset_t; + +/** + * @brief Configuration for temperature sensor reading + */ +typedef struct { + temp_sensor_dac_offset_t dac_offset; /*!< The temperature measurement range is configured with a built-in temperature offset DAC. */ + uint8_t clk_div; /*!< Default: 6 */ +} temp_sensor_config_t; + +#define TSENS_CONFIG_DEFAULT() {.dac_offset = TSENS_DAC_L2, \ + .clk_div = 6} + +/** + * @brief Set parameter of temperature sensor. + * @param tsens + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens); + +/** + * @brief Get parameter of temperature sensor. + * @param tsens + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens); + +/** + * @brief Start temperature sensor measure. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG + */ +esp_err_t temp_sensor_start(void); + +/** + * @brief Stop temperature sensor measure. + * @return + * - ESP_OK Success + */ +esp_err_t temp_sensor_stop(void); + +/** + * @brief Read temperature sensor raw data. + * @param tsens_out Pointer to raw data, Range: 0 ~ 255 + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG `tsens_out` is NULL + * - ESP_ERR_INVALID_STATE temperature sensor dont start + */ +esp_err_t temp_sensor_read_raw(uint32_t *tsens_out); + +/** + * @brief Read temperature sensor data that is converted to degrees Celsius. + * @note Should not be called from interrupt. + * @param celsius The measure output value. + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG ARG is NULL. + * - ESP_ERR_INVALID_STATE The ambient temperature is out of range. + */ +esp_err_t temp_sensor_read_celsius(float *celsius); + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/esp32c3/rtc_tempsensor.c b/components/driver/esp32c3/rtc_tempsensor.c new file mode 100644 index 0000000000..dc3e118f82 --- /dev/null +++ b/components/driver/esp32c3/rtc_tempsensor.c @@ -0,0 +1,133 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" +#include "esp_log.h" +#include "hal/adc_ll.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/apb_saradc_struct.h" +#include "soc/apb_saradc_reg.h" +#include "soc/system_reg.h" +#include "driver/temp_sensor.h" +#include "regi2c_ctrl.h" +#include "esp32c3/rom/ets_sys.h" + +static const char *TAG = "tsens"; + +#define TSENS_CHECK(res, ret_val) ({ \ + if (!(res)) { \ + ESP_LOGE(TAG, "%s:%d (%s)", __FILE__, __LINE__, __FUNCTION__); \ + return (ret_val); \ + } \ +}) +#define TSENS_XPD_WAIT_DEFAULT 0xFF /* Set wait cycle time(8MHz) from power up to reset enable. */ +#define TSENS_ADC_FACTOR (0.4386) +#define TSENS_DAC_FACTOR (27.88) +#define TSENS_SYS_OFFSET (20.52) + +typedef struct { + int index; + int offset; + int set_val; + int range_min; + int range_max; + int error_max; +} tsens_dac_offset_t; + +static const tsens_dac_offset_t dac_offset[TSENS_DAC_MAX] = { + /* DAC Offset reg_val min max error */ + {TSENS_DAC_L0, -2, 5, 50, 125, 3}, + {TSENS_DAC_L1, -1, 7, 20, 100, 2}, + {TSENS_DAC_L2, 0, 15, -10, 80, 1}, + {TSENS_DAC_L3, 1, 11, -30, 50, 2}, + {TSENS_DAC_L4, 2, 10, -40, 20, 3}, +}; + +esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens) +{ + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); + REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset[tsens.dac_offset].set_val); + APB_SARADC.apb_tsens_ctrl.tsens_clk_div = tsens.clk_div; + APB_SARADC.apb_tsens_ctrl2.tsens_xpd_wait = TSENS_XPD_WAIT_DEFAULT; + APB_SARADC.apb_tsens_ctrl2.tsens_xpd_force = 1; + ESP_LOGD(TAG, "Config temperature range [%d°C ~ %d°C], error < %d°C", + dac_offset[tsens.dac_offset].range_min, + dac_offset[tsens.dac_offset].range_max, + dac_offset[tsens.dac_offset].error_max); + return ESP_OK; +} + +esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens) +{ + TSENS_CHECK(tsens != NULL, ESP_ERR_INVALID_ARG); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD); + SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU); + tsens->dac_offset = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC); + for (int i = TSENS_DAC_L0; i < TSENS_DAC_MAX; i++) { + if (tsens->dac_offset == dac_offset[i].set_val) { + tsens->dac_offset = dac_offset[i].index; + break; + } + } + tsens->clk_div = APB_SARADC.apb_tsens_ctrl.tsens_clk_div; + return ESP_OK; +} + +esp_err_t temp_sensor_start(void) +{ + REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); + APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = 1; + APB_SARADC.apb_tsens_ctrl.tsens_pu = 1; + return ESP_OK; +} + +esp_err_t temp_sensor_stop(void) +{ + APB_SARADC.apb_tsens_ctrl.tsens_pu = 0; + APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = 0; + return ESP_OK; +} + +esp_err_t temp_sensor_read_raw(uint32_t *tsens_out) +{ + TSENS_CHECK(tsens_out != NULL, ESP_ERR_INVALID_ARG); + *tsens_out = APB_SARADC.apb_tsens_ctrl.tsens_out; + return ESP_OK; +} + +esp_err_t temp_sensor_read_celsius(float *celsius) +{ + TSENS_CHECK(celsius != NULL, ESP_ERR_INVALID_ARG); + temp_sensor_config_t tsens; + uint32_t tsens_out = 0; + esp_err_t ret = temp_sensor_get_config(&tsens); + if (ret == ESP_OK) { + ret = temp_sensor_read_raw(&tsens_out); + printf("tsens_out %d\r\n", tsens_out); + TSENS_CHECK(ret == ESP_OK, ret); + const tsens_dac_offset_t *dac = &dac_offset[tsens.dac_offset]; + *celsius = (TSENS_ADC_FACTOR * (float)tsens_out - TSENS_DAC_FACTOR * dac->offset - TSENS_SYS_OFFSET); + if (*celsius < dac->range_min || *celsius > dac->range_max) { + ESP_LOGW(TAG, "Exceeding the temperature range!"); + ret = ESP_ERR_INVALID_STATE; + } + } + return ret; +} diff --git a/components/driver/esp32s2/adc2_init_cal.c b/components/driver/esp32s2/adc2_init_cal.c index 1968cfd49e..944d8fa46f 100644 --- a/components/driver/esp32s2/adc2_init_cal.c +++ b/components/driver/esp32s2/adc2_init_cal.c @@ -18,6 +18,7 @@ Don't put any other code into this file. */ #include "adc2_wifi_private.h" #include "hal/adc_hal.h" +#include "esp_private/adc_cali.h" /** * @brief Set initial code to ADC2 after calibration. ADC2 RTC and ADC2 PWDET controller share the initial code. @@ -28,7 +29,6 @@ static __attribute__((constructor)) void adc2_init_code_calibration(void) const adc_ll_num_t adc_n = ADC_NUM_2; const adc_atten_t atten = ADC_ATTEN_DB_11; const adc_channel_t channel = 0; - extern esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten); adc_cal_offset(adc_n, channel, atten); } diff --git a/components/driver/include/driver/adc_common.h b/components/driver/include/driver/adc_common.h index cbdd377b66..52b7d60c38 100644 --- a/components/driver/include/driver/adc_common.h +++ b/components/driver/include/driver/adc_common.h @@ -17,6 +17,7 @@ #include #include #include "esp_err.h" +#include "sdkconfig.h" #include "driver/gpio.h" #include "hal/adc_types.h" @@ -97,6 +98,13 @@ typedef enum { #define ADC_ATTEN_2_5db ADC_ATTEN_DB_2_5 #define ADC_ATTEN_6db ADC_ATTEN_DB_6 #define ADC_ATTEN_11db ADC_ATTEN_DB_11 + +/** + * The default (max) bit width of the ADC of current version. You can also get the maximum bitwidth + * by `SOC_ADC_MAX_BITWIDTH` defined in soc_caps.h. + */ +#define ADC_WIDTH_BIT_DEFAULT (ADC_WIDTH_MAX-1) + //this definitions are only for being back-compatible #define ADC_WIDTH_9Bit ADC_WIDTH_BIT_9 #define ADC_WIDTH_10Bit ADC_WIDTH_BIT_10 @@ -469,6 +477,7 @@ esp_err_t adc_digi_deinit(void); * * @return * - ESP_ERR_INVALID_STATE Driver state is invalid. + * - ESP_ERR_INVALID_ARG If the combination of arguments is invalid. * - ESP_OK On success */ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config); diff --git a/components/driver/include/esp_private/adc_cali.h b/components/driver/include/esp_private/adc_cali.h new file mode 100644 index 0000000000..ab577a3121 --- /dev/null +++ b/components/driver/include/esp_private/adc_cali.h @@ -0,0 +1,41 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Internal header for calibration, don't use in app + +#include "sdkconfig.h" +#include "esp_err.h" +#include "hal/adc_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !CONFIG_IDF_TARGET_ESP32 + +/** + * @brief Calibrate the offset of ADC. (Based on the pre-stored efuse or actual calibration) + * + * @param adc_n ADC unit to calibrate + * @param channel Target channel if really do calibration + * @param atten Attenuation to use + * @return Always ESP_OK + */ +extern esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten); + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/driver/rtc_module.c b/components/driver/rtc_module.c index f19d2b6899..56d5b40751 100644 --- a/components/driver/rtc_module.c +++ b/components/driver/rtc_module.c @@ -18,7 +18,6 @@ #include "esp_types.h" #include "esp_log.h" #include "soc/rtc_periph.h" -#include "soc/sens_periph.h" #include "soc/syscon_periph.h" #include "soc/rtc.h" #include "soc/periph_defs.h" diff --git a/components/driver/test/test_adc_dma.c b/components/driver/test/test_adc_dma.c new file mode 100644 index 0000000000..d9504cd6d4 --- /dev/null +++ b/components/driver/test/test_adc_dma.c @@ -0,0 +1,272 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include "test_utils.h" + +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3) +//API only supported for C3 now. + +#include "driver/adc.h" +#include "esp_adc_cal.h" +#include "esp_log.h" + +#define TEST_COUNT 4096 +#define MAX_ARRAY_SIZE 4096 +#define TEST_ATTEN ADC_ATTEN_MAX //Set to ADC_ATTEN_*db to test a single attenuation only + +static int s_adc_count[MAX_ARRAY_SIZE]={}; +static int s_adc_offset = -1; + +static int insert_point(uint32_t value) +{ + const bool fixed_size = true; + + if (s_adc_offset < 0) { + if (fixed_size) { + TEST_ASSERT_GREATER_OR_EQUAL(4096, MAX_ARRAY_SIZE); + s_adc_offset = 0; //Fixed to 0 because the array can hold all the data in 12 bits + } else { + s_adc_offset = MAX((int)value - MAX_ARRAY_SIZE/2, 0); + } + } + + if (!fixed_size && (value < s_adc_offset || value >= s_adc_offset + MAX_ARRAY_SIZE)) { + TEST_ASSERT_GREATER_OR_EQUAL(s_adc_offset, value); + TEST_ASSERT_LESS_THAN(s_adc_offset + MAX_ARRAY_SIZE, value); + } + + s_adc_count[value - s_adc_offset] ++; + return value - s_adc_offset; +} + +static void reset_array(void) +{ + memset(s_adc_count, 0, sizeof(s_adc_count)); + s_adc_offset = -1; +} + +static uint32_t get_average(void) +{ + uint32_t sum = 0; + int count = 0; + for (int i = 0; i < MAX_ARRAY_SIZE; i++) { + sum += s_adc_count[i] * (s_adc_offset+i); + count += s_adc_count[i]; + } + return sum/count; +} + +static void print_summary(bool figure) +{ + const int MAX_WIDTH=20; + int max_count = 0; + int start = -1; + int end = -1; + uint32_t sum = 0; + int count = 0; + for (int i = 0; i < MAX_ARRAY_SIZE; i++) { + if (s_adc_count[i] > max_count) { + max_count = s_adc_count[i]; + } + if (s_adc_count[i] > 0 && start < 0) { + start = i; + } + if (s_adc_count[i] > 0) { + end = i; + } + count += s_adc_count[i]; + sum += s_adc_count[i] * (s_adc_offset+i); + } + + if (figure) { + for (int i = start; i <= end; i++) { + printf("%4d ", i+s_adc_offset); + int count = s_adc_count[i] * MAX_WIDTH / max_count; + for (int j = 0; j < count; j++) { + putchar('|'); + } + printf(" %d\n", s_adc_count[i]); + } + } + float average = (float)sum/count; + + float variation_square = 0; + for (int i = start; i <= end; i ++) { + if (s_adc_count[i] == 0) { + continue; + } + float delta = i + s_adc_offset - average; + variation_square += (delta * delta) * s_adc_count[i]; + } + + printf("%d points.\n", count); + printf("average: %.1f\n", (float)sum/count); + printf("std: %.2f\n", sqrt(variation_square/count)); +} + +static void continuous_adc_init(uint16_t adc1_chan_mask, uint16_t adc2_chan_mask, adc_channel_t *channel, uint8_t channel_num, adc_atten_t atten) +{ + adc_digi_init_config_t adc_dma_config = { + .max_store_buf_size = TEST_COUNT*2, + .conv_num_each_intr = 128, + .dma_chan = SOC_GDMA_ADC_DMA_CHANNEL, + .adc1_chan_mask = adc1_chan_mask, + .adc2_chan_mask = adc2_chan_mask, + }; + TEST_ESP_OK(adc_digi_initialize(&adc_dma_config)); + + adc_digi_pattern_table_t adc_pattern[10] = {0}; + adc_digi_config_t dig_cfg = { + .conv_limit_en = 0, + .conv_limit_num = 250, + .sample_freq_hz = 83333, + }; + + dig_cfg.adc_pattern_len = channel_num; + for (int i = 0; i < channel_num; i++) { + uint8_t unit = ((channel[i] >> 3) & 0x1); + uint8_t ch = channel[i] & 0x7; + adc_pattern[i].atten = atten; + adc_pattern[i].channel = ch; + adc_pattern[i].unit = unit; + } + dig_cfg.adc_pattern = adc_pattern; + TEST_ESP_OK(adc_digi_controller_config(&dig_cfg)); +} + +TEST_CASE("test_adc_dma", "[adc][ignore][manual]") +{ + uint16_t adc1_chan_mask = BIT(2); + uint16_t adc2_chan_mask = 0; + adc_channel_t channel[1] = {ADC1_CHANNEL_2}; + adc_atten_t target_atten = TEST_ATTEN; + + const int output_data_size = sizeof(adc_digi_output_data_t); + + int buffer_size = TEST_COUNT*output_data_size; + uint8_t* read_buf = malloc(buffer_size); + TEST_ASSERT_NOT_NULL(read_buf); + + adc_atten_t atten; + bool print_figure; + if (target_atten == ADC_ATTEN_MAX) { + atten = ADC_ATTEN_DB_0; + target_atten = ADC_ATTEN_DB_11; + print_figure = false; + } else { + atten = target_atten; + print_figure = true; + } + + while (1) { + ESP_LOGI("TEST_ADC", "Test with atten: %d", atten); + memset(read_buf, 0xce, buffer_size); + + esp_adc_cal_characteristics_t chan1_char = {}; + esp_adc_cal_value_t cal_ret = esp_adc_cal_characterize(ADC_UNIT_1, atten, ADC_WIDTH_12Bit, 0, &chan1_char); + TEST_ASSERT(cal_ret == ESP_ADC_CAL_VAL_EFUSE_TP); + + continuous_adc_init(adc1_chan_mask, adc2_chan_mask, channel, sizeof(channel) / sizeof(adc_channel_t), atten); + adc_digi_start(); + + int remain_count = TEST_COUNT; + while (remain_count) { + int already_got = TEST_COUNT - remain_count; + uint32_t ret_num; + TEST_ESP_OK(adc_digi_read_bytes(read_buf + already_got*output_data_size, + remain_count*output_data_size, &ret_num, ADC_MAX_DELAY)); + + TEST_ASSERT((ret_num % output_data_size) == 0); + remain_count -= ret_num / output_data_size; + } + + adc_digi_output_data_t *p = (void*)read_buf; + reset_array(); + for (int i = 0; i < TEST_COUNT; i++) { + insert_point(p[i].type2.data); + } + + print_summary(print_figure); + + uint32_t raw = get_average(); + uint32_t voltage_mv = esp_adc_cal_raw_to_voltage(raw, &chan1_char); + printf("Voltage = %d mV\n", voltage_mv); + + adc_digi_stop(); + TEST_ESP_OK(adc_digi_deinitialize()); + + if (atten == target_atten) { + break; + } + + atten++; + } + + free(read_buf); +} + +TEST_CASE("test_adc_single", "[adc][ignore][manual]") +{ + adc_atten_t target_atten = TEST_ATTEN; + adc_atten_t atten; + bool print_figure; + if (target_atten == ADC_ATTEN_MAX) { + atten = ADC_ATTEN_DB_0; + target_atten = ADC_ATTEN_DB_11; + print_figure = false; + } else { + atten = target_atten; + print_figure = true; + } + + adc1_config_width(ADC_WIDTH_BIT_12); + + + while (1) { + ESP_LOGI("TEST_ADC", "Test with atten: %d", atten); + + adc1_config_channel_atten(ADC1_CHANNEL_2, atten); + + esp_adc_cal_characteristics_t chan1_char = {}; + esp_adc_cal_value_t cal_ret = esp_adc_cal_characterize(ADC_UNIT_1, atten, ADC_WIDTH_12Bit, 0, &chan1_char); + TEST_ASSERT(cal_ret == ESP_ADC_CAL_VAL_EFUSE_TP); + + + const int test_count = TEST_COUNT; + adc1_channel_t channel = ADC1_CHANNEL_2; + while (1) { + + reset_array(); + + for (int i = 0; i < test_count; i++) { + uint32_t raw = adc1_get_raw(channel); + insert_point(raw); + } + print_summary(print_figure); + break; + } + uint32_t raw = get_average(); + uint32_t voltage_mv = esp_adc_cal_raw_to_voltage(raw, &chan1_char); + printf("Voltage = %d mV\n", voltage_mv); + + if (atten == target_atten) { + break; + } + atten++; + } +} + +#endif diff --git a/components/efuse/CMakeLists.txt b/components/efuse/CMakeLists.txt index 48005d8e2d..04d75ed76c 100644 --- a/components/efuse/CMakeLists.txt +++ b/components/efuse/CMakeLists.txt @@ -11,6 +11,9 @@ if(EXISTS "${COMPONENT_DIR}/${target}") if("esp32s2" STREQUAL "${target}") list(APPEND srcs "src/${target}/esp_efuse_rtc_table.c") endif() + if("esp32c3" STREQUAL "${target}") + list(APPEND srcs "src/${target}/esp_efuse_rtc_calib.c") + endif() endif() list(APPEND srcs "src/esp_efuse_api.c" diff --git a/components/efuse/esp32c3/esp_efuse_table.c b/components/efuse/esp32c3/esp_efuse_table.c index 5bdacd2ac2..06fef0781f 100644 --- a/components/efuse/esp32c3/esp_efuse_table.c +++ b/components/efuse/esp32c3/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 2c7ba2aa68a2748d3de9a5d1fed59b9f +// md5_digest_table 96cd6235ddc0947b4a296add3f942acb // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -392,8 +392,48 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, }; -static const esp_efuse_desc_t SYS_DATA_PART1[] = { - {EFUSE_BLK2, 0, 256}, // System configuration, +static const esp_efuse_desc_t BLOCK2_VERSION[] = { + {EFUSE_BLK2, 128, 3}, // Version of Block2, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 131, 9}, // Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 140, 8}, // ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, }; static const esp_efuse_desc_t USER_DATA[] = { @@ -892,8 +932,58 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[] = { - &SYS_DATA_PART1[0], // System configuration +const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { + &BLOCK2_VERSION[0], // Version of Block2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 NULL }; diff --git a/components/efuse/esp32c3/esp_efuse_table.csv b/components/efuse/esp32c3/esp_efuse_table.csv index c69d56137c..0d9076c6b9 100644 --- a/components/efuse/esp32c3/esp_efuse_table.csv +++ b/components/efuse/esp32c3/esp_efuse_table.csv @@ -126,8 +126,21 @@ SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 +# SYS_DATA_PART1 # +####################### + BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of Block2 + TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data + OCODE, EFUSE_BLK2, 140, 8, ADC OCode + ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 + ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 + ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 + ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 + ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 + ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 + ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 + ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 + ################ -SYS_DATA_PART1, EFUSE_BLK2, 0, 256, System configuration USER_DATA, EFUSE_BLK3, 0, 256, User data KEY0, EFUSE_BLK4, 0, 256, Key0 or user data KEY1, EFUSE_BLK5, 0, 256, Key1 or user data diff --git a/components/efuse/esp32c3/include/esp_efuse_table.h b/components/efuse/esp32c3/include/esp_efuse_table.h index df8ba61e73..7d74200a59 100644 --- a/components/efuse/esp32c3/include/esp_efuse_table.h +++ b/components/efuse/esp32c3/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 2c7ba2aa68a2748d3de9a5d1fed59b9f +// md5_digest_table 96cd6235ddc0947b4a296add3f942acb // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -115,7 +115,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; diff --git a/components/efuse/include/esp32c3/esp_efuse_rtc_calib.h b/components/efuse/include/esp32c3/esp_efuse_rtc_calib.h new file mode 100644 index 0000000000..75a0bb397e --- /dev/null +++ b/components/efuse/include/esp32c3/esp_efuse_rtc_calib.h @@ -0,0 +1,53 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at", +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get the RTC calibration efuse version + * + * @return Version of the stored efuse + */ +int esp_efuse_rtc_calib_get_ver(void); + +/** + * @brief Get the init code in the efuse, for the corresponding attenuation. + * + * @param version Version of the stored efuse + * @param atten Attenuation of the init code + * @return The init code stored in efuse + */ +uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten); + +/** + * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. + * + * @param version Version of the stored efuse + * @param atten Attenuation to use + * @param out_digi Output buffer of the digits + * @param out_vol_mv Output of the voltage, in mV + * @return + * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid + * - ESP_OK: if success + */ +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c b/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c new file mode 100644 index 0000000000..7f0460b41e --- /dev/null +++ b/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c @@ -0,0 +1,84 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" + +int esp_efuse_rtc_calib_get_ver(void) +{ + uint32_t result = 0; + esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3); + return result; +} + +uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten) +{ + assert(version == 1); + const esp_efuse_desc_t** init_code_efuse; + assert(atten < 4); + if (atten == 0) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; + } else if (atten == 1) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; + } else if (atten == 2) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; + } else { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; + } + + int init_code_size = esp_efuse_get_field_size(init_code_efuse); + assert(init_code_size == 10); + + uint32_t init_code = 0; + esp_err_t err = esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size); + assert(err == ESP_OK); + return init_code + 1000; // version 1 logic +} + +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) +{ + const esp_efuse_desc_t** cal_vol_efuse; + uint32_t calib_vol_expected_mv; + if (version != 1) { + return ESP_ERR_INVALID_ARG; + } + if (atten >= 4) { + return ESP_ERR_INVALID_ARG; + } + if (atten == 0) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0; + calib_vol_expected_mv = 400; + } else if (atten == 1) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1; + calib_vol_expected_mv = 550; + } else if (atten == 2) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2; + calib_vol_expected_mv = 750; + } else { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3; + calib_vol_expected_mv = 1370; + } + + int cal_vol_size = esp_efuse_get_field_size(cal_vol_efuse); + assert(cal_vol_size == 10); + + uint32_t cal_vol = 0; + esp_err_t err = esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_size) & 0x3FF; + assert(err == ESP_OK); + + *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol); + *out_vol_mv = calib_vol_expected_mv; + return ESP_OK; +} diff --git a/components/efuse/src/esp_efuse_utility.c b/components/efuse/src/esp_efuse_utility.c index 00735bbff0..a6a303f72e 100644 --- a/components/efuse/src/esp_efuse_utility.c +++ b/components/efuse/src/esp_efuse_utility.c @@ -68,7 +68,7 @@ esp_err_t esp_efuse_utility_process(const esp_efuse_desc_t* field[], void* ptr, if ((bits_counter + num_bits) > req_size) { // Limits the length of the field. num_bits = req_size - bits_counter; } - ESP_EARLY_LOGD(TAG, "In EFUSE_BLK%d__DATA%d_REG is used %d bits starting with %d bit", + ESP_LOGD(TAG, "In EFUSE_BLK%d__DATA%d_REG is used %d bits starting with %d bit", (int)field[i]->efuse_block, num_reg, num_bits, start_bit); err = func_proc(num_reg, field[i]->efuse_block, start_bit, num_bits, ptr, &bits_counter); ++i_reg; diff --git a/components/esp32c3/ld/esp32c3.peripherals.ld b/components/esp32c3/ld/esp32c3.peripherals.ld index 4b6eaa39cc..61164a12cd 100644 --- a/components/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/esp32c3/ld/esp32c3.peripherals.ld @@ -7,7 +7,6 @@ PROVIDE ( GPIO = 0x60004000 ); PROVIDE ( SIGMADELTA = 0x60004f00 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); -PROVIDE ( SENS = 0x60008800 ); PROVIDE ( HINF = 0x6000B000 ); PROVIDE ( I2S1 = 0x6002d000 ); PROVIDE ( I2C0 = 0x60013000 ); diff --git a/components/esp32c3/system_api_esp32c3.c b/components/esp32c3/system_api_esp32c3.c index c0b51b8552..703a68e5b0 100644 --- a/components/esp32c3/system_api_esp32c3.c +++ b/components/esp32c3/system_api_esp32c3.c @@ -102,7 +102,10 @@ void IRAM_ATTR esp_restart_noos(void) SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + // Reset dma + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_freq_set_xtal(); diff --git a/components/esp32s3/system_api_esp32s3.c b/components/esp32s3/system_api_esp32s3.c index 5e787fdd90..924da6fd2b 100644 --- a/components/esp32s3/system_api_esp32s3.c +++ b/components/esp32s3/system_api_esp32s3.c @@ -101,6 +101,13 @@ void IRAM_ATTR esp_restart_noos(void) SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST); REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + // Reset dma + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + + SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + // Set CPU back to XTAL source, no PLL, same as hard reset #if !CONFIG_IDF_ENV_FPGA rtc_clk_cpu_freq_set_xtal(); diff --git a/components/esp_adc_cal/CMakeLists.txt b/components/esp_adc_cal/CMakeLists.txt index 771340a460..61d15d185f 100644 --- a/components/esp_adc_cal/CMakeLists.txt +++ b/components/esp_adc_cal/CMakeLists.txt @@ -10,4 +10,8 @@ elseif(${target} STREQUAL "esp32s2") INCLUDE_DIRS "include" REQUIRES driver efuse) +elseif(${target} STREQUAL "esp32c3") + idf_component_register(SRCS "esp_adc_cal_esp32c3.c" + INCLUDE_DIRS "include" + REQUIRES driver efuse) endif() diff --git a/components/esp_adc_cal/component.mk b/components/esp_adc_cal/component.mk index 5c826b74be..b12080ce87 100644 --- a/components/esp_adc_cal/component.mk +++ b/components/esp_adc_cal/component.mk @@ -3,4 +3,4 @@ # COMPONENT_ADD_INCLUDEDIRS := include -COMPONENT_OBJEXCLUDE += esp_adc_cal_esp32s2.o +COMPONENT_OBJEXCLUDE += esp_adc_cal_esp32s2.o esp_adc_cal_esp32c3.o diff --git a/components/esp_adc_cal/esp_adc_cal_esp32c3.c b/components/esp_adc_cal/esp_adc_cal_esp32c3.c new file mode 100644 index 0000000000..f7e4495e03 --- /dev/null +++ b/components/esp_adc_cal/esp_adc_cal_esp32c3.c @@ -0,0 +1,170 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include +#include +#include "esp_types.h" +#include "esp_err.h" +#include "esp_log.h" +#include "driver/adc.h" +#include "hal/adc_ll.h" +#include "esp32c3/esp_efuse_rtc_calib.h" +#include "esp_adc_cal.h" + + +#define ADC_CALIB_CHECK(cond, err_msg, ret) do {\ + if (!(cond)) { \ + ESP_LOGE(LOG_TAG, err_msg); \ + return (ret); \ + } \ + } while(0) + +const static char LOG_TAG[] = "adc_calib"; + + +/* ------------------------ Characterization Constants ---------------------- */ + +// coeff_a and coeff_b are actually floats +// they are scaled to put them into uint32_t so that the headers do not have to be changed +static const int coeff_a_scaling = 65536; +static const int coeff_b_scaling = 1024; +/* -------------------- Characterization Helper Data Types ------------------ */ +typedef struct { + uint32_t voltage; + uint32_t digi; +} adc_calib_data_ver1; + +typedef struct { + char version_num; + adc_unit_t adc_num; + adc_atten_t atten_level; + union { + adc_calib_data_ver1 ver1; + } efuse_data; +} adc_calib_parsed_info; + +static esp_err_t prepare_calib_data_for(int version_num, adc_unit_t adc_num, adc_atten_t atten, adc_calib_parsed_info *parsed_data_storage) +{ + assert(version_num == 1); + esp_err_t ret; + + parsed_data_storage->version_num = version_num; + parsed_data_storage->adc_num = adc_num; + parsed_data_storage->atten_level = atten; + // V1 we don't have calibration data for ADC2, using the efuse data of ADC1 + uint32_t voltage, digi; + ret = esp_efuse_rtc_calib_get_cal_voltage(version_num, atten, &digi, &voltage); + if (ret != ESP_OK) { + return ret; + } + parsed_data_storage->efuse_data.ver1.voltage = voltage; + parsed_data_storage->efuse_data.ver1.digi = digi; + return ret; +} + +/* ----------------------- Characterization Functions ----------------------- */ +/* + * Estimate the (assumed) linear relationship btwn the measured raw value and the voltage + * with the previously done measurement when the chip was manufactured. + */ +static void calculate_characterization_coefficients(const adc_calib_parsed_info *parsed_data, esp_adc_cal_characteristics_t *chars) +{ + ESP_LOGD(LOG_TAG, "Calib V1, Cal Voltage = %d, Digi out = %d\n", parsed_data->efuse_data.ver1.voltage, parsed_data->efuse_data.ver1.digi); + + chars->coeff_a = coeff_a_scaling * parsed_data->efuse_data.ver1.voltage / parsed_data->efuse_data.ver1.digi; + chars->coeff_b = 0; +} + +/* ------------------------- Public API ------------------------------------- */ +esp_err_t esp_adc_cal_check_efuse(esp_adc_cal_value_t source) +{ + if (source != ESP_ADC_CAL_VAL_EFUSE_TP) { + return ESP_ERR_NOT_SUPPORTED; + } + uint8_t adc_encoding_version = esp_efuse_rtc_calib_get_ver(); + if (adc_encoding_version != 1) { + // current version only accepts encoding ver 1. + return ESP_ERR_INVALID_VERSION; + } + return ESP_OK; +} + +esp_adc_cal_value_t esp_adc_cal_characterize(adc_unit_t adc_num, + adc_atten_t atten, + adc_bits_width_t bit_width, + uint32_t default_vref, + esp_adc_cal_characteristics_t *chars) +{ + esp_err_t ret; + adc_calib_parsed_info efuse_parsed_data = {0}; + // Check parameters + ADC_CALIB_CHECK(adc_num == ADC_UNIT_1 || adc_num == ADC_UNIT_2, "Invalid unit num", ESP_ADC_CAL_VAL_NOT_SUPPORTED); + ADC_CALIB_CHECK(chars != NULL, "Invalid characteristic", ESP_ADC_CAL_VAL_NOT_SUPPORTED); + ADC_CALIB_CHECK(bit_width == ADC_WIDTH_BIT_12, "Invalid bit_width", ESP_ADC_CAL_VAL_NOT_SUPPORTED); + ADC_CALIB_CHECK(atten < 4, "Invalid attenuation", ESP_ADC_CAL_VAL_NOT_SUPPORTED); + + int version_num = esp_efuse_rtc_calib_get_ver(); + ADC_CALIB_CHECK(version_num == 1, "No calibration efuse burnt", ESP_ADC_CAL_VAL_NOT_SUPPORTED); + + memset(chars, 0, sizeof(esp_adc_cal_characteristics_t)); + + // make sure adc is calibrated. + ret = prepare_calib_data_for(version_num, adc_num, atten, &efuse_parsed_data); + if (ret != ESP_OK) { + abort(); + } + + calculate_characterization_coefficients(&efuse_parsed_data, chars); + ESP_LOGD(LOG_TAG, "adc%d (atten leven %d) calibration done: A:%d B:%d\n", adc_num, atten, chars->coeff_a, chars->coeff_b); + + // Initialize remaining fields + chars->adc_num = adc_num; + chars->atten = atten; + chars->bit_width = bit_width; + + // in esp32c3 we only use the two point method to calibrate the adc. + return ESP_ADC_CAL_VAL_EFUSE_TP; +} + +uint32_t esp_adc_cal_raw_to_voltage(uint32_t adc_reading, const esp_adc_cal_characteristics_t *chars) +{ + ADC_CALIB_CHECK(chars != NULL, "No characteristic input.", ESP_ERR_INVALID_ARG); + + return adc_reading * chars->coeff_a / coeff_a_scaling + chars->coeff_b / coeff_b_scaling; +} + +esp_err_t esp_adc_cal_get_voltage(adc_channel_t channel, + const esp_adc_cal_characteristics_t *chars, + uint32_t *voltage) +{ + // Check parameters + ADC_CALIB_CHECK(chars != NULL, "No characteristic input.", ESP_ERR_INVALID_ARG); + ADC_CALIB_CHECK(voltage != NULL, "No output buffer.", ESP_ERR_INVALID_ARG); + + int adc_reading; + if (chars->adc_num == ADC_UNIT_1) { + //Check if channel is valid on ADC1 + ADC_CALIB_CHECK((adc1_channel_t)channel < ADC1_CHANNEL_MAX, "Invalid channel", ESP_ERR_INVALID_ARG); + adc_reading = adc1_get_raw(channel); + } else { + //Check if channel is valid on ADC2 + ADC_CALIB_CHECK((adc2_channel_t)channel < ADC2_CHANNEL_MAX, "Invalid channel", ESP_ERR_INVALID_ARG); + if (adc2_get_raw(channel, chars->bit_width, &adc_reading) != ESP_OK) { + return ESP_ERR_TIMEOUT; //Timed out waiting for ADC2 + } + } + *voltage = esp_adc_cal_raw_to_voltage((uint32_t)adc_reading, chars); + return ESP_OK; +} diff --git a/components/esp_adc_cal/include/esp_adc_cal.h b/components/esp_adc_cal/include/esp_adc_cal.h index 5a65b0f37d..b7afb383f6 100644 --- a/components/esp_adc_cal/include/esp_adc_cal.h +++ b/components/esp_adc_cal/include/esp_adc_cal.h @@ -30,7 +30,8 @@ typedef enum { ESP_ADC_CAL_VAL_EFUSE_VREF = 0, /**< Characterization based on reference voltage stored in eFuse*/ ESP_ADC_CAL_VAL_EFUSE_TP = 1, /**< Characterization based on Two Point values stored in eFuse*/ ESP_ADC_CAL_VAL_DEFAULT_VREF = 2, /**< Characterization based on default reference voltage*/ - ESP_ADC_CAL_VAL_MAX + ESP_ADC_CAL_VAL_MAX, + ESP_ADC_CAL_VAL_NOT_SUPPORTED = ESP_ADC_CAL_VAL_MAX, } esp_adc_cal_value_t; /** diff --git a/components/esp_hw_support/port/esp32c3/private_include/regi2c_lp_bias.h b/components/esp_hw_support/port/esp32c3/private_include/regi2c_lp_bias.h index 7cf3b457ce..f89a53f0b4 100644 --- a/components/esp_hw_support/port/esp32c3/private_include/regi2c_lp_bias.h +++ b/components/esp_hw_support/port/esp32c3/private_include/regi2c_lp_bias.h @@ -30,6 +30,18 @@ #define I2C_ULP_IR_RESETB_MSB 0 #define I2C_ULP_IR_RESETB_LSB 0 +#define I2C_ULP_IR_FORCE_XPD_CK 0 +#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 +#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 + +#define I2C_ULP_IR_FORCE_XPD_IPH 0 +#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4 +#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4 + +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6 +#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6 + #define I2C_ULP_O_DONE_FLAG 3 #define I2C_ULP_O_DONE_FLAG_MSB 0 #define I2C_ULP_O_DONE_FLAG_LSB 0 @@ -38,14 +50,10 @@ #define I2C_ULP_BG_O_DONE_FLAG_MSB 3 #define I2C_ULP_BG_O_DONE_FLAG_LSB 3 -#define I2C_ULP_IR_FORCE_XPD_IPH 0 -#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4 -#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4 +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 6 +#define I2C_ULP_IR_FORCE_CODE_LSB 6 -#define I2C_ULP_IR_FORCE_XPD_CK 0 -#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2 -#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2 - -#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0 -#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6 -#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6 +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 diff --git a/components/esp_hw_support/port/esp32c3/regi2c_ctrl.h b/components/esp_hw_support/port/esp32c3/regi2c_ctrl.h index a8a07a8c1b..cec9f76d97 100644 --- a/components/esp_hw_support/port/esp32c3/regi2c_ctrl.h +++ b/components/esp_hw_support/port/esp32c3/regi2c_ctrl.h @@ -43,10 +43,16 @@ extern "C" { #define ANA_CONFIG_REG 0x6000E044 #define ANA_CONFIG_S (8) #define ANA_CONFIG_M (0x3FF) -/* Clear to enable APLL */ -#define I2C_APLL_M (BIT(14)) -/* Clear to enable BBPLL */ -#define I2C_BBPLL_M (BIT(17)) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ +#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */ + + +#define ANA_CONFIG2_REG 0x6000E048 +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) /* ROM functions which read/write internal control bus */ uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 5cd7259bb7..d9b193fb9c 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -24,7 +24,6 @@ #include "esp32c3/rom/gpio.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" -#include "soc/sens_reg.h" #include "soc/efuse_reg.h" #include "soc/syscon_reg.h" #include "soc/system_reg.h" diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c index 0960f6e67b..3c4314a85e 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk_init.c @@ -21,7 +21,6 @@ #include "esp32c3/rom/uart.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" -#include "soc/sens_periph.h" #include "soc/efuse_periph.h" #include "soc/apb_ctrl_reg.h" #include "hal/cpu_hal.h" @@ -56,7 +55,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) /* Enable the internal bus used to configure PLLs */ SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S); - CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_APLL_M | ANA_I2C_BBPLL_M); rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; esp_rom_uart_tx_wait_idle(0); diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 2f09d06c02..f6f952c04b 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -24,9 +24,14 @@ #include "soc/system_reg.h" #include "regi2c_ctrl.h" #include "soc_log.h" +#include "esp_efuse.h" +#include "esp_efuse_table.h" static const char *TAG = "rtc_init"; +static void set_ocode_by_efuse(int calib_version); +static void calibrate_ocode(void); + void rtc_init(rtc_config_t cfg) { REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); @@ -135,54 +140,13 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); } if (cfg.cali_ocode) { - /* - Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration(must close PLL). - Method: - 1. read current cpu config, save in old_config; - 2. switch cpu to xtal because PLL will be closed when o-code calibration; - 3. begin o-code calibration; - 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; - 5. set cpu to old-config. - */ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; - rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_x32k)) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { - cal_clk = RTC_CAL_8MD256; + uint32_t rtc_calib_version = 0; + esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3); + if (rtc_calib_version == 1) { + set_ocode_by_efuse(rtc_calib_version); + } else { + calibrate_ocode(); } - - uint64_t max_delay_time_us = 10000; - uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); - uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); - uint64_t cycle0 = rtc_time_get(); - uint64_t timeout_cycle = cycle0 + max_delay_cycle; - uint64_t cycle1 = 0; - - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - rtc_clk_cpu_freq_set_xtal(); - - - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); - bool odone_flag = 0; - bool bg_odone_flag = 0; - while (1) { - odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); - bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); - cycle1 = rtc_time_get(); - if (odone_flag && bg_odone_flag) { - break; - } - if (cycle1 >= timeout_cycle) { - SOC_LOGW(TAG, "o_code calibration fail\n"); - break; - } - } - rtc_clk_cpu_freq_set_config(&old_config); } } @@ -223,3 +187,65 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) val |= RTC_CNTL_SDIO_PD_EN; REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); } + +static void set_ocode_by_efuse(int calib_version) +{ + assert(calib_version == 1); + // use efuse ocode. + uint32_t ocode; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8); + assert(err == ESP_OK); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); +} + +static void calibrate_ocode(void) +{ + /* + Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL). + Method: + 1. read current cpu config, save in old_config; + 2. switch cpu to xtal because PLL will be closed when o-code calibration; + 3. begin o-code calibration; + 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; + 5. set cpu to old-config. + */ + rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); + rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; + rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_freq == (rtc_slow_freq_x32k)) { + cal_clk = RTC_CAL_32K_XTAL; + } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + cal_clk = RTC_CAL_8MD256; + } + + uint64_t max_delay_time_us = 10000; + uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); + uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); + uint64_t cycle0 = rtc_time_get(); + uint64_t timeout_cycle = cycle0 + max_delay_cycle; + uint64_t cycle1 = 0; + + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + rtc_clk_cpu_freq_set_xtal(); + + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); + bool odone_flag = 0; + bool bg_odone_flag = 0; + while (1) { + odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); + bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); + cycle1 = rtc_time_get(); + if (odone_flag && bg_odone_flag) { + break; + } + if (cycle1 >= timeout_cycle) { + SOC_LOGW(TAG, "o_code calibration fail\n"); + break; + } + } + rtc_clk_cpu_freq_set_config(&old_config); +} diff --git a/components/esp_hw_support/port/esp32s2/private_include/regi2c_ulp.h b/components/esp_hw_support/port/esp32s2/private_include/regi2c_ulp.h index de38328a2c..4be3a499d2 100644 --- a/components/esp_hw_support/port/esp32s2/private_include/regi2c_ulp.h +++ b/components/esp_hw_support/port/esp32s2/private_include/regi2c_ulp.h @@ -38,9 +38,10 @@ #define I2C_ULP_BG_O_DONE_FLAG_MSB 3 #define I2C_ULP_BG_O_DONE_FLAG_LSB 3 -#define I2C_ULP_OCODE_ADDR 6 -#define I2C_ULP_OCODE_ADDR_MSB 7 -#define I2C_ULP_OCODE_ADDR_LSB 0 -#define I2C_ULP_IR_FORCE_CODE_ADDR 5 -#define I2C_ULP_IR_FORCE_CODE_ADDR_MSB 6 -#define I2C_ULP_IR_FORCE_CODE_ADDR_LSB 6 +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 6 +#define I2C_ULP_IR_FORCE_CODE_LSB 6 + +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index dfbff46150..a71251eb61 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -28,6 +28,9 @@ #include "esp_efuse_table.h" static const char *TAG = "rtc_init"; +static void set_ocode_by_efuse(int calib_version); +static void calibrate_ocode(void); + void rtc_init(rtc_config_t cfg) { CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); @@ -152,68 +155,9 @@ void rtc_init(rtc_config_t cfg) uint32_t rtc_calib_version = 0; esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32); if (rtc_calib_version == 2) { - // use efuse ocode. - uint32_t ocode1 = 0; - uint32_t ocode2 = 0; - uint32_t ocode; - esp_efuse_read_block(2, &ocode1, 16*8, 4); - esp_efuse_read_block(2, &ocode2, 18*8, 3); - ocode = (ocode2 << 4) + ocode1; - if (ocode >> 6) { - ocode = 93 - (ocode ^ (1 << 6)); - } else { - ocode = 93 + ocode; - } - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_OCODE_ADDR, ocode); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE_ADDR, 1); + set_ocode_by_efuse(rtc_calib_version); } else { - /* - Bangap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration(must close PLL). - Method: - 1. read current cpu config, save in old_config; - 2. switch cpu to xtal because PLL will be closed when o-code calibration; - 3. begin o-code calibration; - 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; - 5. set cpu to old-config. - */ - rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); - rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; - rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; - rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == (rtc_slow_freq_x32k)) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == rtc_slow_freq_8MD256) { - cal_clk = RTC_CAL_8MD256; - } - - uint64_t max_delay_time_us = 10000; - uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); - uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); - uint64_t cycle0 = rtc_time_get(); - uint64_t timeout_cycle = cycle0 + max_delay_cycle; - uint64_t cycle1 = 0; - - rtc_cpu_freq_config_t old_config; - rtc_clk_cpu_freq_get_config(&old_config); - rtc_clk_cpu_freq_set_xtal(); - - - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); - bool odone_flag = 0; - bool bg_odone_flag = 0; - while(1) { - odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); - bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); - cycle1 = rtc_time_get(); - if (odone_flag && bg_odone_flag) - break; - if (cycle1 >= timeout_cycle) { - SOC_LOGW(TAG, "o_code calibration fail"); - break; - } - } - rtc_clk_cpu_freq_set_config(&old_config); + calibrate_ocode(); } } } @@ -269,3 +213,72 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) val |= RTC_CNTL_SDIO_PD_EN; REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val); } + +static void set_ocode_by_efuse(int calib_version) +{ + assert(calib_version == 2); + // use efuse ocode. + uint32_t ocode1 = 0; + uint32_t ocode2 = 0; + uint32_t ocode; + esp_efuse_read_block(2, &ocode1, 16*8, 4); + esp_efuse_read_block(2, &ocode2, 18*8, 3); + ocode = (ocode2 << 4) + ocode1; + if (ocode >> 6) { + ocode = 93 - (ocode ^ (1 << 6)); + } else { + ocode = 93 + ocode; + } + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); +} + +static void calibrate_ocode(void) +{ + /* + Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL). + Method: + 1. read current cpu config, save in old_config; + 2. switch cpu to xtal because PLL will be closed when o-code calibration; + 3. begin o-code calibration; + 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout; + 5. set cpu to old-config. + */ + rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); + rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; + rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; + rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_freq == (rtc_slow_freq_x32k)) { + cal_clk = RTC_CAL_32K_XTAL; + } else if (slow_clk_freq == rtc_slow_freq_8MD256) { + cal_clk = RTC_CAL_8MD256; + } + + uint64_t max_delay_time_us = 10000; + uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); + uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period); + uint64_t cycle0 = rtc_time_get(); + uint64_t timeout_cycle = cycle0 + max_delay_cycle; + uint64_t cycle1 = 0; + + rtc_cpu_freq_config_t old_config; + rtc_clk_cpu_freq_get_config(&old_config); + rtc_clk_cpu_freq_set_xtal(); + + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); + bool odone_flag = 0; + bool bg_odone_flag = 0; + while(1) { + odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); + bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); + cycle1 = rtc_time_get(); + if (odone_flag && bg_odone_flag) + break; + if (cycle1 >= timeout_cycle) { + SOC_LOGW(TAG, "o_code calibration fail"); + break; + } + } + rtc_clk_cpu_freq_set_config(&old_config); +} diff --git a/components/esp_hw_support/test/test_rtc_clk.c b/components/esp_hw_support/test/test_rtc_clk.c index 8d8acc04b8..9d3d3d4895 100644 --- a/components/esp_hw_support/test/test_rtc_clk.c +++ b/components/esp_hw_support/test/test_rtc_clk.c @@ -1,9 +1,12 @@ #include #include "unity.h" +#include "soc/soc_caps.h" #include "soc/rtc.h" #include "soc/rtc_periph.h" +#if SOC_ADC_SUPPORT_RTC_CTRL #include "soc/sens_periph.h" +#endif #include "soc/gpio_periph.h" #include "hal/gpio_ll.h" #include "driver/rtc_io.h" diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c index d2467a4cf9..2f9d42c589 100644 --- a/components/esp_system/port/soc/esp32c3/clk.c +++ b/components/esp_system/port/soc/esp32c3/clk.c @@ -75,6 +75,11 @@ static const char *TAG = "clk"; { #if !CONFIG_IDF_ENV_FPGA rtc_config_t cfg = RTC_CONFIG_DEFAULT(); + RESET_REASON rst_reas; + rst_reas = rtc_get_reset_reason(0); + if (rst_reas == POWERON_RESET) { + cfg.cali_ocode = 1; + } rtc_init(cfg); assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 68e3cbfac6..b3b5b2305a 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -30,11 +30,11 @@ if(NOT BOOTLOADER_BUILD) "sha_hal.c" "aes_hal.c" "twai_hal.c" - "twai_hal_iram.c") + "twai_hal_iram.c" + "adc_hal.c") if(${target} STREQUAL "esp32") list(APPEND srcs - "adc_hal.c" "dac_hal.c" "mcpwm_hal.c" "pcnt_hal.c" @@ -52,7 +52,6 @@ if(NOT BOOTLOADER_BUILD) if(${target} STREQUAL "esp32s2") list(APPEND srcs - "adc_hal.c" "dac_hal.c" "pcnt_hal.c" "spi_flash_hal_gpspi.c" @@ -70,7 +69,6 @@ if(NOT BOOTLOADER_BUILD) if(${target} STREQUAL "esp32s3") list(APPEND srcs - "adc_hal.c" "dac_hal.c" "gdma_hal.c" "pcnt_hal.c" diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c index 787bc71039..4cb8922a86 100644 --- a/components/hal/adc_hal.c +++ b/components/hal/adc_hal.c @@ -15,7 +15,9 @@ #include "hal/adc_hal.h" #include "hal/adc_hal_conf.h" + #if CONFIG_IDF_TARGET_ESP32C3 +#include "soc/gdma_channel.h" #include "soc/soc.h" #include "esp_rom_sys.h" #endif @@ -37,6 +39,7 @@ void adc_hal_deinit(void) adc_ll_set_power_manage(ADC_POWER_SW_OFF); } +#ifndef CONFIG_IDF_TARGET_ESP32C3 int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value) { adc_ll_rtc_enable_channel(adc_n, channel); @@ -45,6 +48,7 @@ int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value) *value = adc_ll_rtc_get_convert_value(adc_n); return (int)adc_ll_rtc_analysis_raw_data(adc_n, (uint16_t)(*value)); } +#endif #if CONFIG_IDF_TARGET_ESP32C3 //This feature is currently supported on ESP32C3, will be supported on other chips soon @@ -108,6 +112,8 @@ void adc_hal_digi_start(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t adc_ll_digi_dma_enable(); //enable sar adc timer adc_ll_digi_trigger_enable(); + //reset the adc state + adc_ll_digi_reset(); } void adc_hal_digi_stop(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config) @@ -139,7 +145,7 @@ void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config) * This limitation will be removed in hardware future versions. * */ - uint32_t digi_clk = APB_CLK_FREQ / (adc_digi_config->dig_clk.div_num + adc_digi_config->dig_clk.div_a / adc_digi_config->dig_clk.div_b + 1); + uint32_t digi_clk = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1); //Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough. uint32_t delay = (1000 * 1000) / digi_clk + 1; //3 ADC digital controller clock cycle @@ -183,14 +189,17 @@ void adc_hal_set_onetime_atten(adc_atten_t atten) adc_ll_onetime_set_atten(atten); } -uint32_t adc_hal_adc1_read(void) +esp_err_t adc_hal_single_read(adc_ll_num_t unit, int *out_raw) { - return adc_ll_adc1_read(); -} - -uint32_t adc_hal_adc2_read(void) -{ - return adc_ll_adc2_read(); + if (unit == ADC_NUM_1) { + *out_raw = adc_ll_adc1_read(); + } else if (unit == ADC_NUM_2) { + *out_raw = adc_ll_adc2_read(); + if (adc_ll_analysis_raw_data(unit, *out_raw)) { + return ESP_ERR_INVALID_STATE; + } + } + return ESP_OK; } //--------------------INTR------------------------------- diff --git a/components/hal/esp32c3/adc_hal.c b/components/hal/esp32c3/adc_hal.c index b000a6c9d8..105dff6490 100644 --- a/components/hal/esp32c3/adc_hal.c +++ b/components/hal/esp32c3/adc_hal.c @@ -14,8 +14,20 @@ // The HAL layer for ADC (ESP32-C3 specific part) +#include +#include "soc/soc_caps.h" #include "hal/adc_hal.h" #include "hal/adc_types.h" +#include "soc/soc.h" + +//Currently we don't have context for the ADC HAL. So HAL variables are temporarily put here. But +//please don't follow this code. Create a context for your own HAL! + +static bool s_filter_enabled[SOC_ADC_DIGI_FILTER_NUM] = {}; +static adc_digi_filter_t s_filter[SOC_ADC_DIGI_FILTER_NUM] = {}; + +static bool s_monitor_enabled[SOC_ADC_DIGI_MONITOR_NUM] = {}; +static adc_digi_monitor_t s_monitor_config[SOC_ADC_DIGI_MONITOR_NUM] = {}; /*--------------------------------------------------------------- Digital controller setting @@ -33,14 +45,6 @@ void adc_hal_digi_deinit(void) adc_hal_deinit(); } -uint32_t adc_hal_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd, bool force_cal); - -static inline void adc_set_init_code(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) -{ - uint32_t cal_val = adc_hal_calibration(adc_n, channel, atten, true, false); - adc_hal_set_calibration_param(adc_n, cal_val); -} - void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) { //only one pattern table is supported on C3, but LL still needs one argument. @@ -51,9 +55,8 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) if (cfg->adc_pattern_len) { adc_ll_digi_clear_pattern_table(pattern_both); adc_ll_digi_set_pattern_table_len(pattern_both, cfg->adc_pattern_len); - for (int i = 0; i < cfg->adc_pattern_len; i++) { + for (uint32_t i = 0; i < cfg->adc_pattern_len; i++) { adc_ll_digi_set_pattern_table(pattern_both, i, cfg->adc_pattern[i]); - adc_set_init_code(pattern_both, cfg->adc_pattern[i].channel, cfg->adc_pattern[i].atten); } } @@ -65,24 +68,17 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) adc_ll_digi_convert_limit_disable(); } - adc_ll_digi_set_trigger_interval(cfg->interval); - adc_hal_digi_clk_config(&cfg->dig_clk); + //clock + uint32_t interval = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / cfg->sample_freq_hz; + adc_ll_digi_set_trigger_interval(interval); + adc_hal_digi_clk_config(); } -/** - * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. - * Enable clock and select clock source for ADC digital controller. - * Expression: controller_clk = APLL/APB * (div_num + div_b / div_a). - * - * @note ADC and DAC digital controller share the same frequency divider. - * Please set a reasonable frequency division factor to meet the sampling frequency of the ADC and the output frequency of the DAC. - * - * @param clk Refer to ``adc_digi_clk_t``. - */ -void adc_hal_digi_clk_config(const adc_digi_clk_t *clk) +void adc_hal_digi_clk_config(void) { - adc_ll_digi_controller_clk_div(clk->div_num, clk->div_b, clk->div_a); - adc_ll_digi_controller_clk_enable(clk->use_apll); + //Here we set the clock divider factor to make the digital clock to 5M Hz + adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT); + adc_ll_digi_controller_clk_enable(0); } /** @@ -103,17 +99,65 @@ void adc_hal_digi_disable(void) adc_ll_digi_dma_disable(); } -/** - * Config monitor of adc digital controller. - * - * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. - * @param config Refer to `adc_digi_monitor_t`. - */ -void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config) +static void filter_update(adc_digi_filter_idx_t idx) { - adc_ll_digi_monitor_set_mode(adc_n, config->mode); - adc_ll_digi_monitor_set_thres(adc_n, config->threshold); + //ESP32-C3 has no enable bit, the filter will be enabled when the filter channel is configured + if (s_filter_enabled[idx]) { + adc_ll_digi_filter_set_factor(idx, &s_filter[idx]); + } else { + adc_ll_digi_filter_disable(idx); + } +} + +/** + * Set adc digital controller filter factor. + * + * @param idx ADC filter unit. + * @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +void adc_hal_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) +{ + s_filter[idx] = *filter; + filter_update(idx); +} + +/** + * Get adc digital controller filter factor. + * + * @param adc_n ADC unit. + * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + */ +void adc_hal_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) +{ + *filter = s_filter[idx]; +} + +void adc_hal_digi_filter_enable(adc_digi_filter_idx_t filter_idx, bool enable) +{ + s_filter_enabled[filter_idx] = enable; + filter_update(filter_idx); +} + +static void update_monitor(adc_digi_monitor_idx_t idx) +{ + //ESP32-C3 has no enable bit, the monitor will be enabled when the monitor channel is configured + if (s_monitor_enabled[idx]) { + adc_ll_digi_monitor_set_mode(idx, &s_monitor_config[idx]); + } else { + adc_ll_digi_monitor_disable(idx); + } +} + +void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config) +{ + s_monitor_config[idx] = *config; + update_monitor(idx); +} + +void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable) +{ + s_monitor_enabled[mon_idx] = enable; + update_monitor(mon_idx); } /*--------------------------------------------------------------- @@ -136,98 +180,3 @@ void adc_hal_arbiter_config(adc_arbiter_t *config) adc_ll_set_arbiter_work_mode(config->mode); adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri); } - -/*--------------------------------------------------------------- - ADC calibration setting ----------------------------------------------------------------*/ - -#define ADC_HAL_CAL_OFFSET_RANGE (4096) -#define ADC_HAL_CAL_TIMES (10) - -static uint16_t s_adc_cali_param[ADC_NUM_MAX][ADC_ATTEN_MAX] = { {0}, {0} }; - -static uint32_t adc_hal_read_self_cal(adc_ll_num_t adc_n, int channel) -{ - adc_ll_rtc_start_convert(adc_n, channel); - while (adc_ll_rtc_convert_is_done(adc_n) != true); - return (uint32_t)adc_ll_rtc_get_convert_value(adc_n); -} - -uint32_t adc_hal_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd, bool force_cal) -{ - if (!force_cal) { - if (s_adc_cali_param[adc_n][atten]) { - return (uint32_t)s_adc_cali_param[adc_n][atten]; - } - } - - uint32_t code_list[ADC_HAL_CAL_TIMES] = {0}; - uint32_t code_sum = 0; - uint32_t code_h = 0; - uint32_t code_l = 0; - uint32_t chk_code = 0; - uint32_t dout = 0; - - adc_hal_set_power_manage(ADC_POWER_SW_ON); - if (adc_n == ADC_NUM_2) { - adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); - adc_hal_arbiter_config(&config); - } - adc_hal_set_controller(adc_n, ADC_CTRL_RTC); //Set controller - - // adc_hal_arbiter_config(adc_arbiter_t *config) - adc_ll_calibration_prepare(adc_n, channel, internal_gnd); - - /* Enable/disable internal connect GND (for calibration). */ - if (internal_gnd) { - adc_ll_rtc_disable_channel(adc_n, channel); - adc_ll_set_atten(adc_n, 0, atten); // Note: when disable all channel, HW auto select channel0 atten param. - } else { - adc_ll_rtc_enable_channel(adc_n, channel); - adc_ll_set_atten(adc_n, channel, atten); - } - - for (uint8_t rpt = 0 ; rpt < ADC_HAL_CAL_TIMES ; rpt ++) { - code_h = ADC_HAL_CAL_OFFSET_RANGE; - code_l = 0; - chk_code = (code_h + code_l) / 2; - adc_ll_set_calibration_param(adc_n, chk_code); - dout = adc_hal_read_self_cal(adc_n, channel); - while (code_h - code_l > 1) { - if (dout == 0) { - code_h = chk_code; - } else { - code_l = chk_code; - } - chk_code = (code_h + code_l) / 2; - adc_ll_set_calibration_param(adc_n, chk_code); - dout = adc_hal_read_self_cal(adc_n, channel); - if ((code_h - code_l == 1)) { - chk_code += 1; - adc_ll_set_calibration_param(adc_n, chk_code); - dout = adc_hal_read_self_cal(adc_n, channel); - } - } - code_list[rpt] = chk_code; - code_sum += chk_code; - } - code_l = code_list[0]; - code_h = code_list[0]; - for (uint8_t i = 0 ; i < ADC_HAL_CAL_TIMES ; i++) { - if (code_l > code_list[i]) { - code_l = code_list[i]; - } - if (code_h < code_list[i]) { - code_h = code_list[i]; - } - } - chk_code = code_h + code_l; - dout = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4) - ? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) - : (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1; - - adc_ll_set_calibration_param(adc_n, dout); - adc_ll_calibration_finish(adc_n); - s_adc_cali_param[adc_n][atten] = (uint16_t)dout; - return dout; -} diff --git a/components/hal/esp32c3/include/hal/adc_hal.h b/components/hal/esp32c3/include/hal/adc_hal.h index 9055be8868..122d438d3e 100644 --- a/components/hal/esp32c3/include/hal/adc_hal.h +++ b/components/hal/esp32c3/include/hal/adc_hal.h @@ -75,70 +75,62 @@ void adc_hal_digi_disable(void); /** * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. * Enable clock and select clock source for ADC digital controller. - * Expression: controller_clk = APLL/APB * (div_num + div_b / div_a). + * Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1). * * @param clk Refer to `adc_digi_clk_t`. */ -void adc_hal_digi_clk_config(const adc_digi_clk_t *clk); +void adc_hal_digi_clk_config(void); /** * Reset adc digital controller filter. * - * @param adc_n ADC unit. + * @param filter_idx ADC filter unit. */ -#define adc_hal_digi_filter_reset(adc_n) adc_ll_digi_filter_reset(adc_n) +#define adc_hal_digi_filter_reset(filter_idx) adc_ll_digi_filter_reset(filter_idx) /** * Set adc digital controller filter factor. * - * @param adc_n ADC unit. - * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + * @param filter_idx ADC filter unit. + * @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). */ -#define adc_hal_digi_filter_set_factor(adc_n, factor) adc_ll_digi_filter_set_factor(adc_n, factor) +void adc_hal_digi_filter_set_factor(adc_digi_filter_idx_t filter_idx, adc_digi_filter_t *filter); /** * Get adc digital controller filter factor. * - * @param adc_n ADC unit. + * @param filter_idx ADC filter unit. * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). */ -#define adc_hal_digi_filter_get_factor(adc_n, factor) adc_ll_digi_filter_get_factor(adc_n, factor) +void adc_hal_digi_filter_get_factor(adc_digi_filter_idx_t filter_idx, adc_digi_filter_t *filter); /** * Enable/disable adc digital controller filter. * Filtering the ADC data to obtain smooth data at higher sampling rates. * * @note The filter will filter all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. + * @param filter_idx ADC filter unit. + * @param enable True to enable the filter, otherwise disable. */ -#define adc_hal_digi_filter_enable(adc_n, enable) adc_ll_digi_filter_enable(adc_n, enable) - -/** - * Get the filtered data of adc digital controller filter. - * The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API. - * - * @note The filter will filter all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. - * @return Filtered data. - */ -#define adc_hal_digi_filter_read_data(adc_n) adc_ll_digi_filter_read_data(adc_n) +void adc_hal_digi_filter_enable(adc_digi_filter_idx_t filter_idx, bool enable); /** * Config monitor of adc digital controller. * - * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. + * @note If the channel info is not supported, the monitor function will not be enabled. + * @param mon_idx ADC monitor index. * @param config Refer to `adc_digi_monitor_t`. */ -void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config); +void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t mon_idx, adc_digi_monitor_t *config); /** * Enable/disable monitor of adc digital controller. * * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. + * @param mon_idx ADC monitor index. + * @param enable True to enable the monitor, otherwise disable. */ -#define adc_hal_digi_monitor_enable(adc_n, enable) adc_ll_digi_monitor_enable(adc_n, enable) +void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable); /** * Enable interrupt of adc digital controller by bitmask. @@ -197,14 +189,6 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config) */ #define adc_hal_digi_reset() adc_ll_digi_reset() -/*--------------------------------------------------------------- - RTC controller setting ----------------------------------------------------------------*/ -/** - * Reset RTC controller FSM. - */ -#define adc_hal_rtc_reset() adc_ll_rtc_reset() - /*--------------------------------------------------------------- Common setting ---------------------------------------------------------------*/ @@ -226,21 +210,6 @@ void adc_hal_arbiter_config(adc_arbiter_t *config); ADC calibration setting ---------------------------------------------------------------*/ -/** - * Calibrate the ADC using internal connections. - * - * @note Different ADC units and different attenuation options use different calibration data (initial data). - * - * @param adc_n ADC index number. - * @param channel adc channel number. - * @param atten The attenuation for the channel - * @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage. - * false: Use IO external voltage as calibration voltage. - * - * @return - * - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set. - */ -uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd); /** * Set the calibration result (initial data) to ADC. diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h index 4e923babb5..913b59ed35 100644 --- a/components/hal/esp32c3/include/hal/adc_ll.h +++ b/components/hal/esp32c3/include/hal/adc_ll.h @@ -15,20 +15,25 @@ #include #include +#include "regi2c_ctrl.h" +#include "esp_attr.h" + #include "soc/adc_periph.h" #include "hal/adc_types.h" #include "soc/apb_saradc_struct.h" #include "soc/apb_saradc_reg.h" #include "soc/rtc_cntl_struct.h" #include "soc/rtc_cntl_reg.h" -#include "regi2c_ctrl.h" -#include "esp_attr.h" - #ifdef __cplusplus extern "C" { #endif +#define ADC_LL_ADC2_CHANNEL_MAX 1 +#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 +#define ADC_LL_CLKM_DIV_B_DEFAULT 1 +#define ADC_LL_CLKM_DIV_A_DEFAULT 0 + typedef enum { ADC_NUM_1 = 0, /*!< SAR ADC 1 */ ADC_NUM_2 = 1, /*!< SAR ADC 2 */ @@ -55,32 +60,6 @@ typedef enum { } adc_ll_intr_t; FLAG_ATTR(adc_ll_intr_t) -#ifdef _MSC_VER -#pragma pack(push, 1) -#endif /* _MSC_VER */ - -/** - * @brief Analyze whether the obtained raw data is correct. - * ADC2 use arbiter by default. The arbitration result can be judged by the flag bit in the original data. - * - */ -typedef struct { - union { - struct { - uint16_t data: 13; /*! 0), The data is invalid. */ - }; - uint16_t val; - }; -} adc_ll_rtc_output_data_t; - -#ifdef _MSC_VER -#pragma pack(pop) -#endif /* _MSC_VER */ - /** * @brief ADC controller type selection. * @@ -95,7 +74,7 @@ typedef enum { ADC2_CTRL_FORCE_PWDET = 3, /*!> offset)); // clear old data - tab |= ((uint32_t)pattern.val << 18) >> offset; // Fill in the new data + tab &= (~(0xFC0000 >> offset)); // Clear old data + tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back - } /** @@ -237,9 +195,6 @@ static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pa */ static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n) { - /* - * channel 可以配置为0～6， 其中 0～4 代表 ADC1 ， 5 代表 ADC2 ， 6 代表有 EN_TEST 的测试选项，可以采样内部的一些电压信号 - */ APB_SARADC.ctrl.sar_patt_p_clear = 1; APB_SARADC.ctrl.sar_patt_p_clear = 0; } @@ -271,10 +226,11 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) } /** - * Sets the number of interval clock cycles for the digital controller to trigger the measurement. + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. * - * @note The trigger interval should not be less than the sampling time of the SAR ADC. - * @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095. + * @note The trigger interval should not be smaller than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095. */ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) { @@ -303,7 +259,7 @@ static inline void adc_ll_digi_trigger_disable(void) * * @param div_num Division factor. Range: 1 ~ 255. * @param div_b Division factor. Range: 1 ~ 63. - * @param div_a Division factor. Range: 1 ~ 63. + * @param div_a Division factor. Range: 0 ~ 63. */ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a) { @@ -349,18 +305,18 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n) /** * Set adc digital controller filter factor. * - * @param adc_n ADC unit. - * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). + * @note If the channel info is not supported, the filter function will not be enabled. + * @param idx ADC filter unit. + * @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). */ -static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor) +static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) { - adc_channel_t channel = 0; - if (!APB_SARADC.filter_ctrl0.filter_channel0) { - APB_SARADC.filter_ctrl0.filter_channel0 = (adc_n<<4) | channel; - APB_SARADC.filter_ctrl1.filter_factor0 = factor; - } else if (!APB_SARADC.filter_ctrl0.filter_channel1) { - APB_SARADC.filter_ctrl0.filter_channel1 = (adc_n<<4) | channel; - APB_SARADC.filter_ctrl1.filter_factor1 = factor; + if (idx == ADC_DIGI_FILTER_IDX0) { + APB_SARADC.filter_ctrl0.filter_channel0 = (filter->adc_unit << 3) | (filter->channel & 0x7); + APB_SARADC.filter_ctrl1.filter_factor0 = filter->mode; + } else if (idx == ADC_DIGI_FILTER_IDX1) { + APB_SARADC.filter_ctrl0.filter_channel1 = (filter->adc_unit << 3) | (filter->channel & 0x7); + APB_SARADC.filter_ctrl1.filter_factor1 = filter->mode; } } @@ -370,70 +326,71 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi * @param adc_n ADC unit. * @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64). */ -static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor) +static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter) { - abort(); // TODO ESP32-C3 IDF-2528 + if (idx == ADC_DIGI_FILTER_IDX0) { + filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel0 >> 3) & 0x1; + filter->channel = APB_SARADC.filter_ctrl0.filter_channel0 & 0x7; + filter->mode = APB_SARADC.filter_ctrl1.filter_factor0; + } else if (idx == ADC_DIGI_FILTER_IDX1) { + filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel1 >> 3) & 0x1; + filter->channel = APB_SARADC.filter_ctrl0.filter_channel1 & 0x7; + filter->mode = APB_SARADC.filter_ctrl1.filter_factor1; + } } /** - * Enable/disable adc digital controller filter. + * Disable adc digital controller filter. * Filtering the ADC data to obtain smooth data at higher sampling rates. * - * @note The filter will filter all the enabled channel data of the each ADC unit at the same time. + * @note If the channel info is not supported, the filter function will not be enabled. * @param adc_n ADC unit. */ -static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable) +static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx) { - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Get the filtered data of adc digital controller filter. - * The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API. - * - * @note The filter will filter all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. - * @return Filtered data. - */ -static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n) -{ - abort(); // TODO ESP32-C3 IDF-2094 + if (idx == ADC_DIGI_FILTER_IDX0) { + APB_SARADC.filter_ctrl0.filter_channel0 = 0xF; + APB_SARADC.filter_ctrl1.filter_factor0 = 0; + } else if (idx == ADC_DIGI_FILTER_IDX1) { + APB_SARADC.filter_ctrl0.filter_channel1 = 0xF; + APB_SARADC.filter_ctrl1.filter_factor1 = 0; + } } /** * Set monitor mode of adc digital controller. * - * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. + * @note If the channel info is not supported, the monitor function will not be enabled. * @param adc_n ADC unit. * @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt. * false: If ADC_OUT < threshold, Generates monitor interrupt. */ -static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger) +static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg) { - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Set monitor threshold of adc digital controller. - * - * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. - * @param adc_n ADC unit. - * @param threshold Monitor threshold. - */ -static inline void adc_ll_digi_monitor_set_thres(adc_ll_num_t adc_n, uint32_t threshold) -{ - abort(); // TODO ESP32-C3 IDF-2094 + if (idx == ADC_DIGI_MONITOR_IDX0) { + APB_SARADC.thres0_ctrl.thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + APB_SARADC.thres0_ctrl.thres0_high = cfg->h_threshold; + APB_SARADC.thres0_ctrl.thres0_low = cfg->l_threshold; + } else { // ADC_DIGI_MONITOR_IDX1 + APB_SARADC.thres1_ctrl.thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7); + APB_SARADC.thres1_ctrl.thres1_high = cfg->h_threshold; + APB_SARADC.thres1_ctrl.thres1_low = cfg->l_threshold; + } } /** * Enable/disable monitor of adc digital controller. * - * @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time. + * @note If the channel info is not supported, the monitor function will not be enabled. * @param adc_n ADC unit. */ -static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable) +static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx) { - abort(); // TODO ESP32-C3 IDF-2094 + if (idx == ADC_DIGI_MONITOR_IDX0) { + APB_SARADC.thres0_ctrl.thres0_channel = 0xF; + } else { // ADC_DIGI_MONITOR_IDX1 + APB_SARADC.thres1_ctrl.thres1_channel = 0xF; + } } /** @@ -444,7 +401,27 @@ static inline void adc_ll_digi_monitor_enable(adc_ll_num_t adc_n, bool enable) */ static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t intr) { - abort(); // TODO ESP32-C3 IDF-2094 + if (adc_n == ADC_NUM_1) { + if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { + APB_SARADC.int_ena.adc1_done = 1; + } + } else { // adc_n == ADC_NUM_2 + if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { + APB_SARADC.int_ena.adc2_done = 1; + } + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) { + APB_SARADC.int_ena.thres0_high = 1; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) { + APB_SARADC.int_ena.thres0_low = 1; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) { + APB_SARADC.int_ena.thres1_high = 1; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) { + APB_SARADC.int_ena.thres1_low = 1; + } } /** @@ -455,7 +432,27 @@ static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t i */ static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t intr) { - abort(); // TODO ESP32-C3 IDF-2094 + if (adc_n == ADC_NUM_1) { + if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { + APB_SARADC.int_ena.adc1_done = 0; + } + } else { // adc_n == ADC_NUM_2 + if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { + APB_SARADC.int_ena.adc2_done = 0; + } + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) { + APB_SARADC.int_ena.thres0_high = 0; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) { + APB_SARADC.int_ena.thres0_low = 0; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) { + APB_SARADC.int_ena.thres1_high = 0; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) { + APB_SARADC.int_ena.thres1_low = 0; + } } /** @@ -466,7 +463,27 @@ static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t */ static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t intr) { - abort(); // TODO ESP32-C3 IDF-2094 + if (adc_n == ADC_NUM_1) { + if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { + APB_SARADC.int_clr.adc1_done = 1; + } + } else { // adc_n == ADC_NUM_2 + if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) { + APB_SARADC.int_clr.adc2_done = 1; + } + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) { + APB_SARADC.int_clr.thres0_high = 1; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) { + APB_SARADC.int_clr.thres0_low = 1; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) { + APB_SARADC.int_clr.thres1_high = 1; + } + if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) { + APB_SARADC.int_clr.thres1_low = 1; + } } /** @@ -478,7 +495,32 @@ static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t in */ static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n) { - abort(); // TODO ESP32-C3 IDF-2094 + uint32_t int_st = APB_SARADC.int_st.val; + uint32_t ret_msk = 0; + + if (adc_n == ADC_NUM_1) { + if (int_st & APB_SARADC_ADC1_DONE_INT_ST_M) { + ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE; + } + } else { // adc_n == ADC_NUM_2 + if (int_st & APB_SARADC_ADC2_DONE_INT_ST_M) { + ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE; + } + } + if (int_st & APB_SARADC_THRES0_HIGH_INT_ST) { + ret_msk |= ADC_DIGI_INTR_MASK_MONITOR0_HIGH; + } + if (int_st & APB_SARADC_THRES0_LOW_INT_ST_M) { + ret_msk |= ADC_DIGI_INTR_MASK_MONITOR0_LOW; + } + if (int_st & APB_SARADC_THRES1_HIGH_INT_ST_M) { + ret_msk |= ADC_DIGI_INTR_MASK_MONITOR1_HIGH; + } + if (int_st & APB_SARADC_THRES1_LOW_INT_ST_M) { + ret_msk |= ADC_DIGI_INTR_MASK_MONITOR1_LOW; + } + + return ret_msk; } /** @@ -528,7 +570,8 @@ static inline void adc_ll_digi_reset(void) */ static inline void adc_ll_pwdet_set_cct(uint32_t cct) { - abort(); // TODO ESP32-C3 IDF-2094 + /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ + RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; } /** @@ -539,153 +582,32 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct) */ static inline uint32_t adc_ll_pwdet_get_cct(void) { - abort(); // TODO ESP32-C3 IDF-2094 -} - -/*--------------------------------------------------------------- - RTC controller setting ----------------------------------------------------------------*/ -/** - * Set adc output data format for RTC controller. - * - * @note ESP32S2 RTC controller only support 13bit. - * @prarm adc_n ADC unit. - * @prarm bits Output data bits width option. - */ -static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits) -{ - return; -} - -/** - * Enable adc channel to start convert. - * - * @note Only one channel can be selected for once measurement. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Disable adc channel to start convert. - * - * @note Only one channel can be selected in once measurement. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n, int channel) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Start conversion once by software for RTC controller. - * - * @note It may be block to wait conversion idle for ADC1. - * - * @param adc_n ADC unit. - * @param channel ADC channel number for each ADCn. - */ -static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Check the conversion done flag for each ADCn for RTC controller. - * - * @param adc_n ADC unit. - * @return - * -true : The conversion process is finish. - * -false : The conversion process is not finish. - */ -static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Get the converted value for each ADCn for RTC controller. - * - * @param adc_n ADC unit. - * @return - * - Converted value. - */ -static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * ADC module RTC output data invert or not. - * - * @param adc_n ADC unit. - * @param inv_en data invert or not. - */ -static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Enable ADCn conversion complete interrupt for RTC controller. - * - * @param adc_n ADC unit. - */ -static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Disable ADCn conversion complete interrupt for RTC controller. - * - * @param adc_n ADC unit. - */ -static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Reset RTC controller FSM. - */ -static inline void adc_ll_rtc_reset(void) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize. - * - * @note Only ADC2 have arbiter function. - * @param cycle range: [0,4]. - */ -static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle) -{ - abort(); // TODO ESP32-C3 IDF-2094 + /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */ + return RTCCNTL.sensor_ctrl.sar2_pwdet_cct; } /** * Analyze whether the obtained raw data is correct. - * ADC2 can use arbiter. The arbitration result can be judged by the flag bit in the original data. + * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data. * * @param adc_n ADC unit. * @param raw_data ADC raw data input (convert value). * @return - * - 0: The data is correct to use. - * - 1: The data is invalid. The current controller is not enabled by the arbiter. - * - 2: The data is invalid. The current controller process was interrupted by a higher priority controller. - * - -1: The data is error. + * - 0: The data is correct to use. + * - -1: The data is invalid. */ -static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data) +static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data) { - abort(); // TODO ESP32-C3 IDF-2094 + if (adc_n == ADC_NUM_1) { + return ADC_RTC_DATA_OK; + } + + //The raw data API returns value without channel information. Read value directly from the register + if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) { + return ADC_RTC_DATA_FAIL; + } + + return ADC_RTC_DATA_OK; } /*--------------------------------------------------------------- @@ -702,13 +624,13 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) // Bit0 0:SW mode power down 1: SW mode power on */ if (manage == ADC_POWER_SW_ON) { APB_SARADC.ctrl.sar_clk_gated = 1; - APB_SARADC.ctrl.xpd_sar_force = SENS_FORCE_XPD_SAR_PU; + APB_SARADC.ctrl.xpd_sar_force = 3; } else if (manage == ADC_POWER_BY_FSM) { APB_SARADC.ctrl.sar_clk_gated = 1; - APB_SARADC.ctrl.xpd_sar_force = SENS_FORCE_XPD_SAR_FSM; + APB_SARADC.ctrl.xpd_sar_force = 0; } else if (manage == ADC_POWER_SW_OFF) { - APB_SARADC.ctrl.xpd_sar_force = SENS_FORCE_XPD_SAR_PD; - APB_SARADC.ctrl.sar_clk_gated = 1; + APB_SARADC.ctrl.xpd_sar_force = 2; + APB_SARADC.ctrl.sar_clk_gated = 0; } } @@ -720,67 +642,17 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage) */ static inline adc_ll_power_t adc_ll_get_power_manage(void) { - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`. - * - * @param div Division factor. - */ -static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Set the attenuation of a particular channel on ADCn. - * - * @note For any given channel, this function must be called before the first time conversion. - * - * The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage, - * usually 3.3V) requires setting >0dB signal attenuation for that ADC channel. - * - * When VDD_A is 3.3V: - * - * - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V - * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V - * - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V - * - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below) - * - * @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured - * bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.) - * - * @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage. - * - * Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges: - * - * - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV - * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV - * - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV - * - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV - * - * For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges. - * - * @param adc_n ADC unit. - * @param channel ADCn channel number. - * @param atten The attenuation option. - */ -static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Get the attenuation of a particular channel on ADCn. - * - * @param adc_n ADC unit. - * @param channel ADCn channel number. - * @return atten The attenuation option. - */ -static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t channel) -{ - abort(); // TODO ESP32-C3 IDF-2094 + /* Bit1 0:Fsm 1: SW mode + Bit0 0:SW mode power down 1: SW mode power on */ + adc_ll_power_t manage; + if (APB_SARADC.ctrl.xpd_sar_force == 3) { + manage = ADC_POWER_SW_ON; + } else if (APB_SARADC.ctrl.xpd_sar_force == 2) { + manage = ADC_POWER_SW_OFF; + } else { + manage = ADC_POWER_BY_FSM; + } + return manage; } /** @@ -793,9 +665,9 @@ static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t cha * @param adc_n ADC unit. * @param ctrl ADC controller. */ -static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl) +static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_controller_t ctrl) { - abort(); // TODO ESP32-C3 IDF-2094 + //NOTE: ULP is removed on C3, please remove ULP related (if there still are any) code and this comment } /** @@ -810,7 +682,6 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t */ static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode) { - SENS.sar_meas2_mux.sar2_rtc_force = 0; // Enable arbiter in wakeup mode if (mode == ADC_ARB_MODE_FIX) { APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0; APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1; @@ -866,37 +737,7 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, } } -/** - * Force switch ADC2 to RTC controller in sleep mode. Shield arbiter. - * In sleep mode, the arbiter is in power-down mode. - * Need to switch the controller to RTC to shield the control of the arbiter. - * After waking up, it needs to switch to arbiter control. - * - * @note The hardware will do this automatically. In normal use, there is no need to call this interface to manually switch the controller. - * @note Only support ADC2. - */ -static inline void adc_ll_enable_sleep_controller(void) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - -/** - * Force switch ADC2 to arbiter in wakeup mode. - * In sleep mode, the arbiter is in power-down mode. - * Need to switch the controller to RTC to shield the control of the arbiter. - * After waking up, it needs to switch to arbiter control. - * - * @note The hardware will do this automatically. In normal use, there is no need to call this interface to manually switch the controller. - * @note Only support ADC2. - */ -static inline void adc_ll_disable_sleep_controller(void) -{ - abort(); // TODO ESP32-C3 IDF-2094 -} - /* ADC calibration code. */ -#define ADC_HAL_CAL_OFFSET_RANGE (4096) -#define ADC_HAL_CAL_TIMES (10) /** * Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration. @@ -910,7 +751,25 @@ static inline void adc_ll_disable_sleep_controller(void) */ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd) { - abort(); // TODO ESP32-C3 IDF-2526 + /* Should be called before writing I2C registers. */ + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); + + /* Enable/disable internal connect GND (for calibration). */ + if (adc_n == ADC_NUM_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4); + if (internal_gnd) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + } + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4); + if (internal_gnd) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); + } + } } /** @@ -920,7 +779,11 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t */ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) { - abort(); // TODO ESP32-C3 IDF-2526 + if (adc_n == ADC_NUM_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0); + } } /** @@ -932,7 +795,70 @@ static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n) */ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t param) { - abort(); // TODO ESP32-C3 IDF-2526 + uint8_t msb = param >> 8; + uint8_t lsb = param & 0xFF; + if (adc_n == ADC_NUM_1) { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); + } +} +/* Temp code end. */ + +/** + * Output ADCn inter reference voltage to ADC2 channels. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC1's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @param[in] adc ADC unit select + * @param[in] channel ADC1 channel number + * @param[in] en Enable/disable the reference voltage output + */ +static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) +{ + if (en) { + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3); + SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); + + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF; + APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF; + APB_SARADC.onetime_sample.adc1_onetime_sample = 1; + APB_SARADC.onetime_sample.onetime_channel = channel; + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU); + if (adc == ADC_NUM_1) { + /* Config test mux to route v_ref to ADC1 Channels */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); + } else { + /* Config test mux to route v_ref to ADC2 Channels */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + } + } else { + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + APB_SARADC.onetime_sample.adc1_onetime_sample = 0; + APB_SARADC.onetime_sample.onetime_channel = 0xf; + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE); + } } /*--------------------------------------------------------------- @@ -998,7 +924,8 @@ static inline void adc_ll_adc1_onetime_sample_dis(void) static inline uint32_t adc_ll_adc1_read(void) { - return APB_SARADC.apb_saradc1_data_status.adc1_data; + //On ESP32C3, valid data width is 12-bit + return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff); } //--------------------------------adc2------------------------------// @@ -1014,8 +941,10 @@ static inline void adc_ll_adc2_onetime_sample_dis(void) static inline uint32_t adc_ll_adc2_read(void) { - return APB_SARADC.apb_saradc2_data_status.adc2_data; + //On ESP32C3, valid data width is 12-bit + return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff); } + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h index 7eedf5b936..1d306db61a 100644 --- a/components/hal/esp32s2/include/hal/adc_ll.h +++ b/components/hal/esp32s2/include/hal/adc_ll.h @@ -268,11 +268,11 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en) } /** - * Sets the number of interval clock cycles for the digital controller to trigger the measurement. - * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``. + * Set the interval clock cycle for the digital controller to trigger the measurement. + * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. * - * @note The trigger interval should not be less than the sampling time of the SAR ADC. - * @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095. + * @note The trigger interval should be larger than the sampling time of the SAR ADC. + * @param cycle The clock cycle (trigger interval) of the measurement. Range: 40 ~ 4095. */ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle) { diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h index ea952b6472..dc048d4ad2 100644 --- a/components/hal/include/hal/adc_hal.h +++ b/components/hal/include/hal/adc_hal.h @@ -134,6 +134,7 @@ void adc_hal_deinit(void); */ #define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct() +#ifndef CONFIG_IDF_TARGET_ESP32C3 /*--------------------------------------------------------------- RTC controller setting ---------------------------------------------------------------*/ @@ -167,6 +168,7 @@ int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value); * @prarm adc_n ADC unit. */ #define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en) +#endif /** * Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels. @@ -213,6 +215,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg); #include "hal/dma_types.h" #include "hal/adc_ll.h" #include "hal/dma_types.h" +#include "esp_err.h" typedef struct adc_dma_hal_context_t { gdma_dev_t *dev; //address of the general DMA @@ -259,9 +262,7 @@ void adc_hal_onetime_channel(adc_ll_num_t unit, adc_channel_t channel); void adc_hal_set_onetime_atten(adc_atten_t atten); -uint32_t adc_hal_adc1_read(void); - -uint32_t adc_hal_adc2_read(void); +esp_err_t adc_hal_single_read(adc_ll_num_t unit, int *out_raw); void adc_hal_intr_enable(adc_event_t event); diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h index dea8ab0ec1..247a84a5e4 100644 --- a/components/hal/include/hal/adc_types.h +++ b/components/hal/include/hal/adc_types.h @@ -17,6 +17,7 @@ #include #include "sdkconfig.h" #include "soc/soc_caps.h" +#include "esp_attr.h" /** * @brief ADC unit enumeration. @@ -88,7 +89,9 @@ typedef enum { ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. */ ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. */ ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. */ -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 +#elif SOC_ADC_MAX_BITWIDTH == 12 + ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. */ +#elif SOC_ADC_MAX_BITWIDTH == 13 ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. */ #endif ADC_WIDTH_MAX, @@ -139,7 +142,7 @@ typedef struct { uint8_t reserved: 2; /*!< reserved0 */ #endif }; - uint8_t val; /*! ADC_CHANNEL_MAX), The data is invalid. */ - uint32_t unit: 1; /*! ADC_CHANNEL_MAX), The data is invalid. */ + uint32_t unit: 1; /*! threshold, Generates monitor interrupt. */ +#else ADC_DIGI_MONITOR_HIGH = 0, /*! threshold, Generates monitor interrupt. */ ADC_DIGI_MONITOR_LOW, /*!= 1 diff --git a/components/soc/esp32c3/include/soc/sens_reg.h b/components/soc/esp32c3/include/soc/sens_reg.h deleted file mode 100644 index 95420e84a2..0000000000 --- a/components/soc/esp32c3/include/soc/sens_reg.h +++ /dev/null @@ -1,1733 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SENS_REG_H_ -#define _SOC_SENS_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0000) -/* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: enable saradc1 to send out interrupt*/ -#define SENS_SAR1_INT_EN (BIT(29)) -#define SENS_SAR1_INT_EN_M (BIT(29)) -#define SENS_SAR1_INT_EN_V 0x1 -#define SENS_SAR1_INT_EN_S 29 -/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: Invert SAR ADC1 data*/ -#define SENS_SAR1_DATA_INV (BIT(28)) -#define SENS_SAR1_DATA_INV_M (BIT(28)) -#define SENS_SAR1_DATA_INV_V 0x1 -#define SENS_SAR1_DATA_INV_S 28 -/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: */ -#define SENS_SAR1_SAMPLE_NUM 0x000000FF -#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S)) -#define SENS_SAR1_SAMPLE_NUM_V 0xFF -#define SENS_SAR1_SAMPLE_NUM_S 19 -/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define SENS_SAR1_CLK_GATED (BIT(18)) -#define SENS_SAR1_CLK_GATED_M (BIT(18)) -#define SENS_SAR1_CLK_GATED_V 0x1 -#define SENS_SAR1_CLK_GATED_S 18 -/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: clock divider*/ -#define SENS_SAR1_CLK_DIV 0x000000FF -#define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S)) -#define SENS_SAR1_CLK_DIV_V 0xFF -#define SENS_SAR1_CLK_DIV_S 0 - -#define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x0004) -/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR1_READER_STATUS 0xFFFFFFFF -#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S)) -#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF -#define SENS_SAR1_READER_STATUS_S 0 - -#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x0008) -/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 -#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) -#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 -#define SENS_AMP_SHORT_REF_GND_FORCE_S 30 -/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FORCE 0x00000003 -#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) -#define SENS_AMP_SHORT_REF_FORCE_V 0x3 -#define SENS_AMP_SHORT_REF_FORCE_S 28 -/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FORCE 0x00000003 -#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) -#define SENS_AMP_RST_FB_FORCE_V 0x3 -#define SENS_AMP_RST_FB_FORCE_S 26 -/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: */ -#define SENS_FORCE_XPD_AMP 0x00000003 -#define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) -#define SENS_FORCE_XPD_AMP_V 0x3 -#define SENS_FORCE_XPD_AMP_S 24 -#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down -#define SENS_FORCE_XPD_AMP_PD 2 // Force power down -#define SENS_FORCE_XPD_AMP_PU 3 // Force power up - -#define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0x000c) -/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW*/ -#define SENS_SAR1_EN_PAD_FORCE (BIT(31)) -#define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) -#define SENS_SAR1_EN_PAD_FORCE_V 0x1 -#define SENS_SAR1_EN_PAD_FORCE_S 31 -/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ -/*description: SAR ADC1 pad enable bitmap*/ -#define SENS_SAR1_EN_PAD 0x00000FFF -#define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) -#define SENS_SAR1_EN_PAD_V 0xFFF -#define SENS_SAR1_EN_PAD_S 19 -/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SAR ADC1 controller (in RTC) is started by SW*/ -#define SENS_MEAS1_START_FORCE (BIT(18)) -#define SENS_MEAS1_START_FORCE_M (BIT(18)) -#define SENS_MEAS1_START_FORCE_V 0x1 -#define SENS_MEAS1_START_FORCE_S 18 -/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: SAR ADC1 controller (in RTC) starts conversion*/ -#define SENS_MEAS1_START_SAR (BIT(17)) -#define SENS_MEAS1_START_SAR_M (BIT(17)) -#define SENS_MEAS1_START_SAR_V 0x1 -#define SENS_MEAS1_START_SAR_S 17 -/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: SAR ADC1 conversion done indication*/ -#define SENS_MEAS1_DONE_SAR (BIT(16)) -#define SENS_MEAS1_DONE_SAR_M (BIT(16)) -#define SENS_MEAS1_DONE_SAR_V 0x1 -#define SENS_MEAS1_DONE_SAR_S 16 -/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: SAR ADC1 data*/ -#define SENS_MEAS1_DATA_SAR 0x0000FFFF -#define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S)) -#define SENS_MEAS1_DATA_SAR_V 0xFFFF -#define SENS_MEAS1_DATA_SAR_S 0 - -#define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x0010) -/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL*/ -#define SENS_SAR1_DIG_FORCE (BIT(31)) -#define SENS_SAR1_DIG_FORCE_M (BIT(31)) -#define SENS_SAR1_DIG_FORCE_V 0x1 -#define SENS_SAR1_DIG_FORCE_S 31 - -#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0014) -/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: 2-bit attenuation for each pad*/ -#define SENS_SAR1_ATTEN 0xFFFFFFFF -#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) -#define SENS_SAR1_ATTEN_V 0xFFFFFFFF -#define SENS_SAR1_ATTEN_S 0 - -#define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x0018) -/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT2 0x0000FFFF -#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) -#define SENS_SAR_AMP_WAIT2_V 0xFFFF -#define SENS_SAR_AMP_WAIT2_S 16 -/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT1 0x0000FFFF -#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) -#define SENS_SAR_AMP_WAIT1_V 0xFFFF -#define SENS_SAR_AMP_WAIT1_S 0 - -#define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x001c) -/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ -/*description: */ -#define SENS_SAR_AMP_WAIT3 0x0000FFFF -#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) -#define SENS_SAR_AMP_WAIT3_V 0xFFFF -#define SENS_SAR_AMP_WAIT3_S 16 -/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) -#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) -#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 -#define SENS_SAR_RSTB_FSM_IDLE_S 6 -/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_XPD_SAR_FSM_IDLE (BIT(5)) -#define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) -#define SENS_XPD_SAR_FSM_IDLE_V 0x1 -#define SENS_XPD_SAR_FSM_IDLE_S 5 -/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 -#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 -/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) -#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) -#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 -#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 -/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) -#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) -#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 -#define SENS_AMP_RST_FB_FSM_IDLE_S 2 -/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) -#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) -#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 -#define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 -/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) -#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) -#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 -#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 - -#define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x0020) -/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */ -/*description: */ -#define SENS_SAR_RSTB_FSM 0x0000000F -#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) -#define SENS_SAR_RSTB_FSM_V 0xF -#define SENS_SAR_RSTB_FSM_S 24 -/* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */ -/*description: */ -#define SENS_XPD_SAR_FSM 0x0000000F -#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) -#define SENS_XPD_SAR_FSM_V 0xF -#define SENS_XPD_SAR_FSM_S 20 -/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F -#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) -#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF -#define SENS_AMP_SHORT_REF_GND_FSM_S 16 -/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_AMP_SHORT_REF_FSM 0x0000000F -#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) -#define SENS_AMP_SHORT_REF_FSM_V 0xF -#define SENS_AMP_SHORT_REF_FSM_S 12 -/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */ -/*description: */ -#define SENS_AMP_RST_FB_FSM 0x0000000F -#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) -#define SENS_AMP_RST_FB_FSM_V 0xF -#define SENS_AMP_RST_FB_FSM_S 8 -/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */ -/*description: */ -#define SENS_XPD_SAR_AMP_FSM 0x0000000F -#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) -#define SENS_XPD_SAR_AMP_FSM_V 0xF -#define SENS_XPD_SAR_AMP_FSM_S 4 -/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ -/*description: */ -#define SENS_SAR1_DAC_XPD_FSM 0x0000000F -#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) -#define SENS_SAR1_DAC_XPD_FSM_V 0xF -#define SENS_SAR1_DAC_XPD_FSM_S 0 - -#define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x0024) -/* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: enable saradc2 to send out interrupt*/ -#define SENS_SAR2_INT_EN (BIT(30)) -#define SENS_SAR2_INT_EN_M (BIT(30)) -#define SENS_SAR2_INT_EN_V 0x1 -#define SENS_SAR2_INT_EN_S 30 -/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Invert SAR ADC2 data*/ -#define SENS_SAR2_DATA_INV (BIT(29)) -#define SENS_SAR2_DATA_INV_M (BIT(29)) -#define SENS_SAR2_DATA_INV_V 0x1 -#define SENS_SAR2_DATA_INV_S 29 -/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ -/*description: */ -#define SENS_SAR2_SAMPLE_NUM 0x000000FF -#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S)) -#define SENS_SAR2_SAMPLE_NUM_V 0xFF -#define SENS_SAR2_SAMPLE_NUM_S 19 -/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define SENS_SAR2_CLK_GATED (BIT(18)) -#define SENS_SAR2_CLK_GATED_M (BIT(18)) -#define SENS_SAR2_CLK_GATED_V 0x1 -#define SENS_SAR2_CLK_GATED_S 18 -/* SENS_SAR2_WAIT_ARB_CYCLE : R/W ;bitpos:[17:16] ;default: 2'b1 ; */ -/*description: wait arbit stable after sar_done*/ -#define SENS_SAR2_WAIT_ARB_CYCLE 0x00000003 -#define SENS_SAR2_WAIT_ARB_CYCLE_M ((SENS_SAR2_WAIT_ARB_CYCLE_V)<<(SENS_SAR2_WAIT_ARB_CYCLE_S)) -#define SENS_SAR2_WAIT_ARB_CYCLE_V 0x3 -#define SENS_SAR2_WAIT_ARB_CYCLE_S 16 -/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ -/*description: clock divider*/ -#define SENS_SAR2_CLK_DIV 0x000000FF -#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S)) -#define SENS_SAR2_CLK_DIV_V 0xFF -#define SENS_SAR2_CLK_DIV_S 0 - -#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x0028) -/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR2_READER_STATUS 0xFFFFFFFF -#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) -#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF -#define SENS_SAR2_READER_STATUS_S 0 - -#define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x002c) -/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ -/*description: */ -#define SENS_SAR2_XPD_WAIT 0x000000FF -#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) -#define SENS_SAR2_XPD_WAIT_V 0xFF -#define SENS_SAR2_XPD_WAIT_S 24 -/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */ -/*description: */ -#define SENS_SAR2_RSTB_WAIT 0x000000FF -#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) -#define SENS_SAR2_RSTB_WAIT_V 0xFF -#define SENS_SAR2_RSTB_WAIT_S 16 -/* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */ -/*description: */ -#define SENS_SAR2_STANDBY_WAIT 0x000000FF -#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S)) -#define SENS_SAR2_STANDBY_WAIT_V 0xFF -#define SENS_SAR2_STANDBY_WAIT_S 8 -/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define SENS_SAR2_RSTB_FORCE 0x00000003 -#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) -#define SENS_SAR2_RSTB_FORCE_V 0x3 -#define SENS_SAR2_RSTB_FORCE_S 6 -/* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: SAR2_EN_TEST*/ -#define SENS_SAR2_EN_TEST (BIT(5)) -#define SENS_SAR2_EN_TEST_M (BIT(5)) -#define SENS_SAR2_EN_TEST_V 0x1 -#define SENS_SAR2_EN_TEST_S 5 -/* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: rtc control pkdet enable*/ -#define SENS_SAR2_PKDET_CAL_EN (BIT(4)) -#define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) -#define SENS_SAR2_PKDET_CAL_EN_V 0x1 -#define SENS_SAR2_PKDET_CAL_EN_S 4 -/* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: rtc control pwdet enable*/ -#define SENS_SAR2_PWDET_CAL_EN (BIT(3)) -#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) -#define SENS_SAR2_PWDET_CAL_EN_V 0x1 -#define SENS_SAR2_PWDET_CAL_EN_S 3 -/* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: saradc2_cntl_fsm*/ -#define SENS_SAR2_CNTL_STATE 0x00000007 -#define SENS_SAR2_CNTL_STATE_M ((SENS_SAR2_CNTL_STATE_V)<<(SENS_SAR2_CNTL_STATE_S)) -#define SENS_SAR2_CNTL_STATE_V 0x7 -#define SENS_SAR2_CNTL_STATE_S 0 - -#define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x0030) -/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW*/ -#define SENS_SAR2_EN_PAD_FORCE (BIT(31)) -#define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) -#define SENS_SAR2_EN_PAD_FORCE_V 0x1 -#define SENS_SAR2_EN_PAD_FORCE_S 31 -/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ -/*description: SAR ADC2 pad enable bitmap*/ -#define SENS_SAR2_EN_PAD 0x00000FFF -#define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) -#define SENS_SAR2_EN_PAD_V 0xFFF -#define SENS_SAR2_EN_PAD_S 19 -/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: 1: SAR ADC2 controller (in RTC) is started by SW*/ -#define SENS_MEAS2_START_FORCE (BIT(18)) -#define SENS_MEAS2_START_FORCE_M (BIT(18)) -#define SENS_MEAS2_START_FORCE_V 0x1 -#define SENS_MEAS2_START_FORCE_S 18 -/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: SAR ADC2 controller (in RTC) starts conversion*/ -#define SENS_MEAS2_START_SAR (BIT(17)) -#define SENS_MEAS2_START_SAR_M (BIT(17)) -#define SENS_MEAS2_START_SAR_V 0x1 -#define SENS_MEAS2_START_SAR_S 17 -/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: SAR ADC2 conversion done indication*/ -#define SENS_MEAS2_DONE_SAR (BIT(16)) -#define SENS_MEAS2_DONE_SAR_M (BIT(16)) -#define SENS_MEAS2_DONE_SAR_V 0x1 -#define SENS_MEAS2_DONE_SAR_S 16 -/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: SAR ADC2 data*/ -#define SENS_MEAS2_DATA_SAR 0x0000FFFF -#define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S)) -#define SENS_MEAS2_DATA_SAR_V 0xFFFF -#define SENS_MEAS2_DATA_SAR_S 0 - -#define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x0034) -/* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: in sleep force to use rtc to control ADC*/ -#define SENS_SAR2_RTC_FORCE (BIT(31)) -#define SENS_SAR2_RTC_FORCE_M (BIT(31)) -#define SENS_SAR2_RTC_FORCE_V 0x1 -#define SENS_SAR2_RTC_FORCE_S 31 -/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: SAR2_PWDET_CCT*/ -#define SENS_SAR2_PWDET_CCT 0x00000007 -#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) -#define SENS_SAR2_PWDET_CCT_V 0x7 -#define SENS_SAR2_PWDET_CCT_S 28 - -#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) -/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: 2-bit attenuation for each pad*/ -#define SENS_SAR2_ATTEN 0xFFFFFFFF -#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) -#define SENS_SAR2_ATTEN_V 0xFFFFFFFF -#define SENS_SAR2_ATTEN_S 0 - -#define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x003c) -/* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SENS_SARCLK_EN (BIT(31)) -#define SENS_SARCLK_EN_M (BIT(31)) -#define SENS_SARCLK_EN_V 0x1 -#define SENS_SARCLK_EN_S 31 -/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ -/*description: */ -#define SENS_FORCE_XPD_SAR 0x00000003 -#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) -#define SENS_FORCE_XPD_SAR_V 0x3 -#define SENS_FORCE_XPD_SAR_S 29 - -#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x0040) -/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ -/*description: */ -#define SENS_MEAS_STATUS 0x000000FF -#define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S)) -#define SENS_MEAS_STATUS_V 0xFF -#define SENS_MEAS_STATUS_S 22 -/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR0 0x000007FF -#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) -#define SENS_I2C_SLAVE_ADDR0_V 0x7FF -#define SENS_I2C_SLAVE_ADDR0_S 11 -/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR1 0x000007FF -#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) -#define SENS_I2C_SLAVE_ADDR1_V 0x7FF -#define SENS_I2C_SLAVE_ADDR1_S 0 - -#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0044) -/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR2 0x000007FF -#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) -#define SENS_I2C_SLAVE_ADDR2_V 0x7FF -#define SENS_I2C_SLAVE_ADDR2_S 11 -/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR3 0x000007FF -#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) -#define SENS_I2C_SLAVE_ADDR3_V 0x7FF -#define SENS_I2C_SLAVE_ADDR3_S 0 - -#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0048) -/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR4 0x000007FF -#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) -#define SENS_I2C_SLAVE_ADDR4_V 0x7FF -#define SENS_I2C_SLAVE_ADDR4_S 11 -/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR5 0x000007FF -#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) -#define SENS_I2C_SLAVE_ADDR5_V 0x7FF -#define SENS_I2C_SLAVE_ADDR5_S 0 - -#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x004c) -/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR6 0x000007FF -#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) -#define SENS_I2C_SLAVE_ADDR6_V 0x7FF -#define SENS_I2C_SLAVE_ADDR6_S 11 -/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SENS_I2C_SLAVE_ADDR7 0x000007FF -#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) -#define SENS_I2C_SLAVE_ADDR7_V 0x7FF -#define SENS_I2C_SLAVE_ADDR7_S 0 - -#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x0050) -/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: temperature sensor dump out*/ -#define SENS_TSENS_DUMP_OUT (BIT(24)) -#define SENS_TSENS_DUMP_OUT_M (BIT(24)) -#define SENS_TSENS_DUMP_OUT_V 0x1 -#define SENS_TSENS_DUMP_OUT_S 24 -/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 1: dump out & power up controlled by SW*/ -#define SENS_TSENS_POWER_UP_FORCE (BIT(23)) -#define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) -#define SENS_TSENS_POWER_UP_FORCE_V 0x1 -#define SENS_TSENS_POWER_UP_FORCE_S 23 -/* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: temperature sensor power up*/ -#define SENS_TSENS_POWER_UP (BIT(22)) -#define SENS_TSENS_POWER_UP_M (BIT(22)) -#define SENS_TSENS_POWER_UP_V 0x1 -#define SENS_TSENS_POWER_UP_S 22 -/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ -/*description: temperature sensor clock divider*/ -#define SENS_TSENS_CLK_DIV 0x000000FF -#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) -#define SENS_TSENS_CLK_DIV_V 0xFF -#define SENS_TSENS_CLK_DIV_S 14 -/* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: invert temperature sensor data*/ -#define SENS_TSENS_IN_INV (BIT(13)) -#define SENS_TSENS_IN_INV_M (BIT(13)) -#define SENS_TSENS_IN_INV_V 0x1 -#define SENS_TSENS_IN_INV_S 13 -/* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: enable temperature sensor to send out interrupt*/ -#define SENS_TSENS_INT_EN (BIT(12)) -#define SENS_TSENS_INT_EN_M (BIT(12)) -#define SENS_TSENS_INT_EN_V 0x1 -#define SENS_TSENS_INT_EN_S 12 -/* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: indicate temperature sensor out ready*/ -#define SENS_TSENS_READY (BIT(8)) -#define SENS_TSENS_READY_M (BIT(8)) -#define SENS_TSENS_READY_V 0x1 -#define SENS_TSENS_READY_S 8 -/* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: temperature sensor data out*/ -#define SENS_TSENS_OUT 0x000000FF -#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) -#define SENS_TSENS_OUT_V 0xFF -#define SENS_TSENS_OUT_S 0 - -#define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x0054) -/* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define SENS_TSENS_CLK_INV (BIT(14)) -#define SENS_TSENS_CLK_INV_M (BIT(14)) -#define SENS_TSENS_CLK_INV_V 0x1 -#define SENS_TSENS_CLK_INV_S 14 -/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define SENS_TSENS_XPD_FORCE 0x00000003 -#define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V)<<(SENS_TSENS_XPD_FORCE_S)) -#define SENS_TSENS_XPD_FORCE_V 0x3 -#define SENS_TSENS_XPD_FORCE_S 12 -/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ -/*description: */ -#define SENS_TSENS_XPD_WAIT 0x00000FFF -#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) -#define SENS_TSENS_XPD_WAIT_V 0xFFF -#define SENS_TSENS_XPD_WAIT_S 0 - -#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0058) -/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: I2C started by SW*/ -#define SENS_SAR_I2C_START_FORCE (BIT(29)) -#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) -#define SENS_SAR_I2C_START_FORCE_V 0x1 -#define SENS_SAR_I2C_START_FORCE_S 29 -/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: start I2C*/ -#define SENS_SAR_I2C_START (BIT(28)) -#define SENS_SAR_I2C_START_M (BIT(28)) -#define SENS_SAR_I2C_START_V 0x1 -#define SENS_SAR_I2C_START_S 28 -/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ -/*description: I2C control data*/ -#define SENS_SAR_I2C_CTRL 0x0FFFFFFF -#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) -#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF -#define SENS_SAR_I2C_CTRL_S 0 - -#define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x005c) -/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hF ; */ -/*description: indicate which pad is approach pad0*/ -#define SENS_TOUCH_APPROACH_PAD0 0x0000000F -#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S)) -#define SENS_TOUCH_APPROACH_PAD0_V 0xF -#define SENS_TOUCH_APPROACH_PAD0_S 28 -/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hF ; */ -/*description: indicate which pad is approach pad1*/ -#define SENS_TOUCH_APPROACH_PAD1 0x0000000F -#define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V)<<(SENS_TOUCH_APPROACH_PAD1_S)) -#define SENS_TOUCH_APPROACH_PAD1_V 0xF -#define SENS_TOUCH_APPROACH_PAD1_S 24 -/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hF ; */ -/*description: indicate which pad is approach pad2*/ -#define SENS_TOUCH_APPROACH_PAD2 0x0000000F -#define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V)<<(SENS_TOUCH_APPROACH_PAD2_S)) -#define SENS_TOUCH_APPROACH_PAD2_V 0xF -#define SENS_TOUCH_APPROACH_PAD2_S 20 -/* SENS_TOUCH_UNIT_END : RO ;bitpos:[19] ;default: 1'd0 ; */ -/*description: touch_unit_done*/ -#define SENS_TOUCH_UNIT_END (BIT(19)) -#define SENS_TOUCH_UNIT_END_M (BIT(19)) -#define SENS_TOUCH_UNIT_END_V 0x1 -#define SENS_TOUCH_UNIT_END_S 19 -/* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */ -/*description: touch_denoise_done*/ -#define SENS_TOUCH_DENOISE_END (BIT(18)) -#define SENS_TOUCH_DENOISE_END_M (BIT(18)) -#define SENS_TOUCH_DENOISE_END_V 0x1 -#define SENS_TOUCH_DENOISE_END_S 18 -/* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 3: smooth data 2: baseline 1 0: raw_data*/ -#define SENS_TOUCH_DATA_SEL 0x00000003 -#define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S)) -#define SENS_TOUCH_DATA_SEL_V 0x3 -#define SENS_TOUCH_DATA_SEL_S 16 -/* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ -/*description: clear all touch active status*/ -#define SENS_TOUCH_STATUS_CLR (BIT(15)) -#define SENS_TOUCH_STATUS_CLR_M (BIT(15)) -#define SENS_TOUCH_STATUS_CLR_V 0x1 -#define SENS_TOUCH_STATUS_CLR_S 15 -/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7FFF ; */ -/*description: touch controller output enable*/ -#define SENS_TOUCH_OUTEN 0x00007FFF -#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S)) -#define SENS_TOUCH_OUTEN_V 0x7FFF -#define SENS_TOUCH_OUTEN_S 0 - -#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x0060) -/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 1*/ -#define SENS_TOUCH_OUT_TH1 0x003FFFFF -#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) -#define SENS_TOUCH_OUT_TH1_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH1_S 0 - -#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0064) -/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 2*/ -#define SENS_TOUCH_OUT_TH2 0x003FFFFF -#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) -#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH2_S 0 - -#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0068) -/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 3*/ -#define SENS_TOUCH_OUT_TH3 0x003FFFFF -#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) -#define SENS_TOUCH_OUT_TH3_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH3_S 0 - -#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x006c) -/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 4*/ -#define SENS_TOUCH_OUT_TH4 0x003FFFFF -#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) -#define SENS_TOUCH_OUT_TH4_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH4_S 0 - -#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x0070) -/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 5*/ -#define SENS_TOUCH_OUT_TH5 0x003FFFFF -#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) -#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH5_S 0 - -#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x0074) -/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 6*/ -#define SENS_TOUCH_OUT_TH6 0x003FFFFF -#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) -#define SENS_TOUCH_OUT_TH6_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH6_S 0 - -#define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x0078) -/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 7*/ -#define SENS_TOUCH_OUT_TH7 0x003FFFFF -#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) -#define SENS_TOUCH_OUT_TH7_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH7_S 0 - -#define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x007c) -/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 8*/ -#define SENS_TOUCH_OUT_TH8 0x003FFFFF -#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) -#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH8_S 0 - -#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x0080) -/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 9*/ -#define SENS_TOUCH_OUT_TH9 0x003FFFFF -#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) -#define SENS_TOUCH_OUT_TH9_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH9_S 0 - -#define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x0084) -/* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 10*/ -#define SENS_TOUCH_OUT_TH10 0x003FFFFF -#define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V)<<(SENS_TOUCH_OUT_TH10_S)) -#define SENS_TOUCH_OUT_TH10_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH10_S 0 - -#define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x0088) -/* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 11*/ -#define SENS_TOUCH_OUT_TH11 0x003FFFFF -#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S)) -#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH11_S 0 - -#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x008c) -/* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 12*/ -#define SENS_TOUCH_OUT_TH12 0x003FFFFF -#define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V)<<(SENS_TOUCH_OUT_TH12_S)) -#define SENS_TOUCH_OUT_TH12_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH12_S 0 - -#define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x0090) -/* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 13*/ -#define SENS_TOUCH_OUT_TH13 0x003FFFFF -#define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V)<<(SENS_TOUCH_OUT_TH13_S)) -#define SENS_TOUCH_OUT_TH13_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH13_S 0 - -#define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x0094) -/* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: Finger threshold for touch pad 14*/ -#define SENS_TOUCH_OUT_TH14 0x003FFFFF -#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S)) -#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF -#define SENS_TOUCH_OUT_TH14_S 0 - -#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x00d4) -/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TOUCH_MEAS_DONE (BIT(31)) -#define SENS_TOUCH_MEAS_DONE_M (BIT(31)) -#define SENS_TOUCH_MEAS_DONE_V 0x1 -#define SENS_TOUCH_MEAS_DONE_S 31 -/* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */ -/*description: Clear touch channel*/ -#define SENS_TOUCH_CHANNEL_CLR 0x00007FFF -#define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V)<<(SENS_TOUCH_CHANNEL_CLR_S)) -#define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF -#define SENS_TOUCH_CHANNEL_CLR_S 15 -/* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ -/*description: touch active status*/ -#define SENS_TOUCH_PAD_ACTIVE 0x00007FFF -#define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V)<<(SENS_TOUCH_PAD_ACTIVE_S)) -#define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF -#define SENS_TOUCH_PAD_ACTIVE_S 0 - -#define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0x00d8) -/* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: */ -#define SENS_TOUCH_SCAN_CURR 0x0000000F -#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S)) -#define SENS_TOUCH_SCAN_CURR_V 0xF -#define SENS_TOUCH_SCAN_CURR_S 22 -/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: the counter for touch pad 0*/ -#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF -#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S)) -#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF -#define SENS_TOUCH_DENOISE_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0x00dc) -/* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V)<<(SENS_TOUCH_PAD1_DEBOUNCE_S)) -#define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD1_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD1_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD1_DATA 0x003FFFFF -#define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V)<<(SENS_TOUCH_PAD1_DATA_S)) -#define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD1_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0x00e0) -/* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V)<<(SENS_TOUCH_PAD2_DEBOUNCE_S)) -#define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD2_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD2_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD2_DATA 0x003FFFFF -#define SENS_TOUCH_PAD2_DATA_M ((SENS_TOUCH_PAD2_DATA_V)<<(SENS_TOUCH_PAD2_DATA_S)) -#define SENS_TOUCH_PAD2_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD2_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0x00e4) -/* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S)) -#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD3_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD3_DATA 0x003FFFFF -#define SENS_TOUCH_PAD3_DATA_M ((SENS_TOUCH_PAD3_DATA_V)<<(SENS_TOUCH_PAD3_DATA_S)) -#define SENS_TOUCH_PAD3_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD3_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0x00e8) -/* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V)<<(SENS_TOUCH_PAD4_DEBOUNCE_S)) -#define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD4_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD4_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD4_DATA 0x003FFFFF -#define SENS_TOUCH_PAD4_DATA_M ((SENS_TOUCH_PAD4_DATA_V)<<(SENS_TOUCH_PAD4_DATA_S)) -#define SENS_TOUCH_PAD4_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD4_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0x00ec) -/* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S)) -#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD5_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD5_DATA 0x003FFFFF -#define SENS_TOUCH_PAD5_DATA_M ((SENS_TOUCH_PAD5_DATA_V)<<(SENS_TOUCH_PAD5_DATA_S)) -#define SENS_TOUCH_PAD5_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD5_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0x00f0) -/* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V)<<(SENS_TOUCH_PAD6_DEBOUNCE_S)) -#define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD6_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD6_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD6_DATA 0x003FFFFF -#define SENS_TOUCH_PAD6_DATA_M ((SENS_TOUCH_PAD6_DATA_V)<<(SENS_TOUCH_PAD6_DATA_S)) -#define SENS_TOUCH_PAD6_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD6_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0x00f4) -/* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S)) -#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD7_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD7_DATA 0x003FFFFF -#define SENS_TOUCH_PAD7_DATA_M ((SENS_TOUCH_PAD7_DATA_V)<<(SENS_TOUCH_PAD7_DATA_S)) -#define SENS_TOUCH_PAD7_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD7_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0x00f8) -/* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V)<<(SENS_TOUCH_PAD8_DEBOUNCE_S)) -#define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD8_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD8_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD8_DATA 0x003FFFFF -#define SENS_TOUCH_PAD8_DATA_M ((SENS_TOUCH_PAD8_DATA_V)<<(SENS_TOUCH_PAD8_DATA_S)) -#define SENS_TOUCH_PAD8_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD8_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0x00fc) -/* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S)) -#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD9_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD9_DATA 0x003FFFFF -#define SENS_TOUCH_PAD9_DATA_M ((SENS_TOUCH_PAD9_DATA_V)<<(SENS_TOUCH_PAD9_DATA_S)) -#define SENS_TOUCH_PAD9_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD9_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0x0100) -/* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V)<<(SENS_TOUCH_PAD10_DEBOUNCE_S)) -#define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD10_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD10_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD10_DATA 0x003FFFFF -#define SENS_TOUCH_PAD10_DATA_M ((SENS_TOUCH_PAD10_DATA_V)<<(SENS_TOUCH_PAD10_DATA_S)) -#define SENS_TOUCH_PAD10_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD10_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0x0104) -/* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S)) -#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD11_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD11_DATA 0x003FFFFF -#define SENS_TOUCH_PAD11_DATA_M ((SENS_TOUCH_PAD11_DATA_V)<<(SENS_TOUCH_PAD11_DATA_S)) -#define SENS_TOUCH_PAD11_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD11_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0x0108) -/* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V)<<(SENS_TOUCH_PAD12_DEBOUNCE_S)) -#define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD12_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD12_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD12_DATA 0x003FFFFF -#define SENS_TOUCH_PAD12_DATA_M ((SENS_TOUCH_PAD12_DATA_V)<<(SENS_TOUCH_PAD12_DATA_S)) -#define SENS_TOUCH_PAD12_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD12_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0x010c) -/* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S)) -#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD13_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD13_DATA 0x003FFFFF -#define SENS_TOUCH_PAD13_DATA_M ((SENS_TOUCH_PAD13_DATA_V)<<(SENS_TOUCH_PAD13_DATA_S)) -#define SENS_TOUCH_PAD13_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD13_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0x0110) -/* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 -#define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V)<<(SENS_TOUCH_PAD14_DEBOUNCE_S)) -#define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 -#define SENS_TOUCH_PAD14_DEBOUNCE_S 29 -/* SENS_TOUCH_PAD14_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_PAD14_DATA 0x003FFFFF -#define SENS_TOUCH_PAD14_DATA_M ((SENS_TOUCH_PAD14_DATA_V)<<(SENS_TOUCH_PAD14_DATA_S)) -#define SENS_TOUCH_PAD14_DATA_V 0x3FFFFF -#define SENS_TOUCH_PAD14_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS15_REG (DR_REG_SENS_BASE + 0x0114) -/* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ -/*description: */ -#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 -#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S)) -#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 -#define SENS_TOUCH_SLP_DEBOUNCE_S 29 -/* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: */ -#define SENS_TOUCH_SLP_DATA 0x003FFFFF -#define SENS_TOUCH_SLP_DATA_M ((SENS_TOUCH_SLP_DATA_V)<<(SENS_TOUCH_SLP_DATA_S)) -#define SENS_TOUCH_SLP_DATA_V 0x3FFFFF -#define SENS_TOUCH_SLP_DATA_S 0 - -#define SENS_SAR_TOUCH_STATUS16_REG (DR_REG_SENS_BASE + 0x0118) -/* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF -#define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V)<<(SENS_TOUCH_SLP_APPROACH_CNT_S)) -#define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF -#define SENS_TOUCH_SLP_APPROACH_CNT_S 24 -/* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF -#define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V)<<(SENS_TOUCH_APPROACH_PAD0_CNT_S)) -#define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF -#define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 -/* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF -#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S)) -#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF -#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 -/* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ -/*description: */ -#define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF -#define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V)<<(SENS_TOUCH_APPROACH_PAD2_CNT_S)) -#define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF -#define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 - -#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x011c) -/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: invert PDAC_CLK*/ -#define SENS_DAC_CLK_INV (BIT(25)) -#define SENS_DAC_CLK_INV_M (BIT(25)) -#define SENS_DAC_CLK_INV_V 0x1 -#define SENS_DAC_CLK_INV_S 25 -/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: force PDAC_CLK to high*/ -#define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) -#define SENS_DAC_CLK_FORCE_HIGH_M (BIT(24)) -#define SENS_DAC_CLK_FORCE_HIGH_V 0x1 -#define SENS_DAC_CLK_FORCE_HIGH_S 24 -/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 1: force PDAC_CLK to low*/ -#define SENS_DAC_CLK_FORCE_LOW (BIT(23)) -#define SENS_DAC_CLK_FORCE_LOW_M (BIT(23)) -#define SENS_DAC_CLK_FORCE_LOW_V 0x1 -#define SENS_DAC_CLK_FORCE_LOW_S 23 -/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: 1: DAC1 & DAC2 use DMA*/ -#define SENS_DAC_DIG_FORCE (BIT(22)) -#define SENS_DAC_DIG_FORCE_M (BIT(22)) -#define SENS_DAC_DIG_FORCE_V 0x1 -#define SENS_DAC_DIG_FORCE_S 22 -/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ -/*description: */ -#define SENS_DEBUG_BIT_SEL 0x0000001F -#define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S)) -#define SENS_DEBUG_BIT_SEL_V 0x1F -#define SENS_DEBUG_BIT_SEL_S 17 -/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: enable CW generator*/ -#define SENS_SW_TONE_EN (BIT(16)) -#define SENS_SW_TONE_EN_M (BIT(16)) -#define SENS_SW_TONE_EN_V 0x1 -#define SENS_SW_TONE_EN_S 16 -/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: frequency step for CW generator*/ -#define SENS_SW_FSTEP 0x0000FFFF -#define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S)) -#define SENS_SW_FSTEP_V 0xFFFF -#define SENS_SW_FSTEP_S 0 - -#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x0120) -/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ -/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]*/ -#define SENS_DAC_CW_EN2 (BIT(25)) -#define SENS_DAC_CW_EN2_M (BIT(25)) -#define SENS_DAC_CW_EN2_V 0x1 -#define SENS_DAC_CW_EN2_S 25 -/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]*/ -#define SENS_DAC_CW_EN1 (BIT(24)) -#define SENS_DAC_CW_EN1_M (BIT(24)) -#define SENS_DAC_CW_EN1_V 0x1 -#define SENS_DAC_CW_EN1_S 24 -/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: 00: do not invert any bits*/ -#define SENS_DAC_INV2 0x00000003 -#define SENS_DAC_INV2_M ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S)) -#define SENS_DAC_INV2_V 0x3 -#define SENS_DAC_INV2_S 22 -/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ -/*description: 00: do not invert any bits*/ -#define SENS_DAC_INV1 0x00000003 -#define SENS_DAC_INV1_M ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S)) -#define SENS_DAC_INV1_V 0x3 -#define SENS_DAC_INV1_S 20 -/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: 00: no scale*/ -#define SENS_DAC_SCALE2 0x00000003 -#define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S)) -#define SENS_DAC_SCALE2_V 0x3 -#define SENS_DAC_SCALE2_S 18 -/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ -/*description: 00: no scale*/ -#define SENS_DAC_SCALE1 0x00000003 -#define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S)) -#define SENS_DAC_SCALE1_V 0x3 -#define SENS_DAC_SCALE1_S 16 -/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: DC offset for DAC2 CW generator*/ -#define SENS_DAC_DC2 0x000000FF -#define SENS_DAC_DC2_M ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S)) -#define SENS_DAC_DC2_V 0xFF -#define SENS_DAC_DC2_S 8 -/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: DC offset for DAC1 CW generator*/ -#define SENS_DAC_DC1 0x000000FF -#define SENS_DAC_DC1_M ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S)) -#define SENS_DAC_DC1_V 0xFF -#define SENS_DAC_DC1_S 0 - -#define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0x0124) -/* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: check cocpu whether in ebreak*/ -#define SENS_COCPU_EBREAK (BIT(30)) -#define SENS_COCPU_EBREAK_M (BIT(30)) -#define SENS_COCPU_EBREAK_V 0x1 -#define SENS_COCPU_EBREAK_S 30 -/* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: check cocpu whether in trap state*/ -#define SENS_COCPU_TRAP (BIT(29)) -#define SENS_COCPU_TRAP_M (BIT(29)) -#define SENS_COCPU_TRAP_V 0x1 -#define SENS_COCPU_TRAP_S 29 -/* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: check cocpu whether in interrupt state*/ -#define SENS_COCPU_EOI (BIT(28)) -#define SENS_COCPU_EOI_M (BIT(28)) -#define SENS_COCPU_EOI_V 0x1 -#define SENS_COCPU_EOI_S 28 -/* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: check cocpu whether in reset state*/ -#define SENS_COCPU_RESET_N (BIT(27)) -#define SENS_COCPU_RESET_N_M (BIT(27)) -#define SENS_COCPU_RESET_N_V 0x1 -#define SENS_COCPU_RESET_N_S 27 -/* SENS_COCPU_CLK_EN_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: check cocpu whether clk on*/ -#define SENS_COCPU_CLK_EN_ST (BIT(26)) -#define SENS_COCPU_CLK_EN_ST_M (BIT(26)) -#define SENS_COCPU_CLK_EN_ST_V 0x1 -#define SENS_COCPU_CLK_EN_ST_S 26 -/* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: trigger cocpu debug registers*/ -#define SENS_COCPU_DBG_TRIGGER (BIT(25)) -#define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) -#define SENS_COCPU_DBG_TRIGGER_V 0x1 -#define SENS_COCPU_DBG_TRIGGER_S 25 - -#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0x0128) -/* SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S 11 -/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 10 -/* SENS_COCPU_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S 9 -/* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: int from super watch dog*/ -#define SENS_COCPU_SWD_INT_RAW (BIT(8)) -#define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) -#define SENS_COCPU_SWD_INT_RAW_V 0x1 -#define SENS_COCPU_SWD_INT_RAW_S 8 -/* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: int from software*/ -#define SENS_COCPU_SW_INT_RAW (BIT(7)) -#define SENS_COCPU_SW_INT_RAW_M (BIT(7)) -#define SENS_COCPU_SW_INT_RAW_V 0x1 -#define SENS_COCPU_SW_INT_RAW_S 7 -/* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: int from start*/ -#define SENS_COCPU_START_INT_RAW (BIT(6)) -#define SENS_COCPU_START_INT_RAW_M (BIT(6)) -#define SENS_COCPU_START_INT_RAW_V 0x1 -#define SENS_COCPU_START_INT_RAW_S 6 -/* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: int from tsens*/ -#define SENS_COCPU_TSENS_INT_RAW (BIT(5)) -#define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_RAW_V 0x1 -#define SENS_COCPU_TSENS_INT_RAW_S 5 -/* SENS_COCPU_SENS2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: int from saradc2*/ -#define SENS_COCPU_SENS2_INT_RAW (BIT(4)) -#define SENS_COCPU_SENS2_INT_RAW_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_RAW_V 0x1 -#define SENS_COCPU_SENS2_INT_RAW_S 4 -/* SENS_COCPU_SENS1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: int from saradc1*/ -#define SENS_COCPU_SENS1_INT_RAW (BIT(3)) -#define SENS_COCPU_SENS1_INT_RAW_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_RAW_V 0x1 -#define SENS_COCPU_SENS1_INT_RAW_S 3 -/* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: int from touch active*/ -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 -/* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: int from touch inactive*/ -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 -/* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: int from touch done*/ -#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 - -#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0x012c) -/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S 11 -/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 10 -/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S 9 -/* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ENA (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_V 0x1 -#define SENS_COCPU_SWD_INT_ENA_S 8 -/* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: cocpu int enable*/ -#define SENS_COCPU_SW_INT_ENA (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_M (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_V 0x1 -#define SENS_COCPU_SW_INT_ENA_S 7 -/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA (BIT(6)) -#define SENS_COCPU_START_INT_ENA_M (BIT(6)) -#define SENS_COCPU_START_INT_ENA_V 0x1 -#define SENS_COCPU_START_INT_ENA_S 6 -/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_S 5 -/* SENS_COCPU_SENS2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ENA (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_V 0x1 -#define SENS_COCPU_SENS2_INT_ENA_S 4 -/* SENS_COCPU_SENS1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ENA (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_V 0x1 -#define SENS_COCPU_SENS1_INT_ENA_S 3 -/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 -/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 -/* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 - -#define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0x0130) -/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S 11 -/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 10 -/* SENS_COCPU_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S 9 -/* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ST (BIT(8)) -#define SENS_COCPU_SWD_INT_ST_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ST_V 0x1 -#define SENS_COCPU_SWD_INT_ST_S 8 -/* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: cocpu int status*/ -#define SENS_COCPU_SW_INT_ST (BIT(7)) -#define SENS_COCPU_SW_INT_ST_M (BIT(7)) -#define SENS_COCPU_SW_INT_ST_V 0x1 -#define SENS_COCPU_SW_INT_ST_S 7 -/* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ST (BIT(6)) -#define SENS_COCPU_START_INT_ST_M (BIT(6)) -#define SENS_COCPU_START_INT_ST_V 0x1 -#define SENS_COCPU_START_INT_ST_S 6 -/* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ST (BIT(5)) -#define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ST_V 0x1 -#define SENS_COCPU_TSENS_INT_ST_S 5 -/* SENS_COCPU_SENS2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ST (BIT(4)) -#define SENS_COCPU_SENS2_INT_ST_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ST_V 0x1 -#define SENS_COCPU_SENS2_INT_ST_S 4 -/* SENS_COCPU_SENS1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ST (BIT(3)) -#define SENS_COCPU_SENS1_INT_ST_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ST_V 0x1 -#define SENS_COCPU_SENS1_INT_ST_S 3 -/* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 -/* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 -/* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 - -#define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0x0134) -/* SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S 11 -/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 10 -/* SENS_COCPU_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S 9 -/* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_CLR (BIT(8)) -#define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) -#define SENS_COCPU_SWD_INT_CLR_V 0x1 -#define SENS_COCPU_SWD_INT_CLR_S 8 -/* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: cocpu int clear*/ -#define SENS_COCPU_SW_INT_CLR (BIT(7)) -#define SENS_COCPU_SW_INT_CLR_M (BIT(7)) -#define SENS_COCPU_SW_INT_CLR_V 0x1 -#define SENS_COCPU_SW_INT_CLR_S 7 -/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_CLR (BIT(6)) -#define SENS_COCPU_START_INT_CLR_M (BIT(6)) -#define SENS_COCPU_START_INT_CLR_V 0x1 -#define SENS_COCPU_START_INT_CLR_S 6 -/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_CLR (BIT(5)) -#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_CLR_V 0x1 -#define SENS_COCPU_TSENS_INT_CLR_S 5 -/* SENS_COCPU_SENS2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_CLR (BIT(4)) -#define SENS_COCPU_SENS2_INT_CLR_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_CLR_V 0x1 -#define SENS_COCPU_SENS2_INT_CLR_S 4 -/* SENS_COCPU_SENS1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_CLR (BIT(3)) -#define SENS_COCPU_SENS1_INT_CLR_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_CLR_V 0x1 -#define SENS_COCPU_SENS1_INT_CLR_S 3 -/* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 -/* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 -/* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 - -#define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0x0138) -/* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */ -/*description: cocpu mem address output*/ -#define SENS_COCPU_MEM_ADDR 0x00001FFF -#define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V)<<(SENS_COCPU_MEM_ADDR_S)) -#define SENS_COCPU_MEM_ADDR_V 0x1FFF -#define SENS_COCPU_MEM_ADDR_S 19 -/* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */ -/*description: cocpu mem write enable output*/ -#define SENS_COCPU_MEM_WEN 0x0000000F -#define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V)<<(SENS_COCPU_MEM_WEN_S)) -#define SENS_COCPU_MEM_WEN_V 0xF -#define SENS_COCPU_MEM_WEN_S 15 -/* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: cocpu mem ready input*/ -#define SENS_COCPU_MEM_RDY (BIT(14)) -#define SENS_COCPU_MEM_RDY_M (BIT(14)) -#define SENS_COCPU_MEM_RDY_V 0x1 -#define SENS_COCPU_MEM_RDY_S 14 -/* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: cocpu mem valid output*/ -#define SENS_COCPU_MEM_VLD (BIT(13)) -#define SENS_COCPU_MEM_VLD_M (BIT(13)) -#define SENS_COCPU_MEM_VLD_V 0x1 -#define SENS_COCPU_MEM_VLD_S 13 -/* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */ -/*description: cocpu Program counter*/ -#define SENS_COCPU_PC 0x00001FFF -#define SENS_COCPU_PC_M ((SENS_COCPU_PC_V)<<(SENS_COCPU_PC_S)) -#define SENS_COCPU_PC_V 0x1FFF -#define SENS_COCPU_PC_S 0 - -#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0x013c) -/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled - by FSM in ULP-coprocessor*/ -#define SENS_HALL_PHASE_FORCE (BIT(31)) -#define SENS_HALL_PHASE_FORCE_M (BIT(31)) -#define SENS_HALL_PHASE_FORCE_V 0x1 -#define SENS_HALL_PHASE_FORCE_S 31 -/* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Reverse phase of hall sensor*/ -#define SENS_HALL_PHASE (BIT(30)) -#define SENS_HALL_PHASE_M (BIT(30)) -#define SENS_HALL_PHASE_V 0x1 -#define SENS_HALL_PHASE_S 30 -/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by - FSM in ULP-coprocessor*/ -#define SENS_XPD_HALL_FORCE (BIT(29)) -#define SENS_XPD_HALL_FORCE_M (BIT(29)) -#define SENS_XPD_HALL_FORCE_V 0x1 -#define SENS_XPD_HALL_FORCE_S 29 -/* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Power on hall sensor and connect to VP and VN*/ -#define SENS_XPD_HALL (BIT(28)) -#define SENS_XPD_HALL_M (BIT(28)) -#define SENS_XPD_HALL_V 0x1 -#define SENS_XPD_HALL_S 28 - -#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x0140) -/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SENS_SAR_NOUSE 0xFFFFFFFF -#define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S)) -#define SENS_SAR_NOUSE_V 0xFFFFFFFF -#define SENS_SAR_NOUSE_S 0 - -#define SENS_SAR_PERI_CLK_GATE_CONF_REG (DR_REG_SENS_BASE + 0x0144) -/* SENS_IOMUX_CLK_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: */ -#define SENS_IOMUX_CLK_EN (BIT(31)) -#define SENS_IOMUX_CLK_EN_M (BIT(31)) -#define SENS_IOMUX_CLK_EN_V 0x1 -#define SENS_IOMUX_CLK_EN_S 31 -/* SENS_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SENS_CLK_EN (BIT(30)) -#define SENS_CLK_EN_M (BIT(30)) -#define SENS_CLK_EN_V 0x1 -#define SENS_CLK_EN_S 30 -/* SENS_TSENS_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TSENS_CLK_EN (BIT(29)) -#define SENS_TSENS_CLK_EN_M (BIT(29)) -#define SENS_TSENS_CLK_EN_V 0x1 -#define SENS_TSENS_CLK_EN_S 29 -/* SENS_RTC_I2C_CLK_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SENS_RTC_I2C_CLK_EN (BIT(27)) -#define SENS_RTC_I2C_CLK_EN_M (BIT(27)) -#define SENS_RTC_I2C_CLK_EN_V 0x1 -#define SENS_RTC_I2C_CLK_EN_S 27 -/* SENS_DAC_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SENS_DAC_CLK_EN (BIT(26)) -#define SENS_DAC_CLK_EN_M (BIT(26)) -#define SENS_DAC_CLK_EN_V 0x1 -#define SENS_DAC_CLK_EN_S 26 - -#define SENS_SAR_PERI_RESET_CONF_REG (DR_REG_SENS_BASE + 0x0148) -/* SENS_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SENS_RESET (BIT(30)) -#define SENS_RESET_M (BIT(30)) -#define SENS_RESET_V 0x1 -#define SENS_RESET_S 30 -/* SENS_TSENS_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SENS_TSENS_RESET (BIT(29)) -#define SENS_TSENS_RESET_M (BIT(29)) -#define SENS_TSENS_RESET_V 0x1 -#define SENS_TSENS_RESET_S 29 -#define SENS_FORCE_XPD_SAR_SW_M (BIT1) -#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down -#define SENS_FORCE_XPD_SAR_PD 2 // Force power down -#define SENS_FORCE_XPD_SAR_PU 3 // Force power up -/* SENS_RTC_I2C_RESET : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SENS_RTC_I2C_RESET (BIT(27)) -#define SENS_RTC_I2C_RESET_M (BIT(27)) -#define SENS_RTC_I2C_RESET_V 0x1 -#define SENS_RTC_I2C_RESET_S 27 -/* SENS_DAC_RESET : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SENS_DAC_RESET (BIT(26)) -#define SENS_DAC_RESET_M (BIT(26)) -#define SENS_DAC_RESET_V 0x1 -#define SENS_DAC_RESET_S 26 -/* SENS_COCPU_RESET : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_RESET (BIT(25)) -#define SENS_COCPU_RESET_M (BIT(25)) -#define SENS_COCPU_RESET_V 0x1 -#define SENS_COCPU_RESET_S 25 - -#define SENS_SAR_COCPU_INT_ENA_W1TS_REG (DR_REG_SENS_BASE + 0x014c) -/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 11 -/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 10 -/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S 9 -/* SENS_COCPU_SWD_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ENA_W1TS (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TS_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SWD_INT_ENA_W1TS_S 8 -/* SENS_COCPU_SW_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SW_INT_ENA_W1TS (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TS_M (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SW_INT_ENA_W1TS_S 7 -/* SENS_COCPU_START_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA_W1TS (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TS_M (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_START_INT_ENA_W1TS_S 6 -/* SENS_COCPU_TSENS_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA_W1TS (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TS_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_W1TS_S 5 -/* SENS_COCPU_SENS2_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ENA_W1TS (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TS_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SENS2_INT_ENA_W1TS_S 4 -/* SENS_COCPU_SENS1_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ENA_W1TS (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TS_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_SENS1_INT_ENA_W1TS_S 3 -/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S 2 -/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S 1 -/* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S 0 - -#define SENS_SAR_COCPU_INT_ENA_W1TC_REG (DR_REG_SENS_BASE + 0x0150) -/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(11)) -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 11 -/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(10)) -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 10 -/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(9)) -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S 9 -/* SENS_COCPU_SWD_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SWD_INT_ENA_W1TC (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TC_M (BIT(8)) -#define SENS_COCPU_SWD_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SWD_INT_ENA_W1TC_S 8 -/* SENS_COCPU_SW_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SW_INT_ENA_W1TC (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TC_M (BIT(7)) -#define SENS_COCPU_SW_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SW_INT_ENA_W1TC_S 7 -/* SENS_COCPU_START_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_START_INT_ENA_W1TC (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TC_M (BIT(6)) -#define SENS_COCPU_START_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_START_INT_ENA_W1TC_S 6 -/* SENS_COCPU_TSENS_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TSENS_INT_ENA_W1TC (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TC_M (BIT(5)) -#define SENS_COCPU_TSENS_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TSENS_INT_ENA_W1TC_S 5 -/* SENS_COCPU_SENS2_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS2_INT_ENA_W1TC (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TC_M (BIT(4)) -#define SENS_COCPU_SENS2_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SENS2_INT_ENA_W1TC_S 4 -/* SENS_COCPU_SENS1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_SENS1_INT_ENA_W1TC (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TC_M (BIT(3)) -#define SENS_COCPU_SENS1_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_SENS1_INT_ENA_W1TC_S 3 -/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(2)) -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S 2 -/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(1)) -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S 1 -/* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M (BIT(0)) -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V 0x1 -#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S 0 - -#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x0154) -/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1909160 ; */ -/*description: */ -#define SENS_SAR_DATE 0x0FFFFFFF -#define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) -#define SENS_SAR_DATE_V 0xFFFFFFF -#define SENS_SAR_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SENS_REG_H_ */ diff --git a/components/soc/esp32c3/include/soc/sens_struct.h b/components/soc/esp32c3/include/soc/sens_struct.h deleted file mode 100644 index 4a084b9111..0000000000 --- a/components/soc/esp32c3/include/soc/sens_struct.h +++ /dev/null @@ -1,504 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SENS_STRUCT_H_ -#define _SOC_SENS_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t sar1_clk_div: 8; /*clock divider*/ - uint32_t reserved8: 10; - uint32_t sar1_clk_gated: 1; - uint32_t sar1_sample_num: 8; - uint32_t reserved27: 1; - uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/ - uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/ - uint32_t reserved30: 2; - }; - uint32_t val; - } sar_reader1_ctrl; - uint32_t sar_reader1_status; /**/ - union { - struct { - uint32_t reserved0: 24; - uint32_t force_xpd_amp: 2; - uint32_t amp_rst_fb_force: 2; - uint32_t amp_short_ref_force: 2; - uint32_t amp_short_ref_gnd_force: 2; - }; - uint32_t val; - } sar_meas1_ctrl1; - union { - struct { - uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ - uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ - uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/ - uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/ - uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/ - uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/ - }; - uint32_t val; - } sar_meas1_ctrl2; - union { - struct { - uint32_t reserved0: 31; - uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ - }; - uint32_t val; - } sar_meas1_mux; - uint32_t sar_atten1; /*2-bit attenuation for each pad*/ - union { - struct { - uint32_t sar_amp_wait1:16; - uint32_t sar_amp_wait2:16; - }; - uint32_t val; - } sar_amp_ctrl1; - union { - struct { - uint32_t sar1_dac_xpd_fsm_idle: 1; - uint32_t xpd_sar_amp_fsm_idle: 1; - uint32_t amp_rst_fb_fsm_idle: 1; - uint32_t amp_short_ref_fsm_idle: 1; - uint32_t amp_short_ref_gnd_fsm_idle: 1; - uint32_t xpd_sar_fsm_idle: 1; - uint32_t sar_rstb_fsm_idle: 1; - uint32_t reserved7: 9; - uint32_t sar_amp_wait3: 16; - }; - uint32_t val; - } sar_amp_ctrl2; - union { - struct { - uint32_t sar1_dac_xpd_fsm: 4; - uint32_t xpd_sar_amp_fsm: 4; - uint32_t amp_rst_fb_fsm: 4; - uint32_t amp_short_ref_fsm: 4; - uint32_t amp_short_ref_gnd_fsm: 4; - uint32_t xpd_sar_fsm: 4; - uint32_t sar_rstb_fsm: 4; - uint32_t reserved28: 4; - }; - uint32_t val; - } sar_amp_ctrl3; - union { - struct { - uint32_t sar2_clk_div: 8; /*clock divider*/ - uint32_t reserved8: 8; - uint32_t sar2_wait_arb_cycle: 2; /*wait arbit stable after sar_done*/ - uint32_t sar2_clk_gated: 1; - uint32_t sar2_sample_num: 8; - uint32_t reserved27: 2; - uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/ - uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/ - uint32_t reserved31: 1; - }; - uint32_t val; - } sar_reader2_ctrl; - uint32_t sar_reader2_status; /**/ - union { - struct { - uint32_t sar2_cntl_state: 3; /*saradc2_cntl_fsm*/ - uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/ - uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/ - uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/ - uint32_t sar2_rstb_force: 2; - uint32_t sar2_standby_wait: 8; - uint32_t sar2_rstb_wait: 8; - uint32_t sar2_xpd_wait: 8; - }; - uint32_t val; - } sar_meas2_ctrl1; - union { - struct { - uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ - uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ - uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/ - uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/ - uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/ - uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/ - }; - uint32_t val; - } sar_meas2_ctrl2; - union { - struct { - uint32_t reserved0: 28; - uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/ - uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/ - }; - uint32_t val; - } sar_meas2_mux; - uint32_t sar_atten2; /*2-bit attenuation for each pad*/ - union { - struct { - uint32_t reserved0: 29; - uint32_t force_xpd_sar: 2; - uint32_t sarclk_en: 1; - }; - uint32_t val; - } sar_power_xpd_sar; - union { - struct { - uint32_t i2c_slave_addr1: 11; - uint32_t i2c_slave_addr0: 11; - uint32_t meas_status: 8; - uint32_t reserved30: 2; - }; - uint32_t val; - } sar_slave_addr1; - union { - struct { - uint32_t i2c_slave_addr3:11; - uint32_t i2c_slave_addr2:11; - uint32_t reserved22: 10; - }; - uint32_t val; - } sar_slave_addr2; - union { - struct { - uint32_t i2c_slave_addr5:11; - uint32_t i2c_slave_addr4:11; - uint32_t reserved22: 10; - }; - uint32_t val; - } sar_slave_addr3; - union { - struct { - uint32_t i2c_slave_addr7:11; - uint32_t i2c_slave_addr6:11; - uint32_t reserved22: 10; - }; - uint32_t val; - } sar_slave_addr4; - union { - struct { - uint32_t tsens_out: 8; /*temperature sensor data out*/ - uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/ - uint32_t reserved9: 3; - uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/ - uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/ - uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/ - uint32_t tsens_power_up: 1; /*temperature sensor power up*/ - uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/ - uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/ - uint32_t reserved25: 7; - }; - uint32_t val; - } sar_tctrl; - union { - struct { - uint32_t tsens_xpd_wait: 12; - uint32_t tsens_xpd_force: 2; - uint32_t tsens_clk_inv: 1; - uint32_t reserved15: 17; - }; - uint32_t val; - } sar_tctrl2; - union { - struct { - uint32_t sar_i2c_ctrl: 28; /*I2C control data*/ - uint32_t sar_i2c_start: 1; /*start I2C*/ - uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/ - uint32_t reserved30: 2; - }; - uint32_t val; - } sar_i2c_ctrl; - union { - struct { - uint32_t touch_outen: 15; /*touch controller output enable*/ - uint32_t touch_status_clr: 1; /*clear all touch active status*/ - uint32_t touch_data_sel: 2; /*3: smooth data 2: baseline 1 0: raw_data*/ - uint32_t touch_denoise_end: 1; /*touch_denoise_done*/ - uint32_t touch_unit_end: 1; /*touch_unit_done*/ - uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/ - uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/ - uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/ - }; - uint32_t val; - } sar_touch_conf; - union { - struct { - uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ - uint32_t reserved22: 10; - }; - uint32_t val; - } touch_thresh[14]; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - union { - struct { - uint32_t touch_pad_active: 15; /*touch active status*/ - uint32_t touch_channel_clr:15; /*Clear touch channel*/ - uint32_t reserved30: 1; - uint32_t touch_meas_done: 1; - }; - uint32_t val; - } sar_touch_chn_st; - union { - struct { - uint32_t touch_denoise_data:22; /*the counter for touch pad 0*/ - uint32_t touch_scan_curr: 4; - uint32_t reserved26: 6; - }; - uint32_t val; - } sar_touch_status0; - union { - struct { - uint32_t touch_pad1_data: 22; - uint32_t reserved22: 7; - uint32_t touch_pad_debounce: 3; - }; - uint32_t val; - } sar_touch_status[14]; - union { - struct { - uint32_t touch_slp_data: 22; - uint32_t reserved22: 7; - uint32_t touch_slp_debounce: 3; - }; - uint32_t val; - } sar_touch_status15; - union { - struct { - uint32_t touch_approach_pad2_cnt: 8; - uint32_t touch_approach_pad1_cnt: 8; - uint32_t touch_approach_pad0_cnt: 8; - uint32_t touch_slp_approach_cnt: 8; - }; - uint32_t val; - } sar_touch_status16; - union { - struct { - uint32_t sw_fstep: 16; /*frequency step for CW generator*/ - uint32_t sw_tone_en: 1; /*1: enable CW generator*/ - uint32_t debug_bit_sel: 5; - uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/ - uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/ - uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/ - uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/ - uint32_t reserved26: 6; - }; - uint32_t val; - } sar_dac_ctrl1; - union { - struct { - uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ - uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ - uint32_t dac_scale1: 2; /*00: no scale*/ - uint32_t dac_scale2: 2; /*00: no scale*/ - uint32_t dac_inv1: 2; /*00: do not invert any bits*/ - uint32_t dac_inv2: 2; /*00: do not invert any bits*/ - uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/ - uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/ - uint32_t reserved26: 6; - }; - uint32_t val; - } sar_dac_ctrl2; - union { - struct { - uint32_t reserved0: 25; - uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/ - uint32_t clk_en_st: 1; /*check cocpu whether clk on*/ - uint32_t reset_n: 1; /*check cocpu whether in reset state*/ - uint32_t eoi: 1; /*check cocpu whether in interrupt state*/ - uint32_t trap: 1; /*check cocpu whether in trap state*/ - uint32_t ebreak: 1; /*check cocpu whether in ebreak*/ - uint32_t reserved31: 1; - }; - uint32_t val; - } sar_cocpu_state; - union { - struct { - uint32_t touch_done: 1; /*int from touch done*/ - uint32_t touch_inactive: 1; /*int from touch inactive*/ - uint32_t touch_active: 1; /*int from touch active*/ - uint32_t saradc1: 1; /*int from saradc1*/ - uint32_t saradc2: 1; /*int from saradc2*/ - uint32_t tsens: 1; /*int from tsens*/ - uint32_t start: 1; /*int from start*/ - uint32_t sw: 1; /*int from software*/ - uint32_t swd: 1; /*int from super watch dog*/ - uint32_t touch_timeout: 1; - uint32_t touch_approach_loop_done: 1; - uint32_t touch_scan_done: 1; - uint32_t reserved12: 20; - }; - uint32_t val; - } sar_cocpu_int_raw; - union { - struct { - uint32_t touch_done: 1; - uint32_t touch_inactive: 1; - uint32_t touch_active: 1; - uint32_t saradc1: 1; - uint32_t saradc2: 1; - uint32_t tsens: 1; - uint32_t start: 1; - uint32_t sw: 1; /*cocpu int enable*/ - uint32_t swd: 1; - uint32_t touch_timeout: 1; - uint32_t touch_approach_loop_done: 1; - uint32_t touch_scan_done: 1; - uint32_t reserved12: 20; - }; - uint32_t val; - } sar_cocpu_int_ena; - union { - struct { - uint32_t touch_done: 1; - uint32_t touch_inactive: 1; - uint32_t touch_active: 1; - uint32_t saradc1: 1; - uint32_t saradc2: 1; - uint32_t tsens: 1; - uint32_t start: 1; - uint32_t sw: 1; /*cocpu int status*/ - uint32_t swd: 1; - uint32_t touch_timeout: 1; - uint32_t touch_approach_loop_done: 1; - uint32_t touch_scan_done: 1; - uint32_t reserved12: 20; - }; - uint32_t val; - } sar_cocpu_int_st; - union { - struct { - uint32_t touch_done: 1; - uint32_t touch_inactive: 1; - uint32_t touch_active: 1; - uint32_t saradc1: 1; - uint32_t saradc2: 1; - uint32_t tsens: 1; - uint32_t start: 1; - uint32_t sw: 1; /*cocpu int clear*/ - uint32_t swd: 1; - uint32_t touch_timeout: 1; - uint32_t touch_approach_loop_done: 1; - uint32_t touch_scan_done: 1; - uint32_t reserved12: 20; - }; - uint32_t val; - } sar_cocpu_int_clr; - union { - struct { - uint32_t pc: 13; /*cocpu Program counter*/ - uint32_t mem_vld: 1; /*cocpu mem valid output*/ - uint32_t mem_rdy: 1; /*cocpu mem ready input*/ - uint32_t mem_wen: 4; /*cocpu mem write enable output*/ - uint32_t mem_addr: 13; /*cocpu mem address output*/ - }; - uint32_t val; - } sar_cocpu_debug; - union { - struct { - uint32_t reserved0: 28; - uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ - uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/ - uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ - uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/ - }; - uint32_t val; - } sar_hall_ctrl; - uint32_t sar_nouse; /**/ - union { - struct { - uint32_t reserved0: 26; - uint32_t dac_clk_en: 1; - uint32_t rtc_i2c_clk_en: 1; - uint32_t reserved28: 1; - uint32_t tsens_clk_en: 1; - uint32_t saradc_clk_en: 1; - uint32_t iomux_clk_en: 1; - }; - uint32_t val; - } sar_peri_clk_gate_conf; - union { - struct { - uint32_t reserved0: 25; - uint32_t reset: 1; - uint32_t dac_reset: 1; - uint32_t rtc_i2c_reset: 1; - uint32_t reserved28: 1; - uint32_t tsens_reset: 1; - uint32_t saradc_reset: 1; - uint32_t reserved31: 1; - }; - uint32_t val; - } sar_peri_reset_conf; - union { - struct { - uint32_t touch_done_w1ts: 1; - uint32_t touch_inactive_w1ts: 1; - uint32_t touch_active_w1ts: 1; - uint32_t saradc1_w1ts: 1; - uint32_t saradc2_w1ts: 1; - uint32_t tsens_w1ts: 1; - uint32_t start_w1ts: 1; - uint32_t sw_w1ts: 1; - uint32_t swd_w1ts: 1; - uint32_t touch_timeout_w1ts: 1; - uint32_t touch_approach_loop_done_w1ts: 1; - uint32_t touch_scan_done_w1ts: 1; - uint32_t reserved12: 20; - }; - uint32_t val; - } sar_cocpu_int_ena_w1ts; - union { - struct { - uint32_t touch_done_w1tc: 1; - uint32_t touch_inactive_w1tc: 1; - uint32_t touch_active_w1tc: 1; - uint32_t saradc1_w1tc: 1; - uint32_t saradc2_w1tc: 1; - uint32_t tsens_w1tc: 1; - uint32_t start_w1tc: 1; - uint32_t sw_w1tc: 1; - uint32_t swd_w1tc: 1; - uint32_t touch_timeout_w1tc: 1; - uint32_t touch_approach_loop_done_w1tc: 1; - uint32_t touch_scan_done_w1tc: 1; - uint32_t reserved12: 20; - }; - uint32_t val; - } sar_cocpu_int_ena_w1tc; - union { - struct { - uint32_t sar_date: 28; - uint32_t reserved28: 4; - }; - uint32_t val; - } sardate; -} sens_dev_t; -extern sens_dev_t SENS; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_SENS_STRUCT_H_ */ diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index a236e2e6fc..0f256f5843 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -102,19 +102,17 @@ #define SOC_AES_SUPPORT_AES_256 (1) /*-------------------------- ADC CAPS -------------------------------*/ -#define SOC_ADC_PERIPH_NUM (2) -#define SOC_ADC_PATT_LEN_MAX (16) - -#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) -#define SOC_ADC_MAX_CHANNEL_NUM (10) - -/** - * Check if adc support digital controller (DMA) mode. - * @value - * - 1 : support; - * - 0 : not support; - */ -#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1 +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_PATT_LEN_MAX (16) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) +#define SOC_ADC_MAX_CHANNEL_NUM (10) +#define SOC_ADC_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1 +//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ #define SOC_APB_BACKUP_DMA (1) diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 11454d5b2a..6368926b85 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -55,9 +55,9 @@ /*-------------------------- ADC CAPS ----------------------------------------*/ #define SOC_ADC_PERIPH_NUM (2) #define SOC_ADC_PATT_LEN_MAX (16) - #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) #define SOC_ADC_MAX_CHANNEL_NUM (10) +#define SOC_ADC_MAX_BITWIDTH (13) /** * Check if adc support digital controller (DMA) mode. @@ -66,6 +66,7 @@ * - 0 : not support; */ #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1) +#define SOC_ADC_SUPPORT_RTC_CTRL 1 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 diff --git a/components/soc/esp32s3/include/soc/adc_caps.h b/components/soc/esp32s3/include/soc/adc_caps.h index c6ea4cfaf9..1460198b12 100644 --- a/components/soc/esp32s3/include/soc/adc_caps.h +++ b/components/soc/esp32s3/include/soc/adc_caps.h @@ -15,9 +15,10 @@ #define SOC_ADC_PERIPH_NUM (2) #define SOC_ADC_PATT_LEN_MAX (16) - #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) #define SOC_ADC_MAX_CHANNEL_NUM (10) +#define SOC_ADC_MAX_BITWIDTH (13) + /** * Check if adc support digital controller (DMA) mode. @@ -26,3 +27,4 @@ * - 0 : not support; */ #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1) +#define SOC_ADC_SUPPORT_RTC_CTRL 1 diff --git a/components/soc/include/soc/adc_periph.h b/components/soc/include/soc/adc_periph.h index 9cb75283eb..796ea18e90 100644 --- a/components/soc/include/soc/adc_periph.h +++ b/components/soc/include/soc/adc_periph.h @@ -17,8 +17,12 @@ #include "soc/soc.h" #include "soc/soc_caps.h" #include "soc/syscon_struct.h" + +#if SOC_ADC_SUPPORT_RTC_CTRL #include "soc/sens_reg.h" #include "soc/sens_struct.h" +#endif + #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #include "soc/rtc_io_struct.h" #endif diff --git a/components/soc/include/soc/rtc_io_periph.h b/components/soc/include/soc/rtc_io_periph.h index 3bf77472ce..e9309771c6 100644 --- a/components/soc/include/soc/rtc_io_periph.h +++ b/components/soc/include/soc/rtc_io_periph.h @@ -19,16 +19,17 @@ #include "soc/soc_caps.h" #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED - #include "soc/rtc_io_channel.h" #include "soc/rtc_io_reg.h" #include "soc/rtc_io_struct.h" - #endif #include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_struct.h" + +#if SOC_ADC_SUPPORT_RTC_CTRL #include "soc/sens_struct.h" +#endif #ifdef __cplusplus extern "C" diff --git a/docs/en/api-reference/peripherals/adc.rst b/docs/en/api-reference/peripherals/adc.rst index b5876ffe1b..abba6594dc 100644 --- a/docs/en/api-reference/peripherals/adc.rst +++ b/docs/en/api-reference/peripherals/adc.rst @@ -76,7 +76,7 @@ Reading voltage on ADC1 channel 0 ({IDF_TARGET_ADC1_CH0}):: int val = adc1_get_raw(ADC1_CHANNEL_0); The input voltage in the above example is from 0 to 1.1 V (0 dB attenuation). The input range can be extended by setting a higher attenuation, see :cpp:type:`adc_atten_t`. -An example of using the ADC driver including calibration (discussed below) is available at esp-idf: :example:`peripherals/adc` +An example of using the ADC driver including calibration (discussed below) is available at esp-idf: :example:`peripherals/adc/adc` Reading voltage on ADC2 channel 7 ({IDF_TARGET_ADC2_CH7}):: @@ -95,7 +95,7 @@ Reading voltage on ADC2 channel 7 ({IDF_TARGET_ADC2_CH7}):: } The reading may fail due to collision with Wi-Fi, should check it. -An example using the ADC2 driver to read the output of DAC is available in esp-idf: :example:`peripherals/adc2` +An example using the ADC2 driver to read the output of DAC is available in esp-idf: :example:`peripherals/adc/adc2` .. only:: esp32 diff --git a/examples/peripherals/adc/CMakeLists.txt b/examples/peripherals/adc/adc/CMakeLists.txt similarity index 100% rename from examples/peripherals/adc/CMakeLists.txt rename to examples/peripherals/adc/adc/CMakeLists.txt diff --git a/examples/peripherals/adc/Makefile b/examples/peripherals/adc/adc/Makefile similarity index 100% rename from examples/peripherals/adc/Makefile rename to examples/peripherals/adc/adc/Makefile diff --git a/examples/peripherals/adc/README.md b/examples/peripherals/adc/adc/README.md similarity index 100% rename from examples/peripherals/adc/README.md rename to examples/peripherals/adc/adc/README.md diff --git a/examples/peripherals/adc/main/CMakeLists.txt b/examples/peripherals/adc/adc/main/CMakeLists.txt similarity index 100% rename from examples/peripherals/adc/main/CMakeLists.txt rename to examples/peripherals/adc/adc/main/CMakeLists.txt diff --git a/examples/peripherals/adc/main/adc1_example_main.c b/examples/peripherals/adc/adc/main/adc1_example_main.c similarity index 100% rename from examples/peripherals/adc/main/adc1_example_main.c rename to examples/peripherals/adc/adc/main/adc1_example_main.c diff --git a/examples/peripherals/adc/main/component.mk b/examples/peripherals/adc/adc/main/component.mk similarity index 100% rename from examples/peripherals/adc/main/component.mk rename to examples/peripherals/adc/adc/main/component.mk diff --git a/examples/peripherals/adc2/CMakeLists.txt b/examples/peripherals/adc/adc2/CMakeLists.txt similarity index 100% rename from examples/peripherals/adc2/CMakeLists.txt rename to examples/peripherals/adc/adc2/CMakeLists.txt diff --git a/examples/peripherals/adc2/Makefile b/examples/peripherals/adc/adc2/Makefile similarity index 100% rename from examples/peripherals/adc2/Makefile rename to examples/peripherals/adc/adc2/Makefile diff --git a/examples/peripherals/adc2/README.md b/examples/peripherals/adc/adc2/README.md similarity index 100% rename from examples/peripherals/adc2/README.md rename to examples/peripherals/adc/adc2/README.md diff --git a/examples/peripherals/adc2/main/CMakeLists.txt b/examples/peripherals/adc/adc2/main/CMakeLists.txt similarity index 100% rename from examples/peripherals/adc2/main/CMakeLists.txt rename to examples/peripherals/adc/adc2/main/CMakeLists.txt diff --git a/examples/peripherals/adc2/main/Kconfig.projbuild b/examples/peripherals/adc/adc2/main/Kconfig.projbuild similarity index 100% rename from examples/peripherals/adc2/main/Kconfig.projbuild rename to examples/peripherals/adc/adc2/main/Kconfig.projbuild diff --git a/examples/peripherals/adc2/main/adc2_example_main.c b/examples/peripherals/adc/adc2/main/adc2_example_main.c similarity index 100% rename from examples/peripherals/adc2/main/adc2_example_main.c rename to examples/peripherals/adc/adc2/main/adc2_example_main.c diff --git a/examples/peripherals/adc2/main/component.mk b/examples/peripherals/adc/adc2/main/component.mk similarity index 100% rename from examples/peripherals/adc2/main/component.mk rename to examples/peripherals/adc/adc2/main/component.mk diff --git a/examples/peripherals/adc/adc_dma/CMakeLists.txt b/examples/peripherals/adc/adc_dma/CMakeLists.txt new file mode 100644 index 0000000000..b01d635218 --- /dev/null +++ b/examples/peripherals/adc/adc_dma/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.5) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(adc) diff --git a/examples/peripherals/adc/adc_dma/README.md b/examples/peripherals/adc/adc_dma/README.md new file mode 100644 index 0000000000..8d349d76f3 --- /dev/null +++ b/examples/peripherals/adc/adc_dma/README.md @@ -0,0 +1,63 @@ +| Supported Targets | ESP32-C3 | +| ----------------- | -------- | + +# ADC DMA Example + +(See the README.md file in the upper level 'examples' directory for more information about examples.) + +This example shows how to use DMA-Read-APIs and Single-Read-APIs to read voltage from GPIO pins via ADC controller. + +## How to use example + +### Hardware Required + +* A development board with ESP32C3 SoC +* A USB cable for power supply and programming + +For `single_read` (Single-Read-APIs example), we use `ADC1_CHANNEL_2`, `ADC1_CHANNEL_3`, `ADC1_CHANNEL_4`, `ADC2_CHANNEL_0`. Hence we need to connect voltage sources (0 ~ 3.3V) to GPIO2, GPIO3, GPIO4, GPIO5 respectively. + +For `continuous_read` (DMA-Read-APIs example), we use `ADC1_CHANNEL_0`, `ADC1_CHANNEL_1` and `ADC2_CHANNEL_0`. Therefore, GPIO0, GPIO1 and GPIO5 should be connected to voltage sources (0 ~ 3.3V). + +If other ADC units/channels are selected in your application, you need to change the GPIO pin (please refer to the `ESP32C3 Technical Reference Manual`). + +### Configure the project + +``` +idf.py menuconfig +``` + +### Build and Flash + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects. + +## Example Output + +Running this example, you will see the following log output on the serial monitor: +``` +I (322) ADC1_CH2: 7c8 +I (322) ADC1_CH3: 278 +I (322) ADC1_CH4: d4b +I (322) ADC2_CH0: 48 +``` +``` +ADC1_CH0: 61b +ADC1_CH1: 39b +ADC2_CH0: 4b +``` + +## Troubleshooting + +* program upload failure + + * Hardware connection is not correct: run `idf.py -p PORT monitor`, and reboot your board to see if there are any output logs. + * The baud rate for downloading is too high: lower your baud rate in the `menuconfig` menu, and try again. + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/peripherals/adc/adc_dma/main/CMakeLists.txt b/examples/peripherals/adc/adc_dma/main/CMakeLists.txt new file mode 100644 index 0000000000..72b0d08bf0 --- /dev/null +++ b/examples/peripherals/adc/adc_dma/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "adc_dma_example_main.c" + INCLUDE_DIRS ".") diff --git a/examples/peripherals/adc/adc_dma/main/adc_dma_example_main.c b/examples/peripherals/adc/adc_dma/main/adc_dma_example_main.c new file mode 100644 index 0000000000..bac3dece22 --- /dev/null +++ b/examples/peripherals/adc/adc_dma/main/adc_dma_example_main.c @@ -0,0 +1,126 @@ +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "esp_log.h" +#include "driver/adc.h" + +#define TIMES 256 +#define DMA_CHANNEL 0 + +static void continuous_adc_init(uint16_t adc1_chan_mask, uint16_t adc2_chan_mask, adc_channel_t *channel, uint8_t channel_num) +{ + esp_err_t ret = ESP_OK; + assert(ret == ESP_OK); + + adc_digi_init_config_t adc_dma_config = { + .max_store_buf_size = 1024, + .conv_num_each_intr = 256, + .dma_chan = SOC_GDMA_ADC_DMA_CHANNEL, + .adc1_chan_mask = adc1_chan_mask, + .adc2_chan_mask = adc2_chan_mask, + }; + ret = adc_digi_initialize(&adc_dma_config); + assert(ret == ESP_OK); + + adc_digi_pattern_table_t adc_pattern[10] = {0}; + + //Do not set the sampling frequency out of the range between `SOC_ADC_SAMPLE_FREQ_THRES_LOW` and `SOC_ADC_SAMPLE_FREQ_THRES_HIGH` + adc_digi_config_t dig_cfg = { + .conv_limit_en = 0, + .conv_limit_num = 250, + .sample_freq_hz = 620, + }; + + dig_cfg.adc_pattern_len = channel_num; + for (int i = 0; i < channel_num; i++) { + uint8_t unit = ((channel[i] >> 3) & 0x1); + uint8_t ch = channel[i] & 0x7; + adc_pattern[i].atten = ADC_ATTEN_DB_0; + adc_pattern[i].channel = ch; + adc_pattern[i].unit = unit; + } + dig_cfg.adc_pattern = adc_pattern; + ret = adc_digi_controller_config(&dig_cfg); + assert(ret == ESP_OK); +} + +static bool check_valid_data(const adc_digi_output_data_t *data) +{ + const unsigned int unit = data->type2.unit; + if (unit > 2) return false; + if (data->type2.channel >= SOC_ADC_CHANNEL_NUM(unit)) return false; + + return true; +} + +static void continuous_read(void *arg) +{ + esp_err_t ret; + uint32_t ret_num = 0; + uint8_t result[TIMES] = {0}; + memset(result, 0xcc, TIMES); + + uint16_t adc1_chan_mask = BIT(0) | BIT(1); + uint16_t adc2_chan_mask = BIT(0); + adc_channel_t channel[3] = {ADC1_CHANNEL_0, ADC1_CHANNEL_1, (ADC2_CHANNEL_0 | 1 << 3)}; + + continuous_adc_init(adc1_chan_mask, adc2_chan_mask, channel, sizeof(channel) / sizeof(adc_channel_t)); + adc_digi_start(); + + int n = 20; + while(n--) { + ret = adc_digi_read_bytes(result, TIMES, &ret_num, ADC_MAX_DELAY); + for (int i = 0; i < ret_num; i+=4) { + adc_digi_output_data_t *p = (void*)&result[i]; + if (check_valid_data(p)) { + printf("ADC%d_CH%d: %x\n", p->type2.unit+1, p->type2.channel, p->type2.data); + } else { + printf("Invalid data [%d_%d_%x]\n", p->type2.unit+1, p->type2.channel, p->type2.data); + } + } + // If you see task WDT in this task, it means the conversion is too fast for the task to handle + } + + adc_digi_stop(); + ret = adc_digi_deinitialize(); + assert(ret == ESP_OK); +} + +static void single_read(void *arg) +{ + esp_err_t ret; + int adc1_reading[3] = {0xcc}; + int adc2_reading[1] = {0xcc}; + + const char TAG_CH[][10] = {"ADC1_CH2", "ADC1_CH3","ADC1_CH4", "ADC2_CH0"}; + + adc1_config_width(ADC_WIDTH_BIT_DEFAULT); + adc1_config_channel_atten(ADC1_CHANNEL_2, ADC_ATTEN_DB_0); + adc1_config_channel_atten(ADC1_CHANNEL_3, ADC_ATTEN_DB_6); + adc1_config_channel_atten(ADC1_CHANNEL_4, ADC_ATTEN_DB_0); + adc2_config_channel_atten(ADC2_CHANNEL_0, ADC_ATTEN_DB_0); + + int n = 20; + while (n--) { + + adc1_reading[0] = adc1_get_raw(ADC1_CHANNEL_2); + adc1_reading[1] = adc1_get_raw(ADC1_CHANNEL_3); + adc1_reading[2] = adc1_get_raw(ADC1_CHANNEL_4); + + for (int i = 0; i < 3; i++) { + ESP_LOGI(TAG_CH[i], "%x", adc1_reading[i]); + } + + ret = adc2_get_raw(ADC2_CHANNEL_0, ADC_WIDTH_BIT_12, &adc2_reading[0]); + assert(ret == ESP_OK); + ESP_LOGI(TAG_CH[3], "%x", adc2_reading[0]); + } +} + +void app_main(void) +{ + single_read(NULL); + continuous_read(NULL); +}