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feat(soc): update modem syscon and lpcon register header and structure file for esp32c61
This commit is contained in:
wuzhenghui
yinqingzhao
@@ -1,7 +1,7 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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@@ -11,366 +11,524 @@
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extern "C" {
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#endif
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#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
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/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_TEST_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
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/** MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_EN (BIT(0))
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#define MODEM_LPCON_CLK_EN_M (BIT(0))
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#define MODEM_LPCON_CLK_EN_V 0x1
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#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
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#define MODEM_LPCON_CLK_EN_V 0x00000001U
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#define MODEM_LPCON_CLK_EN_S 0
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#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
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/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S))
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_LP_TIMER_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3
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/** MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4
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#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
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/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S))
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
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/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_COEX_LP_CLK_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
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/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
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/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
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/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
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/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
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/** MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
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#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC)
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/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_WIFI_LP_CLK_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3
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/** MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4
|
||||
|
||||
#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
|
||||
/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2))
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2))
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2
|
||||
/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S))
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3
|
||||
/** MODEM_LPCON_MODEM_SRC_CLK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
|
||||
/** MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W; bitpos: [1:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M (MODEM_LPCON_CLK_MODEM_AON_FORCE_V << MODEM_LPCON_CLK_MODEM_AON_FORCE_S)
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0
|
||||
/** MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2))
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V << MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2
|
||||
|
||||
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
|
||||
/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S))
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3
|
||||
/** MODEM_LPCON_MODEM_32K_CLK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
|
||||
/** MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S)
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0
|
||||
|
||||
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
|
||||
/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3
|
||||
/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
|
||||
/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_COEX_EN_S 1
|
||||
/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_CLK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
|
||||
/** MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S)
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0
|
||||
/** MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
|
||||
#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_COEX_EN_S 1
|
||||
/** MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
|
||||
/** MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S)
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3
|
||||
|
||||
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C)
|
||||
/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4))
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4))
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_S 4
|
||||
/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
|
||||
/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
|
||||
/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_COEX_FO_S 1
|
||||
/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_CLK_CONF_FORCE_ON_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
|
||||
/** MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S)
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0
|
||||
/** MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
|
||||
#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_COEX_FO_S 1
|
||||
/** MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
|
||||
/** MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S)
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
|
||||
/** MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [4]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4))
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S)
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_S 4
|
||||
|
||||
#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
|
||||
/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
|
||||
/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24
|
||||
/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20
|
||||
/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF
|
||||
/** MODEM_LPCON_CLK_CONF_POWER_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
|
||||
/** MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16
|
||||
/** MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20
|
||||
/** MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24
|
||||
/** MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
|
||||
|
||||
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
|
||||
/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_RST_LP_TIMER (BIT(3))
|
||||
#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3))
|
||||
#define MODEM_LPCON_RST_LP_TIMER_V 0x1
|
||||
#define MODEM_LPCON_RST_LP_TIMER_S 3
|
||||
/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
|
||||
#define MODEM_LPCON_RST_I2C_MST_M (BIT(2))
|
||||
#define MODEM_LPCON_RST_I2C_MST_V 0x1
|
||||
#define MODEM_LPCON_RST_I2C_MST_S 2
|
||||
/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_RST_COEX (BIT(1))
|
||||
#define MODEM_LPCON_RST_COEX_M (BIT(1))
|
||||
#define MODEM_LPCON_RST_COEX_V 0x1
|
||||
#define MODEM_LPCON_RST_COEX_S 1
|
||||
/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_RST_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
|
||||
/** MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_WIFIPWR (BIT(0))
|
||||
#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0))
|
||||
#define MODEM_LPCON_RST_WIFIPWR_V 0x1
|
||||
#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S)
|
||||
#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_WIFIPWR_S 0
|
||||
/** MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_COEX (BIT(1))
|
||||
#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
|
||||
#define MODEM_LPCON_RST_COEX_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_COEX_S 1
|
||||
/** MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
|
||||
#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
|
||||
#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_I2C_MST_S 2
|
||||
/** MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_LP_TIMER (BIT(3))
|
||||
#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S)
|
||||
#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_LP_TIMER_S 3
|
||||
/** MODEM_LPCON_RST_DCMEM : WO; bitpos: [4]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_DCMEM (BIT(4))
|
||||
#define MODEM_LPCON_RST_DCMEM_M (MODEM_LPCON_RST_DCMEM_V << MODEM_LPCON_RST_DCMEM_S)
|
||||
#define MODEM_LPCON_RST_DCMEM_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_DCMEM_S 4
|
||||
|
||||
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
|
||||
/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S))
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F
|
||||
/** MODEM_LPCON_TICK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
|
||||
/** MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 39;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003FU
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M (MODEM_LPCON_MODEM_PWR_TICK_TARGET_V << MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x0000003FU
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0
|
||||
|
||||
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C)
|
||||
/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23
|
||||
/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20
|
||||
/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19
|
||||
/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16
|
||||
/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_BC_MEM_FORCE (BIT(15))
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15))
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_S 15
|
||||
/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_BC_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S))
|
||||
#define MODEM_LPCON_BC_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_BC_MEM_MODE_S 12
|
||||
/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11))
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11))
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_S 11
|
||||
/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S))
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_S 8
|
||||
/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7))
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7))
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_S 7
|
||||
/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_AGC_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S))
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_S 4
|
||||
/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_DC_MEM_FORCE (BIT(3))
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3))
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_S 3
|
||||
/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_DC_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S))
|
||||
#define MODEM_LPCON_DC_MEM_MODE_V 0x7
|
||||
/** MODEM_LPCON_MEM_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2c)
|
||||
/** MODEM_LPCON_DC_MEM_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DC_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_DC_MEM_MODE_M (MODEM_LPCON_DC_MEM_MODE_V << MODEM_LPCON_DC_MEM_MODE_S)
|
||||
#define MODEM_LPCON_DC_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_DC_MEM_MODE_S 0
|
||||
/** MODEM_LPCON_DC_MEM_FORCE : R/W; bitpos: [3]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DC_MEM_FORCE (BIT(3))
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_M (MODEM_LPCON_DC_MEM_FORCE_V << MODEM_LPCON_DC_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_S 3
|
||||
/** MODEM_LPCON_AGC_MEM_MODE : R/W; bitpos: [6:4]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_AGC_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_M (MODEM_LPCON_AGC_MEM_MODE_V << MODEM_LPCON_AGC_MEM_MODE_S)
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_S 4
|
||||
/** MODEM_LPCON_AGC_MEM_FORCE : R/W; bitpos: [7]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7))
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_M (MODEM_LPCON_AGC_MEM_FORCE_V << MODEM_LPCON_AGC_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_S 7
|
||||
/** MODEM_LPCON_PBUS_MEM_MODE : R/W; bitpos: [10:8]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_M (MODEM_LPCON_PBUS_MEM_MODE_V << MODEM_LPCON_PBUS_MEM_MODE_S)
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_S 8
|
||||
/** MODEM_LPCON_PBUS_MEM_FORCE : R/W; bitpos: [11]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11))
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_M (MODEM_LPCON_PBUS_MEM_FORCE_V << MODEM_LPCON_PBUS_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_S 11
|
||||
/** MODEM_LPCON_BC_MEM_MODE : R/W; bitpos: [14:12]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_BC_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_BC_MEM_MODE_M (MODEM_LPCON_BC_MEM_MODE_V << MODEM_LPCON_BC_MEM_MODE_S)
|
||||
#define MODEM_LPCON_BC_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_BC_MEM_MODE_S 12
|
||||
/** MODEM_LPCON_BC_MEM_FORCE : R/W; bitpos: [15]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_BC_MEM_FORCE (BIT(15))
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_M (MODEM_LPCON_BC_MEM_FORCE_V << MODEM_LPCON_BC_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_S 15
|
||||
/** MODEM_LPCON_I2C_MST_MEM_MODE : R/W; bitpos: [18:16]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_M (MODEM_LPCON_I2C_MST_MEM_MODE_V << MODEM_LPCON_I2C_MST_MEM_MODE_S)
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16
|
||||
/** MODEM_LPCON_I2C_MST_MEM_FORCE : R/W; bitpos: [19]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (MODEM_LPCON_I2C_MST_MEM_FORCE_V << MODEM_LPCON_I2C_MST_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19
|
||||
/** MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W; bitpos: [22:20]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M (MODEM_LPCON_CHAN_FREQ_MEM_MODE_V << MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20
|
||||
/** MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W; bitpos: [23]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23
|
||||
|
||||
#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30)
|
||||
/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S))
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF
|
||||
/** MODEM_LPCON_MEM_RF1_AUX_CTRL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30)
|
||||
/** MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0
|
||||
|
||||
#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34)
|
||||
/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S))
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF
|
||||
/** MODEM_LPCON_MEM_RF2_AUX_CTRL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34)
|
||||
/** MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0
|
||||
|
||||
#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38)
|
||||
/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_AGC_MEM_EN (BIT(2))
|
||||
#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2))
|
||||
#define MODEM_LPCON_AGC_MEM_EN_V 0x1
|
||||
#define MODEM_LPCON_AGC_MEM_EN_S 2
|
||||
/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_PBUS_MEM_EN (BIT(1))
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1))
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_V 0x1
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_S 1
|
||||
/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_APB_MEM_SEL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38)
|
||||
/** MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (MODEM_LPCON_CHAN_FREQ_MEM_EN_V << MODEM_LPCON_CHAN_FREQ_MEM_EN_S)
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0
|
||||
/** MODEM_LPCON_PBUS_MEM_EN : R/W; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_PBUS_MEM_EN (BIT(1))
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_M (MODEM_LPCON_PBUS_MEM_EN_V << MODEM_LPCON_PBUS_MEM_EN_S)
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_S 1
|
||||
/** MODEM_LPCON_AGC_MEM_EN : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_AGC_MEM_EN (BIT(2))
|
||||
#define MODEM_LPCON_AGC_MEM_EN_M (MODEM_LPCON_AGC_MEM_EN_V << MODEM_LPCON_AGC_MEM_EN_S)
|
||||
#define MODEM_LPCON_AGC_MEM_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_AGC_MEM_EN_S 2
|
||||
|
||||
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C)
|
||||
/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_DATE 0x0FFFFFFF
|
||||
#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S))
|
||||
#define MODEM_LPCON_DATE_V 0xFFFFFFF
|
||||
/** MODEM_LPCON_DCMEM_VALID_0_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_0_REG (DR_REG_MODEM_LPCON_BASE + 0x3c)
|
||||
/** MODEM_LPCON__DCMEM_VALID_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_0 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_0_M (MODEM_LPCON__DCMEM_VALID_0_V << MODEM_LPCON__DCMEM_VALID_0_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_0_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_0_S 0
|
||||
|
||||
/** MODEM_LPCON_DCMEM_VALID_1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_1_REG (DR_REG_MODEM_LPCON_BASE + 0x40)
|
||||
/** MODEM_LPCON__DCMEM_VALID_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_1 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_1_M (MODEM_LPCON__DCMEM_VALID_1_V << MODEM_LPCON__DCMEM_VALID_1_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_1_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_1_S 0
|
||||
|
||||
/** MODEM_LPCON_DCMEM_VALID_2_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_2_REG (DR_REG_MODEM_LPCON_BASE + 0x44)
|
||||
/** MODEM_LPCON__DCMEM_VALID_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_2 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_2_M (MODEM_LPCON__DCMEM_VALID_2_V << MODEM_LPCON__DCMEM_VALID_2_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_2_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_2_S 0
|
||||
|
||||
/** MODEM_LPCON_DCMEM_VALID_3_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_3_REG (DR_REG_MODEM_LPCON_BASE + 0x48)
|
||||
/** MODEM_LPCON__DCMEM_VALID_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_3 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_3_M (MODEM_LPCON__DCMEM_VALID_3_V << MODEM_LPCON__DCMEM_VALID_3_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_3_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_3_S 0
|
||||
|
||||
/** MODEM_LPCON_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x4c)
|
||||
/** MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 37814640;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DATE 0x0FFFFFFFU
|
||||
#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
|
||||
#define MODEM_LPCON_DATE_V 0x0FFFFFFFU
|
||||
#define MODEM_LPCON_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
@@ -10,240 +10,228 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} test_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_lp_timer_sel_osc_slow : 1;
|
||||
uint32_t clk_lp_timer_sel_osc_fast : 1;
|
||||
uint32_t clk_lp_timer_sel_xtal : 1;
|
||||
uint32_t clk_lp_timer_sel_xtal32k : 1;
|
||||
uint32_t clk_lp_timer_div_num : 12;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_timer_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_coex_lp_sel_osc_slow : 1;
|
||||
uint32_t clk_coex_lp_sel_osc_fast : 1;
|
||||
uint32_t clk_coex_lp_sel_xtal : 1;
|
||||
uint32_t clk_coex_lp_sel_xtal32k : 1;
|
||||
uint32_t clk_coex_lp_div_num : 12;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} coex_lp_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_lp_sel_osc_slow: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_osc_fast: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal : 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal32k: 1;
|
||||
uint32_t clk_wifipwr_lp_div_num : 12;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} wifi_lp_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_modem_aon_force : 2;
|
||||
uint32_t modem_pwr_clk_src_fo : 1;
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_src_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_modem_32k_sel : 2;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_32k_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_en : 1;
|
||||
uint32_t clk_coex_en : 1;
|
||||
uint32_t clk_i2c_mst_en : 1;
|
||||
uint32_t clk_lp_timer_en : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t reserved14 : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 1;
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t reserved19 : 1;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_fo : 1;
|
||||
uint32_t clk_coex_fo : 1;
|
||||
uint32_t clk_i2c_mst_fo : 1;
|
||||
uint32_t clk_lp_timer_fo : 1;
|
||||
uint32_t clk_fe_mem_fo : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t reserved14 : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 1;
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t reserved19 : 1;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 16;
|
||||
uint32_t clk_wifipwr_st_map : 4;
|
||||
uint32_t clk_coex_st_map : 4;
|
||||
uint32_t clk_i2c_mst_st_map : 4;
|
||||
uint32_t clk_lp_apb_st_map : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_power_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rst_wifipwr : 1;
|
||||
uint32_t rst_coex : 1;
|
||||
uint32_t rst_i2c_mst : 1;
|
||||
uint32_t rst_lp_timer : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t reserved14 : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 1;
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t reserved19 : 1;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rst_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t modem_pwr_tick_target : 6;
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dc_mem_mode : 3;
|
||||
uint32_t dc_mem_force : 1;
|
||||
uint32_t agc_mem_mode : 3;
|
||||
uint32_t agc_mem_force : 1;
|
||||
uint32_t pbus_mem_mode : 3;
|
||||
uint32_t pbus_mem_force : 1;
|
||||
uint32_t bc_mem_mode : 3;
|
||||
uint32_t bc_mem_force : 1;
|
||||
uint32_t i2c_mst_mem_mode : 3;
|
||||
uint32_t i2c_mst_mem_force : 1;
|
||||
uint32_t chan_freq_mem_mode : 3;
|
||||
uint32_t chan_freq_mem_force : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_conf;
|
||||
uint32_t mem_rf1_aux_ctrl;
|
||||
uint32_t mem_rf2_aux_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t chan_freq_mem_en : 1;
|
||||
uint32_t pbus_mem_en : 1;
|
||||
uint32_t agc_mem_en : 1;
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_mem_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
/** Group: configure_register */
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved_1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_test_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_lp_timer_sel_osc_slow: 1;
|
||||
uint32_t clk_lp_timer_sel_osc_fast: 1;
|
||||
uint32_t clk_lp_timer_sel_xtal: 1;
|
||||
uint32_t clk_lp_timer_sel_xtal32k: 1;
|
||||
uint32_t clk_lp_timer_div_num: 12;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_lp_timer_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_coex_lp_sel_osc_slow: 1;
|
||||
uint32_t clk_coex_lp_sel_osc_fast: 1;
|
||||
uint32_t clk_coex_lp_sel_xtal: 1;
|
||||
uint32_t clk_coex_lp_sel_xtal32k: 1;
|
||||
uint32_t clk_coex_lp_div_num: 12;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_coex_lp_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_lp_sel_osc_slow: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_osc_fast: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal32k: 1;
|
||||
uint32_t clk_wifipwr_lp_div_num: 12;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_wifi_lp_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_modem_aon_force: 2;
|
||||
uint32_t modem_pwr_clk_src_fo: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_modem_src_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_modem_32k_sel: 2;
|
||||
uint32_t reserved_2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_modem_32k_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_en: 1;
|
||||
uint32_t clk_coex_en: 1;
|
||||
uint32_t clk_i2c_mst_en: 1;
|
||||
uint32_t clk_lp_timer_en: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_fo: 1;
|
||||
uint32_t clk_coex_fo: 1;
|
||||
uint32_t clk_i2c_mst_fo: 1;
|
||||
uint32_t clk_lp_timer_fo: 1;
|
||||
uint32_t clk_fe_mem_fo: 1;
|
||||
uint32_t reserved_5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_clk_conf_force_on_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 16;
|
||||
uint32_t clk_wifipwr_st_map: 4;
|
||||
uint32_t clk_coex_st_map: 4;
|
||||
uint32_t clk_i2c_mst_st_map: 4;
|
||||
uint32_t clk_lp_apb_st_map: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_clk_conf_power_st_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t rst_wifipwr: 1;
|
||||
uint32_t rst_coex: 1;
|
||||
uint32_t rst_i2c_mst: 1;
|
||||
uint32_t rst_lp_timer: 1;
|
||||
uint32_t rst_dcmem: 1;
|
||||
uint32_t reserved_5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_rst_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_pwr_tick_target: 6;
|
||||
uint32_t reserved_6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_tick_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t dc_mem_mode: 3;
|
||||
uint32_t dc_mem_force: 1;
|
||||
uint32_t agc_mem_mode: 3;
|
||||
uint32_t agc_mem_force: 1;
|
||||
uint32_t pbus_mem_mode: 3;
|
||||
uint32_t pbus_mem_force: 1;
|
||||
uint32_t bc_mem_mode: 3;
|
||||
uint32_t bc_mem_force: 1;
|
||||
uint32_t i2c_mst_mem_mode: 3;
|
||||
uint32_t i2c_mst_mem_force: 1;
|
||||
uint32_t chan_freq_mem_mode: 3;
|
||||
uint32_t chan_freq_mem_force: 1;
|
||||
uint32_t reserved_24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_mem_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_pwr_rf1_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_mem_rf1_aux_ctrl_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_pwr_rf2_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_mem_rf2_aux_ctrl_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t chan_freq_mem_en: 1;
|
||||
uint32_t pbus_mem_en: 1;
|
||||
uint32_t agc_mem_en: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_apb_mem_sel_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_0: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_0_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_1: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_1_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_2: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_2_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_3: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_3_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_date_t;
|
||||
|
||||
typedef struct {
|
||||
volatile modem_lpcon_test_conf_t test_conf;
|
||||
volatile modem_lpcon_lp_timer_conf_t lp_timer_conf;
|
||||
volatile modem_lpcon_coex_lp_clk_conf_t coex_lp_clk_conf;
|
||||
volatile modem_lpcon_wifi_lp_clk_conf_t wifi_lp_clk_conf;
|
||||
volatile modem_lpcon_modem_src_clk_conf_t modem_src_clk_conf;
|
||||
volatile modem_lpcon_modem_32k_clk_conf_t modem_32k_clk_conf;
|
||||
volatile modem_lpcon_clk_conf_t clk_conf;
|
||||
volatile modem_lpcon_clk_conf_force_on_t clk_conf_force_on;
|
||||
volatile modem_lpcon_clk_conf_power_st_t clk_conf_power_st;
|
||||
volatile modem_lpcon_rst_conf_t rst_conf;
|
||||
volatile modem_lpcon_tick_conf_t tick_conf;
|
||||
volatile modem_lpcon_mem_conf_t mem_conf;
|
||||
volatile modem_lpcon_mem_rf1_aux_ctrl_t mem_rf1_aux_ctrl;
|
||||
volatile modem_lpcon_mem_rf2_aux_ctrl_t mem_rf2_aux_ctrl;
|
||||
volatile modem_lpcon_apb_mem_sel_t apb_mem_sel;
|
||||
volatile modem_lpcon_dcmem_valid_0_t dcmem_valid_0;
|
||||
volatile modem_lpcon_dcmem_valid_1_t dcmem_valid_1;
|
||||
volatile modem_lpcon_dcmem_valid_2_t dcmem_valid_2;
|
||||
volatile modem_lpcon_dcmem_valid_3_t dcmem_valid_3;
|
||||
volatile modem_lpcon_date_t date;
|
||||
} modem_lpcon_dev_t;
|
||||
|
||||
extern modem_lpcon_dev_t MODEM_LPCON;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure");
|
||||
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x50, "Invalid size of modem_lpcon_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
@@ -10,164 +10,194 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t modem_ant_force_sel_bt : 1;
|
||||
uint32_t modem_ant_force_sel_wifi : 1;
|
||||
uint32_t fpga_debug_clkswitch : 1;
|
||||
uint32_t fpga_debug_clk80 : 1;
|
||||
uint32_t fpga_debug_clk40 : 1;
|
||||
uint32_t fpga_debug_clk20 : 1;
|
||||
uint32_t fpga_debug_clk10 : 1;
|
||||
uint32_t modem_mem_mode_force : 1;
|
||||
uint32_t modem_dis_wifi6_force : 1;
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} test_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pwdet_sar_clock_ena : 1;
|
||||
uint32_t pwdet_clk_div_num : 8;
|
||||
uint32_t clk_tx_dac_inv_ena : 1;
|
||||
uint32_t clk_rx_adc_inv_ena : 1;
|
||||
uint32_t clk_pwdet_adc_inv_ena : 1;
|
||||
uint32_t clk_i2c_mst_sel_160m : 1;
|
||||
uint32_t reserved13 : 8;
|
||||
uint32_t clk_data_dump_mux : 1;
|
||||
uint32_t clk_etm_en : 1;
|
||||
uint32_t clk_zb_apb_en : 1;
|
||||
uint32_t clk_zbmac_en : 1;
|
||||
uint32_t clk_modem_sec_ecb_en : 1;
|
||||
uint32_t clk_modem_sec_ccm_en : 1;
|
||||
uint32_t clk_modem_sec_bah_en : 1;
|
||||
uint32_t clk_modem_sec_apb_en : 1;
|
||||
uint32_t clk_modem_sec_en : 1;
|
||||
uint32_t clk_ble_timer_en : 1;
|
||||
uint32_t clk_data_dump_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_fo : 1;
|
||||
uint32_t clk_wifimac_fo : 1;
|
||||
uint32_t clk_wifi_apb_fo : 1;
|
||||
uint32_t clk_fe_fo : 1;
|
||||
uint32_t clk_fe_apb_fo : 1;
|
||||
uint32_t clk_btbb_fo : 1;
|
||||
uint32_t clk_btmac_fo : 1;
|
||||
uint32_t clk_bt_apb_fo : 1;
|
||||
uint32_t clk_zbmac_fo : 1;
|
||||
uint32_t clk_zbmac_apb_fo : 1;
|
||||
uint32_t reserved10 : 13;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t clk_etm_fo : 1;
|
||||
uint32_t clk_modem_sec_fo : 1;
|
||||
uint32_t clk_ble_timer_fo : 1;
|
||||
uint32_t clk_data_dump_fo : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 8;
|
||||
uint32_t clk_zb_st_map : 4;
|
||||
uint32_t clk_fe_st_map : 4;
|
||||
uint32_t clk_bt_st_map : 4;
|
||||
uint32_t clk_wifi_st_map : 4;
|
||||
uint32_t clk_modem_peri_st_map : 4;
|
||||
uint32_t clk_modem_apb_st_map : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_power_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t rst_wifibb : 1;
|
||||
uint32_t rst_wifimac : 1;
|
||||
uint32_t rst_fe_pwdet_adc : 1;
|
||||
uint32_t rst_fe_dac : 1;
|
||||
uint32_t rst_fe_adc : 1;
|
||||
uint32_t rst_fe_ahb : 1;
|
||||
uint32_t rst_fe : 1;
|
||||
uint32_t rst_btmac_apb : 1;
|
||||
uint32_t rst_btmac : 1;
|
||||
uint32_t rst_btbb_apb : 1;
|
||||
uint32_t rst_btbb : 1;
|
||||
uint32_t reserved19 : 3;
|
||||
uint32_t rst_etm : 1;
|
||||
uint32_t rst_zbmac_apb : 1;
|
||||
uint32_t rst_zbmac : 1;
|
||||
uint32_t rst_modem_ecb : 1;
|
||||
uint32_t rst_modem_ccm : 1;
|
||||
uint32_t rst_modem_bah : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t rst_modem_sec : 1;
|
||||
uint32_t rst_ble_timer : 1;
|
||||
uint32_t rst_data_dump : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_rst_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_22m_en : 1;
|
||||
uint32_t clk_wifibb_40m_en : 1;
|
||||
uint32_t clk_wifibb_44m_en : 1;
|
||||
uint32_t clk_wifibb_80m_en : 1;
|
||||
uint32_t clk_wifibb_40x_en : 1;
|
||||
uint32_t clk_wifibb_80x_en : 1;
|
||||
uint32_t clk_wifibb_40x1_en : 1;
|
||||
uint32_t clk_wifibb_80x1_en : 1;
|
||||
uint32_t clk_wifibb_160x1_en : 1;
|
||||
uint32_t clk_wifimac_en : 1;
|
||||
uint32_t clk_wifi_apb_en : 1;
|
||||
uint32_t clk_fe_20m_en : 1;
|
||||
uint32_t clk_fe_40m_en : 1;
|
||||
uint32_t clk_fe_80m_en : 1;
|
||||
uint32_t clk_fe_160m_en : 1;
|
||||
uint32_t clk_fe_apb_en : 1;
|
||||
uint32_t clk_bt_apb_en : 1;
|
||||
uint32_t clk_btbb_en : 1;
|
||||
uint32_t clk_btmac_en : 1;
|
||||
uint32_t clk_fe_pwdet_adc_en : 1;
|
||||
uint32_t clk_fe_adc_en : 1;
|
||||
uint32_t clk_fe_dac_en : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf1;
|
||||
uint32_t wifi_bb_cfg;
|
||||
uint32_t mem_rf1_conf;
|
||||
uint32_t mem_rf2_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
/** Group: configure_register */
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t modem_ant_force_sel_bt: 1;
|
||||
uint32_t modem_ant_force_sel_wifi: 1;
|
||||
uint32_t fpga_debug_clkswitch: 1;
|
||||
uint32_t fpga_debug_clk80: 1;
|
||||
uint32_t fpga_debug_clk40: 1;
|
||||
uint32_t fpga_debug_clk20: 1;
|
||||
uint32_t fpga_debug_clk10: 1;
|
||||
uint32_t modem_mem_mode_force: 1;
|
||||
uint32_t modem_dis_wifi6_force: 1;
|
||||
uint32_t reserved_10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_test_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t pwdet_sar_clock_ena: 1;
|
||||
uint32_t pwdet_clk_div_num: 8;
|
||||
uint32_t clk_tx_dac_inv_ena: 1;
|
||||
uint32_t clk_rx_adc_inv_ena: 1;
|
||||
uint32_t clk_pwdet_adc_inv_ena: 1;
|
||||
uint32_t clk_i2c_mst_sel_160m: 1;
|
||||
uint32_t reserved_13: 8;
|
||||
uint32_t clk_data_dump_mux: 1;
|
||||
uint32_t clk_etm_en: 1;
|
||||
uint32_t clk_zb_apb_en: 1;
|
||||
uint32_t clk_zbmac_en: 1;
|
||||
uint32_t clk_modem_sec_ecb_en: 1;
|
||||
uint32_t clk_modem_sec_ccm_en: 1;
|
||||
uint32_t clk_modem_sec_bah_en: 1;
|
||||
uint32_t clk_modem_sec_apb_en: 1;
|
||||
uint32_t clk_modem_sec_en: 1;
|
||||
uint32_t clk_ble_timer_en: 1;
|
||||
uint32_t clk_data_dump_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_fo: 1;
|
||||
uint32_t clk_wifimac_fo: 1;
|
||||
uint32_t clk_wifi_apb_fo: 1;
|
||||
uint32_t clk_fe_fo: 1;
|
||||
uint32_t clk_fe_apb_fo: 1;
|
||||
uint32_t clk_btbb_fo: 1;
|
||||
uint32_t clk_btmac_fo: 1;
|
||||
uint32_t clk_bt_apb_fo: 1;
|
||||
uint32_t clk_zbmac_fo: 1;
|
||||
uint32_t clk_zbmac_apb_fo: 1;
|
||||
uint32_t reserved_10: 18;
|
||||
uint32_t clk_etm_fo: 1;
|
||||
uint32_t clk_modem_sec_fo: 1;
|
||||
uint32_t clk_ble_timer_fo: 1;
|
||||
uint32_t clk_data_dump_fo: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf_force_on_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 8;
|
||||
uint32_t clk_zb_st_map: 4;
|
||||
uint32_t clk_fe_st_map: 4;
|
||||
uint32_t clk_bt_st_map: 4;
|
||||
uint32_t clk_wifi_st_map: 4;
|
||||
uint32_t clk_modem_peri_st_map: 4;
|
||||
uint32_t clk_modem_apb_st_map: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf_power_st_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 8;
|
||||
uint32_t rst_wifibb: 1;
|
||||
uint32_t rst_wifimac: 1;
|
||||
uint32_t rst_fe_pwdet_adc: 1;
|
||||
uint32_t rst_fe_dac: 1;
|
||||
uint32_t rst_fe_adc: 1;
|
||||
uint32_t rst_fe_ahb: 1;
|
||||
uint32_t rst_fe: 1;
|
||||
uint32_t rst_btmac_apb: 1;
|
||||
uint32_t rst_btmac: 1;
|
||||
uint32_t rst_btbb_apb: 1;
|
||||
uint32_t rst_btbb: 1;
|
||||
uint32_t reserved_19: 3;
|
||||
uint32_t rst_etm: 1;
|
||||
uint32_t rst_zbmac_apb: 1;
|
||||
uint32_t rst_zbmac: 1;
|
||||
uint32_t rst_modem_ecb: 1;
|
||||
uint32_t rst_modem_ccm: 1;
|
||||
uint32_t rst_modem_bah: 1;
|
||||
uint32_t reserved_28: 1;
|
||||
uint32_t rst_modem_sec: 1;
|
||||
uint32_t rst_ble_timer: 1;
|
||||
uint32_t rst_data_dump: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_modem_rst_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_22m_en: 1;
|
||||
uint32_t clk_wifibb_40m_en: 1;
|
||||
uint32_t clk_wifibb_44m_en: 1;
|
||||
uint32_t clk_wifibb_80m_en: 1;
|
||||
uint32_t clk_wifibb_40x_en: 1;
|
||||
uint32_t clk_wifibb_80x_en: 1;
|
||||
uint32_t clk_wifibb_40x1_en: 1;
|
||||
uint32_t clk_wifibb_80x1_en: 1;
|
||||
uint32_t clk_wifibb_160x1_en: 1;
|
||||
uint32_t clk_wifimac_en: 1;
|
||||
uint32_t clk_wifi_apb_en: 1;
|
||||
uint32_t clk_fe_20m_en: 1;
|
||||
uint32_t clk_fe_40m_en: 1;
|
||||
uint32_t clk_fe_80m_en: 1;
|
||||
uint32_t clk_fe_160m_en: 1;
|
||||
uint32_t clk_fe_apb_en: 1;
|
||||
uint32_t clk_bt_apb_en: 1;
|
||||
uint32_t clk_btbb_en: 1;
|
||||
uint32_t clk_btmac_en: 1;
|
||||
uint32_t clk_fe_pwdet_adc_en: 1;
|
||||
uint32_t clk_fe_adc_en: 1;
|
||||
uint32_t clk_fe_dac_en: 1;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t wifi_bb_cfg: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_wifi_bb_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t fe_cfg: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_fe_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_rf1_mem_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_mem_rf1_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_rf2_mem_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_mem_rf2_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_date_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile modem_syscon_test_conf_reg_t test_conf;
|
||||
volatile modem_syscon_clk_conf_reg_t clk_conf;
|
||||
volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
|
||||
volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st;
|
||||
volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
|
||||
volatile modem_syscon_clk_conf1_reg_t clk_conf1;
|
||||
volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
|
||||
volatile modem_syscon_fe_cfg_reg_t fe_cfg;
|
||||
volatile modem_syscon_mem_rf1_conf_reg_t mem_rf1_conf;
|
||||
volatile modem_syscon_mem_rf2_conf_reg_t mem_rf2_conf;
|
||||
volatile modem_syscon_date_reg_t date;
|
||||
} modem_syscon_dev_t;
|
||||
|
||||
extern modem_syscon_dev_t MODEM_SYSCON;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
|
||||
_Static_assert(sizeof(modem_syscon_dev_t) == 0x2c, "Invalid size of modem_syscon_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Reference in New Issue
Block a user