From acda9a7a7ed889674477f2bb7062ef9839ecbc60 Mon Sep 17 00:00:00 2001 From: armando Date: Wed, 14 May 2025 11:36:14 +0800 Subject: [PATCH 1/2] feat(cache): supported cache driver on h21 --- .../esp_rom/esp32h21/include/esp32h21/rom/cache.h | 2 -- components/esp_system/port/soc/esp32h21/Kconfig.cache | 11 +++++++++++ components/hal/esp32h21/include/hal/cache_ll.h | 9 ++------- 3 files changed, 13 insertions(+), 9 deletions(-) create mode 100644 components/esp_system/port/soc/esp32h21/Kconfig.cache diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h b/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h index eafc044bc4..ab7e90f47a 100644 --- a/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h @@ -13,8 +13,6 @@ extern "C" { #endif -//TODO: [ESP32H21] IDF-11525 - /** \defgroup cache_apis, cache operation related apis * @brief cache apis */ diff --git a/components/esp_system/port/soc/esp32h21/Kconfig.cache b/components/esp_system/port/soc/esp32h21/Kconfig.cache new file mode 100644 index 0000000000..eaa2069e97 --- /dev/null +++ b/components/esp_system/port/soc/esp32h21/Kconfig.cache @@ -0,0 +1,11 @@ +menu "Cache config" + + config CACHE_L1_CACHE_SIZE + hex + default 0x4000 + + config CACHE_L1_CACHE_LINE_SIZE + int + default 32 + +endmenu # Cache config diff --git a/components/hal/esp32h21/include/hal/cache_ll.h b/components/hal/esp32h21/include/hal/cache_ll.h index 77fcdfca2f..cd0f1cfcbd 100644 --- a/components/hal/esp32h21/include/hal/cache_ll.h +++ b/components/hal/esp32h21/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,13 +10,12 @@ #include #include "soc/cache_reg.h" +#include "soc/cache_struct.h" #include "soc/ext_mem_defs.h" #include "hal/cache_types.h" #include "hal/assert.h" #include "rom/cache.h" -//TODO: [ESP32H21] IDF-11525, inherit from h2 - #ifdef __cplusplus extern "C" { #endif @@ -187,7 +186,6 @@ __attribute__((always_inline)) #endif static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len) { - //TODO: [ESP32H21] IDF-11525, inherit from h2 HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); cache_bus_mask_t mask = (cache_bus_mask_t)0; @@ -213,7 +211,6 @@ __attribute__((always_inline)) #endif static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) { - //TODO: [ESP32H21] IDF-11525, inherit from h2 HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); //On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); @@ -236,7 +233,6 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma __attribute__((always_inline)) static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) { - //TODO: [ESP32H21] IDF-11525, inherit from h2 HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL); //On esp32h21, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); @@ -263,7 +259,6 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m __attribute__((always_inline)) static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id) { - //TODO: [ESP32H21] IDF-11525, inherit from h2 bool valid = false; uint32_t vaddr_end = vaddr_start + len - 1; From 0c6aeecde43ce202c9772be4d9bf9548ad43f78d Mon Sep 17 00:00:00 2001 From: armando Date: Wed, 14 May 2025 11:36:50 +0800 Subject: [PATCH 2/2] feat(cache): supported cache panic driver on h21 --- .../port/soc/esp32h21/cache_err_int.c | 11 ++++++++--- components/hal/esp32h21/include/hal/cache_ll.h | 18 ++++++++++++++---- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/components/esp_system/port/soc/esp32h21/cache_err_int.c b/components/esp_system/port/soc/esp32h21/cache_err_int.c index c5085eb1ea..05a4cbd893 100644 --- a/components/esp_system/port/soc/esp32h21/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h21/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,8 +19,6 @@ #include "hal/cache_ll.h" #include "esp_private/cache_err_int.h" -// TODO: [ESP32H21] IDF-11524 - static const char *TAG = "CACHE_ERR"; const char cache_error_msg[] = "Cache access error"; @@ -64,6 +62,13 @@ void esp_cache_err_int_init(void) esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); + /** + * Here we + * 1. enable the cache fail tracer to take cache error interrupt into effect. + * 2. clear potential cache error interrupt raw bits + * 3. enable cache error interrupt en bits + */ + cache_ll_l1_enable_fail_tracer(0, true); /* On the hardware side, start by clearing all the bits responsible for cache access error */ cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); /* Then enable cache access error interrupts. */ diff --git a/components/hal/esp32h21/include/hal/cache_ll.h b/components/hal/esp32h21/include/hal/cache_ll.h index cd0f1cfcbd..2f8d8a489e 100644 --- a/components/hal/esp32h21/include/hal/cache_ll.h +++ b/components/hal/esp32h21/include/hal/cache_ll.h @@ -273,6 +273,17 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32 return valid; } +/** + * Enable the Cache fail tracer + * + * @param cache_id cache ID + * @param en enable / disable + */ +static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en) +{ + CACHE.trace_ena.l1_cache_trace_ena = en; +} + /*------------------------------------------------------------------------------ * Interrupt *----------------------------------------------------------------------------*/ @@ -284,7 +295,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32 */ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) { - //TODO: [ESP32H21] IDF-11525 + CACHE.l1_cache_acs_fail_int_ena.val |= mask; } /** @@ -295,7 +306,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3 */ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) { - //TODO: [ESP32H21] IDF-11525 + CACHE.l1_cache_acs_fail_int_clr.val = mask; } /** @@ -308,8 +319,7 @@ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32 */ static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) { - //TODO: [ESP32H21] IDF-11525 - return 0; + return CACHE.l1_cache_acs_fail_int_st.val & mask; } #ifdef __cplusplus