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Udate instruction set documentation for Esp32 and Esp32s2.

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Sleep instruction removed from S2 instruction set.
LDx/STx instructions descritioin fix offset range to 13 bits (11 bits signed 32 bit words offset).
Remove I2C RD/WR operations from S2.
This commit is contained in:
Dmitry Yakovlev
2020-10-17 02:44:47 +08:00
committed by Krzysztof Budzynski
parent 0289d1cc81
commit 0a8afd13a2
4 changed files with 44 additions and 84 deletions
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docs/en/api-guides/ulp_instruction_set.rst
+3 -3
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@@ -358,7 +358,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
**Operands**
- *Rsrc* – Register R[0..3], holds the 16-bit value to store
- *Rdst* – Register R[0..3], address of the destination, in 32-bit words
- *Offset* – 10-bit signed value, offset in bytes
- *Offset* – 13-bit signed value, offset in bytes
**Cycles**
4 cycles to execute, 4 cycles to fetch next instruction
@@ -395,7 +395,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
*Rsrc* – Register R[0..3], holds address of destination, in 32-bit words
*Offset* – 10-bit signed value, offset in bytes
*Offset* – 13-bit signed value, offset in bytes
**Cycles**
4 cycles to execute, 4 cycles to fetch next instruction
@@ -786,7 +786,7 @@ Note that when accessing RTC memories and RTC registers, ULP coprocessor has low
**Operands**
- *Rdst* – Destination Register R[0..3], result will be stored to this register
- *Sar_sel* – Select ADC: 0 = SARADC1, 1 = SARADC2
- *Mux* - selected PAD, SARADC Pad[Mux+1] is enabled
- *Mux* - selected PAD, SARADC Pad[Mux-1] is enabled. If the user passes Mux value 1, then ADC pad 0 gets used.
**Cycles**
``23 + max(1, SAR_AMP_WAIT1) + max(1, SAR_AMP_WAIT2) + max(1, SAR_AMP_WAIT3) + SARx_SAMPLE_CYCLE + SARx_SAMPLE_BIT`` cycles to execute, 4 cycles to fetch next instruction