diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index b636530415..965c7627f9 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -246,11 +246,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); + ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0); REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } @@ -268,11 +268,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); + ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0); REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } diff --git a/components/soc/esp32c61/register/soc/cache_reg.h b/components/soc/esp32c61/register/soc/cache_reg.h index d0e294a28c..3235f2dc32 100644 --- a/components/soc/esp32c61/register/soc/cache_reg.h +++ b/components/soc/esp32c61/register/soc/cache_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,504 +11,61 @@ extern "C" { #endif -/** CACHE_L1_ICACHE_CTRL_REG register - * L1 instruction Cache(L1-ICache) control register - */ -#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0) -/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable - */ -#define CACHE_L1_ICACHE_SHUT_IBUS0 (BIT(0)) -#define CACHE_L1_ICACHE_SHUT_IBUS0_M (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S) -#define CACHE_L1_ICACHE_SHUT_IBUS0_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS0_S 0 -/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable - */ -#define CACHE_L1_ICACHE_SHUT_IBUS1 (BIT(1)) -#define CACHE_L1_ICACHE_SHUT_IBUS1_M (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S) -#define CACHE_L1_ICACHE_SHUT_IBUS1_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS1_S 1 -/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE_SHUT_IBUS2 (BIT(2)) -#define CACHE_L1_ICACHE_SHUT_IBUS2_M (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S) -#define CACHE_L1_ICACHE_SHUT_IBUS2_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS2_S 2 -/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE_SHUT_IBUS3 (BIT(3)) -#define CACHE_L1_ICACHE_SHUT_IBUS3_M (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S) -#define CACHE_L1_ICACHE_SHUT_IBUS3_V 0x00000001U -#define CACHE_L1_ICACHE_SHUT_IBUS3_S 3 -/** CACHE_L1_ICACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE_UNDEF_OP 0x000000FFU -#define CACHE_L1_ICACHE_UNDEF_OP_M (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S) -#define CACHE_L1_ICACHE_UNDEF_OP_V 0x000000FFU -#define CACHE_L1_ICACHE_UNDEF_OP_S 8 - /** CACHE_L1_CACHE_CTRL_REG register - * L1 data Cache(L1-Cache) control register + * L1 data cache (L1 cache) control register */ #define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4) /** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS0 to access the L1 cache. + * 0: Enable + * 1: Disable */ #define CACHE_L1_CACHE_SHUT_BUS0 (BIT(0)) #define CACHE_L1_CACHE_SHUT_BUS0_M (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S) #define CACHE_L1_CACHE_SHUT_BUS0_V 0x00000001U #define CACHE_L1_CACHE_SHUT_BUS0_S 0 /** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS1 to access the L1 cache. + * 0: Enable + * 1: Disable */ #define CACHE_L1_CACHE_SHUT_BUS1 (BIT(1)) #define CACHE_L1_CACHE_SHUT_BUS1_M (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S) #define CACHE_L1_CACHE_SHUT_BUS1_V 0x00000001U #define CACHE_L1_CACHE_SHUT_BUS1_S 1 -/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_CACHE_SHUT_DBUS2 (BIT(2)) -#define CACHE_L1_CACHE_SHUT_DBUS2_M (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S) -#define CACHE_L1_CACHE_SHUT_DBUS2_V 0x00000001U -#define CACHE_L1_CACHE_SHUT_DBUS2_S 2 -/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_CACHE_SHUT_DBUS3 (BIT(3)) -#define CACHE_L1_CACHE_SHUT_DBUS3_M (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S) -#define CACHE_L1_CACHE_SHUT_DBUS3_V 0x00000001U -#define CACHE_L1_CACHE_SHUT_DBUS3_S 3 -/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable - */ -#define CACHE_L1_CACHE_SHUT_DMA (BIT(4)) -#define CACHE_L1_CACHE_SHUT_DMA_M (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S) -#define CACHE_L1_CACHE_SHUT_DMA_V 0x00000001U -#define CACHE_L1_CACHE_SHUT_DMA_S 4 -/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ -#define CACHE_L1_CACHE_UNDEF_OP 0x000000FFU -#define CACHE_L1_CACHE_UNDEF_OP_M (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S) -#define CACHE_L1_CACHE_UNDEF_OP_V 0x000000FFU -#define CACHE_L1_CACHE_UNDEF_OP_S 8 - -/** CACHE_L1_BYPASS_CACHE_CONF_REG register - * Bypass Cache configure register - */ -#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8) -/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L1_ICACHE0_EN (BIT(0)) -#define CACHE_BYPASS_L1_ICACHE0_EN_M (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S) -#define CACHE_BYPASS_L1_ICACHE0_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE0_EN_S 0 -/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L1_ICACHE1_EN (BIT(1)) -#define CACHE_BYPASS_L1_ICACHE1_EN_M (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S) -#define CACHE_BYPASS_L1_ICACHE1_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE1_EN_S 1 -/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_BYPASS_L1_ICACHE2_EN (BIT(2)) -#define CACHE_BYPASS_L1_ICACHE2_EN_M (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S) -#define CACHE_BYPASS_L1_ICACHE2_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE2_EN_S 2 -/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_BYPASS_L1_ICACHE3_EN (BIT(3)) -#define CACHE_BYPASS_L1_ICACHE3_EN_M (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S) -#define CACHE_BYPASS_L1_ICACHE3_EN_V 0x00000001U -#define CACHE_BYPASS_L1_ICACHE3_EN_S 3 -/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L1_DCACHE_EN (BIT(4)) -#define CACHE_BYPASS_L1_DCACHE_EN_M (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S) -#define CACHE_BYPASS_L1_DCACHE_EN_V 0x00000001U -#define CACHE_BYPASS_L1_DCACHE_EN_S 4 - -/** CACHE_L1_CACHE_ATOMIC_CONF_REG register - * L1 Cache atomic feature configure register - */ -#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc) -/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable atomic feature on L1-Cache when multiple cores access - * L1-Cache. 1: disable, 1: enable. - */ -#define CACHE_L1_CACHE_ATOMIC_EN (BIT(0)) -#define CACHE_L1_CACHE_ATOMIC_EN_M (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S) -#define CACHE_L1_CACHE_ATOMIC_EN_V 0x00000001U -#define CACHE_L1_CACHE_ATOMIC_EN_S 0 - -/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register - * L1 instruction Cache CacheSize mode configure register - */ -#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10) -/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_256 (BIT(0)) -#define CACHE_L1_ICACHE_CACHESIZE_256_M (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S) -#define CACHE_L1_ICACHE_CACHESIZE_256_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_256_S 0 -/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_512 (BIT(1)) -#define CACHE_L1_ICACHE_CACHESIZE_512_M (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S) -#define CACHE_L1_ICACHE_CACHESIZE_512_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_512_S 1 -/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_1K (BIT(2)) -#define CACHE_L1_ICACHE_CACHESIZE_1K_M (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S) -#define CACHE_L1_ICACHE_CACHESIZE_1K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_1K_S 2 -/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_2K (BIT(3)) -#define CACHE_L1_ICACHE_CACHESIZE_2K_M (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S) -#define CACHE_L1_ICACHE_CACHESIZE_2K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_2K_S 3 -/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_4K (BIT(4)) -#define CACHE_L1_ICACHE_CACHESIZE_4K_M (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S) -#define CACHE_L1_ICACHE_CACHESIZE_4K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_4K_S 4 -/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_8K (BIT(5)) -#define CACHE_L1_ICACHE_CACHESIZE_8K_M (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S) -#define CACHE_L1_ICACHE_CACHESIZE_8K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_8K_S 5 -/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_16K (BIT(6)) -#define CACHE_L1_ICACHE_CACHESIZE_16K_M (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S) -#define CACHE_L1_ICACHE_CACHESIZE_16K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_16K_S 6 -/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_32K (BIT(7)) -#define CACHE_L1_ICACHE_CACHESIZE_32K_M (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S) -#define CACHE_L1_ICACHE_CACHESIZE_32K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_32K_S 7 -/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_64K (BIT(8)) -#define CACHE_L1_ICACHE_CACHESIZE_64K_M (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S) -#define CACHE_L1_ICACHE_CACHESIZE_64K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_64K_S 8 -/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_128K (BIT(9)) -#define CACHE_L1_ICACHE_CACHESIZE_128K_M (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S) -#define CACHE_L1_ICACHE_CACHESIZE_128K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_128K_S 9 -/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_256K (BIT(10)) -#define CACHE_L1_ICACHE_CACHESIZE_256K_M (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S) -#define CACHE_L1_ICACHE_CACHESIZE_256K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_256K_S 10 -/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_512K (BIT(11)) -#define CACHE_L1_ICACHE_CACHESIZE_512K_M (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S) -#define CACHE_L1_ICACHE_CACHESIZE_512K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_512K_S 11 -/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_CACHESIZE_1024K (BIT(12)) -#define CACHE_L1_ICACHE_CACHESIZE_1024K_M (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S) -#define CACHE_L1_ICACHE_CACHESIZE_1024K_V 0x00000001U -#define CACHE_L1_ICACHE_CACHESIZE_1024K_S 12 - -/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register - * L1 instruction Cache BlockSize mode configure register - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14) -/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_8 (BIT(0)) -#define CACHE_L1_ICACHE_BLOCKSIZE_8_M (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_8_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_8_S 0 -/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_16 (BIT(1)) -#define CACHE_L1_ICACHE_BLOCKSIZE_16_M (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_16_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_16_S 1 -/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_32 (BIT(2)) -#define CACHE_L1_ICACHE_BLOCKSIZE_32_M (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_32_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_32_S 2 -/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_64 (BIT(3)) -#define CACHE_L1_ICACHE_BLOCKSIZE_64_M (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_64_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_64_S 3 -/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_128 (BIT(4)) -#define CACHE_L1_ICACHE_BLOCKSIZE_128_M (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_128_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_128_S 4 -/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_ICACHE_BLOCKSIZE_256 (BIT(5)) -#define CACHE_L1_ICACHE_BLOCKSIZE_256_M (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S) -#define CACHE_L1_ICACHE_BLOCKSIZE_256_V 0x00000001U -#define CACHE_L1_ICACHE_BLOCKSIZE_256_S 5 /** CACHE_L1_CACHE_CACHESIZE_CONF_REG register - * L1 data Cache CacheSize mode configure register + * Cache cache size register */ #define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18) -/** CACHE_L1_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_256 (BIT(0)) -#define CACHE_L1_CACHE_CACHESIZE_256_M (CACHE_L1_CACHE_CACHESIZE_256_V << CACHE_L1_CACHE_CACHESIZE_256_S) -#define CACHE_L1_CACHE_CACHESIZE_256_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_256_S 0 -/** CACHE_L1_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_512 (BIT(1)) -#define CACHE_L1_CACHE_CACHESIZE_512_M (CACHE_L1_CACHE_CACHESIZE_512_V << CACHE_L1_CACHE_CACHESIZE_512_S) -#define CACHE_L1_CACHE_CACHESIZE_512_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_512_S 1 -/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_1K (BIT(2)) -#define CACHE_L1_CACHE_CACHESIZE_1K_M (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S) -#define CACHE_L1_CACHE_CACHESIZE_1K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_1K_S 2 -/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-DCache as 2k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_2K (BIT(3)) -#define CACHE_L1_CACHE_CACHESIZE_2K_M (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S) -#define CACHE_L1_CACHE_CACHESIZE_2K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_2K_S 3 -/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-DCache as 4k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_4K (BIT(4)) -#define CACHE_L1_CACHE_CACHESIZE_4K_M (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S) -#define CACHE_L1_CACHE_CACHESIZE_4K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_4K_S 4 -/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-DCache as 8k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_8K (BIT(5)) -#define CACHE_L1_CACHE_CACHESIZE_8K_M (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S) -#define CACHE_L1_CACHE_CACHESIZE_8K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_8K_S 5 -/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-DCache as 16k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_16K (BIT(6)) -#define CACHE_L1_CACHE_CACHESIZE_16K_M (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S) -#define CACHE_L1_CACHE_CACHESIZE_16K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_16K_S 6 -/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 1; - * The field is used to configure cachesize of L1-DCache as 32k bytes. This field and - * all other fields within this register is onehot. +/** CACHE_L1_CACHE_CACHESIZE_32K : RO; bitpos: [7]; default: 1; + * Indicates that cache size is 32 KB. */ #define CACHE_L1_CACHE_CACHESIZE_32K (BIT(7)) #define CACHE_L1_CACHE_CACHESIZE_32K_M (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S) #define CACHE_L1_CACHE_CACHESIZE_32K_V 0x00000001U #define CACHE_L1_CACHE_CACHESIZE_32K_S 7 -/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-DCache as 64k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_64K (BIT(8)) -#define CACHE_L1_CACHE_CACHESIZE_64K_M (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S) -#define CACHE_L1_CACHE_CACHESIZE_64K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_64K_S 8 -/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-DCache as 128k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_128K (BIT(9)) -#define CACHE_L1_CACHE_CACHESIZE_128K_M (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S) -#define CACHE_L1_CACHE_CACHESIZE_128K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_128K_S 9 -/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_256K (BIT(10)) -#define CACHE_L1_CACHE_CACHESIZE_256K_M (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S) -#define CACHE_L1_CACHE_CACHESIZE_256K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_256K_S 10 -/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_512K (BIT(11)) -#define CACHE_L1_CACHE_CACHESIZE_512K_M (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S) -#define CACHE_L1_CACHE_CACHESIZE_512K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_512K_S 11 -/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_CACHESIZE_1024K (BIT(12)) -#define CACHE_L1_CACHE_CACHESIZE_1024K_M (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S) -#define CACHE_L1_CACHE_CACHESIZE_1024K_V 0x00000001U -#define CACHE_L1_CACHE_CACHESIZE_1024K_S 12 /** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register - * L1 data Cache BlockSize mode configure register + * Cache block size register */ #define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c) -/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_8 (BIT(0)) -#define CACHE_L1_CACHE_BLOCKSIZE_8_M (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S) -#define CACHE_L1_CACHE_BLOCKSIZE_8_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_8_S 0 -/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_16 (BIT(1)) -#define CACHE_L1_CACHE_BLOCKSIZE_16_M (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S) -#define CACHE_L1_CACHE_BLOCKSIZE_16_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_16_S 1 -/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1; - * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and - * all other fields within this register is onehot. +/** CACHE_L1_CACHE_BLOCKSIZE_32 : RO; bitpos: [2]; default: 1; + * Indicates that the cache block size is 32 bytes. */ #define CACHE_L1_CACHE_BLOCKSIZE_32 (BIT(2)) #define CACHE_L1_CACHE_BLOCKSIZE_32_M (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S) #define CACHE_L1_CACHE_BLOCKSIZE_32_V 0x00000001U #define CACHE_L1_CACHE_BLOCKSIZE_32_S 2 -/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_64 (BIT(3)) -#define CACHE_L1_CACHE_BLOCKSIZE_64_M (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S) -#define CACHE_L1_CACHE_BLOCKSIZE_64_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_64_S 3 -/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_128 (BIT(4)) -#define CACHE_L1_CACHE_BLOCKSIZE_128_M (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S) -#define CACHE_L1_CACHE_BLOCKSIZE_128_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_128_S 4 -/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L1_CACHE_BLOCKSIZE_256 (BIT(5)) -#define CACHE_L1_CACHE_BLOCKSIZE_256_M (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S) -#define CACHE_L1_CACHE_BLOCKSIZE_256_V 0x00000001U -#define CACHE_L1_CACHE_BLOCKSIZE_256_S 5 /** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register - * Cache wrap around control register + * Cache critical word first control register */ #define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20) -/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to enable L1-ICache0 wrap around mode. - */ -#define CACHE_L1_ICACHE0_WRAP (BIT(0)) -#define CACHE_L1_ICACHE0_WRAP_M (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S) -#define CACHE_L1_ICACHE0_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE0_WRAP_S 0 -/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to enable L1-ICache1 wrap around mode. - */ -#define CACHE_L1_ICACHE1_WRAP (BIT(1)) -#define CACHE_L1_ICACHE1_WRAP_M (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S) -#define CACHE_L1_ICACHE1_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE1_WRAP_S 1 -/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_WRAP (BIT(2)) -#define CACHE_L1_ICACHE2_WRAP_M (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S) -#define CACHE_L1_ICACHE2_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE2_WRAP_S 2 -/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_WRAP (BIT(3)) -#define CACHE_L1_ICACHE3_WRAP_M (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S) -#define CACHE_L1_ICACHE3_WRAP_V 0x00000001U -#define CACHE_L1_ICACHE3_WRAP_S 3 /** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to enable L1-DCache wrap around mode. + * Configures whether to enable the critical word first mode for the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_WRAP (BIT(4)) #define CACHE_L1_CACHE_WRAP_M (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S) @@ -519,36 +76,10 @@ extern "C" { * Cache wrap around control register */ #define CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x24) -/** CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache0 - */ -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS (BIT(0)) -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S 0 -/** CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache1 - */ -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS (BIT(1)) -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S 1 -/** CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS (BIT(2)) -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S 2 -/** CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS (BIT(3)) -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_M (CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S) -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S 3 /** CACHE_L1_CACHE_MISS_DISABLE_ACCESS : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to disable early restart of L1-DCache + * Configures whether to disable early restart function. + * 0: Enable + * 1: Disable */ #define CACHE_L1_CACHE_MISS_DISABLE_ACCESS (BIT(4)) #define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_M (CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S) @@ -556,118 +87,32 @@ extern "C" { #define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S 4 /** CACHE_L1_CACHE_FREEZE_CTRL_REG register - * Cache Freeze control register + * Cache freeze control register */ #define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28) -/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by - * software. - */ -#define CACHE_L1_ICACHE0_FREEZE_EN (BIT(0)) -#define CACHE_L1_ICACHE0_FREEZE_EN_M (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S) -#define CACHE_L1_ICACHE0_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_FREEZE_EN_S 0 -/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ -#define CACHE_L1_ICACHE0_FREEZE_MODE (BIT(1)) -#define CACHE_L1_ICACHE0_FREEZE_MODE_M (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S) -#define CACHE_L1_ICACHE0_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE0_FREEZE_MODE_S 1 -/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE0_FREEZE_DONE (BIT(2)) -#define CACHE_L1_ICACHE0_FREEZE_DONE_M (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S) -#define CACHE_L1_ICACHE0_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE0_FREEZE_DONE_S 2 -/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by - * software. - */ -#define CACHE_L1_ICACHE1_FREEZE_EN (BIT(4)) -#define CACHE_L1_ICACHE1_FREEZE_EN_M (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S) -#define CACHE_L1_ICACHE1_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_FREEZE_EN_S 4 -/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ -#define CACHE_L1_ICACHE1_FREEZE_MODE (BIT(5)) -#define CACHE_L1_ICACHE1_FREEZE_MODE_M (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S) -#define CACHE_L1_ICACHE1_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE1_FREEZE_MODE_S 5 -/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE1_FREEZE_DONE (BIT(6)) -#define CACHE_L1_ICACHE1_FREEZE_DONE_M (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S) -#define CACHE_L1_ICACHE1_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE1_FREEZE_DONE_S 6 -/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FREEZE_EN (BIT(8)) -#define CACHE_L1_ICACHE2_FREEZE_EN_M (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S) -#define CACHE_L1_ICACHE2_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_FREEZE_EN_S 8 -/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FREEZE_MODE (BIT(9)) -#define CACHE_L1_ICACHE2_FREEZE_MODE_M (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S) -#define CACHE_L1_ICACHE2_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE2_FREEZE_MODE_S 9 -/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FREEZE_DONE (BIT(10)) -#define CACHE_L1_ICACHE2_FREEZE_DONE_M (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S) -#define CACHE_L1_ICACHE2_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE2_FREEZE_DONE_S 10 -/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FREEZE_EN (BIT(12)) -#define CACHE_L1_ICACHE3_FREEZE_EN_M (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S) -#define CACHE_L1_ICACHE3_FREEZE_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_FREEZE_EN_S 12 -/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FREEZE_MODE (BIT(13)) -#define CACHE_L1_ICACHE3_FREEZE_MODE_M (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S) -#define CACHE_L1_ICACHE3_FREEZE_MODE_V 0x00000001U -#define CACHE_L1_ICACHE3_FREEZE_MODE_S 13 -/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FREEZE_DONE (BIT(14)) -#define CACHE_L1_ICACHE3_FREEZE_DONE_M (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S) -#define CACHE_L1_ICACHE3_FREEZE_DONE_V 0x00000001U -#define CACHE_L1_ICACHE3_FREEZE_DONE_S 14 /** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0; - * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * Configures whether to enable freeze operation in the L1 cache. It can be cleared by * software. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_FREEZE_EN (BIT(16)) #define CACHE_L1_CACHE_FREEZE_EN_M (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S) #define CACHE_L1_CACHE_FREEZE_EN_V 0x00000001U #define CACHE_L1_CACHE_FREEZE_EN_S 16 /** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0; - * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. + * Configures the freeze mode in the L1 cache. + * 0: Assert busy if a cache miss occurs + * 1: Assert hit if a cache miss occurs */ #define CACHE_L1_CACHE_FREEZE_MODE (BIT(17)) #define CACHE_L1_CACHE_FREEZE_MODE_M (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S) #define CACHE_L1_CACHE_FREEZE_MODE_V 0x00000001U #define CACHE_L1_CACHE_FREEZE_MODE_S 17 /** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0; - * The bit is used to indicate whether freeze operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the freeze operation in L1 cache is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_L1_CACHE_FREEZE_DONE (BIT(18)) #define CACHE_L1_CACHE_FREEZE_DONE_M (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S) @@ -675,80 +120,23 @@ extern "C" { #define CACHE_L1_CACHE_FREEZE_DONE_S 18 /** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register - * Cache data memory access configure register + * Cache data memory access configuration register */ #define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x2c) -/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN (BIT(0)) -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S 0 -/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, - * 1: enable. - */ -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN (BIT(1)) -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S 1 -/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN (BIT(4)) -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S 4 -/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, - * 1: enable. - */ -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN (BIT(5)) -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S 5 -/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN (BIT(8)) -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S 8 -/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN (BIT(9)) -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S 9 -/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN (BIT(12)) -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S) -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S 12 -/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN (BIT(13)) -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S) -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S 13 /** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache data memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) #define CACHE_L1_CACHE_DATA_MEM_RD_EN_M (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S) #define CACHE_L1_CACHE_DATA_MEM_RD_EN_V 0x00000001U #define CACHE_L1_CACHE_DATA_MEM_RD_EN_S 16 /** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache data + * memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) #define CACHE_L1_CACHE_DATA_MEM_WR_EN_M (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S) @@ -756,445 +144,94 @@ extern "C" { #define CACHE_L1_CACHE_DATA_MEM_WR_EN_S 17 /** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register - * Cache tag memory access configure register + * Cache tag memory access configuration register */ #define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30) -/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN (BIT(0)) -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S 0 -/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN (BIT(1)) -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S 1 -/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN (BIT(4)) -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S 4 -/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN (BIT(5)) -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S 5 -/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN (BIT(8)) -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S 8 -/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN (BIT(9)) -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S 9 -/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN (BIT(12)) -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S) -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S 12 -/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN (BIT(13)) -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S) -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S 13 /** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache tag memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) #define CACHE_L1_CACHE_TAG_MEM_RD_EN_M (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S) #define CACHE_L1_CACHE_TAG_MEM_RD_EN_V 0x00000001U #define CACHE_L1_CACHE_TAG_MEM_RD_EN_S 16 /** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache tag memory. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) #define CACHE_L1_CACHE_TAG_MEM_WR_EN_M (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S) #define CACHE_L1_CACHE_TAG_MEM_WR_EN_V 0x00000001U #define CACHE_L1_CACHE_TAG_MEM_WR_EN_S 17 -/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register - * L1 instruction Cache 0 prelock configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x34) -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache0 prelock. - */ -#define CACHE_L1_ICACHE0_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOCK_RGID_M (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE0_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 0 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x38) -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 0 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x3c) -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 0 prelock section size configure register - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x40) -/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register - * L1 instruction Cache 1 prelock configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x44) -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache1 prelock. - */ -#define CACHE_L1_ICACHE1_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOCK_RGID_M (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE1_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 1 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x48) -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 1 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x4c) -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 1 prelock section size configure register - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x50) -/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register - * L1 instruction Cache 2 prelock configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x54) -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache2 prelock. - */ -#define CACHE_L1_ICACHE2_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOCK_RGID_M (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE2_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 2 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x58) -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 2 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x5c) -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 2 prelock section size configure register - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x60) -/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register - * L1 instruction Cache 3 prelock configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x64) -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S 0 -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache3 prelock. - */ -#define CACHE_L1_ICACHE3_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOCK_RGID_M (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S) -#define CACHE_L1_ICACHE3_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOCK_RGID_S 2 - -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register - * L1 instruction Cache 3 prelock section0 address configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x68) -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register - * L1 instruction Cache 3 prelock section1 address configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x6c) -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register - * L1 instruction Cache 3 prelock section size configure register - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x70) -/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S) -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S 16 - /** CACHE_L1_CACHE_PRELOCK_CONF_REG register * L1 Cache prelock configure register */ #define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x74) /** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 0 of the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) #define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S) #define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V 0x00000001U #define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S 0 /** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 1 of the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) #define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S) #define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V 0x00000001U #define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S 1 -/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 cache prelock. - */ -#define CACHE_L1_CACHE_PRELOCK_RGID 0x0000000FU -#define CACHE_L1_CACHE_PRELOCK_RGID_M (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S) -#define CACHE_L1_CACHE_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L1_CACHE_PRELOCK_RGID_S 2 /** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register - * L1 Cache prelock section0 address configure register + * L1 cache prelocking Section 0 address configuration register */ #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x78) /** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + * Configures the starting virtual address of Section 0 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT0_SIZE. */ #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S) #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 -/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register - * L1 Cache prelock section1 address configure register +/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG register + * L1 cache prelocking Section 1 address configuration register */ -#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) +#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c) /** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + * Configures the starting virtual address of Section 1 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT1_SIZE. */ #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S) #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 -/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register - * L1 Cache prelock section size configure register +/** CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG register + * L1 cache prelocking section size configuration register */ -#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80) +#define CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80) /** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + * Configures the size of Section 0 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG. */ #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S) #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x00003FFFU #define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 /** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + * Configures the size of Section 1 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG. */ #define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFFU #define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S) @@ -1202,48 +239,48 @@ extern "C" { #define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 /** CACHE_LOCK_CTRL_REG register - * Lock-class (manual lock) operation control register + * Locking operation control register */ #define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x84) /** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware after lock - * operation done + * Configures whether to enable lock operation. It will be cleared by hardware after + * the lock operation is done. + * 0: Disable + * 1: Enable */ #define CACHE_LOCK_ENA (BIT(0)) #define CACHE_LOCK_ENA_M (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S) #define CACHE_LOCK_ENA_V 0x00000001U #define CACHE_LOCK_ENA_S 0 /** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by hardware after - * unlock operation done + * Configures whether to enable unlock operation. It will be cleared by hardware after + * the unlock operation is done. + * 0: Disable + * 1: Enable */ #define CACHE_UNLOCK_ENA (BIT(1)) #define CACHE_UNLOCK_ENA_M (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S) #define CACHE_UNLOCK_ENA_V 0x00000001U #define CACHE_UNLOCK_ENA_S 1 /** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate whether unlock/lock operation is finished or not. 0: - * not finished. 1: finished. + * Represents whether the unlock or the lock operation is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_LOCK_DONE (BIT(2)) #define CACHE_LOCK_DONE_M (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S) #define CACHE_LOCK_DONE_V 0x00000001U #define CACHE_LOCK_DONE_S 2 -/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of cache lock/unlock. - */ -#define CACHE_LOCK_RGID 0x0000000FU -#define CACHE_LOCK_RGID_M (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S) -#define CACHE_LOCK_RGID_V 0x0000000FU -#define CACHE_LOCK_RGID_S 3 /** CACHE_LOCK_MAP_REG register - * Lock (manual lock) map configure register + * Locking map configuration register */ #define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x88) /** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply this lock/unlock operation. [4]: L1-Cache + * Configures which level of cache in the two-level cache structure to perform the + * locking or the unlocking operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: reserved */ #define CACHE_LOCK_MAP 0x0000003FU #define CACHE_LOCK_MAP_M (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S) @@ -1251,12 +288,12 @@ extern "C" { #define CACHE_LOCK_MAP_S 0 /** CACHE_LOCK_ADDR_REG register - * Lock (manual lock) address configure register + * Locking address configuration register */ #define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x8c) /** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the lock/unlock operation, - * which should be used together with CACHE_LOCK_SIZE_REG + * Configures the starting virtual address for the locking or unlocking operation. + * This field should be configured together with CACHE_LOCK_SIZE_REG. */ #define CACHE_LOCK_ADDR 0xFFFFFFFFU #define CACHE_LOCK_ADDR_M (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S) @@ -1264,12 +301,12 @@ extern "C" { #define CACHE_LOCK_ADDR_S 0 /** CACHE_LOCK_SIZE_REG register - * Lock (manual lock) size configure register + * Locking size configuration register */ #define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x90) /** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the lock/unlock operation, which - * should be used together with CACHE_LOCK_ADDR_REG + * Configures the size for the locking or unlocking operation. This field should be + * configured together with CACHE_LOCK_ADDR_REG. */ #define CACHE_LOCK_SIZE 0x0000FFFFU #define CACHE_LOCK_SIZE_M (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S) @@ -1277,73 +314,68 @@ extern "C" { #define CACHE_LOCK_SIZE_S 0 /** CACHE_SYNC_CTRL_REG register - * Sync-class operation control register + * Sync operation control register */ #define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x94) -/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by hardware - * after invalidate operation done. Note that this bit and the other sync-bits - * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. +/** CACHE_INVALIDATE_ENA : RW; bitpos: [0]; default: 1; + * Configures whether to enable the invalidatation operation. Hardware will clear it + * once the operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_INVALIDATE_ENA (BIT(0)) #define CACHE_INVALIDATE_ENA_M (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S) #define CACHE_INVALIDATE_ENA_V 0x00000001U #define CACHE_INVALIDATE_ENA_S 0 /** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware after - * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, - * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those - * bits can not be set to 1 at the same time. + * Configures whether to enable the clean operation. Hardware will clear it once the + * operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_CLEAN_ENA (BIT(1)) #define CACHE_CLEAN_ENA_M (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S) #define CACHE_CLEAN_ENA_V 0x00000001U #define CACHE_CLEAN_ENA_S 1 /** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by hardware after - * writeback operation done. Note that this bit and the other sync-bits - * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back operation. Hardware will clear it once + * the operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_WRITEBACK_ENA (BIT(2)) #define CACHE_WRITEBACK_ENA_M (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S) #define CACHE_WRITEBACK_ENA_V 0x00000001U #define CACHE_WRITEBACK_ENA_S 2 /** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0; - * The bit is used to enable writeback-invalidate operation. It will be cleared by - * hardware after writeback-invalidate operation done. Note that this bit and the - * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, - * that is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back invalidation operation. Hardware will + * clear it once the operation has finished. + * 0: Disable + * 1: Enable */ #define CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) #define CACHE_WRITEBACK_INVALIDATE_ENA_M (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S) #define CACHE_WRITEBACK_INVALIDATE_ENA_V 0x00000001U #define CACHE_WRITEBACK_INVALIDATE_ENA_S 3 /** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0; - * The bit is used to indicate whether sync operation (invalidate, clean, writeback, - * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + * Represents whether the synchronization operation is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_SYNC_DONE (BIT(4)) #define CACHE_SYNC_DONE_M (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S) #define CACHE_SYNC_DONE_V 0x00000001U #define CACHE_SYNC_DONE_S 4 -/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0; - * The bit is used to set the gid of cache sync operation (invalidate, clean, - * writeback, writeback_invalidate) - */ -#define CACHE_SYNC_RGID 0x0000000FU -#define CACHE_SYNC_RGID_M (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S) -#define CACHE_SYNC_RGID_V 0x0000000FU -#define CACHE_SYNC_RGID_S 5 /** CACHE_SYNC_MAP_REG register - * Sync map configure register + * Sync map configuration register */ #define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x98) /** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply the sync operation. [4]: L1-Cache + * Configures which caches in the two-level cache structure will apply the sync + * operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: Reserved */ #define CACHE_SYNC_MAP 0x0000003FU #define CACHE_SYNC_MAP_M (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S) @@ -1351,12 +383,12 @@ extern "C" { #define CACHE_SYNC_MAP_S 0 /** CACHE_SYNC_ADDR_REG register - * Sync address configure register + * Sync address configuration register */ #define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0x9c) /** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the sync operation, which - * should be used together with CACHE_SYNC_SIZE_REG + * Configures the starting virtual address for the synchronization operation. This + * field should be configured together with CACHE_SYNC_SIZE_REG. */ #define CACHE_SYNC_ADDR 0xFFFFFFFFU #define CACHE_SYNC_ADDR_M (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S) @@ -1364,862 +396,148 @@ extern "C" { #define CACHE_SYNC_ADDR_S 0 /** CACHE_SYNC_SIZE_REG register - * Sync size configure register + * Sync size configuration register */ #define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa0) /** CACHE_SYNC_SIZE : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the sync operation, which should be - * used together with CACHE_SYNC_ADDR_REG + * Configures the size for the synchronization operation. This field should be + * configured together with CACHE_SYNC_ADDR_REG. */ #define CACHE_SYNC_SIZE 0x01FFFFFFU #define CACHE_SYNC_SIZE_M (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S) #define CACHE_SYNC_SIZE_V 0x01FFFFFFU #define CACHE_SYNC_SIZE_S 0 -/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register - * L1 instruction Cache 0 preload-operation control register - */ -#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa4) -/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache0. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE0_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_PRELOAD_ENA_M (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE0_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE0_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE0_PRELOAD_DONE_M (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE0_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE0_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache0 preload. - */ -#define CACHE_L1_ICACHE0_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOAD_RGID_M (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE0_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE0_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register - * L1 instruction Cache 0 preload address configure register - */ -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xa8) -/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache0, which - * should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE0_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register - * L1 instruction Cache 0 preload size configure register - */ -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xac) -/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE0_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S 0 - -/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register - * L1 instruction Cache 1 preload-operation control register - */ -#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb0) -/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache1. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE1_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE1_PRELOAD_ENA_M (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE1_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE1_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE1_PRELOAD_DONE_M (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE1_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE1_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache1 preload. - */ -#define CACHE_L1_ICACHE1_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOAD_RGID_M (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE1_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE1_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register - * L1 instruction Cache 1 preload address configure register - */ -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb4) -/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache1, which - * should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE1_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register - * L1 instruction Cache 1 preload size configure register - */ -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb8) -/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE1_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S 0 - -/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register - * L1 instruction Cache 2 preload-operation control register - */ -#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xbc) -/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache2. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE2_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE2_PRELOAD_ENA_M (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE2_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE2_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE2_PRELOAD_DONE_M (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE2_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE2_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache2 preload. - */ -#define CACHE_L1_ICACHE2_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOAD_RGID_M (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE2_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE2_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register - * L1 instruction Cache 2 preload address configure register - */ -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc0) -/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache2, which - * should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE2_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register - * L1 instruction Cache 2 preload size configure register - */ -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc4) -/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE2_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S 0 - -/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register - * L1 instruction Cache 3 preload-operation control register - */ -#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc8) -/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache3. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L1_ICACHE3_PRELOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE3_PRELOAD_ENA_M (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S) -#define CACHE_L1_ICACHE3_PRELOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOAD_ENA_S 0 -/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L1_ICACHE3_PRELOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE3_PRELOAD_DONE_M (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S) -#define CACHE_L1_ICACHE3_PRELOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOAD_DONE_S 1 -/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L1_ICACHE3_PRELOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S) -#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S 2 -/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache3 preload. - */ -#define CACHE_L1_ICACHE3_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOAD_RGID_M (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S) -#define CACHE_L1_ICACHE3_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE3_PRELOAD_RGID_S 3 - -/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register - * L1 instruction Cache 3 preload address configure register - */ -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xcc) -/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache3, which - * should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - */ -#define CACHE_L1_ICACHE3_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S) -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S 0 - -/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register - * L1 instruction Cache 3 preload size configure register - */ -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd0) -/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - */ -#define CACHE_L1_ICACHE3_PRELOAD_SIZE 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S) -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V 0x00003FFFU -#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S 0 - /** CACHE_L1_CACHE_PRELOAD_CTRL_REG register - * L1 Cache preload-operation control register + * L1 cache preloading operation control register */ #define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd4) /** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-Cache. It will be cleared by - * hardware automatically after preload operation is done. + * Configures whether to enable the preloading operation in the L1 cache. It will be + * cleared by hardware automatically after the preloading operation is done. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_PRELOAD_ENA (BIT(0)) #define CACHE_L1_CACHE_PRELOAD_ENA_M (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S) #define CACHE_L1_CACHE_PRELOAD_ENA_V 0x00000001U #define CACHE_L1_CACHE_PRELOAD_ENA_S 0 /** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. + * Represents whether the preloading operation is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_L1_CACHE_PRELOAD_DONE (BIT(1)) #define CACHE_L1_CACHE_PRELOAD_DONE_M (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S) #define CACHE_L1_CACHE_PRELOAD_DONE_V 0x00000001U #define CACHE_L1_CACHE_PRELOAD_DONE_S 1 /** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. + * Configures the direction of the preloading operation. + * 0: Ascending + * 1: Descending */ #define CACHE_L1_CACHE_PRELOAD_ORDER (BIT(2)) #define CACHE_L1_CACHE_PRELOAD_ORDER_M (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S) #define CACHE_L1_CACHE_PRELOAD_ORDER_V 0x00000001U #define CACHE_L1_CACHE_PRELOAD_ORDER_S 2 -/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 cache preload. - */ -#define CACHE_L1_CACHE_PRELOAD_RGID 0x0000000FU -#define CACHE_L1_CACHE_PRELOAD_RGID_M (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S) -#define CACHE_L1_CACHE_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L1_CACHE_PRELOAD_RGID_S 3 -/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register - * L1 Cache preload address configure register +/** CACHE_L1_CACHE_PRELOAD_ADDR_REG register + * L1 cache preloading address configuration register */ -#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8) +#define CACHE_L1_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8) /** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-Cache, which - * should be used together with L1_CACHE_PRELOAD_SIZE_REG + * Configures the starting virtual address for the preloading operation in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOAD_SIZE_REG. */ #define CACHE_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOAD_ADDR_M (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S) #define CACHE_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU #define CACHE_L1_CACHE_PRELOAD_ADDR_S 0 -/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register - * L1 Cache preload size configure register +/** CACHE_L1_CACHE_PRELOAD_SIZE_REG register + * L1 cache preloading size configuration register */ -#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc) +#define CACHE_L1_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc) /** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + * Configures the size of Section 0 for the preloading operation in the L1 cache. This + * field should be configured together with CACHE_L1_CACHE_PRELOAD_ADDR_REG. */ #define CACHE_L1_CACHE_PRELOAD_SIZE 0x00003FFFU #define CACHE_L1_CACHE_PRELOAD_SIZE_M (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S) #define CACHE_L1_CACHE_PRELOAD_SIZE_V 0x00003FFFU #define CACHE_L1_CACHE_PRELOAD_SIZE_S 0 -/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 0 autoload-operation control register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe0) -/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache0. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache0. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache0 autoload. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 0 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe4) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 0 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xe8) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 0 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xec) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 0 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf0) -/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 1 autoload-operation control register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf4) -/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache1. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache1. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache1 autoload. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 1 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xf8) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 1 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xfc) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 1 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x100) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 1 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x104) -/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 2 autoload-operation control register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x108) -/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache2. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache2. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache2 autoload. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 2 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x10c) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 2 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x110) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 2 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x114) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 2 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x118) -/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register - * L1 instruction Cache 3 autoload-operation control register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x11c) -/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, - * 0: disable. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S 0 -/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S 1 -/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: - * ascending. 1: descending. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S 2 -/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache3. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache3. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache3 autoload. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S 10 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register - * L1 instruction Cache 3 autoload section 0 address configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x120) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register - * L1 instruction Cache 3 autoload section 0 size configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x124) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register - * L1 instruction Cache 3 autoload section 1 address configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x128) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register - * L1 instruction Cache 3 autoload section 1 size configure register - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x12c) -/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S 0 - /** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register - * L1 Cache autoload-operation control register + * L1 cache autoloading operation control register */ #define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x130) /** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, - * 0: disable. + * Configures whether to enable the autoloading operation in the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_AUTOLOAD_ENA (BIT(0)) #define CACHE_L1_CACHE_AUTOLOAD_ENA_M (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S) #define CACHE_L1_CACHE_AUTOLOAD_ENA_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_ENA_S 0 /** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the autoloading operation in the L1 cache is finished. + * 0: Not finished + * 1: Finished */ #define CACHE_L1_CACHE_AUTOLOAD_DONE (BIT(1)) #define CACHE_L1_CACHE_AUTOLOAD_DONE_M (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S) #define CACHE_L1_CACHE_AUTOLOAD_DONE_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_DONE_S 1 /** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-Cache. 0: - * ascending. 1: descending. + * Configures the direction of the autoloading operation in the L1 cache. + * 0: Ascending + * 1: Descending */ #define CACHE_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) #define CACHE_L1_CACHE_AUTOLOAD_ORDER_M (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S) #define CACHE_L1_CACHE_AUTOLOAD_ORDER_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_ORDER_S 2 /** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + * Configures the trigger mode of the autoloading operation in the L1 cache. + * 0/3: Triggered by misses + * 1: Triggered by hits + * 2: Triggered by misses or hits */ #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S) #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U #define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 /** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-Cache. + * Configures whether to enable Section 0 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S) #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 /** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-Cache. + * Configures whether to enable Section 1 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S) #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L1-Cache. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S 10 -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L1-Cache. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S 11 -/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l1 cache autoload. - */ -#define CACHE_L1_CACHE_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L1_CACHE_AUTOLOAD_RGID_M (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S) -#define CACHE_L1_CACHE_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L1_CACHE_AUTOLOAD_RGID_S 12 /** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register - * L1 Cache autoload section 0 address configure register + * L1 cache autoloading Section 0 address configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x134) /** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the starting virtual address of Section 0 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S) @@ -2227,13 +545,13 @@ extern "C" { #define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 /** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register - * L1 Cache autoload section 0 size configure register + * L1 cache autoloading Section 0 size configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x138) /** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the size of Section 0 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x01FFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S) @@ -2241,13 +559,13 @@ extern "C" { #define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 /** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register - * L1 Cache autoload section 1 address configure register + * L1 cache autoloading Section 1 address configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x13c) /** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the starting virtual address of Section 1 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S) @@ -2255,378 +573,104 @@ extern "C" { #define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 /** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register - * L1 Cache autoload section 1 size configure register + * L1 cache autoloading Section 1 size configuration register */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x140) /** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the size of Section 1 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x01FFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S) #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0x01FFFFFFU #define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register - * L1 Cache autoload section 2 address configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x144) -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S 0 - -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register - * L1 Cache autoload section 2 size configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x148) -/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S 0 - -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register - * L1 Cache autoload section 1 address configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x14c) -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S 0 - -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register - * L1 Cache autoload section 1 size configure register - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x150) -/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S) -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V 0x01FFFFFFU -#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S 0 - /** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register - * Cache Access Counter Interrupt enable register + * Cache access counter interrupt enable register */ #define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x154) -/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_ENA (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_ENA_M (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S) -#define CACHE_L1_IBUS0_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_ENA_S 0 -/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_ENA (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_ENA_M (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S) -#define CACHE_L1_IBUS1_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_ENA_S 1 -/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_OVF_INT_ENA (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_ENA_M (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S) -#define CACHE_L1_IBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_ENA_S 2 -/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_OVF_INT_ENA (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_ENA_M (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S) -#define CACHE_L1_IBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_ENA_S 3 /** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * Write 1 to enable L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_ENA (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_ENA_M (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S) #define CACHE_L1_BUS0_OVF_INT_ENA_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_ENA_S 4 /** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * Write 1 to enable L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_ENA (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_ENA_M (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S) #define CACHE_L1_BUS1_OVF_INT_ENA_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_ENA_S 5 -/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_OVF_INT_ENA (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_ENA_M (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S) -#define CACHE_L1_DBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_ENA_S 6 -/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_OVF_INT_ENA (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_ENA_M (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S) -#define CACHE_L1_DBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_ENA_S 7 /** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register - * Cache Access Counter Interrupt clear register + * Cache access counter interrupt clear register */ #define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x158) -/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due - * to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_CLR (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_CLR_M (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S) -#define CACHE_L1_IBUS0_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_CLR_S 0 -/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due - * to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_CLR (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_CLR_M (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S) -#define CACHE_L1_IBUS1_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_CLR_S 1 -/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_OVF_INT_CLR (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_CLR_M (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S) -#define CACHE_L1_IBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_CLR_S 2 -/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_OVF_INT_CLR (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_CLR_M (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S) -#define CACHE_L1_IBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_CLR_S 3 /** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus0 accesses L1-DCache. + * Write 1 to clear L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_CLR (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_CLR_M (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S) #define CACHE_L1_BUS0_OVF_INT_CLR_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_CLR_S 4 /** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus1 accesses L1-DCache. + * Write 1 to clear L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_CLR (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_CLR_M (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S) #define CACHE_L1_BUS1_OVF_INT_CLR_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_CLR_S 5 -/** CACHE_L1_DBUS2_OVF_INT_CLR : R/W; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_OVF_INT_CLR (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_CLR_M (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S) -#define CACHE_L1_DBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_CLR_S 6 -/** CACHE_L1_DBUS3_OVF_INT_CLR : R/W; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_OVF_INT_CLR (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_CLR_M (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S) -#define CACHE_L1_DBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_CLR_S 7 /** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register - * Cache Access Counter Interrupt raw register + * Cache access counter interrupt raw register */ #define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x15c) -/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 - * due to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_RAW (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_RAW_M (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S) -#define CACHE_L1_IBUS0_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_RAW_S 0 -/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 - * due to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_RAW (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_RAW_M (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S) -#define CACHE_L1_IBUS1_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_RAW_S 1 -/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 - * due to bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_OVF_INT_RAW (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_RAW_M (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S) -#define CACHE_L1_IBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_RAW_S 2 -/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 - * due to bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_OVF_INT_RAW (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_RAW_M (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S) -#define CACHE_L1_IBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_RAW_S 3 /** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus0 accesses L1-DCache. + * The raw interrupt status of L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_RAW (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_RAW_M (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S) #define CACHE_L1_BUS0_OVF_INT_RAW_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_RAW_S 4 /** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus1 accesses L1-DCache. + * The raw interrupt status of L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_RAW (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_RAW_M (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S) #define CACHE_L1_BUS1_OVF_INT_RAW_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_RAW_S 5 -/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_OVF_INT_RAW (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_RAW_M (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S) -#define CACHE_L1_DBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_RAW_S 6 -/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_OVF_INT_RAW (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_RAW_M (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S) -#define CACHE_L1_DBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_RAW_S 7 /** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register - * Cache Access Counter Interrupt status register + * Cache access counter interrupt status register */ #define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x160) -/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_OVF_INT_ST (BIT(0)) -#define CACHE_L1_IBUS0_OVF_INT_ST_M (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S) -#define CACHE_L1_IBUS0_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS0_OVF_INT_ST_S 0 -/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_OVF_INT_ST (BIT(1)) -#define CACHE_L1_IBUS1_OVF_INT_ST_M (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S) -#define CACHE_L1_IBUS1_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS1_OVF_INT_ST_S 1 -/** CACHE_L1_IBUS2_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_OVF_INT_ST (BIT(2)) -#define CACHE_L1_IBUS2_OVF_INT_ST_M (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S) -#define CACHE_L1_IBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS2_OVF_INT_ST_S 2 -/** CACHE_L1_IBUS3_OVF_INT_ST : RO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_OVF_INT_ST (BIT(3)) -#define CACHE_L1_IBUS3_OVF_INT_ST_M (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S) -#define CACHE_L1_IBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_IBUS3_OVF_INT_ST_S 3 /** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * The masked interrupt status of L1_BUS0_OVF_INT. */ #define CACHE_L1_BUS0_OVF_INT_ST (BIT(4)) #define CACHE_L1_BUS0_OVF_INT_ST_M (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S) #define CACHE_L1_BUS0_OVF_INT_ST_V 0x00000001U #define CACHE_L1_BUS0_OVF_INT_ST_S 4 /** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * The masked interrupt status of L1_BUS1_OVF_INT. */ #define CACHE_L1_BUS1_OVF_INT_ST (BIT(5)) #define CACHE_L1_BUS1_OVF_INT_ST_M (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S) #define CACHE_L1_BUS1_OVF_INT_ST_V 0x00000001U #define CACHE_L1_BUS1_OVF_INT_ST_S 5 -/** CACHE_L1_DBUS2_OVF_INT_ST : RO; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_OVF_INT_ST (BIT(6)) -#define CACHE_L1_DBUS2_OVF_INT_ST_M (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S) -#define CACHE_L1_DBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_DBUS2_OVF_INT_ST_S 6 -/** CACHE_L1_DBUS3_OVF_INT_ST : RO; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_OVF_INT_ST (BIT(7)) -#define CACHE_L1_DBUS3_OVF_INT_ST_M (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S) -#define CACHE_L1_DBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L1_DBUS3_OVF_INT_ST_S 7 /** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register - * Cache Access Fail Configuration register + * Cache access failed interrupt configuration register */ #define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x164) -/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l1 icache0 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE (BIT(0)) -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S 0 -/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : HRO; bitpos: [1]; default: 0; - * The bit is used to configure l1 icache1 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE (BIT(1)) -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S 1 -/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : HRO; bitpos: [2]; default: 0; - * The bit is used to configure l1 icache2 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE (BIT(2)) -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S 2 -/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : HRO; bitpos: [3]; default: 0; - * The bit is used to configure l1 icache3 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE (BIT(3)) -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S 3 /** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0; - * The bit is used to configure l1 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request + * Configures whether to pass the exception of cache accessing lower-level memory to + * the upper-level device. + * 0: Do not pass to the upper-level device + * 1: Pass to the upper-level device */ #define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE (BIT(4)) #define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S) @@ -2634,42 +678,11 @@ extern "C" { #define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register - * Cache Access Fail Interrupt enable register + * Cache access failed interrupt enable register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168) -/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_ENA (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FAIL_INT_ENA (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FAIL_INT_ENA (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S) -#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S 3 /** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to enable L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_ENA (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_ENA_M (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S) @@ -2677,42 +690,11 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_ENA_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register - * L1-Cache Access Fail Interrupt clear register + * L1 cache access failed interrupt clear register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c) -/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_CLR : WT; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FAIL_INT_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_CLR : WT; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FAIL_INT_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S) -#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S 3 /** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to clear L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_CLR (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_CLR_M (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S) @@ -2720,39 +702,11 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_CLR_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register - * Cache Access Fail Interrupt raw register + * Cache access failed interrupt raw register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170) -/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache0. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_RAW (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache1. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_RAW (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache2. - */ -#define CACHE_L1_ICACHE2_FAIL_INT_RAW (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache3. - */ -#define CACHE_L1_ICACHE3_FAIL_INT_RAW (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S) -#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S 3 /** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-DCache. + * The raw interrupt status of L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_RAW (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_RAW_M (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S) @@ -2760,42 +714,11 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_RAW_S 4 /** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register - * Cache Access Fail Interrupt status register + * Cache access failed interrupt status register */ #define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174) -/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due - * to cpu accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_INT_ST (BIT(0)) -#define CACHE_L1_ICACHE0_FAIL_INT_ST_M (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE0_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE0_FAIL_INT_ST_S 0 -/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due - * to cpu accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_INT_ST (BIT(1)) -#define CACHE_L1_ICACHE1_FAIL_INT_ST_M (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE1_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE1_FAIL_INT_ST_S 1 -/** CACHE_L1_ICACHE2_FAIL_INT_ST : RO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_FAIL_INT_ST (BIT(2)) -#define CACHE_L1_ICACHE2_FAIL_INT_ST_M (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE2_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE2_FAIL_INT_ST_S 2 -/** CACHE_L1_ICACHE3_FAIL_INT_ST : RO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_FAIL_INT_ST (BIT(3)) -#define CACHE_L1_ICACHE3_FAIL_INT_ST_M (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S) -#define CACHE_L1_ICACHE3_FAIL_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE3_FAIL_INT_ST_S 3 /** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-DCache due - * to cpu accesses L1-DCache. + * The masked interrupt status of L1_CACHE_FAIL_INT. */ #define CACHE_L1_CACHE_FAIL_INT_ST (BIT(4)) #define CACHE_L1_CACHE_FAIL_INT_ST_M (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S) @@ -2803,324 +726,52 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_INT_ST_S 4 /** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register - * Cache Access Counter enable and clear register + * Cache access counter enable and clear register */ #define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178) -/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable ibus0 counter in L1-ICache0. - */ -#define CACHE_L1_IBUS0_CNT_ENA (BIT(0)) -#define CACHE_L1_IBUS0_CNT_ENA_M (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S) -#define CACHE_L1_IBUS0_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS0_CNT_ENA_S 0 -/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable ibus1 counter in L1-ICache1. - */ -#define CACHE_L1_IBUS1_CNT_ENA (BIT(1)) -#define CACHE_L1_IBUS1_CNT_ENA_M (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S) -#define CACHE_L1_IBUS1_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS1_CNT_ENA_S 1 -/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_CNT_ENA (BIT(2)) -#define CACHE_L1_IBUS2_CNT_ENA_M (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S) -#define CACHE_L1_IBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS2_CNT_ENA_S 2 -/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_CNT_ENA (BIT(3)) -#define CACHE_L1_IBUS3_CNT_ENA_M (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S) -#define CACHE_L1_IBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L1_IBUS3_CNT_ENA_S 3 /** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable dbus0 counter in L1-DCache. + * Configures whether to enable the BUS0 counters in the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_BUS0_CNT_ENA (BIT(4)) #define CACHE_L1_BUS0_CNT_ENA_M (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S) #define CACHE_L1_BUS0_CNT_ENA_V 0x00000001U #define CACHE_L1_BUS0_CNT_ENA_S 4 /** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0; - * The bit is used to enable dbus1 counter in L1-DCache. + * Configures whether to enable the BUS1 counters in the L1 cache. + * 0: Disable + * 1: Enable */ #define CACHE_L1_BUS1_CNT_ENA (BIT(5)) #define CACHE_L1_BUS1_CNT_ENA_M (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S) #define CACHE_L1_BUS1_CNT_ENA_V 0x00000001U #define CACHE_L1_BUS1_CNT_ENA_S 5 -/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_CNT_ENA (BIT(6)) -#define CACHE_L1_DBUS2_CNT_ENA_M (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S) -#define CACHE_L1_DBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L1_DBUS2_CNT_ENA_S 6 -/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_CNT_ENA (BIT(7)) -#define CACHE_L1_DBUS3_CNT_ENA_M (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S) -#define CACHE_L1_DBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L1_DBUS3_CNT_ENA_S 7 -/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0; - * The bit is used to clear ibus0 counter in L1-ICache0. - */ -#define CACHE_L1_IBUS0_CNT_CLR (BIT(16)) -#define CACHE_L1_IBUS0_CNT_CLR_M (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S) -#define CACHE_L1_IBUS0_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS0_CNT_CLR_S 16 -/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0; - * The bit is used to clear ibus1 counter in L1-ICache1. - */ -#define CACHE_L1_IBUS1_CNT_CLR (BIT(17)) -#define CACHE_L1_IBUS1_CNT_CLR_M (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S) -#define CACHE_L1_IBUS1_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS1_CNT_CLR_S 17 -/** CACHE_L1_IBUS2_CNT_CLR : WT; bitpos: [18]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS2_CNT_CLR (BIT(18)) -#define CACHE_L1_IBUS2_CNT_CLR_M (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S) -#define CACHE_L1_IBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS2_CNT_CLR_S 18 -/** CACHE_L1_IBUS3_CNT_CLR : WT; bitpos: [19]; default: 0; - * Reserved - */ -#define CACHE_L1_IBUS3_CNT_CLR (BIT(19)) -#define CACHE_L1_IBUS3_CNT_CLR_M (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S) -#define CACHE_L1_IBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L1_IBUS3_CNT_CLR_S 19 /** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0; - * The bit is used to clear dbus0 counter in L1-DCache. + * Configures whether to clear the BUS0 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ #define CACHE_L1_BUS0_CNT_CLR (BIT(20)) #define CACHE_L1_BUS0_CNT_CLR_M (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S) #define CACHE_L1_BUS0_CNT_CLR_V 0x00000001U #define CACHE_L1_BUS0_CNT_CLR_S 20 /** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0; - * The bit is used to clear dbus1 counter in L1-DCache. + * Configures whether to clear the BUS1 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ #define CACHE_L1_BUS1_CNT_CLR (BIT(21)) #define CACHE_L1_BUS1_CNT_CLR_M (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S) #define CACHE_L1_BUS1_CNT_CLR_V 0x00000001U #define CACHE_L1_BUS1_CNT_CLR_S 21 -/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS2_CNT_CLR (BIT(22)) -#define CACHE_L1_DBUS2_CNT_CLR_M (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S) -#define CACHE_L1_DBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L1_DBUS2_CNT_CLR_S 22 -/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0; - * Reserved - */ -#define CACHE_L1_DBUS3_CNT_CLR (BIT(23)) -#define CACHE_L1_DBUS3_CNT_CLR_M (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S) -#define CACHE_L1_DBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L1_DBUS3_CNT_CLR_S 23 - -/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register - * L1-ICache bus0 Hit-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c) -/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_HIT_CNT_M (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S) -#define CACHE_L1_IBUS0_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_HIT_CNT_S 0 - -/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register - * L1-ICache bus0 Miss-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180) -/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_MISS_CNT_M (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S) -#define CACHE_L1_IBUS0_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_MISS_CNT_S 0 - -/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register - * L1-ICache bus0 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184) -/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-ICache0. - */ -#define CACHE_L1_IBUS0_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_CONFLICT_CNT_M (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S) -#define CACHE_L1_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus0 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x188) -/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register - * L1-ICache bus1 Hit-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c) -/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_HIT_CNT_M (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S) -#define CACHE_L1_IBUS1_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_HIT_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register - * L1-ICache bus1 Miss-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190) -/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_MISS_CNT_M (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S) -#define CACHE_L1_IBUS1_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_MISS_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register - * L1-ICache bus1 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194) -/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-ICache1. - */ -#define CACHE_L1_IBUS1_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_CONFLICT_CNT_M (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S) -#define CACHE_L1_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus1 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x198) -/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register - * L1-ICache bus2 Hit-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c) -/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_HIT_CNT_M (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S) -#define CACHE_L1_IBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_HIT_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register - * L1-ICache bus2 Miss-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0) -/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_MISS_CNT_M (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S) -#define CACHE_L1_IBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_MISS_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register - * L1-ICache bus2 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4) -/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-ICache2. - */ -#define CACHE_L1_IBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_CONFLICT_CNT_M (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S) -#define CACHE_L1_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus2 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1a8) -/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register - * L1-ICache bus3 Hit-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac) -/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_HIT_CNT_M (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S) -#define CACHE_L1_IBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_HIT_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register - * L1-ICache bus3 Miss-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0) -/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_MISS_CNT_M (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S) -#define CACHE_L1_IBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_MISS_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register - * L1-ICache bus3 Conflict-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4) -/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-ICache3. - */ -#define CACHE_L1_IBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_CONFLICT_CNT_M (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S) -#define CACHE_L1_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register - * L1-ICache bus3 Next-Level-Access Counter register - */ -#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1b8) -/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S 0 /** CACHE_L1_BUS0_ACS_HIT_CNT_REG register - * L1-Cache bus0 Hit-Access Counter register + * L1 cache BUS0 hit-access counter register */ #define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc) /** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-Cache. + * Represents the number of hits when BUS0 accesses the L1 cache. */ #define CACHE_L1_BUS0_HIT_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_HIT_CNT_M (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S) @@ -3128,11 +779,11 @@ extern "C" { #define CACHE_L1_BUS0_HIT_CNT_S 0 /** CACHE_L1_BUS0_ACS_MISS_CNT_REG register - * L1-Cache bus0 Miss-Access Counter register + * L1 cache BUS0 missed-access counter register */ #define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0) /** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-Cache. + * Represents the number of misses when BUS0 accesses the L1 cache. */ #define CACHE_L1_BUS0_MISS_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_MISS_CNT_M (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S) @@ -3140,36 +791,37 @@ extern "C" { #define CACHE_L1_BUS0_MISS_CNT_S 0 /** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register - * L1-Cache bus0 Conflict-Access Counter register + * L1 cache BUS0 conflicting-access Counter register */ #define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4) -/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-Cache. +/** CACHE_L1_BUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; + * Represents the number of access conflicts when BUS0 accesses the L1 cache. */ -#define CACHE_L1_BUS0_CONFLICT_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S) -#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S 0 +#define CACHE_L1_BUS0_CONFLICT_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_CNT_M (CACHE_L1_BUS0_CONFLICT_CNT_V << CACHE_L1_BUS0_CONFLICT_CNT_S) +#define CACHE_L1_BUS0_CONFLICT_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS0_CONFLICT_CNT_S 0 -/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register - * L1-Cache bus0 Next-Level-Access Counter register +/** CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG register + * L1 cache BUS0 reads the lower-level memory */ -#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) +#define CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8) /** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus0 accessing L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's read access. */ #define CACHE_L1_BUS0_NXTLVL_RD_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_NXTLVL_RD_CNT_M (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S) #define CACHE_L1_BUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU #define CACHE_L1_BUS0_NXTLVL_RD_CNT_S 0 -/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus0 WB-Access Counter register +/** CACHE_L1_BUS0_ACS_NXTLVL_WR_CNT_REG register + * L1 cache BUS0 writes the lower-level memory */ -#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) +#define CACHE_L1_BUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc) /** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's write access. */ #define CACHE_L1_BUS0_NXTLVL_WR_CNT 0xFFFFFFFFU #define CACHE_L1_BUS0_NXTLVL_WR_CNT_M (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S) @@ -3177,11 +829,11 @@ extern "C" { #define CACHE_L1_BUS0_NXTLVL_WR_CNT_S 0 /** CACHE_L1_BUS1_ACS_HIT_CNT_REG register - * L1-Cache bus1 Hit-Access Counter register + * L1 cache BUS1 hit-access counter register */ #define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d0) /** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-Cache. + * Represents the number of hits when BUS1 accesses the L1 cache. */ #define CACHE_L1_BUS1_HIT_CNT 0xFFFFFFFFU #define CACHE_L1_BUS1_HIT_CNT_M (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S) @@ -3189,11 +841,11 @@ extern "C" { #define CACHE_L1_BUS1_HIT_CNT_S 0 /** CACHE_L1_BUS1_ACS_MISS_CNT_REG register - * L1-Cache bus1 Miss-Access Counter register + * L1 cache BUS1 missed-access counter register */ #define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d4) /** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-Cache. + * Represents the number of misses when BUS1 accesses the L1 cache. */ #define CACHE_L1_BUS1_MISS_CNT 0xFFFFFFFFU #define CACHE_L1_BUS1_MISS_CNT_M (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S) @@ -3201,11 +853,11 @@ extern "C" { #define CACHE_L1_BUS1_MISS_CNT_S 0 /** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register - * L1-Cache bus1 Conflict-Access Counter register + * L1 cache BUS1 conflicting-access counter register */ #define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d8) /** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-Cache. + * Represents the number of access conflicts when BUS1 accesses the L1 cache. */ #define CACHE_L1_BUS1_CONFLICT_CNT 0xFFFFFFFFU #define CACHE_L1_BUS1_CONFLICT_CNT_M (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S) @@ -3213,301 +865,63 @@ extern "C" { #define CACHE_L1_BUS1_CONFLICT_CNT_S 0 /** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register - * L1-DCache bus1 Next-Level-Access Counter register + * L1 cache BUS1 reads the lower-level memory */ #define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1dc) -/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus1 accessing L1-Cache. +/** CACHE_L1_BUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's read access. */ -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S 0 +#define CACHE_L1_BUS1_NXTLVL_RD_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_RD_CNT_M (CACHE_L1_BUS1_NXTLVL_RD_CNT_V << CACHE_L1_BUS1_NXTLVL_RD_CNT_S) +#define CACHE_L1_BUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_RD_CNT_S 0 /** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus1 WB-Access Counter register + * L1 cache BUS1 writes the lower-level memory */ #define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e0) -/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus1 accesses L1-Cache. +/** CACHE_L1_BUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's write access. */ -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S) -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S 0 +#define CACHE_L1_BUS1_NXTLVL_WR_CNT 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_WR_CNT_M (CACHE_L1_BUS1_NXTLVL_WR_CNT_V << CACHE_L1_BUS1_NXTLVL_WR_CNT_S) +#define CACHE_L1_BUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU +#define CACHE_L1_BUS1_NXTLVL_WR_CNT_S 0 -/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register - * L1-DCache bus2 Hit-Access Counter register +/** CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG register + * L1 cache access failed ID and attribution recording register */ -#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4) -/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_HIT_CNT_M (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S) -#define CACHE_L1_DBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_HIT_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register - * L1-DCache bus2 Miss-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e8) -/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_MISS_CNT_M (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S) -#define CACHE_L1_DBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_MISS_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register - * L1-DCache bus2 Conflict-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec) -/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-DCache. - */ -#define CACHE_L1_DBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_CONFLICT_CNT_M (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S) -#define CACHE_L1_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register - * L1-DCache bus2 Next-Level-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f0) -/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus2 accessing L1-Cache. - */ -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus2 WB-Access Counter register - */ -#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f4) -/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus2 accesses L1-Cache. - */ -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S) -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register - * L1-DCache bus3 Hit-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1f8) -/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_HIT_CNT_M (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S) -#define CACHE_L1_DBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_HIT_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register - * L1-DCache bus3 Miss-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1fc) -/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_MISS_CNT_M (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S) -#define CACHE_L1_DBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_MISS_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register - * L1-DCache bus3 Conflict-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x200) -/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-DCache. - */ -#define CACHE_L1_DBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_CONFLICT_CNT_M (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S) -#define CACHE_L1_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register - * L1-DCache bus3 Next-Level-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x204) -/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus3 accessing L1-Cache. - */ -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S 0 - -/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register - * L1-DCache bus3 WB-Access Counter register - */ -#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x208) -/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. - */ -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S) -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S 0 - -/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c) -/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache0 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ID_M (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S) -#define CACHE_L1_ICACHE0_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ID_S 0 -/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache0 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ATTR_M (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S) -#define CACHE_L1_ICACHE0_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE0_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210) -/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache0 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE0_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_FAIL_ADDR_M (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S) -#define CACHE_L1_ICACHE0_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE0_FAIL_ADDR_S 0 - -/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214) -/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache1 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ID_M (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S) -#define CACHE_L1_ICACHE1_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ID_S 0 -/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache1 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ATTR_M (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S) -#define CACHE_L1_ICACHE1_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE1_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218) -/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache1 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE1_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_FAIL_ADDR_M (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S) -#define CACHE_L1_ICACHE1_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE1_FAIL_ADDR_S 0 - -/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c) -/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache2 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE2_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ID_M (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S) -#define CACHE_L1_ICACHE2_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ID_S 0 -/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache2 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE2_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ATTR_M (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S) -#define CACHE_L1_ICACHE2_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE2_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220) -/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache2 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE2_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_FAIL_ADDR_M (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S) -#define CACHE_L1_ICACHE2_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE2_FAIL_ADDR_S 0 - -/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register - * L1-ICache0 Access Fail ID/attribution information register - */ -#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x224) -/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache3 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE3_FAIL_ID 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ID_M (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S) -#define CACHE_L1_ICACHE3_FAIL_ID_V 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ID_S 0 -/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache3 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE3_FAIL_ATTR 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ATTR_M (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S) -#define CACHE_L1_ICACHE3_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L1_ICACHE3_FAIL_ATTR_S 16 - -/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register - * L1-ICache0 Access Fail Address information register - */ -#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x228) -/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache3 accesses L1-ICache. - */ -#define CACHE_L1_ICACHE3_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_FAIL_ADDR_M (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S) -#define CACHE_L1_ICACHE3_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L1_ICACHE3_FAIL_ADDR_S 0 - -/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register - * L1-Cache Access Fail ID/attribution information register - */ -#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c) +#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c) /** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache accesses L1-Cache. + * Represents the ID of the failed access to the L1 cache. + * Bit 4: BUS0 + * Bit 5: BUS1 + * Others: reserved */ #define CACHE_L1_CACHE_FAIL_ID 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ID_M (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S) #define CACHE_L1_CACHE_FAIL_ID_V 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ID_S 0 /** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache accesses L1-Cache. + * Represents the attribute of the failed access to the L1 cache. + * Bit 0: Fetching instructions + * Bit 1: Reading data + * Bit 7: non-cacheable + * Others: reserved */ #define CACHE_L1_CACHE_FAIL_ATTR 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ATTR_M (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S) #define CACHE_L1_CACHE_FAIL_ATTR_V 0x0000FFFFU #define CACHE_L1_CACHE_FAIL_ATTR_S 16 -/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register - * L1-Cache Access Fail Address information register +/** CACHE_L1_CACHE_ACS_FAIL_ADDR_REG register + * L1 cache access failed address information register */ -#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230) +#define CACHE_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230) /** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache accesses L1-Cache. + * Represents the address of the failed access to the L1 cache. */ #define CACHE_L1_CACHE_FAIL_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_FAIL_ADDR_M (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S) @@ -3515,91 +929,32 @@ extern "C" { #define CACHE_L1_CACHE_FAIL_ADDR_S 0 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register - * L1-Cache Access Fail Interrupt enable register + * Sync and preloading operation interrupt enable register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x234) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload - * operation is done, interrupt occurs. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload - * operation is done, interrupt occurs. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation. If preload - * operation is done, interrupt occurs. + * Write 1 to enable L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S) #define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S 4 /** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation done. + * Write 1 to enable CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_ENA (BIT(6)) #define CACHE_SYNC_DONE_INT_ENA_M (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S) #define CACHE_SYNC_DONE_INT_ENA_V 0x00000001U #define CACHE_SYNC_DONE_INT_ENA_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation error. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation error. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation error. + * Write 1 to enable CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S) #define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S 11 /** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation error. + * Write 1 to enable CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_ENA (BIT(13)) #define CACHE_SYNC_ERR_INT_ENA_M (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S) @@ -3607,92 +962,32 @@ extern "C" { #define CACHE_SYNC_ERR_INT_ENA_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register - * Sync Preload operation Interrupt clear register + * Sync and preloading operation interrupt clear register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x238) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation - * is done. + * Write 1 to clear L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S) #define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S 4 /** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0; - * The bit is used to clear interrupt that occurs only when Cache sync-operation is - * done. + * Write 1 to clear CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_CLR (BIT(6)) #define CACHE_SYNC_DONE_INT_CLR_M (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S) #define CACHE_SYNC_DONE_INT_CLR_V 0x00000001U #define CACHE_SYNC_DONE_INT_CLR_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0; - * The bit is used to clear interrupt of L1-ICache0 preload-operation error. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; - * The bit is used to clear interrupt of L1-ICache1 preload-operation error. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0; - * The bit is used to clear interrupt of L1-Cache preload-operation error. + * Write 1 to clear L1_CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S) #define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S 11 /** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0; - * The bit is used to clear interrupt of Cache sync-operation error. + * Write 1 to clear CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_CLR (BIT(13)) #define CACHE_SYNC_ERR_INT_CLR_M (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S) @@ -3700,95 +995,32 @@ extern "C" { #define CACHE_SYNC_ERR_INT_CLR_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register - * Sync Preload operation Interrupt raw register + * Sync and preloading operation interrupt raw register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x23c) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is - * done. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is - * done. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is - * done. + * The raw interrupt status of L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S) #define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S 4 /** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + * The raw interrupt status of CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_RAW (BIT(6)) #define CACHE_SYNC_DONE_INT_RAW_M (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S) #define CACHE_SYNC_DONE_INT_RAW_V 0x00000001U #define CACHE_SYNC_DONE_INT_RAW_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation - * error occurs. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation - * error occurs. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error - * occurs. + * The raw interrupt status of L1_CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S) #define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S 11 /** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation error - * occurs. + * The raw interrupt status of CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_RAW (BIT(13)) #define CACHE_SYNC_ERR_INT_RAW_M (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S) @@ -3796,92 +1028,32 @@ extern "C" { #define CACHE_SYNC_ERR_INT_RAW_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register - * L1-Cache Access Fail Interrupt status register + * Sync and preloading operation interrupt status register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x240) -/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S 0 -/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S 1 -/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S 2 -/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S) -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S 3 /** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-Cache - * preload-operation is done. + * The masked interrupt status of L1_CACHE_PLD_DONE_INT. */ #define CACHE_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) #define CACHE_L1_CACHE_PLD_DONE_INT_ST_M (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S) #define CACHE_L1_CACHE_PLD_DONE_INT_ST_V 0x00000001U #define CACHE_L1_CACHE_PLD_DONE_INT_ST_S 4 /** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0; - * The bit indicates the status of the interrupt that occurs only when Cache - * sync-operation is done. + * The masked interrupt status of CACHE_SYNC_DONE_INT. */ #define CACHE_SYNC_DONE_INT_ST (BIT(6)) #define CACHE_SYNC_DONE_INT_ST_M (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S) #define CACHE_SYNC_DONE_INT_ST_V 0x00000001U #define CACHE_SYNC_DONE_INT_ST_S 6 -/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST (BIT(7)) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S 7 -/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST (BIT(8)) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S 8 -/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST (BIT(9)) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S 9 -/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST (BIT(10)) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S) -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S 10 /** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0; - * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + * The masked interrupt status of L1_CACHE_PLD_ERR_INT. */ #define CACHE_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) #define CACHE_L1_CACHE_PLD_ERR_INT_ST_M (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S) #define CACHE_L1_CACHE_PLD_ERR_INT_ST_V 0x00000001U #define CACHE_L1_CACHE_PLD_ERR_INT_ST_S 11 /** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0; - * The bit indicates the status of the interrupt of Cache sync-operation error. + * The masked interrupt status of CACHE_SYNC_ERR_INT. */ #define CACHE_SYNC_ERR_INT_ST (BIT(13)) #define CACHE_SYNC_ERR_INT_ST_M (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S) @@ -3889,47 +1061,24 @@ extern "C" { #define CACHE_SYNC_ERR_INT_ST_S 13 /** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register - * Cache Sync/Preload Operation exception register + * Cache sync and preloading operation exception register */ #define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x244) -/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache0. - */ -#define CACHE_L1_ICACHE0_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S 0 -/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache1. - */ -#define CACHE_L1_ICACHE1_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S 2 -/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S 4 -/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_ERR_CODE 0x00000003U -#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S) -#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S 6 /** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0; - * The value 2 is Only available which means preload size is error in L1-Cache. + * Represents the error code for the failed preloading operation. + * 2: The preloading size in the L1 cache is wrong + * Other values: reserved */ #define CACHE_L1_CACHE_PLD_ERR_CODE 0x00000003U #define CACHE_L1_CACHE_PLD_ERR_CODE_M (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S) #define CACHE_L1_CACHE_PLD_ERR_CODE_V 0x00000003U #define CACHE_L1_CACHE_PLD_ERR_CODE_S 8 /** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0; - * The values 0-2 are available which means sync map, command conflict and size are - * error in Cache System. + * Represents the error code for the failed synchronization operation. + * 0: Incorrect synchronization map + * 1: Synchronization command conflict + * 2: Incorrect synchronization size + * 3: Reserved */ #define CACHE_SYNC_ERR_CODE 0x00000003U #define CACHE_SYNC_ERR_CODE_M (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S) @@ -3937,42 +1086,15 @@ extern "C" { #define CACHE_SYNC_ERR_CODE_S 12 /** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register - * Cache Sync Reset control register + * Cache sync reset control register */ #define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x248) -/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0; - * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ -#define CACHE_L1_ICACHE0_SYNC_RST (BIT(0)) -#define CACHE_L1_ICACHE0_SYNC_RST_M (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S) -#define CACHE_L1_ICACHE0_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE0_SYNC_RST_S 0 -/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0; - * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ -#define CACHE_L1_ICACHE1_SYNC_RST (BIT(1)) -#define CACHE_L1_ICACHE1_SYNC_RST_M (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S) -#define CACHE_L1_ICACHE1_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE1_SYNC_RST_S 1 -/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_SYNC_RST (BIT(2)) -#define CACHE_L1_ICACHE2_SYNC_RST_M (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S) -#define CACHE_L1_ICACHE2_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE2_SYNC_RST_S 2 -/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_SYNC_RST (BIT(3)) -#define CACHE_L1_ICACHE3_SYNC_RST_M (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S) -#define CACHE_L1_ICACHE3_SYNC_RST_V 0x00000001U -#define CACHE_L1_ICACHE3_SYNC_RST_S 3 /** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0; - * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. + * Configures whether to reset the synchronization logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * synchronization logic occurs. */ #define CACHE_L1_CACHE_SYNC_RST (BIT(4)) #define CACHE_L1_CACHE_SYNC_RST_M (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S) @@ -3980,45 +1102,15 @@ extern "C" { #define CACHE_L1_CACHE_SYNC_RST_S 4 /** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register - * Cache Preload Reset control register + * Cache preloading reset control register */ #define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c) -/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0; - * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ -#define CACHE_L1_ICACHE0_PLD_RST (BIT(0)) -#define CACHE_L1_ICACHE0_PLD_RST_M (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S) -#define CACHE_L1_ICACHE0_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE0_PLD_RST_S 0 -/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0; - * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ -#define CACHE_L1_ICACHE1_PLD_RST (BIT(1)) -#define CACHE_L1_ICACHE1_PLD_RST_M (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S) -#define CACHE_L1_ICACHE1_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE1_PLD_RST_S 1 -/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_PLD_RST (BIT(2)) -#define CACHE_L1_ICACHE2_PLD_RST_M (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S) -#define CACHE_L1_ICACHE2_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE2_PLD_RST_S 2 -/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_PLD_RST (BIT(3)) -#define CACHE_L1_ICACHE3_PLD_RST_M (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S) -#define CACHE_L1_ICACHE3_PLD_RST_V 0x00000001U -#define CACHE_L1_ICACHE3_PLD_RST_S 3 /** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0; - * set this bit to reset preload-logic inside L1-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. + * Configures whether to reset the preloading logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * preloading logic occurs. */ #define CACHE_L1_CACHE_PLD_RST (BIT(4)) #define CACHE_L1_CACHE_PLD_RST_M (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S) @@ -4026,169 +1118,40 @@ extern "C" { #define CACHE_L1_CACHE_PLD_RST_S 4 /** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register - * Cache Autoload buffer clear control register + * Cache autoloading buffer clear control register */ #define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x250) -/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, - * autoload will not work in L1-ICache0. This bit should not be active when autoload - * works in L1-ICache0. - */ -#define CACHE_L1_ICACHE0_ALD_BUF_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S 0 -/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, - * autoload will not work in L1-ICache1. This bit should not be active when autoload - * works in L1-ICache1. - */ -#define CACHE_L1_ICACHE1_ALD_BUF_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S 1 -/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_ALD_BUF_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S 2 -/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_ALD_BUF_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S) -#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S 3 /** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0; - * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, - * autoload will not work in L1-Cache. This bit should not be active when autoload - * works in L1-Cache. + * Configures whether to clear the autoloading buffer inside the L1 cache. + * 0: Not clear the buffer. Recommended when autoloading of L1 cache is used. + * 1: Clear the buffer. Once set, autoloading of L1 cache will stop working. */ #define CACHE_L1_CACHE_ALD_BUF_CLR (BIT(4)) #define CACHE_L1_CACHE_ALD_BUF_CLR_M (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S) #define CACHE_L1_CACHE_ALD_BUF_CLR_V 0x00000001U #define CACHE_L1_CACHE_ALD_BUF_CLR_S 4 -/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register - * Unallocate request buffer clear registers - */ -#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254) -/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responded but not completed. - */ -#define CACHE_L1_ICACHE0_UNALLOC_CLR (BIT(0)) -#define CACHE_L1_ICACHE0_UNALLOC_CLR_M (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE0_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE0_UNALLOC_CLR_S 0 -/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responded but not completed. - */ -#define CACHE_L1_ICACHE1_UNALLOC_CLR (BIT(1)) -#define CACHE_L1_ICACHE1_UNALLOC_CLR_M (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE1_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE1_UNALLOC_CLR_S 1 -/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_UNALLOC_CLR (BIT(2)) -#define CACHE_L1_ICACHE2_UNALLOC_CLR_M (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE2_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE2_UNALLOC_CLR_S 2 -/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_UNALLOC_CLR (BIT(3)) -#define CACHE_L1_ICACHE3_UNALLOC_CLR_M (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S) -#define CACHE_L1_ICACHE3_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_ICACHE3_UNALLOC_CLR_S 3 -/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responded but not completed. - */ -#define CACHE_L1_CACHE_UNALLOC_CLR (BIT(4)) -#define CACHE_L1_CACHE_UNALLOC_CLR_M (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S) -#define CACHE_L1_CACHE_UNALLOC_CLR_V 0x00000001U -#define CACHE_L1_CACHE_UNALLOC_CLR_S 4 - /** CACHE_L1_CACHE_OBJECT_CTRL_REG register - * Cache Tag and Data memory Object control register + * Cache tag and data memory object control register */ #define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x258) -/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0; - * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L1_ICACHE0_TAG_OBJECT (BIT(0)) -#define CACHE_L1_ICACHE0_TAG_OBJECT_M (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S) -#define CACHE_L1_ICACHE0_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE0_TAG_OBJECT_S 0 -/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0; - * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L1_ICACHE1_TAG_OBJECT (BIT(1)) -#define CACHE_L1_ICACHE1_TAG_OBJECT_M (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S) -#define CACHE_L1_ICACHE1_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE1_TAG_OBJECT_S 1 -/** CACHE_L1_ICACHE2_TAG_OBJECT : R/W; bitpos: [2]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_TAG_OBJECT (BIT(2)) -#define CACHE_L1_ICACHE2_TAG_OBJECT_M (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S) -#define CACHE_L1_ICACHE2_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE2_TAG_OBJECT_S 2 -/** CACHE_L1_ICACHE3_TAG_OBJECT : R/W; bitpos: [3]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_TAG_OBJECT (BIT(3)) -#define CACHE_L1_ICACHE3_TAG_OBJECT_M (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S) -#define CACHE_L1_ICACHE3_TAG_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE3_TAG_OBJECT_S 3 /** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0; - * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache tag memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ #define CACHE_L1_CACHE_TAG_OBJECT (BIT(4)) #define CACHE_L1_CACHE_TAG_OBJECT_M (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S) #define CACHE_L1_CACHE_TAG_OBJECT_V 0x00000001U #define CACHE_L1_CACHE_TAG_OBJECT_S 4 -/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0; - * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ -#define CACHE_L1_ICACHE0_MEM_OBJECT (BIT(6)) -#define CACHE_L1_ICACHE0_MEM_OBJECT_M (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S) -#define CACHE_L1_ICACHE0_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE0_MEM_OBJECT_S 6 -/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0; - * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ -#define CACHE_L1_ICACHE1_MEM_OBJECT (BIT(7)) -#define CACHE_L1_ICACHE1_MEM_OBJECT_M (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S) -#define CACHE_L1_ICACHE1_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE1_MEM_OBJECT_S 7 -/** CACHE_L1_ICACHE2_MEM_OBJECT : R/W; bitpos: [8]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE2_MEM_OBJECT (BIT(8)) -#define CACHE_L1_ICACHE2_MEM_OBJECT_M (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S) -#define CACHE_L1_ICACHE2_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE2_MEM_OBJECT_S 8 -/** CACHE_L1_ICACHE3_MEM_OBJECT : R/W; bitpos: [9]; default: 0; - * Reserved - */ -#define CACHE_L1_ICACHE3_MEM_OBJECT (BIT(9)) -#define CACHE_L1_ICACHE3_MEM_OBJECT_M (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S) -#define CACHE_L1_ICACHE3_MEM_OBJECT_V 0x00000001U -#define CACHE_L1_ICACHE3_MEM_OBJECT_S 9 /** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0; - * Set this bit to set L1-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache data memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ #define CACHE_L1_CACHE_MEM_OBJECT (BIT(10)) #define CACHE_L1_CACHE_MEM_OBJECT_M (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S) @@ -4196,12 +1159,15 @@ extern "C" { #define CACHE_L1_CACHE_MEM_OBJECT_S 10 /** CACHE_L1_CACHE_WAY_OBJECT_REG register - * Cache Tag and Data memory way register + * Cache tag and data memory way register */ #define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x25c) /** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. + * Configures which way in the tag memory or the data memory to access. + * 0: Way 0 + * 1: Way 1 + * 2: Way 2 + * 3: Way 3 */ #define CACHE_L1_CACHE_WAY_OBJECT 0x00000007U #define CACHE_L1_CACHE_WAY_OBJECT_M (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S) @@ -4213,8 +1179,7 @@ extern "C" { */ #define CACHE_L1_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x260) /** CACHE_L1_CACHE_ADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. + * Configures the virtual address inside the tag memory or data memory to access. */ #define CACHE_L1_CACHE_ADDR 0xFFFFFFFFU #define CACHE_L1_CACHE_ADDR_M (CACHE_L1_CACHE_ADDR_V << CACHE_L1_CACHE_ADDR_S) @@ -4222,1853 +1187,18 @@ extern "C" { #define CACHE_L1_CACHE_ADDR_S 0 /** CACHE_L1_CACHE_DEBUG_BUS_REG register - * Cache Tag/data memory content register + * Cache tag and data memory content register */ #define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x264) /** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 612; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. + * Configures the data to write to or the data to read from the tag memory or the data + * memory. */ #define CACHE_L1_CACHE_DEBUG_BUS 0xFFFFFFFFU #define CACHE_L1_CACHE_DEBUG_BUS_M (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S) #define CACHE_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFFU #define CACHE_L1_CACHE_DEBUG_BUS_S 0 -/** CACHE_LEVEL_SPLIT0_REG register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x268) -/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 616; - * Reserved - */ -#define CACHE_LEVEL_SPLIT0 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT0_M (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S) -#define CACHE_LEVEL_SPLIT0_V 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT0_S 0 - -/** CACHE_L2_CACHE_CTRL_REG register - * L2 Cache(L2-Cache) control register - */ -#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x26c) -/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - */ -#define CACHE_L2_CACHE_SHUT_DMA (BIT(4)) -#define CACHE_L2_CACHE_SHUT_DMA_M (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S) -#define CACHE_L2_CACHE_SHUT_DMA_V 0x00000001U -#define CACHE_L2_CACHE_SHUT_DMA_S 4 -/** CACHE_L2_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ -#define CACHE_L2_CACHE_UNDEF_OP 0x000000FFU -#define CACHE_L2_CACHE_UNDEF_OP_M (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S) -#define CACHE_L2_CACHE_UNDEF_OP_V 0x000000FFU -#define CACHE_L2_CACHE_UNDEF_OP_S 8 - -/** CACHE_L2_BYPASS_CACHE_CONF_REG register - * Bypass Cache configure register - */ -#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x270) -/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0; - * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - */ -#define CACHE_BYPASS_L2_CACHE_EN (BIT(5)) -#define CACHE_BYPASS_L2_CACHE_EN_M (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S) -#define CACHE_BYPASS_L2_CACHE_EN_V 0x00000001U -#define CACHE_BYPASS_L2_CACHE_EN_S 5 - -/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register - * L2 Cache CacheSize mode configure register - */ -#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x274) -/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_256 (BIT(0)) -#define CACHE_L2_CACHE_CACHESIZE_256_M (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S) -#define CACHE_L2_CACHE_CACHESIZE_256_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_256_S 0 -/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_512 (BIT(1)) -#define CACHE_L2_CACHE_CACHESIZE_512_M (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S) -#define CACHE_L2_CACHE_CACHESIZE_512_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_512_S 1 -/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_1K (BIT(2)) -#define CACHE_L2_CACHE_CACHESIZE_1K_M (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S) -#define CACHE_L2_CACHE_CACHESIZE_1K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_1K_S 2 -/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_2K (BIT(3)) -#define CACHE_L2_CACHE_CACHESIZE_2K_M (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S) -#define CACHE_L2_CACHE_CACHESIZE_2K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_2K_S 3 -/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_4K (BIT(4)) -#define CACHE_L2_CACHE_CACHESIZE_4K_M (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S) -#define CACHE_L2_CACHE_CACHESIZE_4K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_4K_S 4 -/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_8K (BIT(5)) -#define CACHE_L2_CACHE_CACHESIZE_8K_M (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S) -#define CACHE_L2_CACHE_CACHESIZE_8K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_8K_S 5 -/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_16K (BIT(6)) -#define CACHE_L2_CACHE_CACHESIZE_16K_M (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S) -#define CACHE_L2_CACHE_CACHESIZE_16K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_16K_S 6 -/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_32K (BIT(7)) -#define CACHE_L2_CACHE_CACHESIZE_32K_M (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S) -#define CACHE_L2_CACHE_CACHESIZE_32K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_32K_S 7 -/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_64K (BIT(8)) -#define CACHE_L2_CACHE_CACHESIZE_64K_M (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S) -#define CACHE_L2_CACHE_CACHESIZE_64K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_64K_S 8 -/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_128K (BIT(9)) -#define CACHE_L2_CACHE_CACHESIZE_128K_M (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S) -#define CACHE_L2_CACHE_CACHESIZE_128K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_128K_S 9 -/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_256K (BIT(10)) -#define CACHE_L2_CACHE_CACHESIZE_256K_M (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S) -#define CACHE_L2_CACHE_CACHESIZE_256K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_256K_S 10 -/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_512K (BIT(11)) -#define CACHE_L2_CACHE_CACHESIZE_512K_M (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S) -#define CACHE_L2_CACHE_CACHESIZE_512K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_512K_S 11 -/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_CACHESIZE_1024K (BIT(12)) -#define CACHE_L2_CACHE_CACHESIZE_1024K_M (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S) -#define CACHE_L2_CACHE_CACHESIZE_1024K_V 0x00000001U -#define CACHE_L2_CACHE_CACHESIZE_1024K_S 12 - -/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register - * L2 Cache BlockSize mode configure register - */ -#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278) -/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_8 (BIT(0)) -#define CACHE_L2_CACHE_BLOCKSIZE_8_M (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S) -#define CACHE_L2_CACHE_BLOCKSIZE_8_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_8_S 0 -/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_16 (BIT(1)) -#define CACHE_L2_CACHE_BLOCKSIZE_16_M (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S) -#define CACHE_L2_CACHE_BLOCKSIZE_16_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_16_S 1 -/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_32 (BIT(2)) -#define CACHE_L2_CACHE_BLOCKSIZE_32_M (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S) -#define CACHE_L2_CACHE_BLOCKSIZE_32_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_32_S 2 -/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all - * other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_64 (BIT(3)) -#define CACHE_L2_CACHE_BLOCKSIZE_64_M (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S) -#define CACHE_L2_CACHE_BLOCKSIZE_64_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_64_S 3 -/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_128 (BIT(4)) -#define CACHE_L2_CACHE_BLOCKSIZE_128_M (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S) -#define CACHE_L2_CACHE_BLOCKSIZE_128_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_128_S 4 -/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ -#define CACHE_L2_CACHE_BLOCKSIZE_256 (BIT(5)) -#define CACHE_L2_CACHE_BLOCKSIZE_256_M (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S) -#define CACHE_L2_CACHE_BLOCKSIZE_256_V 0x00000001U -#define CACHE_L2_CACHE_BLOCKSIZE_256_S 5 - -/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register - * Cache wrap around control register - */ -#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x27c) -/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to enable L2-Cache wrap around mode. - */ -#define CACHE_L2_CACHE_WRAP (BIT(5)) -#define CACHE_L2_CACHE_WRAP_M (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S) -#define CACHE_L2_CACHE_WRAP_V 0x00000001U -#define CACHE_L2_CACHE_WRAP_S 5 - -/** CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG register - * Cache wrap around control register - */ -#define CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x280) -/** CACHE_L2_CACHE_MISS_DISABLE_ACCESS : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to disable early restart of L2-Cache - */ -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS (BIT(5)) -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_M (CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S) -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V 0x00000001U -#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S 5 - -/** CACHE_L2_CACHE_FREEZE_CTRL_REG register - * Cache Freeze control register - */ -#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x284) -/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0; - * The bit is used to enable freeze operation on L2-Cache. It can be cleared by - * software. - */ -#define CACHE_L2_CACHE_FREEZE_EN (BIT(20)) -#define CACHE_L2_CACHE_FREEZE_EN_M (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S) -#define CACHE_L2_CACHE_FREEZE_EN_V 0x00000001U -#define CACHE_L2_CACHE_FREEZE_EN_S 20 -/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0; - * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ -#define CACHE_L2_CACHE_FREEZE_MODE (BIT(21)) -#define CACHE_L2_CACHE_FREEZE_MODE_M (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S) -#define CACHE_L2_CACHE_FREEZE_MODE_V 0x00000001U -#define CACHE_L2_CACHE_FREEZE_MODE_S 21 -/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0; - * The bit is used to indicate whether freeze operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L2_CACHE_FREEZE_DONE (BIT(22)) -#define CACHE_L2_CACHE_FREEZE_DONE_M (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S) -#define CACHE_L2_CACHE_FREEZE_DONE_V 0x00000001U -#define CACHE_L2_CACHE_FREEZE_DONE_S 22 - -/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register - * Cache data memory access configure register - */ -#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x288) -/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_DATA_MEM_RD_EN (BIT(20)) -#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S) -#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V 0x00000001U -#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S 20 -/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_DATA_MEM_WR_EN (BIT(21)) -#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S) -#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V 0x00000001U -#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S 21 - -/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register - * Cache tag memory access configure register - */ -#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x28c) -/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_TAG_MEM_RD_EN (BIT(20)) -#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S) -#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V 0x00000001U -#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S 20 -/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ -#define CACHE_L2_CACHE_TAG_MEM_WR_EN (BIT(21)) -#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S) -#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V 0x00000001U -#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S 21 - -/** CACHE_L2_CACHE_PRELOCK_CONF_REG register - * L2 Cache prelock configure register - */ -#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x290) -/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L2-Cache. - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN (BIT(0)) -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S) -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V 0x00000001U -#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S 0 -/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L2-Cache. - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN (BIT(1)) -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S) -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V 0x00000001U -#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S 1 -/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l2 cache prelock. - */ -#define CACHE_L2_CACHE_PRELOCK_RGID 0x0000000FU -#define CACHE_L2_CACHE_PRELOCK_RGID_M (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S) -#define CACHE_L2_CACHE_PRELOCK_RGID_V 0x0000000FU -#define CACHE_L2_CACHE_PRELOCK_RGID_S 2 - -/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register - * L2 Cache prelock section0 address configure register - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x294) -/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S) -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S 0 - -/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register - * L2 Cache prelock section1 address configure register - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x298) -/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S) -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S 0 - -/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register - * L2 Cache prelock section size configure register - */ -#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x29c) -/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S) -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S 0 -/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535; - * Those bits are used to configure the size of the second section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - */ -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S) -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S 16 - -/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register - * L2 Cache preload-operation control register - */ -#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0) -/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L2-Cache. It will be cleared by - * hardware automatically after preload operation is done. - */ -#define CACHE_L2_CACHE_PRELOAD_ENA (BIT(0)) -#define CACHE_L2_CACHE_PRELOAD_ENA_M (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S) -#define CACHE_L2_CACHE_PRELOAD_ENA_V 0x00000001U -#define CACHE_L2_CACHE_PRELOAD_ENA_S 0 -/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ -#define CACHE_L2_CACHE_PRELOAD_DONE (BIT(1)) -#define CACHE_L2_CACHE_PRELOAD_DONE_M (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S) -#define CACHE_L2_CACHE_PRELOAD_DONE_V 0x00000001U -#define CACHE_L2_CACHE_PRELOAD_DONE_S 1 -/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ -#define CACHE_L2_CACHE_PRELOAD_ORDER (BIT(2)) -#define CACHE_L2_CACHE_PRELOAD_ORDER_M (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S) -#define CACHE_L2_CACHE_PRELOAD_ORDER_V 0x00000001U -#define CACHE_L2_CACHE_PRELOAD_ORDER_S 2 -/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l2 cache preload. - */ -#define CACHE_L2_CACHE_PRELOAD_RGID 0x0000000FU -#define CACHE_L2_CACHE_PRELOAD_RGID_M (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S) -#define CACHE_L2_CACHE_PRELOAD_RGID_V 0x0000000FU -#define CACHE_L2_CACHE_PRELOAD_RGID_S 3 - -/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register - * L2 Cache preload address configure register - */ -#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4) -/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L2-Cache, which - * should be used together with L2_CACHE_PRELOAD_SIZE_REG - */ -#define CACHE_L2_CACHE_PRELOAD_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOAD_ADDR_M (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S) -#define CACHE_L2_CACHE_PRELOAD_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_PRELOAD_ADDR_S 0 - -/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register - * L2 Cache preload size configure register - */ -#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8) -/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - */ -#define CACHE_L2_CACHE_PRELOAD_SIZE 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOAD_SIZE_M (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S) -#define CACHE_L2_CACHE_PRELOAD_SIZE_V 0x0000FFFFU -#define CACHE_L2_CACHE_PRELOAD_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register - * L2 Cache autoload-operation control register - */ -#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2ac) -/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, - * 0: disable. - */ -#define CACHE_L2_CACHE_AUTOLOAD_ENA (BIT(0)) -#define CACHE_L2_CACHE_AUTOLOAD_ENA_M (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_ENA_S 0 -/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ -#define CACHE_L2_CACHE_AUTOLOAD_DONE (BIT(1)) -#define CACHE_L2_CACHE_AUTOLOAD_DONE_M (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S) -#define CACHE_L2_CACHE_AUTOLOAD_DONE_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_DONE_S 1 -/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L2-Cache. 0: - * ascending. 1: descending. - */ -#define CACHE_L2_CACHE_AUTOLOAD_ORDER (BIT(2)) -#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S) -#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S 2 -/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003U -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S) -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x00000003U -#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S 8 -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S 9 -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA (BIT(10)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S 10 -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L2-Cache. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA (BIT(11)) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V 0x00000001U -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S 11 -/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l2 cache autoload. - */ -#define CACHE_L2_CACHE_AUTOLOAD_RGID 0x0000000FU -#define CACHE_L2_CACHE_AUTOLOAD_RGID_M (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S) -#define CACHE_L2_CACHE_AUTOLOAD_RGID_V 0x0000000FU -#define CACHE_L2_CACHE_AUTOLOAD_RGID_S 12 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register - * L2 Cache autoload section 0 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b0) -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register - * L2 Cache autoload section 0 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2b4) -/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register - * L2 Cache autoload section 1 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8) -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register - * L2 Cache autoload section 1 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc) -/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register - * L2 Cache autoload section 2 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0) -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register - * L2 Cache autoload section 2 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4) -/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register - * L2 Cache autoload section 3 address configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8) -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S 0 - -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register - * L2 Cache autoload section 3 size configure register - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc) -/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S) -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V 0x0FFFFFFFU -#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S 0 - -/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register - * Cache Access Counter Interrupt enable register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d0) -/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_IBUS0_OVF_INT_ENA (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_ENA_M (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S) -#define CACHE_L2_IBUS0_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_ENA_S 8 -/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_IBUS1_OVF_INT_ENA (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_ENA_M (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S) -#define CACHE_L2_IBUS1_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_ENA_S 9 -/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_OVF_INT_ENA (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_ENA_M (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S) -#define CACHE_L2_IBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_ENA_S 10 -/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_OVF_INT_ENA (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_ENA_M (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S) -#define CACHE_L2_IBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_ENA_S 11 -/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_DBUS0_OVF_INT_ENA (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_ENA_M (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S) -#define CACHE_L2_DBUS0_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_ENA_S 12 -/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_DBUS1_OVF_INT_ENA (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_ENA_M (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S) -#define CACHE_L2_DBUS1_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_ENA_S 13 -/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_OVF_INT_ENA (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_ENA_M (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S) -#define CACHE_L2_DBUS2_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_ENA_S 14 -/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_OVF_INT_ENA (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_ENA_M (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S) -#define CACHE_L2_DBUS3_OVF_INT_ENA_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_ENA_S 15 - -/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register - * Cache Access Counter Interrupt clear register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d4) -/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ -#define CACHE_L2_IBUS0_OVF_INT_CLR (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_CLR_M (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S) -#define CACHE_L2_IBUS0_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_CLR_S 8 -/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ -#define CACHE_L2_IBUS1_OVF_INT_CLR (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_CLR_M (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S) -#define CACHE_L2_IBUS1_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_CLR_S 9 -/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_OVF_INT_CLR (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_CLR_M (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S) -#define CACHE_L2_IBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_CLR_S 10 -/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_OVF_INT_CLR (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_CLR_M (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S) -#define CACHE_L2_IBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_CLR_S 11 -/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ -#define CACHE_L2_DBUS0_OVF_INT_CLR (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_CLR_M (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S) -#define CACHE_L2_DBUS0_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_CLR_S 12 -/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ -#define CACHE_L2_DBUS1_OVF_INT_CLR (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_CLR_M (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S) -#define CACHE_L2_DBUS1_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_CLR_S 13 -/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_OVF_INT_CLR (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_CLR_M (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S) -#define CACHE_L2_DBUS2_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_CLR_S 14 -/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_OVF_INT_CLR (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_CLR_M (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S) -#define CACHE_L2_DBUS3_OVF_INT_CLR_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_CLR_S 15 - -/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register - * Cache Access Counter Interrupt raw register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2d8) -/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-ICache0. - */ -#define CACHE_L2_IBUS0_OVF_INT_RAW (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_RAW_M (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S) -#define CACHE_L2_IBUS0_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_RAW_S 8 -/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-ICache1. - */ -#define CACHE_L2_IBUS1_OVF_INT_RAW (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_RAW_M (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S) -#define CACHE_L2_IBUS1_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_RAW_S 9 -/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-ICache2. - */ -#define CACHE_L2_IBUS2_OVF_INT_RAW (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_RAW_M (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S) -#define CACHE_L2_IBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_RAW_S 10 -/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-ICache3. - */ -#define CACHE_L2_IBUS3_OVF_INT_RAW (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_RAW_M (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S) -#define CACHE_L2_IBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_RAW_S 11 -/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-DCache. - */ -#define CACHE_L2_DBUS0_OVF_INT_RAW (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_RAW_M (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S) -#define CACHE_L2_DBUS0_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_RAW_S 12 -/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-DCache. - */ -#define CACHE_L2_DBUS1_OVF_INT_RAW (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_RAW_M (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S) -#define CACHE_L2_DBUS1_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_RAW_S 13 -/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-DCache. - */ -#define CACHE_L2_DBUS2_OVF_INT_RAW (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_RAW_M (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S) -#define CACHE_L2_DBUS2_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_RAW_S 14 -/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-DCache. - */ -#define CACHE_L2_DBUS3_OVF_INT_RAW (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_RAW_M (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S) -#define CACHE_L2_DBUS3_OVF_INT_RAW_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_RAW_S 15 - -/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register - * Cache Access Counter Interrupt status register - */ -#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2dc) -/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_IBUS0_OVF_INT_ST (BIT(8)) -#define CACHE_L2_IBUS0_OVF_INT_ST_M (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S) -#define CACHE_L2_IBUS0_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS0_OVF_INT_ST_S 8 -/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_IBUS1_OVF_INT_ST (BIT(9)) -#define CACHE_L2_IBUS1_OVF_INT_ST_M (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S) -#define CACHE_L2_IBUS1_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS1_OVF_INT_ST_S 9 -/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_OVF_INT_ST (BIT(10)) -#define CACHE_L2_IBUS2_OVF_INT_ST_M (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S) -#define CACHE_L2_IBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS2_OVF_INT_ST_S 10 -/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_OVF_INT_ST (BIT(11)) -#define CACHE_L2_IBUS3_OVF_INT_ST_M (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S) -#define CACHE_L2_IBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_IBUS3_OVF_INT_ST_S 11 -/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ -#define CACHE_L2_DBUS0_OVF_INT_ST (BIT(12)) -#define CACHE_L2_DBUS0_OVF_INT_ST_M (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S) -#define CACHE_L2_DBUS0_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS0_OVF_INT_ST_S 12 -/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ -#define CACHE_L2_DBUS1_OVF_INT_ST (BIT(13)) -#define CACHE_L2_DBUS1_OVF_INT_ST_M (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S) -#define CACHE_L2_DBUS1_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS1_OVF_INT_ST_S 13 -/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_OVF_INT_ST (BIT(14)) -#define CACHE_L2_DBUS2_OVF_INT_ST_M (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S) -#define CACHE_L2_DBUS2_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS2_OVF_INT_ST_S 14 -/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_OVF_INT_ST (BIT(15)) -#define CACHE_L2_DBUS3_OVF_INT_ST_M (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S) -#define CACHE_L2_DBUS3_OVF_INT_ST_V 0x00000001U -#define CACHE_L2_DBUS3_OVF_INT_ST_S 15 - -/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register - * Cache Access Fail Configuration register - */ -#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e0) -/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l2 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request - */ -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE (BIT(0)) -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S) -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V 0x00000001U -#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S 0 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register - * Cache Access Fail Interrupt enable register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2e4) -/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to - * l1 cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_ENA (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_ENA_M (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S) -#define CACHE_L2_CACHE_FAIL_INT_ENA_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_ENA_S 5 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register - * L1-Cache Access Fail Interrupt clear register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2e8) -/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 - * cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_CLR (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_CLR_M (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S) -#define CACHE_L2_CACHE_FAIL_INT_CLR_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_CLR_S 5 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register - * Cache Access Fail Interrupt raw register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2ec) -/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_RAW (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_RAW_M (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S) -#define CACHE_L2_CACHE_FAIL_INT_RAW_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_RAW_S 5 - -/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register - * Cache Access Fail Interrupt status register - */ -#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f0) -/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L2-Cache due - * to l1 cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_INT_ST (BIT(5)) -#define CACHE_L2_CACHE_FAIL_INT_ST_M (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S) -#define CACHE_L2_CACHE_FAIL_INT_ST_V 0x00000001U -#define CACHE_L2_CACHE_FAIL_INT_ST_S 5 - -/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register - * Cache Access Counter enable and clear register - */ -#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2f4) -/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0; - * The bit is used to enable ibus0 counter in L2-Cache. - */ -#define CACHE_L2_IBUS0_CNT_ENA (BIT(8)) -#define CACHE_L2_IBUS0_CNT_ENA_M (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S) -#define CACHE_L2_IBUS0_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS0_CNT_ENA_S 8 -/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0; - * The bit is used to enable ibus1 counter in L2-Cache. - */ -#define CACHE_L2_IBUS1_CNT_ENA (BIT(9)) -#define CACHE_L2_IBUS1_CNT_ENA_M (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S) -#define CACHE_L2_IBUS1_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS1_CNT_ENA_S 9 -/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_CNT_ENA (BIT(10)) -#define CACHE_L2_IBUS2_CNT_ENA_M (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S) -#define CACHE_L2_IBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS2_CNT_ENA_S 10 -/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_CNT_ENA (BIT(11)) -#define CACHE_L2_IBUS3_CNT_ENA_M (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S) -#define CACHE_L2_IBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L2_IBUS3_CNT_ENA_S 11 -/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0; - * The bit is used to enable dbus0 counter in L2-Cache. - */ -#define CACHE_L2_DBUS0_CNT_ENA (BIT(12)) -#define CACHE_L2_DBUS0_CNT_ENA_M (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S) -#define CACHE_L2_DBUS0_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS0_CNT_ENA_S 12 -/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0; - * The bit is used to enable dbus1 counter in L2-Cache. - */ -#define CACHE_L2_DBUS1_CNT_ENA (BIT(13)) -#define CACHE_L2_DBUS1_CNT_ENA_M (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S) -#define CACHE_L2_DBUS1_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS1_CNT_ENA_S 13 -/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_CNT_ENA (BIT(14)) -#define CACHE_L2_DBUS2_CNT_ENA_M (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S) -#define CACHE_L2_DBUS2_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS2_CNT_ENA_S 14 -/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_CNT_ENA (BIT(15)) -#define CACHE_L2_DBUS3_CNT_ENA_M (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S) -#define CACHE_L2_DBUS3_CNT_ENA_V 0x00000001U -#define CACHE_L2_DBUS3_CNT_ENA_S 15 -/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0; - * The bit is used to clear ibus0 counter in L2-Cache. - */ -#define CACHE_L2_IBUS0_CNT_CLR (BIT(24)) -#define CACHE_L2_IBUS0_CNT_CLR_M (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S) -#define CACHE_L2_IBUS0_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS0_CNT_CLR_S 24 -/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0; - * The bit is used to clear ibus1 counter in L2-Cache. - */ -#define CACHE_L2_IBUS1_CNT_CLR (BIT(25)) -#define CACHE_L2_IBUS1_CNT_CLR_M (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S) -#define CACHE_L2_IBUS1_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS1_CNT_CLR_S 25 -/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS2_CNT_CLR (BIT(26)) -#define CACHE_L2_IBUS2_CNT_CLR_M (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S) -#define CACHE_L2_IBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS2_CNT_CLR_S 26 -/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0; - * Reserved - */ -#define CACHE_L2_IBUS3_CNT_CLR (BIT(27)) -#define CACHE_L2_IBUS3_CNT_CLR_M (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S) -#define CACHE_L2_IBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L2_IBUS3_CNT_CLR_S 27 -/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0; - * The bit is used to clear dbus0 counter in L2-Cache. - */ -#define CACHE_L2_DBUS0_CNT_CLR (BIT(28)) -#define CACHE_L2_DBUS0_CNT_CLR_M (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S) -#define CACHE_L2_DBUS0_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS0_CNT_CLR_S 28 -/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0; - * The bit is used to clear dbus1 counter in L2-Cache. - */ -#define CACHE_L2_DBUS1_CNT_CLR (BIT(29)) -#define CACHE_L2_DBUS1_CNT_CLR_M (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S) -#define CACHE_L2_DBUS1_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS1_CNT_CLR_S 29 -/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS2_CNT_CLR (BIT(30)) -#define CACHE_L2_DBUS2_CNT_CLR_M (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S) -#define CACHE_L2_DBUS2_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS2_CNT_CLR_S 30 -/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0; - * Reserved - */ -#define CACHE_L2_DBUS3_CNT_CLR (BIT(31)) -#define CACHE_L2_DBUS3_CNT_CLR_M (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S) -#define CACHE_L2_DBUS3_CNT_CLR_V 0x00000001U -#define CACHE_L2_DBUS3_CNT_CLR_S 31 - -/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register - * L2-Cache bus0 Hit-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8) -/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_HIT_CNT_M (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S) -#define CACHE_L2_IBUS0_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_HIT_CNT_S 0 - -/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register - * L2-Cache bus0 Miss-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc) -/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_MISS_CNT_M (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S) -#define CACHE_L2_IBUS0_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_MISS_CNT_S 0 - -/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register - * L2-Cache bus0 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300) -/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache0 accesses - * L2-Cache due to bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_CONFLICT_CNT_M (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S) -#define CACHE_L2_IBUS0_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus0 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x304) -/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. - */ -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register - * L2-Cache bus1 Hit-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308) -/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_HIT_CNT_M (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S) -#define CACHE_L2_IBUS1_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_HIT_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register - * L2-Cache bus1 Miss-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c) -/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_MISS_CNT_M (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S) -#define CACHE_L2_IBUS1_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_MISS_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register - * L2-Cache bus1 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310) -/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache1 accesses - * L2-Cache due to bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_CONFLICT_CNT_M (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S) -#define CACHE_L2_IBUS1_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus1 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x314) -/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. - */ -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register - * L2-Cache bus2 Hit-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318) -/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_HIT_CNT_M (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S) -#define CACHE_L2_IBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_HIT_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register - * L2-Cache bus2 Miss-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c) -/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_MISS_CNT_M (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S) -#define CACHE_L2_IBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_MISS_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register - * L2-Cache bus2 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320) -/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache2 accesses - * L2-Cache due to bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_CONFLICT_CNT_M (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S) -#define CACHE_L2_IBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus2 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x324) -/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. - */ -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register - * L2-Cache bus3 Hit-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328) -/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_HIT_CNT_M (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S) -#define CACHE_L2_IBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_HIT_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register - * L2-Cache bus3 Miss-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c) -/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_MISS_CNT_M (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S) -#define CACHE_L2_IBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_MISS_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register - * L2-Cache bus3 Conflict-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330) -/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache3 accesses - * L2-Cache due to bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_CONFLICT_CNT_M (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S) -#define CACHE_L2_IBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus3 Next-Level-Access Counter register - */ -#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x334) -/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. - */ -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register - * L2-Cache bus0 Hit-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338) -/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_HIT_CNT_M (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S) -#define CACHE_L2_DBUS0_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_HIT_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register - * L2-Cache bus0 Miss-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c) -/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_MISS_CNT_M (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S) -#define CACHE_L2_DBUS0_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_MISS_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register - * L2-Cache bus0 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340) -/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_CONFLICT_CNT_M (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S) -#define CACHE_L2_DBUS0_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus0 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x344) -/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus0 WB-Access Counter register - */ -#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x348) -/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus0 accessing L1-DCache. - */ -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register - * L2-Cache bus1 Hit-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x34c) -/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_HIT_CNT_M (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S) -#define CACHE_L2_DBUS1_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_HIT_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register - * L2-Cache bus1 Miss-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x350) -/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_MISS_CNT_M (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S) -#define CACHE_L2_DBUS1_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_MISS_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register - * L2-Cache bus1 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x354) -/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_CONFLICT_CNT_M (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S) -#define CACHE_L2_DBUS1_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus1 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x358) -/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus1 WB-Access Counter register - */ -#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x35c) -/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus1 accessing L1-DCache. - */ -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register - * L2-Cache bus2 Hit-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x360) -/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_HIT_CNT_M (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S) -#define CACHE_L2_DBUS2_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_HIT_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register - * L2-Cache bus2 Miss-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x364) -/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_MISS_CNT_M (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S) -#define CACHE_L2_DBUS2_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_MISS_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register - * L2-Cache bus2 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x368) -/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_CONFLICT_CNT_M (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S) -#define CACHE_L2_DBUS2_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus2 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x36c) -/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus2 WB-Access Counter register - */ -#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x370) -/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus2 accessing L1-DCache. - */ -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register - * L2-Cache bus3 Hit-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x374) -/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_HIT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_HIT_CNT_M (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S) -#define CACHE_L2_DBUS3_HIT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_HIT_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register - * L2-Cache bus3 Miss-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x378) -/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_MISS_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_MISS_CNT_M (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S) -#define CACHE_L2_DBUS3_MISS_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_MISS_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register - * L2-Cache bus3 Conflict-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x37c) -/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_CONFLICT_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_CONFLICT_CNT_M (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S) -#define CACHE_L2_DBUS3_CONFLICT_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_CONFLICT_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register - * L2-Cache bus3 Next-Level-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x380) -/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S) -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S 0 - -/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register - * L2-Cache bus3 WB-Access Counter register - */ -#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x384) -/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus3 accessing L1-DCache. - */ -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S) -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V 0xFFFFFFFFU -#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S 0 - -/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register - * L2-Cache Access Fail ID/attribution information register - */ -#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x388) -/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when L1-Cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_ID 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ID_M (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S) -#define CACHE_L2_CACHE_FAIL_ID_V 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ID_S 0 -/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when L1-Cache accesses L2-Cache - * due to cache accessing L1-Cache. - */ -#define CACHE_L2_CACHE_FAIL_ATTR 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ATTR_M (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S) -#define CACHE_L2_CACHE_FAIL_ATTR_V 0x0000FFFFU -#define CACHE_L2_CACHE_FAIL_ATTR_S 16 - -/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register - * L2-Cache Access Fail Address information register - */ -#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x38c) -/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when L1-Cache accesses L2-Cache. - */ -#define CACHE_L2_CACHE_FAIL_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_FAIL_ADDR_M (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S) -#define CACHE_L2_CACHE_FAIL_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_FAIL_ADDR_S 0 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register - * L1-Cache Access Fail Interrupt enable register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x390) -/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation error. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register - * Sync Preload operation Interrupt clear register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x394) -/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation - * is done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0; - * The bit is used to clear interrupt of L2-Cache preload-operation error. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register - * Sync Preload operation Interrupt raw register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x398) -/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is - * done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error - * occurs. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register - * L1-Cache Access Fail Interrupt status register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x39c) -/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L2-Cache - * preload-operation is done. - */ -#define CACHE_L2_CACHE_PLD_DONE_INT_ST (BIT(5)) -#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S) -#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V 0x00000001U -#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S 5 -/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0; - * The bit indicates the status of the interrupt of L2-Cache preload-operation error. - */ -#define CACHE_L2_CACHE_PLD_ERR_INT_ST (BIT(12)) -#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S) -#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V 0x00000001U -#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S 12 - -/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register - * Cache Sync/Preload Operation exception register - */ -#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a0) -/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0; - * The value 2 is Only available which means preload size is error in L2-Cache. - */ -#define CACHE_L2_CACHE_PLD_ERR_CODE 0x00000003U -#define CACHE_L2_CACHE_PLD_ERR_CODE_M (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S) -#define CACHE_L2_CACHE_PLD_ERR_CODE_V 0x00000003U -#define CACHE_L2_CACHE_PLD_ERR_CODE_S 10 - -/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register - * Cache Sync Reset control register - */ -#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a4) -/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0; - * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ -#define CACHE_L2_CACHE_SYNC_RST (BIT(5)) -#define CACHE_L2_CACHE_SYNC_RST_M (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S) -#define CACHE_L2_CACHE_SYNC_RST_V 0x00000001U -#define CACHE_L2_CACHE_SYNC_RST_S 5 - -/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register - * Cache Preload Reset control register - */ -#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a8) -/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0; - * set this bit to reset preload-logic inside L2-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ -#define CACHE_L2_CACHE_PLD_RST (BIT(5)) -#define CACHE_L2_CACHE_PLD_RST_M (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S) -#define CACHE_L2_CACHE_PLD_RST_V 0x00000001U -#define CACHE_L2_CACHE_PLD_RST_S 5 - -/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register - * Cache Autoload buffer clear control register - */ -#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac) -/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0; - * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, - * autoload will not work in L2-Cache. This bit should not be active when autoload - * works in L2-Cache. - */ -#define CACHE_L2_CACHE_ALD_BUF_CLR (BIT(5)) -#define CACHE_L2_CACHE_ALD_BUF_CLR_M (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S) -#define CACHE_L2_CACHE_ALD_BUF_CLR_V 0x00000001U -#define CACHE_L2_CACHE_ALD_BUF_CLR_S 5 - -/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register - * Unallocate request buffer clear registers - */ -#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0) -/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0; - * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responded but not completed. - */ -#define CACHE_L2_CACHE_UNALLOC_CLR (BIT(5)) -#define CACHE_L2_CACHE_UNALLOC_CLR_M (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S) -#define CACHE_L2_CACHE_UNALLOC_CLR_V 0x00000001U -#define CACHE_L2_CACHE_UNALLOC_CLR_S 5 - -/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register - * L2 cache access attribute control register - */ -#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4) -/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1; - * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and - * non-cacheable. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_CC (BIT(0)) -#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S 0 -/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1; - * Set this bit to force the request to l2 cache with write-back attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of write-back and - * write-through. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_WB (BIT(1)) -#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S 1 -/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1; - * Set this bit to force the request to l2 cache with write-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * write-miss-allocate and write-miss-no-allocate. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA (BIT(2)) -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S 2 -/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1; - * Set this bit to force the request to l2 cache with read-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * read-miss-allocate and read-miss-no-allocate. - */ -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA (BIT(3)) -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S) -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V 0x00000001U -#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S 3 - -/** CACHE_L2_CACHE_OBJECT_CTRL_REG register - * Cache Tag and Data memory Object control register - */ -#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3b8) -/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0; - * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L2_CACHE_TAG_OBJECT (BIT(5)) -#define CACHE_L2_CACHE_TAG_OBJECT_M (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S) -#define CACHE_L2_CACHE_TAG_OBJECT_V 0x00000001U -#define CACHE_L2_CACHE_TAG_OBJECT_S 5 -/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0; - * Set this bit to set L2-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. - */ -#define CACHE_L2_CACHE_MEM_OBJECT (BIT(11)) -#define CACHE_L2_CACHE_MEM_OBJECT_M (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S) -#define CACHE_L2_CACHE_MEM_OBJECT_V 0x00000001U -#define CACHE_L2_CACHE_MEM_OBJECT_S 11 - -/** CACHE_L2_CACHE_WAY_OBJECT_REG register - * Cache Tag and Data memory way register - */ -#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3bc) -/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. - */ -#define CACHE_L2_CACHE_WAY_OBJECT 0x00000007U -#define CACHE_L2_CACHE_WAY_OBJECT_M (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S) -#define CACHE_L2_CACHE_WAY_OBJECT_V 0x00000007U -#define CACHE_L2_CACHE_WAY_OBJECT_S 0 - -/** CACHE_L2_CACHE_ADDR_REG register - * Cache address register - */ -#define CACHE_L2_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x3c0) -/** CACHE_L2_CACHE_ADDR : HRO; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. - */ -#define CACHE_L2_CACHE_ADDR 0xFFFFFFFFU -#define CACHE_L2_CACHE_ADDR_M (CACHE_L2_CACHE_ADDR_V << CACHE_L2_CACHE_ADDR_S) -#define CACHE_L2_CACHE_ADDR_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_ADDR_S 0 - -/** CACHE_L2_CACHE_DEBUG_BUS_REG register - * Cache Tag/data memory content register - */ -#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3c4) -/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 964; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. - */ -#define CACHE_L2_CACHE_DEBUG_BUS 0xFFFFFFFFU -#define CACHE_L2_CACHE_DEBUG_BUS_M (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S) -#define CACHE_L2_CACHE_DEBUG_BUS_V 0xFFFFFFFFU -#define CACHE_L2_CACHE_DEBUG_BUS_S 0 - -/** CACHE_LEVEL_SPLIT1_REG register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3c8) -/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 968; - * Reserved - */ -#define CACHE_LEVEL_SPLIT1 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT1_M (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S) -#define CACHE_LEVEL_SPLIT1_V 0xFFFFFFFFU -#define CACHE_LEVEL_SPLIT1_S 0 - -/** CACHE_CLOCK_GATE_REG register - * Clock gate control register - */ -#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3cc) -/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable clock gate when access all registers in this module. - */ -#define CACHE_CLK_EN (BIT(0)) -#define CACHE_CLK_EN_M (CACHE_CLK_EN_V << CACHE_CLK_EN_S) -#define CACHE_CLK_EN_V 0x00000001U -#define CACHE_CLK_EN_S 0 - /** CACHE_TRACE_ENA_REG register * Clock gate control register */ @@ -6080,81 +1210,14 @@ extern "C" { #define CACHE_L1_CACHE_TRACE_ENA_M (CACHE_L1_CACHE_TRACE_ENA_V << CACHE_L1_CACHE_TRACE_ENA_S) #define CACHE_L1_CACHE_TRACE_ENA_V 0x00000001U #define CACHE_L1_CACHE_TRACE_ENA_S 0 -/** CACHE_L2_CACHE_TRACE_ENA : HRO; bitpos: [1]; default: 0; - * The bit is used to enable L2-Cache trace for the performance counter and fail tracer - */ -#define CACHE_L2_CACHE_TRACE_ENA (BIT(1)) -#define CACHE_L2_CACHE_TRACE_ENA_M (CACHE_L2_CACHE_TRACE_ENA_V << CACHE_L2_CACHE_TRACE_ENA_S) -#define CACHE_L2_CACHE_TRACE_ENA_V 0x00000001U -#define CACHE_L2_CACHE_TRACE_ENA_S 1 - -/** CACHE_REDUNDANCY_SIG0_REG register - * Cache redundancy signal 0 register - */ -#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3d4) -/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG0 0xFFFFFFFFU -#define CACHE_REDCY_SIG0_M (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S) -#define CACHE_REDCY_SIG0_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG0_S 0 - -/** CACHE_REDUNDANCY_SIG1_REG register - * Cache redundancy signal 1 register - */ -#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3d8) -/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG1 0xFFFFFFFFU -#define CACHE_REDCY_SIG1_M (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S) -#define CACHE_REDCY_SIG1_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG1_S 0 - -/** CACHE_REDUNDANCY_SIG2_REG register - * Cache redundancy signal 2 register - */ -#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3dc) -/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG2 0xFFFFFFFFU -#define CACHE_REDCY_SIG2_M (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S) -#define CACHE_REDCY_SIG2_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG2_S 0 - -/** CACHE_REDUNDANCY_SIG3_REG register - * Cache redundancy signal 3 register - */ -#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3e0) -/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG3 0xFFFFFFFFU -#define CACHE_REDCY_SIG3_M (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S) -#define CACHE_REDCY_SIG3_V 0xFFFFFFFFU -#define CACHE_REDCY_SIG3_S 0 - -/** CACHE_REDUNDANCY_SIG4_REG register - * Cache redundancy signal 0 register - */ -#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3e4) -/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0; - * Those bits are prepared for ECO. - */ -#define CACHE_REDCY_SIG4 0x0000000FU -#define CACHE_REDCY_SIG4_M (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S) -#define CACHE_REDCY_SIG4_V 0x0000000FU -#define CACHE_REDCY_SIG4_S 0 /** CACHE_DATE_REG register * Version control register */ #define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc) /** CACHE_DATE : R/W; bitpos: [27:0]; default: 36774432; - * version control register. Note that this default value stored is the latest date - * when the hardware logic was updated. + * Version control register. Note that the default value is the latest date when the + * hardware logic was updated. */ #define CACHE_DATE 0x0FFFFFFFU #define CACHE_DATE_M (CACHE_DATE_V << CACHE_DATE_S) diff --git a/components/soc/esp32c61/register/soc/cache_struct.h b/components/soc/esp32c61/register/soc/cache_struct.h index 408c01c2c7..ed1c69cd68 100644 --- a/components/soc/esp32c61/register/soc/cache_struct.h +++ b/components/soc/esp32c61/register/soc/cache_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,529 +10,69 @@ extern "C" { #endif -/** Group: Control and configuration registers */ -/** Type of l1_icache_ctrl register - * L1 instruction Cache(L1-ICache) control register - */ -typedef union { - struct { - /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable - */ - uint32_t l1_icache_shut_ibus0:1; - /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable - */ - uint32_t l1_icache_shut_ibus1:1; - /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache_shut_ibus2:1; - /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache_shut_ibus3:1; - uint32_t reserved_4:4; - /** l1_icache_undef_op : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ - uint32_t l1_icache_undef_op:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l1_icache_ctrl_reg_t; - +/** Group: Control and Configuration Registers */ /** Type of l1_cache_ctrl register - * L1 data Cache(L1-Cache) control register + * L1 data cache (L1 cache) control register */ typedef union { struct { /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0; - * The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS0 to access the L1 cache. + * 0: Enable + * 1: Disable */ uint32_t l1_cache_shut_bus0:1; /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0; - * The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable + * Configures whether to disable BUS1 to access the L1 cache. + * 0: Enable + * 1: Disable */ uint32_t l1_cache_shut_bus1:1; - /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_cache_shut_dbus2:1; - /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_cache_shut_dbus3:1; - /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable - */ - uint32_t l1_cache_shut_dma:1; - uint32_t reserved_5:3; - /** l1_cache_undef_op : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ - uint32_t l1_cache_undef_op:8; - uint32_t reserved_16:16; + uint32_t reserved_2:30; }; uint32_t val; } cache_l1_cache_ctrl_reg_t; -/** Type of l2_cache_ctrl register - * L2 Cache(L2-Cache) control register - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0; - * The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - */ - uint32_t l2_cache_shut_dma:1; - uint32_t reserved_5:3; - /** l2_cache_undef_op : R/W; bitpos: [15:8]; default: 0; - * Reserved - */ - uint32_t l2_cache_undef_op:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_ctrl_reg_t; - - -/** Group: Bypass Cache Control and configuration registers */ -/** Type of l1_bypass_cache_conf register - * Bypass Cache configure register - */ -typedef union { - struct { - /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_icache0_en:1; - /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_icache1_en:1; - /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t bypass_l1_icache2_en:1; - /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t bypass_l1_icache3_en:1; - /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l1_dcache_en:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} cache_l1_bypass_cache_conf_reg_t; - -/** Type of l2_bypass_cache_conf register - * Bypass Cache configure register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - */ - uint32_t bypass_l2_cache_en:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_bypass_cache_conf_reg_t; - - -/** Group: Cache Atomic Control and configuration registers */ -/** Type of l1_cache_atomic_conf register - * L1 Cache atomic feature configure register - */ -typedef union { - struct { - /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable atomic feature on L1-Cache when multiple cores access - * L1-Cache. 1: disable, 1: enable. - */ - uint32_t l1_cache_atomic_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} cache_l1_cache_atomic_conf_reg_t; - - -/** Group: Cache Mode Control and configuration registers */ -/** Type of l1_icache_cachesize_conf register - * L1 instruction Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_256:1; - /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_512:1; - /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_1k:1; - /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-ICache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_2k:1; - /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-ICache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_4k:1; - /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-ICache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_8k:1; - /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-ICache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_16k:1; - /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L1-ICache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_32k:1; - /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-ICache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_64k:1; - /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-ICache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_128k:1; - /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-ICache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_256k:1; - /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-ICache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_512k:1; - /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-ICache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_icache_cachesize_1024k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l1_icache_cachesize_conf_reg_t; - -/** Type of l1_icache_blocksize_conf register - * L1 instruction Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_8:1; - /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-ICache as 16 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_16:1; - /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L1-ICache as 32 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_32:1; - /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-ICache as 64 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_64:1; - /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-ICache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_128:1; - /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-ICache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_icache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache_blocksize_conf_reg_t; - /** Type of l1_cache_cachesize_conf register - * L1 data Cache CacheSize mode configure register + * Cache cache size register */ typedef union { struct { - /** l1_cache_cachesize_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_256:1; - /** l1_cache_cachesize_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_512:1; - /** l1_cache_cachesize_1k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_1k:1; - /** l1_cache_cachesize_2k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L1-DCache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_2k:1; - /** l1_cache_cachesize_4k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L1-DCache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_4k:1; - /** l1_cache_cachesize_8k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L1-DCache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_8k:1; - /** l1_cache_cachesize_16k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L1-DCache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_16k:1; - /** l1_cache_cachesize_32k : HRO; bitpos: [7]; default: 1; - * The field is used to configure cachesize of L1-DCache as 32k bytes. This field and - * all other fields within this register is onehot. + uint32_t reserved_0:7; + /** l1_cache_cachesize_32k : RO; bitpos: [7]; default: 1; + * Indicates that cache size is 32 KB. */ uint32_t l1_cache_cachesize_32k:1; - /** l1_cache_cachesize_64k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L1-DCache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_64k:1; - /** l1_cache_cachesize_128k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L1-DCache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_128k:1; - /** l1_cache_cachesize_256k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L1-DCache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_256k:1; - /** l1_cache_cachesize_512k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L1-DCache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_512k:1; - /** l1_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L1-DCache as 1024k bytes. This field - * and all other fields within this register is onehot. - */ - uint32_t l1_cache_cachesize_1024k:1; - uint32_t reserved_13:19; + uint32_t reserved_8:24; }; uint32_t val; } cache_l1_cache_cachesize_conf_reg_t; /** Type of l1_cache_blocksize_conf register - * L1 data Cache BlockSize mode configure register + * Cache block size register */ typedef union { struct { - /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_8:1; - /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L1-DCache as 16 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_16:1; - /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1; - * The field is used to configureblocksize of L1-DCache as 32 bytes. This field and - * all other fields within this register is onehot. + uint32_t reserved_0:2; + /** l1_cache_blocksize_32 : RO; bitpos: [2]; default: 1; + * Indicates that the cache block size is 32 bytes. */ uint32_t l1_cache_blocksize_32:1; - /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L1-DCache as 64 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_64:1; - /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L1-DCache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_128:1; - /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L1-DCache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l1_cache_blocksize_256:1; - uint32_t reserved_6:26; + uint32_t reserved_3:29; }; uint32_t val; } cache_l1_cache_blocksize_conf_reg_t; -/** Type of l2_cache_cachesize_conf register - * L2 Cache CacheSize mode configure register - */ -typedef union { - struct { - /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_256:1; - /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_512:1; - /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_1k:1; - /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0; - * The field is used to configure cachesize of L2-Cache as 2k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_2k:1; - /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0; - * The field is used to configure cachesize of L2-Cache as 4k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_4k:1; - /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0; - * The field is used to configure cachesize of L2-Cache as 8k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_8k:1; - /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0; - * The field is used to configure cachesize of L2-Cache as 16k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_16k:1; - /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0; - * The field is used to configure cachesize of L2-Cache as 32k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_32k:1; - /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0; - * The field is used to configure cachesize of L2-Cache as 64k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_64k:1; - /** l2_cache_cachesize_128k : HRO; bitpos: [9]; default: 0; - * The field is used to configure cachesize of L2-Cache as 128k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_128k:1; - /** l2_cache_cachesize_256k : HRO; bitpos: [10]; default: 0; - * The field is used to configure cachesize of L2-Cache as 256k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_256k:1; - /** l2_cache_cachesize_512k : HRO; bitpos: [11]; default: 0; - * The field is used to configure cachesize of L2-Cache as 512k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_512k:1; - /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0; - * The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_cachesize_1024k:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_cachesize_conf_reg_t; - -/** Type of l2_cache_blocksize_conf register - * L2 Cache BlockSize mode configure register - */ -typedef union { - struct { - /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0; - * The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_8:1; - /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0; - * The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_16:1; - /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0; - * The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_32:1; - /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0; - * The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all - * other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_64:1; - /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0; - * The field is used to configureblocksize of L2-Cache as 128 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_128:1; - /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0; - * The field is used to configureblocksize of L2-Cache as 256 bytes. This field and - * all other fields within this register is onehot. - */ - uint32_t l2_cache_blocksize_256:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_blocksize_conf_reg_t; - - -/** Group: Wrap Mode Control and configuration registers */ /** Type of l1_cache_wrap_around_ctrl register - * Cache wrap around control register + * Cache critical word first control register */ typedef union { struct { - /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to enable L1-ICache0 wrap around mode. - */ - uint32_t l1_icache0_wrap:1; - /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to enable L1-ICache1 wrap around mode. - */ - uint32_t l1_icache1_wrap:1; - /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_wrap:1; - /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_wrap:1; + uint32_t reserved_0:4; /** l1_cache_wrap : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to enable L1-DCache wrap around mode. + * Configures whether to enable the critical word first mode for the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_wrap:1; uint32_t reserved_5:27; @@ -540,46 +80,16 @@ typedef union { uint32_t val; } cache_l1_cache_wrap_around_ctrl_reg_t; -/** Type of l2_cache_wrap_around_ctrl register - * Cache wrap around control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_wrap : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to enable L2-Cache wrap around mode. - */ - uint32_t l2_cache_wrap:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_wrap_around_ctrl_reg_t; - - -/** Group: Early Restart Control registers */ /** Type of l1_cache_miss_access_ctrl register * Cache wrap around control register */ typedef union { struct { - /** l1_icache0_miss_disable_access : HRO; bitpos: [0]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache0 - */ - uint32_t l1_icache0_miss_disable_access:1; - /** l1_icache1_miss_disable_access : HRO; bitpos: [1]; default: 0; - * Set this bit as 1 to disable early restart of L1-ICache1 - */ - uint32_t l1_icache1_miss_disable_access:1; - /** l1_icache2_miss_disable_access : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_miss_disable_access:1; - /** l1_icache3_miss_disable_access : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_miss_disable_access:1; + uint32_t reserved_0:4; /** l1_cache_miss_disable_access : R/W; bitpos: [4]; default: 0; - * Set this bit as 1 to disable early restart of L1-DCache + * Configures whether to disable early restart function. + * 0: Enable + * 1: Disable */ uint32_t l1_cache_miss_disable_access:1; uint32_t reserved_5:27; @@ -587,99 +97,31 @@ typedef union { uint32_t val; } cache_l1_cache_miss_access_ctrl_reg_t; -/** Type of l2_cache_miss_access_ctrl register - * Cache wrap around control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_miss_disable_access : HRO; bitpos: [5]; default: 0; - * Set this bit as 1 to disable early restart of L2-Cache - */ - uint32_t l2_cache_miss_disable_access:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_miss_access_ctrl_reg_t; - -/** Group: Cache Freeze Control registers */ +/** Group: Cache Freeze Control Registers */ /** Type of l1_cache_freeze_ctrl register - * Cache Freeze control register + * Cache freeze control register */ typedef union { struct { - /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable freeze operation on L1-ICache0. It can be cleared by - * software. - */ - uint32_t l1_icache0_freeze_en:1; - /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_icache0_freeze_mode:1; - /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache0_freeze_done:1; - uint32_t reserved_3:1; - /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable freeze operation on L1-ICache1. It can be cleared by - * software. - */ - uint32_t l1_icache1_freeze_en:1; - /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0; - * The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l1_icache1_freeze_mode:1; - /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0; - * The bit is used to indicate whether freeze operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache1_freeze_done:1; - uint32_t reserved_7:1; - /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_en:1; - /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_mode:1; - /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache2_freeze_done:1; - uint32_t reserved_11:1; - /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_en:1; - /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_mode:1; - /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l1_icache3_freeze_done:1; - uint32_t reserved_15:1; + uint32_t reserved_0:16; /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable freeze operation on L1-Cache. It can be cleared by + * Configures whether to enable freeze operation in the L1 cache. It can be cleared by * software. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_freeze_en:1; /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0; - * The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. + * Configures the freeze mode in the L1 cache. + * 0: Assert busy if a cache miss occurs + * 1: Assert hit if a cache miss occurs */ uint32_t l1_cache_freeze_mode:1; /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0; - * The bit is used to indicate whether freeze operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the freeze operation in L1 cache is finished. + * 0: Not finished + * 1: Finished */ uint32_t l1_cache_freeze_done:1; uint32_t reserved_19:13; @@ -687,87 +129,25 @@ typedef union { uint32_t val; } cache_l1_cache_freeze_ctrl_reg_t; -/** Type of l2_cache_freeze_ctrl register - * Cache Freeze control register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable freeze operation on L2-Cache. It can be cleared by - * software. - */ - uint32_t l2_cache_freeze_en:1; - /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0; - * The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access - * will not stuck. 1: a miss-access will stuck. - */ - uint32_t l2_cache_freeze_mode:1; - /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0; - * The bit is used to indicate whether freeze operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l2_cache_freeze_done:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} cache_l2_cache_freeze_ctrl_reg_t; - -/** Group: Cache Data Memory Access Control and Configuration registers */ +/** Group: Cache Data Memory Access Control and Configuration Registers */ /** Type of l1_cache_data_mem_acs_conf register - * Cache data memory access configure register + * Cache data memory access configuration register */ typedef union { struct { - /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_data_mem_rd_en:1; - /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, - * 1: enable. - */ - uint32_t l1_icache0_data_mem_wr_en:1; - uint32_t reserved_2:2; - /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_data_mem_rd_en:1; - /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, - * 1: enable. - */ - uint32_t l1_icache1_data_mem_wr_en:1; - uint32_t reserved_6:2; - /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_data_mem_rd_en:1; - /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_data_mem_wr_en:1; - uint32_t reserved_10:2; - /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_data_mem_rd_en:1; - /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_data_mem_wr_en:1; - uint32_t reserved_14:2; + uint32_t reserved_0:16; /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache data memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_data_mem_rd_en:1; /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache data + * memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_data_mem_wr_en:1; uint32_t reserved_18:14; @@ -775,82 +155,22 @@ typedef union { uint32_t val; } cache_l1_cache_data_mem_acs_conf_reg_t; -/** Type of l2_cache_data_mem_acs_conf register - * Cache data memory access configure register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_data_mem_rd_en:1; - /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_data_mem_wr_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} cache_l2_cache_data_mem_acs_conf_reg_t; - - -/** Group: Cache Tag Memory Access Control and Configuration registers */ /** Type of l1_cache_tag_mem_acs_conf register - * Cache tag memory access configure register + * Cache tag memory access configuration register */ typedef union { struct { - /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_tag_mem_rd_en:1; - /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache0_tag_mem_wr_en:1; - uint32_t reserved_2:2; - /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 0; - * The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_tag_mem_rd_en:1; - /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 0; - * The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l1_icache1_tag_mem_wr_en:1; - uint32_t reserved_6:2; - /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_mem_rd_en:1; - /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_mem_wr_en:1; - uint32_t reserved_10:2; - /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_mem_rd_en:1; - /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_mem_wr_en:1; - uint32_t reserved_14:2; + uint32_t reserved_0:16; /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 0; - * The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to read the L1 cache tag memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_tag_mem_rd_en:1; /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 0; - * The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: - * enable. + * Configures whether to enable the configuration bus to write the L1 cache tag memory. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_tag_mem_wr_en:1; uint32_t reserved_18:14; @@ -858,492 +178,123 @@ typedef union { uint32_t val; } cache_l1_cache_tag_mem_acs_conf_reg_t; -/** Type of l2_cache_tag_mem_acs_conf register - * Cache tag memory access configure register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0; - * The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_tag_mem_rd_en:1; - /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0; - * The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: - * enable. - */ - uint32_t l2_cache_tag_mem_wr_en:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} cache_l2_cache_tag_mem_acs_conf_reg_t; - - -/** Group: Prelock Control and configuration registers */ -/** Type of l1_icache0_prelock_conf register - * L1 instruction Cache 0 prelock configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache0. - */ - uint32_t l1_icache0_prelock_sct0_en:1; - /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache0. - */ - uint32_t l1_icache0_prelock_sct1_en:1; - /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache0 prelock. - */ - uint32_t l1_icache0_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache0_prelock_conf_reg_t; - -/** Type of l1_icache0_prelock_sct0_addr register - * L1 instruction Cache 0 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache0_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache0_prelock_sct0_addr_reg_t; - -/** Type of l1_icache0_prelock_sct1_addr register - * L1 instruction Cache 0 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache0_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache0_prelock_sct1_addr_reg_t; - -/** Type of l1_icache0_prelock_sct_size register - * L1 instruction Cache 0 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache0_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache0_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache0_prelock_sct_size_reg_t; - -/** Type of l1_icache1_prelock_conf register - * L1 instruction Cache 1 prelock configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache1. - */ - uint32_t l1_icache1_prelock_sct0_en:1; - /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache1. - */ - uint32_t l1_icache1_prelock_sct1_en:1; - /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache1 prelock. - */ - uint32_t l1_icache1_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache1_prelock_conf_reg_t; - -/** Type of l1_icache1_prelock_sct0_addr register - * L1 instruction Cache 1 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache1_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache1_prelock_sct0_addr_reg_t; - -/** Type of l1_icache1_prelock_sct1_addr register - * L1 instruction Cache 1 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache1_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache1_prelock_sct1_addr_reg_t; - -/** Type of l1_icache1_prelock_sct_size register - * L1 instruction Cache 1 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache1_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache1_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache1_prelock_sct_size_reg_t; - -/** Type of l1_icache2_prelock_conf register - * L1 instruction Cache 2 prelock configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache2. - */ - uint32_t l1_icache2_prelock_sct0_en:1; - /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache2. - */ - uint32_t l1_icache2_prelock_sct1_en:1; - /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache2 prelock. - */ - uint32_t l1_icache2_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache2_prelock_conf_reg_t; - -/** Type of l1_icache2_prelock_sct0_addr register - * L1 instruction Cache 2 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache2_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache2_prelock_sct0_addr_reg_t; - -/** Type of l1_icache2_prelock_sct1_addr register - * L1 instruction Cache 2 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache2_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache2_prelock_sct1_addr_reg_t; - -/** Type of l1_icache2_prelock_sct_size register - * L1 instruction Cache 2 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache2_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache2_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache2_prelock_sct_size_reg_t; - -/** Type of l1_icache3_prelock_conf register - * L1 instruction Cache 3 prelock configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-ICache3. - */ - uint32_t l1_icache3_prelock_sct0_en:1; - /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-ICache3. - */ - uint32_t l1_icache3_prelock_sct1_en:1; - /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 icache3 prelock. - */ - uint32_t l1_icache3_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l1_icache3_prelock_conf_reg_t; - -/** Type of l1_icache3_prelock_sct0_addr register - * L1 instruction Cache 3 prelock section0 address configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l1_icache3_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache3_prelock_sct0_addr_reg_t; - -/** Type of l1_icache3_prelock_sct1_addr register - * L1 instruction Cache 3 prelock section1 address configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l1_icache3_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache3_prelock_sct1_addr_reg_t; - -/** Type of l1_icache3_prelock_sct_size register - * L1 instruction Cache 3 prelock section size configure register - */ -typedef union { - struct { - /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l1_icache3_prelock_sct0_size:14; - uint32_t reserved_14:2; - /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l1_icache3_prelock_sct1_size:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} cache_l1_icache3_prelock_sct_size_reg_t; +/** Group: Prelock Control and Configuration Registers */ /** Type of l1_cache_prelock_conf register * L1 Cache prelock configure register */ typedef union { struct { /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 0 of the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_prelock_sct0_en:1; /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L1-Cache. + * Configures whether to enable the prelocking function in Section 1 of the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_prelock_sct1_en:1; - /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l1 cache prelock. - */ - uint32_t l1_cache_prelock_rgid:4; - uint32_t reserved_6:26; + uint32_t reserved_2:30; }; uint32_t val; } cache_l1_cache_prelock_conf_reg_t; /** Type of l1_cache_prelock_sct0_addr register - * L1 Cache prelock section0 address configure register + * L1 cache prelocking Section 0 address configuration register */ typedef union { struct { /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG + * Configures the starting virtual address of Section 0 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT0_SIZE. */ uint32_t l1_cache_prelock_sct0_addr:32; }; uint32_t val; } cache_l1_cache_prelock_sct0_addr_reg_t; -/** Type of l1_dcache_prelock_sct1_addr register - * L1 Cache prelock section1 address configure register +/** Type of l1_cache_prelock_sct1_addr register + * L1 cache prelocking Section 1 address configuration register */ typedef union { struct { /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG + * Configures the starting virtual address of Section 1 for prelocking in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOCK_SCT1_SIZE. */ uint32_t l1_cache_prelock_sct1_addr:32; }; uint32_t val; -} cache_l1_dcache_prelock_sct1_addr_reg_t; +} cache_l1_cache_prelock_sct1_addr_reg_t; -/** Type of l1_dcache_prelock_sct_size register - * L1 Cache prelock section size configure register +/** Type of l1_cache_prelock_sct_size register + * L1 cache prelocking section size configuration register */ typedef union { struct { /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG + * Configures the size of Section 0 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG. */ uint32_t l1_cache_prelock_sct0_size:14; uint32_t reserved_14:2; /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383; - * Those bits are used to configure the size of the second section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG + * Configures the size of Section 1 for prelocking in the L1 cache. This field should + * be configured together with CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG. */ uint32_t l1_cache_prelock_sct1_size:14; uint32_t reserved_30:2; }; uint32_t val; -} cache_l1_dcache_prelock_sct_size_reg_t; - -/** Type of l2_cache_prelock_conf register - * L2 Cache prelock configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function on L2-Cache. - */ - uint32_t l2_cache_prelock_sct0_en:1; - /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function on L2-Cache. - */ - uint32_t l2_cache_prelock_sct1_en:1; - /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0; - * The bit is used to set the gid of l2 cache prelock. - */ - uint32_t l2_cache_prelock_rgid:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_prelock_conf_reg_t; - -/** Type of l2_cache_prelock_sct0_addr register - * L2 Cache prelock section0 address configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG - */ - uint32_t l2_cache_prelock_sct0_addr:32; - }; - uint32_t val; -} cache_l2_cache_prelock_sct0_addr_reg_t; - -/** Type of l2_cache_prelock_sct1_addr register - * L2 Cache prelock section1 address configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section of prelock - * on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG - */ - uint32_t l2_cache_prelock_sct1_addr:32; - }; - uint32_t val; -} cache_l2_cache_prelock_sct1_addr_reg_t; - -/** Type of l2_cache_prelock_sct_size register - * L2 Cache prelock section size configure register - */ -typedef union { - struct { - /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - */ - uint32_t l2_cache_prelock_sct0_size:16; - /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535; - * Those bits are used to configure the size of the second section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - */ - uint32_t l2_cache_prelock_sct1_size:16; - }; - uint32_t val; -} cache_l2_cache_prelock_sct_size_reg_t; +} cache_l1_cache_prelock_sct_size_reg_t; -/** Group: Lock Control and configuration registers */ +/** Group: Lock Control and Configuration Registers */ /** Type of lock_ctrl register - * Lock-class (manual lock) operation control register + * Locking operation control register */ typedef union { struct { /** lock_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware after lock - * operation done + * Configures whether to enable lock operation. It will be cleared by hardware after + * the lock operation is done. + * 0: Disable + * 1: Enable */ uint32_t lock_ena:1; /** unlock_ena : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by hardware after - * unlock operation done + * Configures whether to enable unlock operation. It will be cleared by hardware after + * the unlock operation is done. + * 0: Disable + * 1: Enable */ uint32_t unlock_ena:1; /** lock_done : RO; bitpos: [2]; default: 1; - * The bit is used to indicate whether unlock/lock operation is finished or not. 0: - * not finished. 1: finished. + * Represents whether the unlock or the lock operation is finished. + * 0: Not finished + * 1: Finished */ uint32_t lock_done:1; - /** lock_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of cache lock/unlock. - */ - uint32_t lock_rgid:4; - uint32_t reserved_7:25; + uint32_t reserved_3:29; }; uint32_t val; } cache_lock_ctrl_reg_t; /** Type of lock_map register - * Lock (manual lock) map configure register + * Locking map configuration register */ typedef union { struct { /** lock_map : R/W; bitpos: [5:0]; default: 0; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply this lock/unlock operation. [4]: L1-Cache + * Configures which level of cache in the two-level cache structure to perform the + * locking or the unlocking operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: reserved */ uint32_t lock_map:6; uint32_t reserved_6:26; @@ -1352,13 +303,13 @@ typedef union { } cache_lock_map_reg_t; /** Type of lock_addr register - * Lock (manual lock) address configure register + * Locking address configuration register */ typedef union { struct { /** lock_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the lock/unlock operation, - * which should be used together with CACHE_LOCK_SIZE_REG + * Configures the starting virtual address for the locking or unlocking operation. + * This field should be configured together with CACHE_LOCK_SIZE_REG. */ uint32_t lock_addr:32; }; @@ -1366,13 +317,13 @@ typedef union { } cache_lock_addr_reg_t; /** Type of lock_size register - * Lock (manual lock) size configure register + * Locking size configuration register */ typedef union { struct { /** lock_size : R/W; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the lock/unlock operation, which - * should be used together with CACHE_LOCK_ADDR_REG + * Configures the size for the locking or unlocking operation. This field should be + * configured together with CACHE_LOCK_ADDR_REG. */ uint32_t lock_size:16; uint32_t reserved_16:16; @@ -1381,63 +332,61 @@ typedef union { } cache_lock_size_reg_t; -/** Group: Sync Control and configuration registers */ +/** Group: Sync Control and Configuration Registers */ /** Type of sync_ctrl register - * Sync-class operation control register + * Sync operation control register */ typedef union { struct { - /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by hardware - * after invalidate operation done. Note that this bit and the other sync-bits - * (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. + /** invalidate_ena : RW; bitpos: [0]; default: 1; + * Configures whether to enable the invalidatation operation. Hardware will clear it + * once the operation has finished. + * 0: Disable + * 1: Enable */ uint32_t invalidate_ena:1; /** clean_ena : R/W/SC; bitpos: [1]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware after - * clean operation done. Note that this bit and the other sync-bits (invalidate_ena, - * writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those - * bits can not be set to 1 at the same time. + * Configures whether to enable the clean operation. Hardware will clear it once the + * operation has finished. + * 0: Disable + * 1: Enable */ uint32_t clean_ena:1; /** writeback_ena : R/W/SC; bitpos: [2]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by hardware after - * writeback operation done. Note that this bit and the other sync-bits - * (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that - * is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back operation. Hardware will clear it once + * the operation has finished. + * 0: Disable + * 1: Enable */ uint32_t writeback_ena:1; /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0; - * The bit is used to enable writeback-invalidate operation. It will be cleared by - * hardware after writeback-invalidate operation done. Note that this bit and the - * other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, - * that is, those bits can not be set to 1 at the same time. + * Configures whether to enable the write-back invalidation operation. Hardware will + * clear it once the operation has finished. + * 0: Disable + * 1: Enable */ uint32_t writeback_invalidate_ena:1; /** sync_done : RO; bitpos: [4]; default: 0; - * The bit is used to indicate whether sync operation (invalidate, clean, writeback, - * writeback_invalidate) is finished or not. 0: not finished. 1: finished. + * Represents whether the synchronization operation is finished. + * 0: Not finished + * 1: Finished */ uint32_t sync_done:1; - /** sync_rgid : HRO; bitpos: [8:5]; default: 0; - * The bit is used to set the gid of cache sync operation (invalidate, clean, - * writeback, writeback_invalidate) - */ - uint32_t sync_rgid:4; - uint32_t reserved_9:23; + uint32_t reserved_5:27; }; uint32_t val; } cache_sync_ctrl_reg_t; /** Type of sync_map register - * Sync map configure register + * Sync map configuration register */ typedef union { struct { /** sync_map : R/W; bitpos: [5:0]; default: 63; - * Those bits are used to indicate which caches in the two-level cache structure will - * apply the sync operation. [4]: L1-Cache + * Configures which caches in the two-level cache structure will apply the sync + * operation. + * Bit 4: Write 1 to this bit to select the L1 cache + * Other bits: Reserved */ uint32_t sync_map:6; uint32_t reserved_6:26; @@ -1446,13 +395,13 @@ typedef union { } cache_sync_map_reg_t; /** Type of sync_addr register - * Sync address configure register + * Sync address configuration register */ typedef union { struct { /** sync_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the sync operation, which - * should be used together with CACHE_SYNC_SIZE_REG + * Configures the starting virtual address for the synchronization operation. This + * field should be configured together with CACHE_SYNC_SIZE_REG. */ uint32_t sync_addr:32; }; @@ -1460,13 +409,13 @@ typedef union { } cache_sync_addr_reg_t; /** Type of sync_size register - * Sync size configure register + * Sync size configuration register */ typedef union { struct { /** sync_size : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the sync operation, which should be - * used together with CACHE_SYNC_ADDR_REG + * Configures the size for the synchronization operation. This field should be + * configured together with CACHE_SYNC_ADDR_REG. */ uint32_t sync_size:25; uint32_t reserved_25:7; @@ -1475,835 +424,127 @@ typedef union { } cache_sync_size_reg_t; -/** Group: Preload Control and configuration registers */ -/** Type of l1_icache0_preload_ctrl register - * L1 instruction Cache 0 preload-operation control register - */ -typedef union { - struct { - /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache0. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache0_preload_ena:1; - /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache0_preload_done:1; - /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache0_preload_order:1; - /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache0 preload. - */ - uint32_t l1_icache0_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache0_preload_ctrl_reg_t; - -/** Type of l1_icache0_preload_addr register - * L1 instruction Cache 0 preload address configure register - */ -typedef union { - struct { - /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache0, which - * should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - */ - uint32_t l1_icache0_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache0_preload_addr_reg_t; - -/** Type of l1_icache0_preload_size register - * L1 instruction Cache 0 preload size configure register - */ -typedef union { - struct { - /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - */ - uint32_t l1_icache0_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache0_preload_size_reg_t; - -/** Type of l1_icache1_preload_ctrl register - * L1 instruction Cache 1 preload-operation control register - */ -typedef union { - struct { - /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache1. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache1_preload_ena:1; - /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache1_preload_done:1; - /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache1_preload_order:1; - /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache1 preload. - */ - uint32_t l1_icache1_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache1_preload_ctrl_reg_t; - -/** Type of l1_icache1_preload_addr register - * L1 instruction Cache 1 preload address configure register - */ -typedef union { - struct { - /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache1, which - * should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - */ - uint32_t l1_icache1_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache1_preload_addr_reg_t; - -/** Type of l1_icache1_preload_size register - * L1 instruction Cache 1 preload size configure register - */ -typedef union { - struct { - /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - */ - uint32_t l1_icache1_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache1_preload_size_reg_t; - -/** Type of l1_icache2_preload_ctrl register - * L1 instruction Cache 2 preload-operation control register - */ -typedef union { - struct { - /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache2. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache2_preload_ena:1; - /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache2_preload_done:1; - /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache2_preload_order:1; - /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache2 preload. - */ - uint32_t l1_icache2_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache2_preload_ctrl_reg_t; - -/** Type of l1_icache2_preload_addr register - * L1 instruction Cache 2 preload address configure register - */ -typedef union { - struct { - /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache2, which - * should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - */ - uint32_t l1_icache2_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache2_preload_addr_reg_t; - -/** Type of l1_icache2_preload_size register - * L1 instruction Cache 2 preload size configure register - */ -typedef union { - struct { - /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - */ - uint32_t l1_icache2_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache2_preload_size_reg_t; - -/** Type of l1_icache3_preload_ctrl register - * L1 instruction Cache 3 preload-operation control register - */ -typedef union { - struct { - /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-ICache3. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l1_icache3_preload_ena:1; - /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l1_icache3_preload_done:1; - /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l1_icache3_preload_order:1; - /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 icache3 preload. - */ - uint32_t l1_icache3_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l1_icache3_preload_ctrl_reg_t; - -/** Type of l1_icache3_preload_addr register - * L1 instruction Cache 3 preload address configure register - */ -typedef union { - struct { - /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-ICache3, which - * should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - */ - uint32_t l1_icache3_preload_addr:32; - }; - uint32_t val; -} cache_l1_icache3_preload_addr_reg_t; - -/** Type of l1_icache3_preload_size register - * L1 instruction Cache 3 preload size configure register - */ -typedef union { - struct { - /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - */ - uint32_t l1_icache3_preload_size:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache3_preload_size_reg_t; - +/** Group: Preloading Control and Configuration Registers */ /** Type of l1_cache_preload_ctrl register - * L1 Cache preload-operation control register + * L1 cache preloading operation control register */ typedef union { struct { /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L1-Cache. It will be cleared by - * hardware automatically after preload operation is done. + * Configures whether to enable the preloading operation in the L1 cache. It will be + * cleared by hardware automatically after the preloading operation is done. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_preload_ena:1; /** l1_cache_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. + * Represents whether the preloading operation is finished. + * 0: Not finished + * 1: Finished */ uint32_t l1_cache_preload_done:1; /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. + * Configures the direction of the preloading operation. + * 0: Ascending + * 1: Descending */ uint32_t l1_cache_preload_order:1; - /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l1 cache preload. - */ - uint32_t l1_cache_preload_rgid:4; - uint32_t reserved_7:25; + uint32_t reserved_3:29; }; uint32_t val; } cache_l1_cache_preload_ctrl_reg_t; -/** Type of l1_dcache_preload_addr register - * L1 Cache preload address configure register +/** Type of l1_cache_preload_addr register + * L1 cache preloading address configuration register */ typedef union { struct { /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L1-Cache, which - * should be used together with L1_CACHE_PRELOAD_SIZE_REG + * Configures the starting virtual address for the preloading operation in the L1 + * cache. This field should be configured together with + * CACHE_L1_CACHE_PRELOAD_SIZE_REG. */ uint32_t l1_cache_preload_addr:32; }; uint32_t val; -} cache_l1_dcache_preload_addr_reg_t; +} cache_l1_cache_preload_addr_reg_t; -/** Type of l1_dcache_preload_size register - * L1 Cache preload size configure register +/** Type of l1_cache_preload_size register + * L1 cache preloading size configuration register */ typedef union { struct { /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG + * Configures the size of Section 0 for the preloading operation in the L1 cache. This + * field should be configured together with CACHE_L1_CACHE_PRELOAD_ADDR_REG. */ uint32_t l1_cache_preload_size:14; uint32_t reserved_14:18; }; uint32_t val; -} cache_l1_dcache_preload_size_reg_t; - -/** Type of l2_cache_preload_ctrl register - * L2 Cache preload-operation control register - */ -typedef union { - struct { - /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0; - * The bit is used to enable preload operation on L2-Cache. It will be cleared by - * hardware automatically after preload operation is done. - */ - uint32_t l2_cache_preload_ena:1; - /** l2_cache_preload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether preload operation is finished or not. 0: not - * finished. 1: finished. - */ - uint32_t l2_cache_preload_done:1; - /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 0: ascending, 1: - * descending. - */ - uint32_t l2_cache_preload_order:1; - /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0; - * The bit is used to set the gid of l2 cache preload. - */ - uint32_t l2_cache_preload_rgid:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} cache_l2_cache_preload_ctrl_reg_t; - -/** Type of l2_cache_preload_addr register - * L2 Cache preload address configure register - */ -typedef union { - struct { - /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of preload on L2-Cache, which - * should be used together with L2_CACHE_PRELOAD_SIZE_REG - */ - uint32_t l2_cache_preload_addr:32; - }; - uint32_t val; -} cache_l2_cache_preload_addr_reg_t; - -/** Type of l2_cache_preload_size register - * L2 Cache preload size configure register - */ -typedef union { - struct { - /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0; - * Those bits are used to configure the size of the first section of prelock on - * L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - */ - uint32_t l2_cache_preload_size:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_preload_size_reg_t; +} cache_l1_cache_preload_size_reg_t; -/** Group: Autoload Control and configuration registers */ -/** Type of l1_icache0_autoload_ctrl register - * L1 instruction Cache 0 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, - * 0: disable. - */ - uint32_t l1_icache0_autoload_ena:1; - /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache0 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache0_autoload_done:1; - /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache0. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache0_autoload_order:1; - /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache0. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache0_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache0. - */ - uint32_t l1_icache0_autoload_sct0_ena:1; - /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache0. - */ - uint32_t l1_icache0_autoload_sct1_ena:1; - /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache0 autoload. - */ - uint32_t l1_icache0_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache0_autoload_ctrl_reg_t; - -/** Type of l1_icache0_autoload_sct0_addr register - * L1 instruction Cache 0 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache0_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct0_addr_reg_t; - -/** Type of l1_icache0_autoload_sct0_size register - * L1 instruction Cache 0 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache0_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct0_size_reg_t; - -/** Type of l1_icache0_autoload_sct1_addr register - * L1 instruction Cache 0 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache0_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct1_addr_reg_t; - -/** Type of l1_icache0_autoload_sct1_size register - * L1 instruction Cache 0 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache0. Note that it should be used together with - * L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache0_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache0_autoload_sct1_size_reg_t; - -/** Type of l1_icache1_autoload_ctrl register - * L1 instruction Cache 1 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, - * 0: disable. - */ - uint32_t l1_icache1_autoload_ena:1; - /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache1 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache1_autoload_done:1; - /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache1. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache1_autoload_order:1; - /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache1. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache1_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache1. - */ - uint32_t l1_icache1_autoload_sct0_ena:1; - /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache1. - */ - uint32_t l1_icache1_autoload_sct1_ena:1; - /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache1 autoload. - */ - uint32_t l1_icache1_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache1_autoload_ctrl_reg_t; - -/** Type of l1_icache1_autoload_sct0_addr register - * L1 instruction Cache 1 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache1_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct0_addr_reg_t; - -/** Type of l1_icache1_autoload_sct0_size register - * L1 instruction Cache 1 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache1_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct0_size_reg_t; - -/** Type of l1_icache1_autoload_sct1_addr register - * L1 instruction Cache 1 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache1_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct1_addr_reg_t; - -/** Type of l1_icache1_autoload_sct1_size register - * L1 instruction Cache 1 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache1. Note that it should be used together with - * L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache1_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache1_autoload_sct1_size_reg_t; - -/** Type of l1_icache2_autoload_ctrl register - * L1 instruction Cache 2 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, - * 0: disable. - */ - uint32_t l1_icache2_autoload_ena:1; - /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache2 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache2_autoload_done:1; - /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache2. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache2_autoload_order:1; - /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache2. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache2_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache2. - */ - uint32_t l1_icache2_autoload_sct0_ena:1; - /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache2. - */ - uint32_t l1_icache2_autoload_sct1_ena:1; - /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache2 autoload. - */ - uint32_t l1_icache2_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache2_autoload_ctrl_reg_t; - -/** Type of l1_icache2_autoload_sct0_addr register - * L1 instruction Cache 2 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache2_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct0_addr_reg_t; - -/** Type of l1_icache2_autoload_sct0_size register - * L1 instruction Cache 2 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache2_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct0_size_reg_t; - -/** Type of l1_icache2_autoload_sct1_addr register - * L1 instruction Cache 2 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache2_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct1_addr_reg_t; - -/** Type of l1_icache2_autoload_sct1_size register - * L1 instruction Cache 2 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-ICache2. Note that it should be used together with - * L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache2_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache2_autoload_sct1_size_reg_t; - -/** Type of l1_icache3_autoload_ctrl register - * L1 instruction Cache 3 autoload-operation control register - */ -typedef union { - struct { - /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, - * 0: disable. - */ - uint32_t l1_icache3_autoload_ena:1; - /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-ICache3 is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l1_icache3_autoload_done:1; - /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-ICache3. 0: - * ascending. 1: descending. - */ - uint32_t l1_icache3_autoload_order:1; - /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-ICache3. - * 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l1_icache3_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-ICache3. - */ - uint32_t l1_icache3_autoload_sct0_ena:1; - /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-ICache3. - */ - uint32_t l1_icache3_autoload_sct1_ena:1; - /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0; - * The bit is used to set the gid of l1 icache3 autoload. - */ - uint32_t l1_icache3_autoload_rgid:4; - uint32_t reserved_14:18; - }; - uint32_t val; -} cache_l1_icache3_autoload_ctrl_reg_t; - -/** Type of l1_icache3_autoload_sct0_addr register - * L1 instruction Cache 3 autoload section 0 address configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache3_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct0_addr_reg_t; - -/** Type of l1_icache3_autoload_sct0_size register - * L1 instruction Cache 3 autoload section 0 size configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l1_icache3_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct0_size_reg_t; - -/** Type of l1_icache3_autoload_sct1_addr register - * L1 instruction Cache 3 autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-ICache3. Note that it should be used together with - * L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l1_icache3_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct1_addr_reg_t; - -/** Type of l1_icache3_autoload_sct1_size register - * L1 instruction Cache 3 autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Reserved - */ - uint32_t l1_icache3_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l1_icache3_autoload_sct1_size_reg_t; - +/** Group: Autoloading Control and Configuration Registers */ /** Type of l1_cache_autoload_ctrl register - * L1 Cache autoload-operation control register + * L1 cache autoloading operation control register */ typedef union { struct { /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, - * 0: disable. + * Configures whether to enable the autoloading operation in the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_autoload_ena:1; /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L1-Cache is finished or - * not. 0: not finished. 1: finished. + * Represents whether the autoloading operation in the L1 cache is finished. + * 0: Not finished + * 1: Finished */ uint32_t l1_cache_autoload_done:1; /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L1-Cache. 0: - * ascending. 1: descending. + * Configures the direction of the autoloading operation in the L1 cache. + * 0: Ascending + * 1: Descending */ uint32_t l1_cache_autoload_order:1; /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + * Configures the trigger mode of the autoloading operation in the L1 cache. + * 0/3: Triggered by misses + * 1: Triggered by hits + * 2: Triggered by misses or hits */ uint32_t l1_cache_autoload_trigger_mode:2; uint32_t reserved_5:3; /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L1-Cache. + * Configures whether to enable Section 0 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_autoload_sct0_ena:1; /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L1-Cache. + * Configures whether to enable Section 1 for the autoloading operation in the L1 + * cache. + * 0: Disable + * 1: Enable */ uint32_t l1_cache_autoload_sct1_ena:1; - /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct2_ena:1; - /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L1-Cache. - */ - uint32_t l1_cache_autoload_sct3_ena:1; - /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l1 cache autoload. - */ - uint32_t l1_cache_autoload_rgid:4; - uint32_t reserved_16:16; + uint32_t reserved_10:22; }; uint32_t val; } cache_l1_cache_autoload_ctrl_reg_t; /** Type of l1_cache_autoload_sct0_addr register - * L1 Cache autoload section 0 address configure register + * L1 cache autoloading Section 0 address configuration register */ typedef union { struct { /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the starting virtual address of Section 0 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ uint32_t l1_cache_autoload_sct0_addr:32; }; @@ -2311,14 +552,14 @@ typedef union { } cache_l1_cache_autoload_sct0_addr_reg_t; /** Type of l1_cache_autoload_sct0_size register - * L1 Cache autoload section 0 size configure register + * L1 cache autoloading Section 0 size configuration register */ typedef union { struct { /** l1_cache_autoload_sct0_size : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + * Configures the size of Section 0 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA. */ uint32_t l1_cache_autoload_sct0_size:25; uint32_t reserved_25:7; @@ -2327,14 +568,14 @@ typedef union { } cache_l1_cache_autoload_sct0_size_reg_t; /** Type of l1_cache_autoload_sct1_addr register - * L1 Cache autoload section 1 address configure register + * L1 cache autoloading Section 1 address configuration register */ typedef union { struct { /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the starting virtual address of Section 1 for the autoloading operation + * in the L1 cache. Note that it should be used together with + * CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE and CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ uint32_t l1_cache_autoload_sct1_addr:32; }; @@ -2342,14 +583,14 @@ typedef union { } cache_l1_cache_autoload_sct1_addr_reg_t; /** Type of l1_cache_autoload_sct1_size register - * L1 Cache autoload section 1 size configure register + * L1 cache autoloading Section 1 size configuration register */ typedef union { struct { /** l1_cache_autoload_sct1_size : R/W; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + * Configures the size of Section 1 for the autoloading operation in the L1 cache. + * Note that it should be used together with CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR and + * CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA. */ uint32_t l1_cache_autoload_sct1_size:25; uint32_t reserved_25:7; @@ -2357,459 +598,110 @@ typedef union { uint32_t val; } cache_l1_cache_autoload_sct1_size_reg_t; -/** Type of l1_cache_autoload_sct2_addr register - * L1 Cache autoload section 2 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l1_cache_autoload_sct2_addr:32; - }; - uint32_t val; -} cache_l1_cache_autoload_sct2_addr_reg_t; -/** Type of l1_cache_autoload_sct2_size register - * L1 Cache autoload section 2 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct2_size : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l1_cache_autoload_sct2_size:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} cache_l1_cache_autoload_sct2_size_reg_t; - -/** Type of l1_cache_autoload_sct3_addr register - * L1 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l1_cache_autoload_sct3_addr:32; - }; - uint32_t val; -} cache_l1_cache_autoload_sct3_addr_reg_t; - -/** Type of l1_cache_autoload_sct3_size register - * L1 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l1_cache_autoload_sct3_size : HRO; bitpos: [24:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L1-Cache. Note that it should be used together with - * L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l1_cache_autoload_sct3_size:25; - uint32_t reserved_25:7; - }; - uint32_t val; -} cache_l1_cache_autoload_sct3_size_reg_t; - -/** Type of l2_cache_autoload_ctrl register - * L2 Cache autoload-operation control register - */ -typedef union { - struct { - /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, - * 0: disable. - */ - uint32_t l2_cache_autoload_ena:1; - /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1; - * The bit is used to indicate whether autoload operation on L2-Cache is finished or - * not. 0: not finished. 1: finished. - */ - uint32_t l2_cache_autoload_done:1; - /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0; - * The bit is used to configure the direction of autoload operation on L2-Cache. 0: - * ascending. 1: descending. - */ - uint32_t l2_cache_autoload_order:1; - /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0; - * The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: - * miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - */ - uint32_t l2_cache_autoload_trigger_mode:2; - uint32_t reserved_5:3; - /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable the first section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct0_ena:1; - /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable the second section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct1_ena:1; - /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0; - * The bit is used to enable the third section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct2_ena:1; - /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0; - * The bit is used to enable the fourth section for autoload operation on L2-Cache. - */ - uint32_t l2_cache_autoload_sct3_ena:1; - /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0; - * The bit is used to set the gid of l2 cache autoload. - */ - uint32_t l2_cache_autoload_rgid:4; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_autoload_ctrl_reg_t; - -/** Type of l2_cache_autoload_sct0_addr register - * L2 Cache autoload section 0 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the first section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l2_cache_autoload_sct0_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct0_addr_reg_t; - -/** Type of l2_cache_autoload_sct0_size register - * L2 Cache autoload section 0 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the first section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - */ - uint32_t l2_cache_autoload_sct0_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct0_size_reg_t; - -/** Type of l2_cache_autoload_sct1_addr register - * L2 Cache autoload section 1 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the second section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l2_cache_autoload_sct1_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct1_addr_reg_t; - -/** Type of l2_cache_autoload_sct1_size register - * L2 Cache autoload section 1 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the second section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - */ - uint32_t l2_cache_autoload_sct1_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct1_size_reg_t; - -/** Type of l2_cache_autoload_sct2_addr register - * L2 Cache autoload section 2 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the third section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l2_cache_autoload_sct2_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct2_addr_reg_t; - -/** Type of l2_cache_autoload_sct2_size register - * L2 Cache autoload section 2 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the third section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - */ - uint32_t l2_cache_autoload_sct2_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct2_size_reg_t; - -/** Type of l2_cache_autoload_sct3_addr register - * L2 Cache autoload section 3 address configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits are used to configure the start address of the fourth section for - * autoload operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l2_cache_autoload_sct3_addr:32; - }; - uint32_t val; -} cache_l2_cache_autoload_sct3_addr_reg_t; - -/** Type of l2_cache_autoload_sct3_size register - * L2 Cache autoload section 3 size configure register - */ -typedef union { - struct { - /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0; - * Those bits are used to configure the size of the fourth section for autoload - * operation on L2-Cache. Note that it should be used together with - * L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. - */ - uint32_t l2_cache_autoload_sct3_size:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} cache_l2_cache_autoload_sct3_size_reg_t; - - -/** Group: Interrupt registers */ +/** Group: Interrupt Registers */ /** Type of l1_cache_acs_cnt_int_ena register - * Cache Access Counter Interrupt enable register + * Cache access counter interrupt enable register */ typedef union { struct { - /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_ena:1; - /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_ena:1; - /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_ena:1; - /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_ena:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * Write 1 to enable L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_ena:1; /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * Write 1 to enable L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_ena:1; - /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_ena:1; - /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_ena:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_ena_reg_t; /** Type of l1_cache_acs_cnt_int_clr register - * Cache Access Counter Interrupt clear register + * Cache access counter interrupt clear register */ typedef union { struct { - /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due - * to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_clr:1; - /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due - * to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_clr:1; - /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_clr:1; - /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_clr:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus0 accesses L1-DCache. + * Write 1 to clear L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_clr:1; /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L1-DCache due - * to bus1 accesses L1-DCache. + * Write 1 to clear L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_clr:1; - /** l1_dbus2_ovf_int_clr : R/W; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_clr:1; - /** l1_dbus3_ovf_int_clr : R/W; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_clr:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_clr_reg_t; /** Type of l1_cache_acs_cnt_int_raw register - * Cache Access Counter Interrupt raw register + * Cache access counter interrupt raw register */ typedef union { struct { - /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 - * due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_raw:1; - /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 - * due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_raw:1; - /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 - * due to bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_ovf_int_raw:1; - /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 - * due to bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_ovf_int_raw:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus0 accesses L1-DCache. + * The raw interrupt status of L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_raw:1; /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus1 accesses L1-DCache. + * The raw interrupt status of L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_raw:1; - /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_ovf_int_raw:1; - /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache - * due to bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_ovf_int_raw:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_raw_reg_t; /** Type of l1_cache_acs_cnt_int_st register - * Cache Access Counter Interrupt status register + * Cache access counter interrupt status register */ typedef union { struct { - /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache0 due to bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_ovf_int_st:1; - /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-ICache1 due to bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_ovf_int_st:1; - /** l1_ibus2_ovf_int_st : RO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_ovf_int_st:1; - /** l1_ibus3_ovf_int_st : RO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_ovf_int_st:1; + uint32_t reserved_0:4; /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus0 accesses L1-DCache. + * The masked interrupt status of L1_BUS0_OVF_INT. */ uint32_t l1_bus0_ovf_int_st:1; /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L1-DCache due to bus1 accesses L1-DCache. + * The masked interrupt status of L1_BUS1_OVF_INT. */ uint32_t l1_bus1_ovf_int_st:1; - /** l1_dbus2_ovf_int_st : RO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_ovf_int_st:1; - /** l1_dbus3_ovf_int_st : RO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_ovf_int_st:1; - uint32_t reserved_8:24; + uint32_t reserved_6:26; }; uint32_t val; } cache_l1_cache_acs_cnt_int_st_reg_t; -/** Type of l1_cache_acs_fail_int_ena register - * Cache Access Fail Interrupt enable register +/** Type of l1_cache_acs_fail_ctrl register + * Cache access failed interrupt configuration register */ typedef union { struct { - /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. + uint32_t reserved_0:4; + /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; + * Configures whether to pass the exception of cache accessing lower-level memory to + * the upper-level device. + * 0: Do not pass to the upper-level device + * 1: Pass to the upper-level device */ - uint32_t l1_icache0_fail_int_ena:1; - /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ - uint32_t l1_icache1_fail_int_ena:1; - /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_ena:1; - /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_ena:1; + uint32_t l1_cache_acs_fail_check_mode:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} cache_l1_cache_acs_fail_ctrl_reg_t; + +/** Type of l1_cache_acs_fail_int_ena register + * Cache access failed interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:4; /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to enable L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_ena:1; uint32_t reserved_5:27; @@ -2818,31 +710,13 @@ typedef union { } cache_l1_cache_acs_fail_int_ena_reg_t; /** Type of l1_cache_acs_fail_int_clr register - * L1-Cache Access Fail Interrupt clear register + * L1 cache access failed interrupt clear register */ typedef union { struct { - /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to - * cpu accesses L1-ICache0. - */ - uint32_t l1_icache0_fail_int_clr:1; - /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to - * cpu accesses L1-ICache1. - */ - uint32_t l1_icache1_fail_int_clr:1; - /** l1_icache2_fail_int_clr : WT; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_clr:1; - /** l1_icache3_fail_int_clr : WT; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_clr:1; + uint32_t reserved_0:4; /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L1-DCache due to - * cpu accesses L1-DCache. + * Write 1 to clear L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_clr:1; uint32_t reserved_5:27; @@ -2851,28 +725,13 @@ typedef union { } cache_l1_cache_acs_fail_int_clr_reg_t; /** Type of l1_cache_acs_fail_int_raw register - * Cache Access Fail Interrupt raw register + * Cache access failed interrupt raw register */ typedef union { struct { - /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache0. - */ - uint32_t l1_icache0_fail_int_raw:1; - /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache1. - */ - uint32_t l1_icache1_fail_int_raw:1; - /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache2. - */ - uint32_t l1_icache2_fail_int_raw:1; - /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-ICache3. - */ - uint32_t l1_icache3_fail_int_raw:1; + uint32_t reserved_0:4; /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L1-DCache. + * The raw interrupt status of L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_raw:1; uint32_t reserved_5:27; @@ -2881,31 +740,13 @@ typedef union { } cache_l1_cache_acs_fail_int_raw_reg_t; /** Type of l1_cache_acs_fail_int_st register - * Cache Access Fail Interrupt status register + * Cache access failed interrupt status register */ typedef union { struct { - /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due - * to cpu accesses L1-ICache. - */ - uint32_t l1_icache0_fail_int_st:1; - /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due - * to cpu accesses L1-ICache. - */ - uint32_t l1_icache1_fail_int_st:1; - /** l1_icache2_fail_int_st : RO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_fail_int_st:1; - /** l1_icache3_fail_int_st : RO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_fail_int_st:1; + uint32_t reserved_0:4; /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L1-DCache due - * to cpu accesses L1-DCache. + * The masked interrupt status of L1_CACHE_FAIL_INT. */ uint32_t l1_cache_fail_int_st:1; uint32_t reserved_5:27; @@ -2914,61 +755,28 @@ typedef union { } cache_l1_cache_acs_fail_int_st_reg_t; /** Type of l1_cache_sync_preload_int_ena register - * L1-Cache Access Fail Interrupt enable register + * Sync and preloading operation interrupt enable register */ typedef union { struct { - /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_icache0_pld_done_int_ena:1; - /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload - * operation is done, interrupt occurs. - */ - uint32_t l1_icache1_pld_done_int_ena:1; - /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_ena:1; - /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_ena:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation. If preload - * operation is done, interrupt occurs. + * Write 1 to enable L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_ena:1; uint32_t reserved_5:1; /** sync_done_int_ena : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation done. + * Write 1 to enable CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_ena:1; - /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0; - * The bit is used to enable interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_ena:1; - /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_ena:1; - /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_ena:1; - /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_ena:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0; - * The bit is used to enable interrupt of L1-Cache preload-operation error. + * Write 1 to enable CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_ena:1; uint32_t reserved_12:1; /** sync_err_int_ena : R/W; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of Cache sync-operation error. + * Write 1 to enable CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_ena:1; uint32_t reserved_14:18; @@ -2977,62 +785,28 @@ typedef union { } cache_l1_cache_sync_preload_int_ena_reg_t; /** Type of l1_cache_sync_preload_int_clr register - * Sync Preload operation Interrupt clear register + * Sync and preloading operation interrupt clear register */ typedef union { struct { - /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ - uint32_t l1_icache0_pld_done_int_clr:1; - /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ - uint32_t l1_icache1_pld_done_int_clr:1; - /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_clr:1; - /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_clr:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0; - * The bit is used to clear interrupt that occurs only when L1-Cache preload-operation - * is done. + * Write 1 to clear L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_clr:1; uint32_t reserved_5:1; /** sync_done_int_clr : WT; bitpos: [6]; default: 0; - * The bit is used to clear interrupt that occurs only when Cache sync-operation is - * done. + * Write 1 to clear CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_clr:1; - /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0; - * The bit is used to clear interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_clr:1; - /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0; - * The bit is used to clear interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_clr:1; - /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_clr:1; - /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_clr:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0; - * The bit is used to clear interrupt of L1-Cache preload-operation error. + * Write 1 to clear L1_CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_clr:1; uint32_t reserved_12:1; /** sync_err_int_clr : WT; bitpos: [13]; default: 0; - * The bit is used to clear interrupt of Cache sync-operation error. + * Write 1 to clear CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_clr:1; uint32_t reserved_14:18; @@ -3041,65 +815,28 @@ typedef union { } cache_l1_cache_sync_preload_int_clr_reg_t; /** Type of l1_cache_sync_preload_int_raw register - * Sync Preload operation Interrupt raw register + * Sync and preloading operation interrupt raw register */ typedef union { struct { - /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is - * done. - */ - uint32_t l1_icache0_pld_done_int_raw:1; - /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is - * done. - */ - uint32_t l1_icache1_pld_done_int_raw:1; - /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_raw:1; - /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_raw:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation is - * done. + * The raw interrupt status of L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_raw:1; uint32_t reserved_5:1; /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation is done. + * The raw interrupt status of CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_raw:1; - /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation - * error occurs. - */ - uint32_t l1_icache0_pld_err_int_raw:1; - /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation - * error occurs. - */ - uint32_t l1_icache1_pld_err_int_raw:1; - /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_raw:1; - /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_raw:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt that occurs only when L1-Cache preload-operation error - * occurs. + * The raw interrupt status of L1_CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_raw:1; uint32_t reserved_12:1; /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt that occurs only when Cache sync-operation error - * occurs. + * The raw interrupt status of CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_raw:1; uint32_t reserved_14:18; @@ -3108,62 +845,28 @@ typedef union { } cache_l1_cache_sync_preload_int_raw_reg_t; /** Type of l1_cache_sync_preload_int_st register - * L1-Cache Access Fail Interrupt status register + * Sync and preloading operation interrupt status register */ typedef union { struct { - /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache0 - * preload-operation is done. - */ - uint32_t l1_icache0_pld_done_int_st:1; - /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-ICache1 - * preload-operation is done. - */ - uint32_t l1_icache1_pld_done_int_st:1; - /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_done_int_st:1; - /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_done_int_st:1; + uint32_t reserved_0:4; /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L1-Cache - * preload-operation is done. + * The masked interrupt status of L1_CACHE_PLD_DONE_INT. */ uint32_t l1_cache_pld_done_int_st:1; uint32_t reserved_5:1; /** sync_done_int_st : RO; bitpos: [6]; default: 0; - * The bit indicates the status of the interrupt that occurs only when Cache - * sync-operation is done. + * The masked interrupt status of CACHE_SYNC_DONE_INT. */ uint32_t sync_done_int_st:1; - /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - */ - uint32_t l1_icache0_pld_err_int_st:1; - /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0; - * The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. - */ - uint32_t l1_icache1_pld_err_int_st:1; - /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_int_st:1; - /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_int_st:1; + uint32_t reserved_7:4; /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0; - * The bit indicates the status of the interrupt of L1-Cache preload-operation error. + * The masked interrupt status of L1_CACHE_PLD_ERR_INT. */ uint32_t l1_cache_pld_err_int_st:1; uint32_t reserved_12:1; /** sync_err_int_st : RO; bitpos: [13]; default: 0; - * The bit indicates the status of the interrupt of Cache sync-operation error. + * The masked interrupt status of CACHE_SYNC_ERR_INT. */ uint32_t sync_err_int_st:1; uint32_t reserved_14:18; @@ -3171,693 +874,53 @@ typedef union { uint32_t val; } cache_l1_cache_sync_preload_int_st_reg_t; -/** Type of l2_cache_acs_cnt_int_ena register - * Cache Access Counter Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_ena:1; - /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_ena:1; - /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_ena:1; - /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_ena:1; - /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_ena:1; - /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0; - * The bit is used to enable interrupt of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_ena:1; - /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_ena:1; - /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_ena:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_ena_reg_t; -/** Type of l2_cache_acs_cnt_int_clr register - * Cache Access Counter Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_clr:1; - /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_clr:1; - /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_clr:1; - /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_clr:1; - /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_clr:1; - /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0; - * The bit is used to clear counters overflow interrupt and counters in L2-Cache due - * to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_clr:1; - /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_clr:1; - /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_clr:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_clr_reg_t; - -/** Type of l2_cache_acs_cnt_int_raw register - * Cache Access Counter Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-ICache0. - */ - uint32_t l2_ibus0_ovf_int_raw:1; - /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-ICache1. - */ - uint32_t l2_ibus1_ovf_int_raw:1; - /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-ICache2. - */ - uint32_t l2_ibus2_ovf_int_raw:1; - /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-ICache3. - */ - uint32_t l2_ibus3_ovf_int_raw:1; - /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus0 accesses L2-DCache. - */ - uint32_t l2_dbus0_ovf_int_raw:1; - /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus1 accesses L2-DCache. - */ - uint32_t l2_dbus1_ovf_int_raw:1; - /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus2 accesses L2-DCache. - */ - uint32_t l2_dbus2_ovf_int_raw:1; - /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0; - * The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache - * due to bus3 accesses L2-DCache. - */ - uint32_t l2_dbus3_ovf_int_raw:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_raw_reg_t; - -/** Type of l2_cache_acs_cnt_int_st register - * Cache Access Counter Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_ibus0_ovf_int_st:1; - /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_ibus1_ovf_int_st:1; - /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_ovf_int_st:1; - /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_ovf_int_st:1; - /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus0 accesses L2-Cache. - */ - uint32_t l2_dbus0_ovf_int_st:1; - /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0; - * The bit indicates the interrupt status of one of counters overflow that occurs in - * L2-Cache due to bus1 accesses L2-Cache. - */ - uint32_t l2_dbus1_ovf_int_st:1; - /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_ovf_int_st:1; - /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_ovf_int_st:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_int_st_reg_t; - -/** Type of l2_cache_acs_fail_int_ena register - * Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of access fail that occurs in L2-Cache due to - * l1 cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_ena:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_ena_reg_t; - -/** Type of l2_cache_acs_fail_int_clr register - * L1-Cache Access Fail Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 - * cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_clr_reg_t; - -/** Type of l2_cache_acs_fail_int_raw register - * Cache Access Fail Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt of access fail that occurs in L2-Cache. - */ - uint32_t l2_cache_fail_int_raw:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_raw_reg_t; - -/** Type of l2_cache_acs_fail_int_st register - * Cache Access Fail Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0; - * The bit indicates the interrupt status of access fail that occurs in L2-Cache due - * to l1 cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_int_st:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_acs_fail_int_st_reg_t; - -/** Type of l2_cache_sync_preload_int_ena register - * L1-Cache Access Fail Interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation done. - */ - uint32_t l2_cache_pld_done_int_ena:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_ena:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_ena_reg_t; - -/** Type of l2_cache_sync_preload_int_clr register - * Sync Preload operation Interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear interrupt that occurs only when L2-Cache preload-operation - * is done. - */ - uint32_t l2_cache_pld_done_int_clr:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0; - * The bit is used to clear interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_clr:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_clr_reg_t; - -/** Type of l2_cache_sync_preload_int_raw register - * Sync Preload operation Interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation is - * done. - */ - uint32_t l2_cache_pld_done_int_raw:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0; - * The raw bit of the interrupt that occurs only when L2-Cache preload-operation error - * occurs. - */ - uint32_t l2_cache_pld_err_int_raw:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_raw_reg_t; - -/** Type of l2_cache_sync_preload_int_st register - * L1-Cache Access Fail Interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0; - * The bit indicates the status of the interrupt that occurs only when L2-Cache - * preload-operation is done. - */ - uint32_t l2_cache_pld_done_int_st:1; - uint32_t reserved_6:6; - /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0; - * The bit indicates the status of the interrupt of L2-Cache preload-operation error. - */ - uint32_t l2_cache_pld_err_int_st:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} cache_l2_cache_sync_preload_int_st_reg_t; - - -/** Group: Cache Access Fail Configuration register */ -/** Type of l1_cache_acs_fail_ctrl register - * Cache Access Fail Configuration register - */ -typedef union { - struct { - /** l1_icache0_acs_fail_check_mode : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l1 icache0 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache0_acs_fail_check_mode:1; - /** l1_icache1_acs_fail_check_mode : HRO; bitpos: [1]; default: 0; - * The bit is used to configure l1 icache1 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache1_acs_fail_check_mode:1; - /** l1_icache2_acs_fail_check_mode : HRO; bitpos: [2]; default: 0; - * The bit is used to configure l1 icache2 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache2_acs_fail_check_mode:1; - /** l1_icache3_acs_fail_check_mode : HRO; bitpos: [3]; default: 0; - * The bit is used to configure l1 icache3 access fail check mode. 0: the access fail - * is not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_icache3_acs_fail_check_mode:1; - /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0; - * The bit is used to configure l1 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l1_cache_acs_fail_check_mode:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} cache_l1_cache_acs_fail_ctrl_reg_t; - -/** Type of l2_cache_acs_fail_ctrl register - * Cache Access Fail Configuration register - */ -typedef union { - struct { - /** l2_cache_acs_fail_check_mode : HRO; bitpos: [0]; default: 0; - * The bit is used to configure l2 cache access fail check mode. 0: the access fail is - * not propagated to the request, 1: the access fail is propagated to the request - */ - uint32_t l2_cache_acs_fail_check_mode:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} cache_l2_cache_acs_fail_ctrl_reg_t; - - -/** Group: Access Statistics registers */ +/** Group: Access Statistics Registers */ /** Type of l1_cache_acs_cnt_ctrl register - * Cache Access Counter enable and clear register + * Cache access counter enable and clear register */ typedef union { struct { - /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0; - * The bit is used to enable ibus0 counter in L1-ICache0. - */ - uint32_t l1_ibus0_cnt_ena:1; - /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable ibus1 counter in L1-ICache1. - */ - uint32_t l1_ibus1_cnt_ena:1; - /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_cnt_ena:1; - /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_cnt_ena:1; + uint32_t reserved_0:4; /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0; - * The bit is used to enable dbus0 counter in L1-DCache. + * Configures whether to enable the BUS0 counters in the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_bus0_cnt_ena:1; /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0; - * The bit is used to enable dbus1 counter in L1-DCache. + * Configures whether to enable the BUS1 counters in the L1 cache. + * 0: Disable + * 1: Enable */ uint32_t l1_bus1_cnt_ena:1; - /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_cnt_ena:1; - /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_cnt_ena:1; - uint32_t reserved_8:8; - /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0; - * The bit is used to clear ibus0 counter in L1-ICache0. - */ - uint32_t l1_ibus0_cnt_clr:1; - /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0; - * The bit is used to clear ibus1 counter in L1-ICache1. - */ - uint32_t l1_ibus1_cnt_clr:1; - /** l1_ibus2_cnt_clr : WT; bitpos: [18]; default: 0; - * Reserved - */ - uint32_t l1_ibus2_cnt_clr:1; - /** l1_ibus3_cnt_clr : WT; bitpos: [19]; default: 0; - * Reserved - */ - uint32_t l1_ibus3_cnt_clr:1; + uint32_t reserved_6:14; /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0; - * The bit is used to clear dbus0 counter in L1-DCache. + * Configures whether to clear the BUS0 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ uint32_t l1_bus0_cnt_clr:1; /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0; - * The bit is used to clear dbus1 counter in L1-DCache. + * Configures whether to clear the BUS1 counters in the L1 cache. + * 0: Not clear + * 1: Clear */ uint32_t l1_bus1_cnt_clr:1; - /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0; - * Reserved - */ - uint32_t l1_dbus2_cnt_clr:1; - /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0; - * Reserved - */ - uint32_t l1_dbus3_cnt_clr:1; - uint32_t reserved_24:8; + uint32_t reserved_22:10; }; uint32_t val; } cache_l1_cache_acs_cnt_ctrl_reg_t; -/** Type of l1_ibus0_acs_hit_cnt register - * L1-ICache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_hit_cnt_reg_t; - -/** Type of l1_ibus0_acs_miss_cnt register - * L1-ICache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_miss_cnt_reg_t; - -/** Type of l1_ibus0_acs_conflict_cnt register - * L1-ICache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-ICache0. - */ - uint32_t l1_ibus0_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register - * L1-ICache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l1_ibus0_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_ibus1_acs_hit_cnt register - * L1-ICache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_hit_cnt_reg_t; - -/** Type of l1_ibus1_acs_miss_cnt register - * L1-ICache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_miss_cnt_reg_t; - -/** Type of l1_ibus1_acs_conflict_cnt register - * L1-ICache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-ICache1. - */ - uint32_t l1_ibus1_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register - * L1-ICache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l1_ibus1_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_ibus2_acs_hit_cnt register - * L1-ICache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_hit_cnt_reg_t; - -/** Type of l1_ibus2_acs_miss_cnt register - * L1-ICache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_miss_cnt_reg_t; - -/** Type of l1_ibus2_acs_conflict_cnt register - * L1-ICache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-ICache2. - */ - uint32_t l1_ibus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register - * L1-ICache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l1_ibus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_ibus3_acs_hit_cnt register - * L1-ICache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_hit_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_hit_cnt_reg_t; - -/** Type of l1_ibus3_acs_miss_cnt register - * L1-ICache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_miss_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_miss_cnt_reg_t; - -/** Type of l1_ibus3_acs_conflict_cnt register - * L1-ICache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-ICache3. - */ - uint32_t l1_ibus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_conflict_cnt_reg_t; - -/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register - * L1-ICache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-ICache accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l1_ibus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t; +/** Group: Access Statistics registers */ /** Type of l1_bus0_acs_hit_cnt register - * L1-Cache bus0 Hit-Access Counter register + * L1 cache BUS0 hit-access counter register */ typedef union { struct { /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus0 accesses L1-Cache. + * Represents the number of hits when BUS0 accesses the L1 cache. */ uint32_t l1_bus0_hit_cnt:32; }; @@ -3865,12 +928,12 @@ typedef union { } cache_l1_bus0_acs_hit_cnt_reg_t; /** Type of l1_bus0_acs_miss_cnt register - * L1-Cache bus0 Miss-Access Counter register + * L1 cache BUS0 missed-access counter register */ typedef union { struct { /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus0 accesses L1-Cache. + * Represents the number of misses when BUS0 accesses the L1 cache. */ uint32_t l1_bus0_miss_cnt:32; }; @@ -3878,52 +941,53 @@ typedef union { } cache_l1_bus0_acs_miss_cnt_reg_t; /** Type of l1_bus0_acs_conflict_cnt register - * L1-Cache bus0 Conflict-Access Counter register + * L1 cache BUS0 conflicting-access Counter register */ typedef union { struct { - /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus0 accesses L1-Cache. + /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; + * Represents the number of access conflicts when BUS0 accesses the L1 cache. */ - uint32_t l1_bus0_conflict_rd_cnt:32; + uint32_t l1_bus0_conflict_cnt:32; }; uint32_t val; } cache_l1_bus0_acs_conflict_cnt_reg_t; -/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register - * L1-Cache bus0 Next-Level-Access Counter register +/** Type of l1_bus0_acs_nxtlvl_rd_cnt register + * L1 cache BUS0 reads the lower-level memory */ typedef union { struct { /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus0 accessing L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's read access. */ uint32_t l1_bus0_nxtlvl_rd_cnt:32; }; uint32_t val; -} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t; +} cache_l1_bus0_acs_nxtlvl_rd_cnt_reg_t; -/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register - * L1-DCache bus0 WB-Access Counter register +/** Type of l1_bus0_acs_nxtlvl_wr_cnt register + * L1 cache BUS0 writes the lower-level memory */ typedef union { struct { /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. + * Represents the number of times that the cache accesses its lower-level module due + * to BUS0's write access. */ uint32_t l1_bus0_nxtlvl_wr_cnt:32; }; uint32_t val; -} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t; +} cache_l1_bus0_acs_nxtlvl_wr_cnt_reg_t; /** Type of l1_bus1_acs_hit_cnt register - * L1-Cache bus1 Hit-Access Counter register + * L1 cache BUS1 hit-access counter register */ typedef union { struct { /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus1 accesses L1-Cache. + * Represents the number of hits when BUS1 accesses the L1 cache. */ uint32_t l1_bus1_hit_cnt:32; }; @@ -3931,12 +995,12 @@ typedef union { } cache_l1_bus1_acs_hit_cnt_reg_t; /** Type of l1_bus1_acs_miss_cnt register - * L1-Cache bus1 Miss-Access Counter register + * L1 cache BUS1 missed-access counter register */ typedef union { struct { /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus1 accesses L1-Cache. + * Represents the number of misses when BUS1 accesses the L1 cache. */ uint32_t l1_bus1_miss_cnt:32; }; @@ -3944,12 +1008,12 @@ typedef union { } cache_l1_bus1_acs_miss_cnt_reg_t; /** Type of l1_bus1_acs_conflict_cnt register - * L1-Cache bus1 Conflict-Access Counter register + * L1 cache BUS1 conflicting-access counter register */ typedef union { struct { /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus1 accesses L1-Cache. + * Represents the number of access conflicts when BUS1 accesses the L1 cache. */ uint32_t l1_bus1_conflict_cnt:32; }; @@ -3957,957 +1021,93 @@ typedef union { } cache_l1_bus1_acs_conflict_cnt_reg_t; /** Type of l1_dbus1_acs_nxtlvl_rd_cnt register - * L1-DCache bus1 Next-Level-Access Counter register + * L1 cache BUS1 reads the lower-level memory */ typedef union { struct { - /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus1 accessing L1-Cache. + /** l1_bus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's read access. */ - uint32_t l1_dbus1_nxtlvl_rd_cnt:32; + uint32_t l1_bus1_nxtlvl_rd_cnt:32; }; uint32_t val; } cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t; /** Type of l1_dbus1_acs_nxtlvl_wr_cnt register - * L1-DCache bus1 WB-Access Counter register + * L1 cache BUS1 writes the lower-level memory */ typedef union { struct { - /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus1 accesses L1-Cache. + /** l1_bus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; + * Represents the number of times that the cache accesses its lower-level module due + * to BUS1's write access. */ - uint32_t l1_dbus1_nxtlvl_wr_cnt:32; + uint32_t l1_bus1_nxtlvl_wr_cnt:32; }; uint32_t val; } cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t; -/** Type of l1_dbus2_acs_hit_cnt register - * L1-DCache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_hit_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_hit_cnt_reg_t; - -/** Type of l1_dbus2_acs_miss_cnt register - * L1-DCache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_miss_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_miss_cnt_reg_t; - -/** Type of l1_dbus2_acs_conflict_cnt register - * L1-DCache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus2 accesses L1-DCache. - */ - uint32_t l1_dbus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_conflict_cnt_reg_t; - -/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register - * L1-DCache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus2 accessing L1-Cache. - */ - uint32_t l1_dbus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register - * L1-DCache bus2 WB-Access Counter register - */ -typedef union { - struct { - /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus2 accesses L1-Cache. - */ - uint32_t l1_dbus2_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l1_dbus3_acs_hit_cnt register - * L1-DCache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_hit_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_hit_cnt_reg_t; - -/** Type of l1_dbus3_acs_miss_cnt register - * L1-DCache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_miss_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_miss_cnt_reg_t; - -/** Type of l1_dbus3_acs_conflict_cnt register - * L1-DCache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when bus3 accesses L1-DCache. - */ - uint32_t l1_dbus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_conflict_cnt_reg_t; - -/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register - * L1-DCache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L1-Cache accesses L2-Cache due to - * bus3 accessing L1-Cache. - */ - uint32_t l1_dbus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register - * L1-DCache bus3 WB-Access Counter register - */ -typedef union { - struct { - /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when bus0 accesses L1-Cache. - */ - uint32_t l1_dbus3_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_cache_acs_cnt_ctrl register - * Cache Access Counter enable and clear register - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0; - * The bit is used to enable ibus0 counter in L2-Cache. - */ - uint32_t l2_ibus0_cnt_ena:1; - /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0; - * The bit is used to enable ibus1 counter in L2-Cache. - */ - uint32_t l2_ibus1_cnt_ena:1; - /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_cnt_ena:1; - /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_cnt_ena:1; - /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0; - * The bit is used to enable dbus0 counter in L2-Cache. - */ - uint32_t l2_dbus0_cnt_ena:1; - /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0; - * The bit is used to enable dbus1 counter in L2-Cache. - */ - uint32_t l2_dbus1_cnt_ena:1; - /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_cnt_ena:1; - /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_cnt_ena:1; - uint32_t reserved_16:8; - /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0; - * The bit is used to clear ibus0 counter in L2-Cache. - */ - uint32_t l2_ibus0_cnt_clr:1; - /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0; - * The bit is used to clear ibus1 counter in L2-Cache. - */ - uint32_t l2_ibus1_cnt_clr:1; - /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0; - * Reserved - */ - uint32_t l2_ibus2_cnt_clr:1; - /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0; - * Reserved - */ - uint32_t l2_ibus3_cnt_clr:1; - /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0; - * The bit is used to clear dbus0 counter in L2-Cache. - */ - uint32_t l2_dbus0_cnt_clr:1; - /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0; - * The bit is used to clear dbus1 counter in L2-Cache. - */ - uint32_t l2_dbus1_cnt_clr:1; - /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0; - * Reserved - */ - uint32_t l2_dbus2_cnt_clr:1; - /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0; - * Reserved - */ - uint32_t l2_dbus3_cnt_clr:1; - }; - uint32_t val; -} cache_l2_cache_acs_cnt_ctrl_reg_t; - -/** Type of l2_ibus0_acs_hit_cnt register - * L2-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_hit_cnt_reg_t; - -/** Type of l2_ibus0_acs_miss_cnt register - * L2-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache0 accesses L2-Cache due to - * bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_miss_cnt_reg_t; - -/** Type of l2_ibus0_acs_conflict_cnt register - * L2-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache0 accesses - * L2-Cache due to bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register - * L2-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. - */ - uint32_t l2_ibus0_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_ibus1_acs_hit_cnt register - * L2-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_hit_cnt_reg_t; - -/** Type of l2_ibus1_acs_miss_cnt register - * L2-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache1 accesses L2-Cache due to - * bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_miss_cnt_reg_t; - -/** Type of l2_ibus1_acs_conflict_cnt register - * L2-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache1 accesses - * L2-Cache due to bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register - * L2-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. - */ - uint32_t l2_ibus1_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_ibus2_acs_hit_cnt register - * L2-Cache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_hit_cnt_reg_t; - -/** Type of l2_ibus2_acs_miss_cnt register - * L2-Cache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache2 accesses L2-Cache due to - * bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_miss_cnt_reg_t; - -/** Type of l2_ibus2_acs_conflict_cnt register - * L2-Cache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache2 accesses - * L2-Cache due to bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register - * L2-Cache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. - */ - uint32_t l2_ibus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_ibus3_acs_hit_cnt register - * L2-Cache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_hit_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_hit_cnt_reg_t; - -/** Type of l2_ibus3_acs_miss_cnt register - * L2-Cache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-ICache3 accesses L2-Cache due to - * bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_miss_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_miss_cnt_reg_t; - -/** Type of l2_ibus3_acs_conflict_cnt register - * L2-Cache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-ICache3 accesses - * L2-Cache due to bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_conflict_cnt_reg_t; - -/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register - * L2-Cache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. - */ - uint32_t l2_ibus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus0_acs_hit_cnt register - * L2-Cache bus0 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_hit_cnt_reg_t; - -/** Type of l2_dbus0_acs_miss_cnt register - * L2-Cache bus0 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_miss_cnt_reg_t; - -/** Type of l2_dbus0_acs_conflict_cnt register - * L2-Cache bus0 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register - * L2-Cache bus0 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register - * L2-Cache bus0 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus0 accessing L1-DCache. - */ - uint32_t l2_dbus0_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_dbus1_acs_hit_cnt register - * L2-Cache bus1 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_hit_cnt_reg_t; - -/** Type of l2_dbus1_acs_miss_cnt register - * L2-Cache bus1 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_miss_cnt_reg_t; - -/** Type of l2_dbus1_acs_conflict_cnt register - * L2-Cache bus1 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register - * L2-Cache bus1 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register - * L2-Cache bus1 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus1 accessing L1-DCache. - */ - uint32_t l2_dbus1_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_dbus2_acs_hit_cnt register - * L2-Cache bus2 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_hit_cnt_reg_t; - -/** Type of l2_dbus2_acs_miss_cnt register - * L2-Cache bus2 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_miss_cnt_reg_t; - -/** Type of l2_dbus2_acs_conflict_cnt register - * L2-Cache bus2 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register - * L2-Cache bus2 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register - * L2-Cache bus2 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus2 accessing L1-DCache. - */ - uint32_t l2_dbus2_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t; - -/** Type of l2_dbus3_acs_hit_cnt register - * L2-Cache bus3 Hit-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of hits when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_hit_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_hit_cnt_reg_t; - -/** Type of l2_dbus3_acs_miss_cnt register - * L2-Cache bus3 Miss-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of missing when L1-DCache accesses L2-Cache due to - * bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_miss_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_miss_cnt_reg_t; - -/** Type of l2_dbus3_acs_conflict_cnt register - * L2-Cache bus3 Conflict-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of access-conflicts when L1-DCache accesses - * L2-Cache due to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_conflict_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_conflict_cnt_reg_t; - -/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register - * L2-Cache bus3 Next-Level-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of times that L2-Cache accesses external memory due - * to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_nxtlvl_rd_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t; - -/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register - * L2-Cache bus3 WB-Access Counter register - */ -typedef union { - struct { - /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0; - * The register records the number of write back when L1-DCache accesses L2-Cache due - * to bus3 accessing L1-DCache. - */ - uint32_t l2_dbus3_nxtlvl_wr_cnt:32; - }; - uint32_t val; -} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t; - /** Group: Access Fail Debug registers */ -/** Type of l1_icache0_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_id:16; - /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache0_acs_fail_id_attr_reg_t; - -/** Type of l1_icache0_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache0 accesses L1-ICache. - */ - uint32_t l1_icache0_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache0_acs_fail_addr_reg_t; - -/** Type of l1_icache1_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_id:16; - /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache1_acs_fail_id_attr_reg_t; - -/** Type of l1_icache1_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache1 accesses L1-ICache. - */ - uint32_t l1_icache1_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache1_acs_fail_addr_reg_t; - -/** Type of l1_icache2_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_id:16; - /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache2_acs_fail_id_attr_reg_t; - -/** Type of l1_icache2_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache2 accesses L1-ICache. - */ - uint32_t l1_icache2_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache2_acs_fail_addr_reg_t; - -/** Type of l1_icache3_acs_fail_id_attr register - * L1-ICache0 Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_id:16; - /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_attr:16; - }; - uint32_t val; -} cache_l1_icache3_acs_fail_id_attr_reg_t; - -/** Type of l1_icache3_acs_fail_addr register - * L1-ICache0 Access Fail Address information register - */ -typedef union { - struct { - /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache3 accesses L1-ICache. - */ - uint32_t l1_icache3_fail_addr:32; - }; - uint32_t val; -} cache_l1_icache3_acs_fail_addr_reg_t; - -/** Type of l1_dcache_acs_fail_id_attr register - * L1-Cache Access Fail ID/attribution information register +/** Type of l1_cache_acs_fail_id_attr register + * L1 cache access failed ID and attribution recording register */ typedef union { struct { /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when cache accesses L1-Cache. + * Represents the ID of the failed access to the L1 cache. + * Bit 4: BUS0 + * Bit 5: BUS1 + * Others: reserved */ uint32_t l1_cache_fail_id:16; /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when cache accesses L1-Cache. + * Represents the attribute of the failed access to the L1 cache. + * Bit 0: Fetching instructions + * Bit 1: Reading data + * Bit 7: non-cacheable + * Others: reserved */ uint32_t l1_cache_fail_attr:16; }; uint32_t val; -} cache_l1_dcache_acs_fail_id_attr_reg_t; +} cache_l1_cache_acs_fail_id_attr_reg_t; -/** Type of l1_dcache_acs_fail_addr register - * L1-Cache Access Fail Address information register +/** Type of l1_cache_acs_fail_addr register + * L1 cache access failed address information register */ typedef union { struct { /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when cache accesses L1-Cache. + * Represents the address of the failed access to the L1 cache. */ uint32_t l1_cache_fail_addr:32; }; uint32_t val; -} cache_l1_dcache_acs_fail_addr_reg_t; - -/** Type of l2_cache_acs_fail_id_attr register - * L2-Cache Access Fail ID/attribution information register - */ -typedef union { - struct { - /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0; - * The register records the ID of fail-access when L1-Cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_id:16; - /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0; - * The register records the attribution of fail-access when L1-Cache accesses L2-Cache - * due to cache accessing L1-Cache. - */ - uint32_t l2_cache_fail_attr:16; - }; - uint32_t val; -} cache_l2_cache_acs_fail_id_attr_reg_t; - -/** Type of l2_cache_acs_fail_addr register - * L2-Cache Access Fail Address information register - */ -typedef union { - struct { - /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0; - * The register records the address of fail-access when L1-Cache accesses L2-Cache. - */ - uint32_t l2_cache_fail_addr:32; - }; - uint32_t val; -} cache_l2_cache_acs_fail_addr_reg_t; +} cache_l1_cache_acs_fail_addr_reg_t; -/** Group: Operation Exception registers */ +/** Group: Access Fail Debug Registers */ /** Type of l1_cache_sync_preload_exception register - * Cache Sync/Preload Operation exception register + * Cache sync and preloading operation exception register */ typedef union { struct { - /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache0. - */ - uint32_t l1_icache0_pld_err_code:2; - /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0; - * The value 2 is Only available which means preload size is error in L1-ICache1. - */ - uint32_t l1_icache1_pld_err_code:2; - /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_err_code:2; - /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_err_code:2; + uint32_t reserved_0:8; /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0; - * The value 2 is Only available which means preload size is error in L1-Cache. + * Represents the error code for the failed preloading operation. + * 2: The preloading size in the L1 cache is wrong + * Other values: reserved */ uint32_t l1_cache_pld_err_code:2; uint32_t reserved_10:2; /** sync_err_code : RO; bitpos: [13:12]; default: 0; - * The values 0-2 are available which means sync map, command conflict and size are - * error in Cache System. + * Represents the error code for the failed synchronization operation. + * 0: Incorrect synchronization map + * 1: Synchronization command conflict + * 2: Incorrect synchronization size + * 3: Reserved */ uint32_t sync_err_code:2; uint32_t reserved_14:18; @@ -4915,49 +1115,20 @@ typedef union { uint32_t val; } cache_l1_cache_sync_preload_exception_reg_t; -/** Type of l2_cache_sync_preload_exception register - * Cache Sync/Preload Operation exception register - */ -typedef union { - struct { - uint32_t reserved_0:10; - /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0; - * The value 2 is Only available which means preload size is error in L2-Cache. - */ - uint32_t l2_cache_pld_err_code:2; - uint32_t reserved_12:20; - }; - uint32_t val; -} cache_l2_cache_sync_preload_exception_reg_t; - -/** Group: Sync Reset control and configuration registers */ +/** Group: Sync Reset Control and Configuration Registers */ /** Type of l1_cache_sync_rst_ctrl register - * Cache Sync Reset control register + * Cache sync reset control register */ typedef union { struct { - /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0; - * set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_icache0_sync_rst:1; - /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0; - * set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l1_icache1_sync_rst:1; - /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_sync_rst:1; - /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_sync_rst:1; + uint32_t reserved_0:4; /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0; - * set this bit to reset sync-logic inside L1-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. + * Configures whether to reset the synchronization logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * synchronization logic occurs. */ uint32_t l1_cache_sync_rst:1; uint32_t reserved_5:27; @@ -4965,53 +1136,18 @@ typedef union { uint32_t val; } cache_l1_cache_sync_rst_ctrl_reg_t; -/** Type of l2_cache_sync_rst_ctrl register - * Cache Sync Reset control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0; - * set this bit to reset sync-logic inside L2-Cache. Recommend that this should only - * be used to initialize sync-logic when some fatal error of sync-logic occurs. - */ - uint32_t l2_cache_sync_rst:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_sync_rst_ctrl_reg_t; - - -/** Group: Preload Reset control and configuration registers */ /** Type of l1_cache_preload_rst_ctrl register - * Cache Preload Reset control register + * Cache preloading reset control register */ typedef union { struct { - /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0; - * set this bit to reset preload-logic inside L1-ICache0. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_icache0_pld_rst:1; - /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0; - * set this bit to reset preload-logic inside L1-ICache1. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l1_icache1_pld_rst:1; - /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_pld_rst:1; - /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_pld_rst:1; + uint32_t reserved_0:4; /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0; - * set this bit to reset preload-logic inside L1-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. + * Configures whether to reset the preloading logic inside the L1 cache. + * 0: Not reset + * 1: Reset + * It is recommended that this field should only be used when a fatal error of the + * preloading logic occurs. */ uint32_t l1_cache_pld_rst:1; uint32_t reserved_5:27; @@ -5019,54 +1155,18 @@ typedef union { uint32_t val; } cache_l1_cache_preload_rst_ctrl_reg_t; -/** Type of l2_cache_preload_rst_ctrl register - * Cache Preload Reset control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0; - * set this bit to reset preload-logic inside L2-Cache. Recommend that this should - * only be used to initialize preload-logic when some fatal error of preload-logic - * occurs. - */ - uint32_t l2_cache_pld_rst:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_preload_rst_ctrl_reg_t; - -/** Group: Autoload buffer clear control and configuration registers */ +/** Group: Autoloading Buffer Clear Control and Configuration Registers */ /** Type of l1_cache_autoload_buf_clr_ctrl register - * Cache Autoload buffer clear control register + * Cache autoloading buffer clear control register */ typedef union { struct { - /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, - * autoload will not work in L1-ICache0. This bit should not be active when autoload - * works in L1-ICache0. - */ - uint32_t l1_icache0_ald_buf_clr:1; - /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0; - * set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, - * autoload will not work in L1-ICache1. This bit should not be active when autoload - * works in L1-ICache1. - */ - uint32_t l1_icache1_ald_buf_clr:1; - /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_ald_buf_clr:1; - /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_ald_buf_clr:1; + uint32_t reserved_0:4; /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0; - * set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, - * autoload will not work in L1-Cache. This bit should not be active when autoload - * works in L1-Cache. + * Configures whether to clear the autoloading buffer inside the L1 cache. + * 0: Not clear the buffer. Recommended when autoloading of L1 cache is used. + * 1: Clear the buffer. Once set, autoloading of L1 cache will stop working. */ uint32_t l1_cache_ald_buf_clr:1; uint32_t reserved_5:27; @@ -5074,126 +1174,29 @@ typedef union { uint32_t val; } cache_l1_cache_autoload_buf_clr_ctrl_reg_t; -/** Type of l2_cache_autoload_buf_clr_ctrl register - * Cache Autoload buffer clear control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0; - * set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, - * autoload will not work in L2-Cache. This bit should not be active when autoload - * works in L2-Cache. - */ - uint32_t l2_cache_ald_buf_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_cache_autoload_buf_clr_ctrl_reg_t; - -/** Group: Unallocate request buffer clear registers */ -/** Type of l1_unallocate_buffer_clear register - * Unallocate request buffer clear registers - */ -typedef union { - struct { - /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache0 where the - * unallocate request is responded but not completed. - */ - uint32_t l1_icache0_unalloc_clr:1; - /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 icache1 where the - * unallocate request is responded but not completed. - */ - uint32_t l1_icache1_unalloc_clr:1; - /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_unalloc_clr:1; - /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_unalloc_clr:1; - /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0; - * The bit is used to clear the unallocate request buffer of l1 cache where the - * unallocate request is responded but not completed. - */ - uint32_t l1_cache_unalloc_clr:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} cache_l1_unallocate_buffer_clear_reg_t; - -/** Type of l2_unallocate_buffer_clear register - * Unallocate request buffer clear registers - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0; - * The bit is used to clear the unallocate request buffer of l2 icache where the - * unallocate request is responded but not completed. - */ - uint32_t l2_cache_unalloc_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} cache_l2_unallocate_buffer_clear_reg_t; - - -/** Group: Tag and Data Memory Access Control and configuration register */ +/** Group: Tag and Data Memory Access Control and Configuration Registers */ /** Type of l1_cache_object_ctrl register - * Cache Tag and Data memory Object control register + * Cache tag and data memory object control register */ typedef union { struct { - /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0; - * Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_icache0_tag_object:1; - /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0; - * Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l1_icache1_tag_object:1; - /** l1_icache2_tag_object : R/W; bitpos: [2]; default: 0; - * Reserved - */ - uint32_t l1_icache2_tag_object:1; - /** l1_icache3_tag_object : R/W; bitpos: [3]; default: 0; - * Reserved - */ - uint32_t l1_icache3_tag_object:1; + uint32_t reserved_0:4; /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0; - * Set this bit to set L1-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache tag memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ uint32_t l1_cache_tag_object:1; - uint32_t reserved_5:1; - /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0; - * Set this bit to set L1-ICache0 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ - uint32_t l1_icache0_mem_object:1; - /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0; - * Set this bit to set L1-ICache1 data memory as object. This bit should be onehot - * with the others fields inside this register. - */ - uint32_t l1_icache1_mem_object:1; - /** l1_icache2_mem_object : R/W; bitpos: [8]; default: 0; - * Reserved - */ - uint32_t l1_icache2_mem_object:1; - /** l1_icache3_mem_object : R/W; bitpos: [9]; default: 0; - * Reserved - */ - uint32_t l1_icache3_mem_object:1; + uint32_t reserved_5:5; /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0; - * Set this bit to set L1-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. + * Configure whether to set the L1 cache data memory as an object. + * 0: Not set + * 1: Set + * This register uses "one-hot encoding," which means that at any time, only one field + * can be valid in conjunction with other fields. */ uint32_t l1_cache_mem_object:1; uint32_t reserved_11:21; @@ -5202,13 +1205,16 @@ typedef union { } cache_l1_cache_object_ctrl_reg_t; /** Type of l1_cache_way_object register - * Cache Tag and Data memory way register + * Cache tag and data memory way register */ typedef union { struct { /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. + * Configures which way in the tag memory or the data memory to access. + * 0: Way 0 + * 1: Way 1 + * 2: Way 2 + * 3: Way 3 */ uint32_t l1_cache_way_object:3; uint32_t reserved_3:29; @@ -5216,178 +1222,34 @@ typedef union { uint32_t val; } cache_l1_cache_way_object_reg_t; -/** Type of l1_cache_addr register - * Cache address register - */ -typedef union { - struct { - /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. - */ - uint32_t l1_cache_addr:32; - }; - uint32_t val; -} cache_l1_cache_addr_reg_t; - /** Type of l1_cache_debug_bus register - * Cache Tag/data memory content register + * Cache tag and data memory content register */ typedef union { struct { /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 612; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. + * Configures the data to write to or the data to read from the tag memory or the data + * memory. */ uint32_t l1_cache_debug_bus:32; }; uint32_t val; } cache_l1_cache_debug_bus_reg_t; -/** Type of l2_cache_object_ctrl register - * Cache Tag and Data memory Object control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0; - * Set this bit to set L2-Cache tag memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l2_cache_tag_object:1; - uint32_t reserved_6:5; - /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0; - * Set this bit to set L2-Cache data memory as object. This bit should be onehot with - * the others fields inside this register. - */ - uint32_t l2_cache_mem_object:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} cache_l2_cache_object_ctrl_reg_t; -/** Type of l2_cache_way_object register - * Cache Tag and Data memory way register - */ -typedef union { - struct { - /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: - * way1, 2: way2, 3: way3, ?, 7: way7. - */ - uint32_t l2_cache_way_object:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} cache_l2_cache_way_object_reg_t; - -/** Type of l2_cache_addr register +/** Group: Tag and Data Memory Access Control and configuration register */ +/** Type of l1_cache_addr register * Cache address register */ typedef union { struct { - /** l2_cache_addr : HRO; bitpos: [31:0]; default: 0; - * Those bits stores the address which will decide where inside the specified tag - * memory object will be accessed. + /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0; + * Configures the virtual address inside the tag memory or data memory to access. */ - uint32_t l2_cache_addr:32; + uint32_t l1_cache_addr:32; }; uint32_t val; -} cache_l2_cache_addr_reg_t; - -/** Type of l2_cache_debug_bus register - * Cache Tag/data memory content register - */ -typedef union { - struct { - /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 964; - * This is a constant place where we can write data to or read data from the tag/data - * memory on the specified cache. - */ - uint32_t l2_cache_debug_bus:32; - }; - uint32_t val; -} cache_l2_cache_debug_bus_reg_t; - - -/** Group: Split L1 and L2 registers */ -/** Type of level_split0 register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -typedef union { - struct { - /** level_split0 : HRO; bitpos: [31:0]; default: 616; - * Reserved - */ - uint32_t level_split0:32; - }; - uint32_t val; -} cache_level_split0_reg_t; - -/** Type of level_split1 register - * USED TO SPLIT L1 CACHE AND L2 CACHE - */ -typedef union { - struct { - /** level_split1 : HRO; bitpos: [31:0]; default: 968; - * Reserved - */ - uint32_t level_split1:32; - }; - uint32_t val; -} cache_level_split1_reg_t; - - -/** Group: L2 cache access attribute control register */ -/** Type of l2_cache_access_attr_ctrl register - * L2 cache access attribute control register - */ -typedef union { - struct { - /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1; - * Set this bit to force the request to l2 cache with cacheable attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of cacheable and - * non-cacheable. - */ - uint32_t l2_cache_access_force_cc:1; - /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1; - * Set this bit to force the request to l2 cache with write-back attribute, otherwise, - * the attribute is propagated from L1 cache or CPU, it could be one of write-back and - * write-through. - */ - uint32_t l2_cache_access_force_wb:1; - /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1; - * Set this bit to force the request to l2 cache with write-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * write-miss-allocate and write-miss-no-allocate. - */ - uint32_t l2_cache_access_force_wma:1; - /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1; - * Set this bit to force the request to l2 cache with read-miss-allocate attribute, - * otherwise, the attribute is propagated from L1 cache or CPU, it could be one of - * read-miss-allocate and read-miss-no-allocate. - */ - uint32_t l2_cache_access_force_rma:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} cache_l2_cache_access_attr_ctrl_reg_t; - - -/** Group: Clock Gate Control and configuration register */ -/** Type of clock_gate register - * Clock gate control register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * The bit is used to enable clock gate when access all registers in this module. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} cache_clock_gate_reg_t; +} cache_l1_cache_addr_reg_t; /** Group: Cache Trace Control register */ @@ -5400,93 +1262,21 @@ typedef union { * The bit is used to enable L1-Cache trace for the performance counter and fail tracer */ uint32_t l1_cache_trace_ena:1; - /** l2_cache_trace_ena : HRO; bitpos: [1]; default: 0; - * The bit is used to enable L2-Cache trace for the performance counter and fail tracer - */ - uint32_t l2_cache_trace_ena:1; - uint32_t reserved_2:30; + uint32_t reserved_1:31; }; uint32_t val; } cache_trace_ena_reg_t; -/** Group: Redundancy register (Prepare for ECO) */ -/** Type of redundancy_sig0 register - * Cache redundancy signal 0 register - */ -typedef union { - struct { - /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig0:32; - }; - uint32_t val; -} cache_redundancy_sig0_reg_t; - -/** Type of redundancy_sig1 register - * Cache redundancy signal 1 register - */ -typedef union { - struct { - /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig1:32; - }; - uint32_t val; -} cache_redundancy_sig1_reg_t; - -/** Type of redundancy_sig2 register - * Cache redundancy signal 2 register - */ -typedef union { - struct { - /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig2:32; - }; - uint32_t val; -} cache_redundancy_sig2_reg_t; - -/** Type of redundancy_sig3 register - * Cache redundancy signal 3 register - */ -typedef union { - struct { - /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig3:32; - }; - uint32_t val; -} cache_redundancy_sig3_reg_t; - -/** Type of redundancy_sig4 register - * Cache redundancy signal 0 register - */ -typedef union { - struct { - /** redcy_sig4 : RO; bitpos: [3:0]; default: 0; - * Those bits are prepared for ECO. - */ - uint32_t redcy_sig4:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} cache_redundancy_sig4_reg_t; - - -/** Group: Version register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 36774432; - * version control register. Note that this default value stored is the latest date - * when the hardware logic was updated. + * Version control register. Note that the default value is the latest date when the + * hardware logic was updated. */ uint32_t date:28; uint32_t reserved_28:4; @@ -5496,12 +1286,9 @@ typedef union { typedef struct { - volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl; + uint32_t reserved_000; volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl; - volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf; - volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf; - volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf; - volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf; + uint32_t reserved_008[4]; volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf; volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf; volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl; @@ -5509,26 +1296,11 @@ typedef struct { volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl; volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf; volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf; - volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf; - volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr; - volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr; - volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size; - volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf; - volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr; - volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr; - volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size; - volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf; - volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr; - volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr; - volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size; - volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf; - volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr; - volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr; - volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size; + uint32_t reserved_034[16]; volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf; volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr; - volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr; - volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size; + volatile cache_l1_cache_prelock_sct1_addr_reg_t l1_cache_prelock_sct1_addr; + volatile cache_l1_cache_prelock_sct_size_reg_t l1_cache_prelock_sct_size; volatile cache_lock_ctrl_reg_t lock_ctrl; volatile cache_lock_map_reg_t lock_map; volatile cache_lock_addr_reg_t lock_addr; @@ -5537,50 +1309,17 @@ typedef struct { volatile cache_sync_map_reg_t sync_map; volatile cache_sync_addr_reg_t sync_addr; volatile cache_sync_size_reg_t sync_size; - volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl; - volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr; - volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size; - volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl; - volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr; - volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size; - volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl; - volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr; - volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size; - volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl; - volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr; - volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size; + uint32_t reserved_0a4[12]; volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl; - volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr; - volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size; - volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl; - volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr; - volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size; - volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr; - volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size; - volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl; - volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr; - volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size; - volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr; - volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size; - volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl; - volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr; - volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size; - volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr; - volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size; - volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl; - volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr; - volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size; - volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr; - volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size; + volatile cache_l1_cache_preload_addr_reg_t l1_cache_preload_addr; + volatile cache_l1_cache_preload_size_reg_t l1_cache_preload_size; + uint32_t reserved_0e0[20]; volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl; volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr; volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size; volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr; volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size; - volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr; - volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size; - volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr; - volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size; + uint32_t reserved_144[4]; volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena; volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr; volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw; @@ -5591,52 +1330,20 @@ typedef struct { volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw; volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st; volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl; - volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt; - volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt; - volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt; - volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt; - volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt; - volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt; - volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt; - volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt; - volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt; - volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt; - volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt; - volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt; - volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt; - volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt; - volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt; - volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt; + uint32_t reserved_17c[16]; volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt; volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt; volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt; - volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt; - volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt; + volatile cache_l1_bus0_acs_nxtlvl_rd_cnt_reg_t l1_bus0_acs_nxtlvl_rd_cnt; + volatile cache_l1_bus0_acs_nxtlvl_wr_cnt_reg_t l1_bus0_acs_nxtlvl_wr_cnt; volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt; volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt; volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt; volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt; volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt; - volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt; - volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt; - volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt; - volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt; - volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt; - volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt; - volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt; - volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt; - volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt; - volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt; - volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr; - volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr; - volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr; - volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr; - volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr; - volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr; - volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr; - volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr; - volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr; - volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr; + uint32_t reserved_1e4[18]; + volatile cache_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr; + volatile cache_l1_cache_acs_fail_addr_reg_t l1_cache_acs_fail_addr; volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena; volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr; volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw; @@ -5645,108 +1352,14 @@ typedef struct { volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl; volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl; volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl; - volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear; + uint32_t reserved_254; volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl; volatile cache_l1_cache_way_object_reg_t l1_cache_way_object; volatile cache_l1_cache_addr_reg_t l1_cache_addr; volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus; - volatile cache_level_split0_reg_t level_split0; - volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl; - volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf; - volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf; - volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf; - volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl; - volatile cache_l2_cache_miss_access_ctrl_reg_t l2_cache_miss_access_ctrl; - volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl; - volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf; - volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf; - volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf; - volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr; - volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr; - volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size; - volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl; - volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr; - volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size; - volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl; - volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr; - volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size; - volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr; - volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size; - volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr; - volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size; - volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr; - volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size; - volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena; - volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr; - volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw; - volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st; - volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl; - volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena; - volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr; - volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw; - volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st; - volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl; - volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt; - volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt; - volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt; - volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt; - volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt; - volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt; - volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt; - volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt; - volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt; - volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt; - volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt; - volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt; - volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt; - volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt; - volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt; - volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt; - volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt; - volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt; - volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt; - volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt; - volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt; - volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt; - volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt; - volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt; - volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt; - volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt; - volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt; - volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt; - volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt; - volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt; - volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt; - volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt; - volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr; - volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr; - volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena; - volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr; - volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw; - volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st; - volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception; - volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl; - volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl; - volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl; - volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear; - volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl; - volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl; - volatile cache_l2_cache_way_object_reg_t l2_cache_way_object; - volatile cache_l2_cache_addr_reg_t l2_cache_addr; - volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus; - volatile cache_level_split1_reg_t level_split1; - volatile cache_clock_gate_reg_t clock_gate; + uint32_t reserved_268[90]; volatile cache_trace_ena_reg_t trace_ena; - volatile cache_redundancy_sig0_reg_t redundancy_sig0; - volatile cache_redundancy_sig1_reg_t redundancy_sig1; - volatile cache_redundancy_sig2_reg_t redundancy_sig2; - volatile cache_redundancy_sig3_reg_t redundancy_sig3; - volatile cache_redundancy_sig4_reg_t redundancy_sig4; - uint32_t reserved_3e8[5]; + uint32_t reserved_3d4[10]; volatile cache_date_reg_t date; } cache_dev_t;