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feat(rom): update rom for c5 eco2

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Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)
This commit is contained in:
laokaiyao
2025-04-08 12:48:49 +08:00
parent 61064b442a
commit 0abc755342
24 changed files with 241 additions and 392 deletions
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8
components/soc/esp32c5/include/soc/interrupts.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -57,6 +57,8 @@ typedef enum {
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_CPU_APM_M0_INTR_SOURCE,
ETS_CPU_APM_M1_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
@@ -77,9 +79,9 @@ typedef enum {
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_APB_ADC_INTR_SOURCE = 62, /**< interrupt of APB ADC, LEVEL*/
ETS_APB_ADC_INTR_SOURCE = 64, /**< interrupt of APB ADC, LEVEL*/
ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE,
ETS_MCPWM0_INTR_SOURCE = 63, /**< interrupt of MCPWM0, LEVEL*/
ETS_MCPWM0_INTR_SOURCE = 65, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,

2
components/soc/esp32c5/include/soc/soc.h
View File

@@ -202,7 +202,7 @@
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4085e9a0
#define SOC_ROM_STACK_START 0x4085e5a0
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.