From 0c6aeecde43ce202c9772be4d9bf9548ad43f78d Mon Sep 17 00:00:00 2001
From: armando <douyiwen@espressif.com>
Date: Wed, 14 May 2025 11:36:50 +0800
Subject: [PATCH] feat(cache): supported cache panic driver on h21

---
 .../port/soc/esp32h21/cache_err_int.c          | 11 ++++++++---
 components/hal/esp32h21/include/hal/cache_ll.h | 18 ++++++++++++++----
 2 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/components/esp_system/port/soc/esp32h21/cache_err_int.c b/components/esp_system/port/soc/esp32h21/cache_err_int.c
index c5085eb1ea..05a4cbd893 100644
--- a/components/esp_system/port/soc/esp32h21/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32h21/cache_err_int.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,8 +19,6 @@
 #include "hal/cache_ll.h"
 #include "esp_private/cache_err_int.h"
 
-// TODO: [ESP32H21] IDF-11524
-
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
@@ -64,6 +62,13 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
+    /**
+     * Here we
+     * 1. enable the cache fail tracer to take cache error interrupt into effect.
+     * 2. clear potential cache error interrupt raw bits
+     * 3. enable cache error interrupt en bits
+     */
+    cache_ll_l1_enable_fail_tracer(0, true);
     /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
diff --git a/components/hal/esp32h21/include/hal/cache_ll.h b/components/hal/esp32h21/include/hal/cache_ll.h
index cd0f1cfcbd..2f8d8a489e 100644
--- a/components/hal/esp32h21/include/hal/cache_ll.h
+++ b/components/hal/esp32h21/include/hal/cache_ll.h
@@ -273,6 +273,17 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
     return valid;
 }
 
+/**
+ * Enable the Cache fail tracer
+ *
+ * @param cache_id    cache ID
+ * @param en          enable / disable
+ */
+static inline void cache_ll_l1_enable_fail_tracer(uint32_t cache_id, bool en)
+{
+    CACHE.trace_ena.l1_cache_trace_ena = en;
+}
+
 /*------------------------------------------------------------------------------
  * Interrupt
  *----------------------------------------------------------------------------*/
@@ -284,7 +295,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
  */
 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
-    //TODO: [ESP32H21] IDF-11525
+    CACHE.l1_cache_acs_fail_int_ena.val |= mask;
 }
 
 /**
@@ -295,7 +306,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3
  */
 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
-    //TODO: [ESP32H21] IDF-11525
+    CACHE.l1_cache_acs_fail_int_clr.val = mask;
 }
 
 /**
@@ -308,8 +319,7 @@ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32
  */
 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
 {
-    //TODO: [ESP32H21] IDF-11525
-    return 0;
+    return CACHE.l1_cache_acs_fail_int_st.val & mask;
 }
 
 #ifdef __cplusplus