diff --git a/Kconfig b/Kconfig index 176c10472a..b2a207e3b6 100644 --- a/Kconfig +++ b/Kconfig @@ -32,8 +32,7 @@ mainmenu "Espressif IoT Development Framework Configuration" config IDF_FIRMWARE_CHIP_ID hex default 0x0000 if IDF_TARGET_ESP32 - # note: S2 beta uses Chip ID 0 still, S2 will use 0x0002 - default 0x0000 if IDF_TARGET_ESP32S2BETA + default 0x0002 if IDF_TARGET_ESP32S2BETA default 0xFFFF menu "SDK tool configuration" diff --git a/components/bootloader/subproject/main/ld/esp32/bootloader.ld b/components/bootloader/subproject/main/ld/esp32/bootloader.ld index 3dca756097..64ecbcc091 100644 --- a/components/bootloader/subproject/main/ld/esp32/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32/bootloader.ld @@ -11,8 +11,6 @@ Linker file used to link the bootloader. MEMORY { - /* I/O */ - dport0_seg (RW) : org = 0x3FF00000, len = 0x10 /* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */ iram_loader_seg (RWX) : org = 0x40078000, len = 0x8000 /* 32KB, APP CPU cache */ /* 63kB, IRAM. We skip the first 1k to prevent the entry point being diff --git a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld index e72ab776d5..25721f2d93 100644 --- a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld @@ -1,22 +1,13 @@ -/* -Linker file used to link the bootloader. -*/ +/* Simplified memory map for the bootloader. + * Make sure the bootloader can load into main memory without overwriting itself. + */ -/* Simplified memory map for the bootloader - - The main purpose is to make sure the bootloader can load into main memory - without overwriting itself. -*/ - MEMORY { - /* I/O */ - dport0_seg (RW) : org = 0x3FF00000, len = 0x10 - iram_loader_seg (RWX) : org = 0x40062000, len = 0x4000 /* 16KB, IRAM */ - iram_seg (RWX) : org = 0x40066000, len = 0x4000 /* 16KB, IRAM */ - /* 8k at the end of DRAM, before ROM data & stack */ - dram_seg (RW) : org = 0x3FFFA000, len = 0x2000 + iram_loader_seg (RWX) : org = 0x40050000, len = 0x4000 /* 16KB, SRAM Block_14 */ + iram_seg (RWX) : org = 0x40054000, len = 0x4000 /* 16KB, SRAM Block_15 */ + dram_seg (RW) : org = 0x3FFE8000, len = 0x2800 /* 10KB, Top of SRAM Block_16, and before ROM data and stack */ } /* Default entry point: */ diff --git a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.rom.ld index 6a9e880fe3..0a600f8dc0 100644 --- a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.rom.ld +++ b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.rom.ld @@ -1,14 +1,13 @@ /* * ESP32S2 ROM address table - * Generated for ROM with MD5sum: f054d40c5f6b9207d3827460a6f5748c + * Generated for ROM with MD5sum: 0a2c7ec5109c17884606d23b47045796 */ -PROVIDE ( ets_update_cpu_frequency = 0x4000d954 ); +PROVIDE (ets_update_cpu_frequency = 0x4000d8a4); -/* ToDo: Following address may need modification */ -PROVIDE ( MD5Final = 0x400056e8 ); -PROVIDE ( MD5Init = 0x40005648 ); -PROVIDE ( MD5Update = 0x40005668 ); +PROVIDE (MD5Final = 0x4000530c); +PROVIDE (MD5Init = 0x4000526c); +PROVIDE (MD5Update = 0x4000528c); /* bootloader will use following functions from xtensa hal library */ -xthal_get_ccount = 0x40015cbc; -xthal_get_ccompare = 0x40015ce8; -xthal_set_ccompare = 0x40015cc4; +xthal_get_ccount = 0x4001aa90; +xthal_get_ccompare = 0x4001aabc; +xthal_set_ccompare = 0x4001aa98; diff --git a/components/bootloader_support/src/bootloader_clock.c b/components/bootloader_support/src/bootloader_clock.c index 7a19d0e684..9e156e583e 100644 --- a/components/bootloader_support/src/bootloader_clock.c +++ b/components/bootloader_support/src/bootloader_clock.c @@ -16,11 +16,12 @@ #include "soc/rtc.h" #include "soc/dport_reg.h" #include "soc/efuse_periph.h" +#include "soc/rtc_cntl_reg.h" #ifdef CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/uart.h" #include "esp32/rom/rtc.h" -#else +#elif CONFIG_IDF_TARGET_ESP32S2BETA #include "esp32s2beta/rom/uart.h" #include "esp32s2beta/rom/rtc.h" #endif diff --git a/components/bootloader_support/src/bootloader_efuse_esp32s2beta.c b/components/bootloader_support/src/bootloader_efuse_esp32s2beta.c index b762d2c4f8..6c2c3a9b64 100644 --- a/components/bootloader_support/src/bootloader_efuse_esp32s2beta.c +++ b/components/bootloader_support/src/bootloader_efuse_esp32s2beta.c @@ -16,12 +16,6 @@ #include "bootloader_clock.h" #include "bootloader_common.h" -int bootloader_clock_get_rated_freq_mhz() -{ - /* No known limitation: all chips are 240MHz rated */ - return 240; -} - uint8_t bootloader_common_get_chip_revision(void) { /* No other revisions for ESP32-S2beta */ diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index 96121c8230..249b466945 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -92,13 +92,14 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size) #else /* Bootloader version, uses ROM functions only */ -#include +#include "soc/dport_reg.h" #if CONFIG_IDF_TARGET_ESP32 -#include -#include +#include "esp32/rom/spi_flash.h" +#include "esp32/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32S2BETA -#include -#include +#include "esp32s2beta/rom/spi_flash.h" +#include "esp32s2beta/rom/cache.h" +#include "soc/cache_memory.h" #endif static const char *TAG = "bootloader_flash"; @@ -121,7 +122,7 @@ static const char *TAG = "bootloader_flash"; #endif #define MMU_FREE_PAGES (MMU_SIZE / FLASH_BLOCK_SIZE) - + static bool mapped; // Current bootloader mapping (ab)used for bootloader_read() @@ -161,7 +162,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) #if CONFIG_IDF_TARGET_ESP32 int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count); #elif CONFIG_IDF_TARGET_ESP32S2BETA - int e = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0); + int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0); #endif if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); @@ -255,7 +256,7 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest #if CONFIG_IDF_TARGET_ESP32 int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1); #elif CONFIG_IDF_TARGET_ESP32S2BETA - int e = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, FLASH_READ_VADDR, map_at, 64, 1, 0); + int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); #endif if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32s2beta.c b/components/bootloader_support/src/bootloader_flash_config_esp32s2beta.c index f6bea6cf4b..32d8906612 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32s2beta.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32s2beta.c @@ -41,12 +41,12 @@ void bootloader_flash_update_id() void IRAM_ATTR bootloader_flash_cs_timing_config() { - SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M); - SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S); - SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M); - SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_HOLD_TIME_V, 1, SPI_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_CS_SETUP_TIME_V, 0, SPI_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); } void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr) @@ -71,48 +71,14 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr) esp_rom_spiflash_config_clk(spi_clk_div, 0); } -void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr) +void IRAM_ATTR bootloader_flash_set_dummy_out(void) { - + REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); + REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); } void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr) { - int spi_cache_dummy = 0; - int drv = 2; - switch (pfhdr->spi_mode) { - case ESP_IMAGE_SPI_MODE_QIO: - spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; - break; - case ESP_IMAGE_SPI_MODE_DIO: - spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3 - break; - case ESP_IMAGE_SPI_MODE_QOUT: - case ESP_IMAGE_SPI_MODE_DOUT: - default: - spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; - break; - } - - /* dummy_len_plus values defined in ROM for SPI flash configuration */ - extern uint8_t g_rom_spiflash_dummy_len_plus[]; - switch (pfhdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_80M: - g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M; - g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M; - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M, - SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - drv = 3; - break; - case ESP_IMAGE_SPI_SPEED_40M: - g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M; - g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M; - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M, - SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - break; - default: - break; - } - - bootloader_configure_spi_pins(drv); + bootloader_configure_spi_pins(1); + bootloader_flash_set_dummy_out(); } diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index f28333214d..4b9fdcb99d 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -11,6 +11,7 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. +#include "sdkconfig.h" #include "bootloader_random.h" #include "soc/cpu.h" #include "soc/wdev_reg.h" @@ -20,6 +21,10 @@ #include "soc/dport_reg.h" #include "soc/i2s_periph.h" #include "esp_log.h" +#include "soc/io_mux_reg.h" +#if CONFIG_IDF_TARGET_ESP32S2BETA +#include "soc/apb_saradc_reg.h" +#endif #ifndef BOOTLOADER_BUILD #include "esp_system.h" @@ -84,9 +89,9 @@ void bootloader_random_enable(void) Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M) in early bootloader startup must have been made. */ +#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S); SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); -#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); #ifdef BOOTLOADER_BUILD @@ -97,6 +102,12 @@ void bootloader_random_enable(void) CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP); CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP); #elif CONFIG_IDF_TARGET_ESP32S2BETA + /* Disable IO1 digital function for random function. */ + PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U); + PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U); + PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U); + WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF); + SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); @@ -107,36 +118,42 @@ void bootloader_random_enable(void) //--[7:4] channel_sel: 10-->en_test //--[3:2] bit_width : 3-->12bit //--[1:0] atten : 1-->3dB attenuation +#if CONFIG_IDF_TARGET_ESP32 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); -#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); #elif CONFIG_IDF_TARGET_ESP32S2BETA + WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); + WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); + WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); + WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); #endif #if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); -#endif SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S); - SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */ -#if CONFIG_IDF_TARGET_ESP32 SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S); -#endif SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S); SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL); CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL); - SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); - SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S); - +#elif CONFIG_IDF_TARGET_ESP32S2BETA + SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S); + SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */ + SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S); + SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL); + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_SAR_SEL); + SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); + SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_TO_I2S); +#endif CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); @@ -179,7 +196,7 @@ void bootloader_random_disable(void) SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); #elif CONFIG_IDF_TARGET_ESP32S2BETA CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); - CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S); SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); #endif @@ -195,7 +212,9 @@ void bootloader_random_disable(void) periph_module_reset(PERIPH_I2S0_MODULE); #endif +#if CONFIG_IDF_TARGET_ESP32 /* Disable pull supply voltage to SAR ADC */ CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S); +#endif } diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 0d0d9ccf82..88b675cb08 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -39,6 +39,8 @@ #include "esp32s2beta/rom/uart.h" #include "esp32s2beta/rom/gpio.h" #include "esp32s2beta/rom/secure_boot.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #else #error "Unsupported IDF_TARGET" #endif @@ -376,7 +378,7 @@ int bootloader_utility_get_selected_boot_partition(const bootloader_state_t *bs) #endif // CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE #ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK - if(otadata[active_otadata].ota_state == ESP_OTA_IMG_VALID) { + if (otadata[active_otadata].ota_state == ESP_OTA_IMG_VALID) { update_anti_rollback(&bs->ota[boot_index]); } #endif // CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK @@ -439,7 +441,7 @@ static void set_actual_ota_seq(const bootloader_state_t *bs, int index) void bootloader_utility_load_boot_image_from_deep_sleep(void) { if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) { - esp_partition_pos_t* partition = bootloader_common_get_rtc_retain_mem_partition(); + esp_partition_pos_t *partition = bootloader_common_get_rtc_retain_mem_partition(); if (partition != NULL) { esp_image_metadata_t image_data; if (bootloader_load_image_no_verify(partition, &image_data) == ESP_OK) { @@ -613,9 +615,7 @@ static void load_image(const esp_image_metadata_t *image_data) #endif ESP_LOGI(TAG, "Disabling RNG early entropy source..."); -#if !CONFIG_IDF_ENV_FPGA bootloader_random_disable(); -#endif // copy loaded segments to RAM, set up caches for mapped segments, and start application unpack_load_app(image_data); @@ -687,10 +687,15 @@ static void set_cache_and_start_app( /* Clear the MMU entries that are already set up, so the new app only has the mappings it creates. */ +#if CONFIG_IDF_TARGET_ESP32 for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) { DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; } - +#elif CONFIG_IDF_TARGET_ESP32S2BETA + for (int i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { + FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; + } +#endif uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK; uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr); ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", @@ -698,8 +703,7 @@ static void set_cache_and_start_app( #if CONFIG_IDF_TARGET_ESP32 rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); #elif CONFIG_IDF_TARGET_ESP32S2BETA - rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, - 64, drom_page_count, 0); + rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); #endif ESP_LOGV(TAG, "rc=%d", rc); #if CONFIG_IDF_TARGET_ESP32 @@ -712,27 +716,17 @@ static void set_cache_and_start_app( irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count); #if CONFIG_IDF_TARGET_ESP32 rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count); - ESP_LOGV(TAG, "rc=%d", rc); #elif CONFIG_IDF_TARGET_ESP32S2BETA - uint32_t iram1_used = 0, irom0_used = 0; + uint32_t iram1_used = 0; if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) { iram1_used = 1; } - if (irom_load_addr + irom_size > IROM0_ADDRESS_LOW) { - irom0_used = 1; + if (iram1_used) { + rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1); + rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1); + REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1); } - if (iram1_used || irom0_used) { - rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1); - rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1); - REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_IRAM1); - if (irom0_used) { - rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, IROM0_ADDRESS_LOW, 0, 64, 64, 1); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0); - REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_IROM0); - } - } - rc = Cache_Ibus_MMU_Set(DPORT_MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); + rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); #endif ESP_LOGV(TAG, "rc=%d", rc); #if CONFIG_IDF_TARGET_ESP32 @@ -747,7 +741,7 @@ static void set_cache_and_start_app( (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 ); #elif CONFIG_IDF_TARGET_ESP32S2BETA - DPORT_REG_CLR_BIT( DPORT_PRO_ICACHE_CTRL1_REG, (DPORT_PRO_ICACHE_MASK_IRAM0) | (DPORT_PRO_ICACHE_MASK_IRAM1 & 0) | (DPORT_PRO_ICACHE_MASK_IROM0 & 0) | DPORT_PRO_ICACHE_MASK_DROM0 ); + REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0 ); #endif #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); diff --git a/components/bootloader_support/src/esp32s2beta/bootloader_esp32s2beta.c b/components/bootloader_support/src/esp32s2beta/bootloader_esp32s2beta.c index 066271e4f7..e0fa0ceb68 100644 --- a/components/bootloader_support/src/esp32s2beta/bootloader_esp32s2beta.c +++ b/components/bootloader_support/src/esp32s2beta/bootloader_esp32s2beta.c @@ -37,54 +37,41 @@ #include "soc/assist_debug_reg.h" #include "soc/cpu.h" #include "soc/dport_reg.h" +#include "soc/extmem_reg.h" #include "soc/rtc.h" #include "soc/spi_periph.h" +#include static const char *TAG = "boot.esp32s2"; - -#define FLASH_CLK_IO SPI_CLK_GPIO_NUM -#define FLASH_CS_IO SPI_CS0_GPIO_NUM -#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM -#define FLASH_SPID_IO SPI_D_GPIO_NUM -#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM -#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM - void bootloader_configure_spi_pins(int drv) { const uint32_t spiconfig = ets_efuse_get_spiconfig(); - if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) { - gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0); - gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0); - gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0); - gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0); - gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0); - gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0); - gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0); - gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0); - gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0); - //select pin function gpio - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIHD_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIWP_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, PIN_FUNC_GPIO); - // flash clock signal should come from IO MUX. - // set drive ability for clock - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, drv, FUN_DRV_S); - -#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64 - uint32_t flash_id = g_rom_flashchip.device_id; - if (flash_id == FLASH_ID_GD25LQ32C) { - // Set drive ability for 1.8v flash in 80Mhz. - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIHD_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIWP_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICS0_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIQ_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPID_U, FUN_DRV, 3, FUN_DRV_S); - } -#endif + uint8_t wp_pin = ets_efuse_get_wp_pad(); + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } else { + clk_gpio_num = spiconfig & 0x3f; + q_gpio_num = (spiconfig >> 6) & 0x3f; + d_gpio_num = (spiconfig >> 12) & 0x3f; + cs0_gpio_num = (spiconfig >> 18) & 0x3f; + hd_gpio_num = (spiconfig >> 24) & 0x3f; + wp_gpio_num = wp_pin; + } + gpio_pad_set_drv(clk_gpio_num, drv); + gpio_pad_set_drv(q_gpio_num, drv); + gpio_pad_set_drv(d_gpio_num, drv); + gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + gpio_pad_set_drv(wp_gpio_num, drv); } } @@ -97,7 +84,7 @@ static void bootloader_reset_mmu(void) /* normal ROM boot exits with DROM0 cache unmasked, but serial bootloader exits with it masked. */ - DPORT_REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0); + REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0); } static void update_flash_config(const esp_image_header_t *bootloader_hdr) @@ -201,7 +188,6 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) static void IRAM_ATTR bootloader_init_flash_configure(void) { - bootloader_flash_gpio_config(&bootloader_image_hdr); bootloader_flash_dummy_config(&bootloader_image_hdr); bootloader_flash_cs_timing_config(); } @@ -236,7 +222,7 @@ static void bootloader_init_uart_console(void) #else // CONFIG_ESP_CONSOLE_UART_NONE const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM; - uartAttach(); + uartAttach(NULL); ets_install_uart_printf(); // Wait for UART FIFO to be empty. @@ -329,7 +315,7 @@ static void bootloader_check_wdt_reset(void) rst_reas[0] = rtc_get_reset_reason(0); if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET || - rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) { + rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) { ESP_LOGW(TAG, "PRO CPU has been reset by WDT."); wdt_rst = 1; } @@ -352,9 +338,15 @@ void abort(void) } } +static void bootloader_super_wdt_auto_feed(void) +{ + REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN); +} + esp_err_t bootloader_init(void) { esp_err_t ret = ESP_OK; + bootloader_super_wdt_auto_feed(); // protect memory region cpu_configure_region_protection(); /* check that static RAM is after the stack */ diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index 8a22e8209c..6d81f1633b 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -24,11 +24,11 @@ #include "bootloader_util.h" #include "bootloader_common.h" #if CONFIG_IDF_TARGET_ESP32 -#include -#include +#include "esp32/rom/rtc.h" +#include "esp32/rom/secure_boot.h" #elif CONFIG_IDF_TARGET_ESP32S2BETA -#include -#include +#include "esp32s2beta/rom/rtc.h" +#include "esp32s2beta/rom/secure_boot.h" #endif /* Checking signatures as part of verifying images is necessary: @@ -107,7 +107,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_ bool do_verify = (mode == ESP_IMAGE_LOAD) || (mode == ESP_IMAGE_VERIFY) || (mode == ESP_IMAGE_VERIFY_SILENT); #else bool do_load = false; // Can't load the image in app mode - bool do_verify = true; // In app mode is avalible only verify mode + bool do_verify = true; // In app mode is available only verify mode #endif bool silent = (mode == ESP_IMAGE_VERIFY_SILENT); esp_err_t err = ESP_OK; @@ -198,13 +198,13 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_ } /* For secure boot on ESP32, we don't calculate SHA or verify signautre on bootloaders. - For ESP32S2, we do verify signature on botoloaders which includes the SHA calculation. + For ESP32S2, we do verify signature on bootloader which includes the SHA calculation. (For non-secure boot, we don't verify any SHA-256 hash appended to the bootloader because esptool.py may have rewritten the header - rely on esptool.py having verified the bootloader at flashing time, instead.) */ bool verify_sha; -#if defined(CONFIG_SECURE_BOOT_ENABLED) && defined(CONFIG_IDF_TARGET_ESP32S2BETA) +#if CONFIG_SECURE_BOOT_ENABLED && CONFIG_IDF_TARGET_ESP32S2BETA verify_sha = true; #else // ESP32, or ESP32S2 without secure boot enabled verify_sha = (data->start_addr != ESP_BOOTLOADER_OFFSET); @@ -378,7 +378,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme #ifdef BOOTLOADER_BUILD /* Before loading segment, check it doesn't clobber bootloader RAM. */ - if (do_load) { + if (do_load && data_len > 0) { const intptr_t load_end = load_addr + data_len; if (load_end < (intptr_t) SOC_DRAM_HIGH) { /* Writing to DRAM */ @@ -638,7 +638,7 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han bootloader_munmap(simple_hash); } -#ifdef CONFIG_IDF_TARGET_ESP32S2BETA +#if CONFIG_IDF_TARGET_ESP32S2BETA // Pad to 4096 byte sector boundary if (end % FLASH_SECTOR_SIZE != 0) { uint32_t pad_len = FLASH_SECTOR_SIZE - (end % FLASH_SECTOR_SIZE); diff --git a/components/driver/periph_ctrl.c b/components/driver/periph_ctrl.c index d448a914bf..2b7e561ff8 100644 --- a/components/driver/periph_ctrl.c +++ b/components/driver/periph_ctrl.c @@ -11,14 +11,14 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#include +#include "esp_types.h" +#include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/xtensa_api.h" #include "soc/dport_reg.h" #include "soc/syscon_reg.h" #include "driver/periph_ctrl.h" -#include "sdkconfig.h" static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED; @@ -116,8 +116,6 @@ static uint32_t get_clk_en_mask(periph_module_t periph) return DPORT_SPI2_DMA_CLK_EN; case PERIPH_SPI3_DMA_MODULE: return DPORT_SPI3_DMA_CLK_EN; - case PERIPH_SPI_SHARED_DMA_MODULE: - return DPORT_SPI_SHARED_DMA_CLK_EN; #endif case PERIPH_SDMMC_MODULE: return DPORT_WIFI_CLK_SDIO_HOST_EN; @@ -220,8 +218,6 @@ static uint32_t get_rst_en_mask(periph_module_t periph, bool enable) return DPORT_SPI2_DMA_RST; case PERIPH_SPI3_DMA_MODULE: return DPORT_SPI3_DMA_RST; - case PERIPH_SPI_SHARED_DMA_MODULE: - return DPORT_SPI_SHARED_DMA_RST; #endif case PERIPH_SDMMC_MODULE: return DPORT_SDIO_HOST_RST; diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index d269cba95d..4792639a18 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -105,8 +105,8 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host) static inline uint32_t get_dma_periph(int dma_chan) { -#ifdef CONFIG_IDF_TARGET_ESP32S2BETA - if (dma_chan==1) { +#if CONFIG_IDF_TARGET_ESP32S2BETA + if (dma_chan == 1) { return PERIPH_SPI2_DMA_MODULE; } else if (dma_chan==2) { return PERIPH_SPI3_DMA_MODULE; @@ -116,7 +116,7 @@ static inline uint32_t get_dma_periph(int dma_chan) abort(); return -1; } -#elif defined(CONFIG_IDF_TARGET_ESP32) +#elif CONFIG_IDF_TARGET_ESP32 return PERIPH_SPI_DMA_MODULE; #endif } @@ -357,12 +357,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf } //Select DMA channel. -#ifdef CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); -#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA) - if (dma_chan==VSPI_HOST) { - DPORT_SET_PERI_REG_MASK(DPORT_SPI_DMA_CHAN_SEL_REG, DPORT_SPI_SHARED_DMA_SEL_M); - } #endif if (flags_o) *flags_o = temp_flag; diff --git a/components/driver/test/include/test/test_common_spi.h b/components/driver/test/include/test/test_common_spi.h index 469004975f..29521ba666 100644 --- a/components/driver/test/include/test/test_common_spi.h +++ b/components/driver/test/include/test/test_common_spi.h @@ -109,7 +109,7 @@ #define PSET_NAME_LEN 30 ///< length of each param set name //test low frequency, high frequency until freq limit for worst case (both GPIO) -#define TEST_FREQ_DEFAULT(){\ +#define TEST_FREQ_DEFAULT(){ \ 1*1000*1000, \ SPI_MASTER_FREQ_8M , \ SPI_MASTER_FREQ_9M , \ @@ -251,4 +251,4 @@ void master_free_device_bus(spi_device_handle_t spi); //use this function to fix the output source when assign multiple funcitons to a same pin void spitest_gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx); -#endif //_TEST_COMMON_SPI_H_ \ No newline at end of file +#endif //_TEST_COMMON_SPI_H_ diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/test_spi_param.c index 20a0811ccf..dd578087b8 100644 --- a/components/driver/test/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -1046,4 +1046,4 @@ spitest_param_set_t mode_conf[] = { }; TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "") -#endif \ No newline at end of file +#endif diff --git a/components/efuse/src/esp32s2beta/esp_efuse_utility.c b/components/efuse/src/esp32s2beta/esp_efuse_utility.c index d741384f54..e1e238da1e 100644 --- a/components/efuse/src/esp32s2beta/esp_efuse_utility.c +++ b/components/efuse/src/esp32s2beta/esp_efuse_utility.c @@ -30,8 +30,8 @@ extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK]; /*Range addresses to read blocks*/ const esp_efuse_range_addr_t range_read_addr_blocks[] = { {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT - {EFUSE_RD_MAC_SPI_8M_0_REG, EFUSE_RD_MAC_SPI_8M_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M - {EFUSE_RD_SYS_DATA0_REG, EFUSE_RD_SYS_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M + {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 @@ -39,24 +39,24 @@ const esp_efuse_range_addr_t range_read_addr_blocks[] = { {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 - {EFUSE_RD_KEY6_DATA0_REG, EFUSE_RD_KEY6_DATA7_REG} // range address of EFUSE_BLK10 KEY6 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 }; static uint32_t write_mass_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; /*Range addresses to write blocks (it is not real regs, it is buffer) */ const esp_efuse_range_addr_t range_write_addr_blocks[] = { - {(uint32_t)&write_mass_blocks[EFUSE_BLK0][0], (uint32_t)&write_mass_blocks[EFUSE_BLK0][5]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK1][0], (uint32_t)&write_mass_blocks[EFUSE_BLK1][5]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK2][0], (uint32_t)&write_mass_blocks[EFUSE_BLK2][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK3][0], (uint32_t)&write_mass_blocks[EFUSE_BLK3][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK4][0], (uint32_t)&write_mass_blocks[EFUSE_BLK4][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK5][0], (uint32_t)&write_mass_blocks[EFUSE_BLK5][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK6][0], (uint32_t)&write_mass_blocks[EFUSE_BLK6][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK7][0], (uint32_t)&write_mass_blocks[EFUSE_BLK7][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK8][0], (uint32_t)&write_mass_blocks[EFUSE_BLK8][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK9][0], (uint32_t)&write_mass_blocks[EFUSE_BLK9][7]}, - {(uint32_t)&write_mass_blocks[EFUSE_BLK10][0], (uint32_t)&write_mass_blocks[EFUSE_BLK10][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, }; #ifndef CONFIG_EFUSE_VIRTUAL @@ -65,7 +65,7 @@ static esp_err_t esp_efuse_set_timing(void) { uint32_t clock = esp_clk_apb_freq(); // ets_efuse_set_timing(clock); - uint32_t clk_div, power_on; + uint32_t clk_div, power_on; //uint32_t power_off; // Support for 7.2.3 chip uint32_t tsup_a = 1, thp_a = 1, tpgm, tpgm_inact; uint32_t tsur_a = 1, thr_a = 1, trd; @@ -153,7 +153,7 @@ void esp_efuse_utility_burn_efuses(void) // After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. // This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. -// The RS coding scheme does not require data changes for the encoded data. esp32s2beta has special registers for this. +// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. // They will be filled during the burn operation. esp_err_t esp_efuse_utility_apply_new_coding_scheme() { @@ -165,7 +165,7 @@ esp_err_t esp_efuse_utility_apply_new_coding_scheme() int num_reg = 0; for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { if (esp_efuse_utility_read_reg(num_block, num_reg)) { - ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); return ESP_ERR_CODING; } } diff --git a/components/esp32s2beta/Kconfig b/components/esp32s2beta/Kconfig index 70754ea014..cc68c99058 100644 --- a/components/esp32s2beta/Kconfig +++ b/components/esp32s2beta/Kconfig @@ -27,10 +27,13 @@ menu "ESP32S2-specific" choice ESP32S2_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" - default ESP32S2_DEFAULT_CPU_FREQ_160 + default ESP32S2_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA + default ESP32S2_DEFAULT_CPU_FREQ_FPGA if IDF_ENV_FPGA help CPU frequency to be set on application startup. + config ESP32S2_DEFAULT_CPU_FREQ_FPGA + bool "FPGA" config ESP32S2_DEFAULT_CPU_FREQ_80 bool "80 MHz" config ESP32S2_DEFAULT_CPU_FREQ_160 @@ -41,6 +44,7 @@ menu "ESP32S2-specific" config ESP32S2_DEFAULT_CPU_FREQ_MHZ int + default 40 if IDF_ENV_FPGA default 80 if ESP32S2_DEFAULT_CPU_FREQ_80 default 160 if ESP32S2_DEFAULT_CPU_FREQ_160 default 240 if ESP32S2_DEFAULT_CPU_FREQ_240 @@ -61,18 +65,6 @@ menu "ESP32S2-specific" bool "16KB" endchoice - choice ESP32S2_INSTRUCTION_CACHE_WAYS - prompt "Instruction cache associated ways" - default ESP32S2_INSTRUCTION_CACHE_8WAYS - help - Instruction cache associated ways to be set on application startup. - - config ESP32S2_INSTRUCTION_CACHE_4WAYS - bool "4 ways" - config ESP32S2_INSTRUCTION_CACHE_8WAYS - bool "8 ways" - endchoice - choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE prompt "Instruction cache line size" default ESP32S2_INSTRUCTION_CACHE_LINE_32B @@ -83,8 +75,6 @@ menu "ESP32S2-specific" bool "16 Bytes" config ESP32S2_INSTRUCTION_CACHE_LINE_32B bool "32 Bytes" - config ESP32S2_INSTRUCTION_CACHE_LINE_64B - bool "64 Bytes" endchoice choice ESP32S2_DATA_CACHE_SIZE @@ -103,18 +93,6 @@ menu "ESP32S2-specific" bool "16KB" endchoice - choice ESP32S2_DATA_CACHE_ASSOCIATED_WAYS - prompt "Data cache associated ways" - default ESP32S2_DATA_CACHE_8WAYS - help - Data cache associated ways to be set on application startup. - - config ESP32S2_DATA_CACHE_4WAYS - bool "4 ways" - config ESP32S2_DATA_CACHE_8WAYS - bool "8 ways" - endchoice - choice ESP32S2_DATA_CACHE_LINE_SIZE prompt "Data cache line size" default ESP32S2_DATA_CACHE_LINE_32B @@ -125,18 +103,8 @@ menu "ESP32S2-specific" bool "16 Bytes" config ESP32S2_DATA_CACHE_LINE_32B bool "32 Bytes" - config ESP32S2_DATA_CACHE_LINE_64B - bool "64 Bytes" endchoice - config ESP32S2_RODATA_USE_DATA_CACHE - depends on ESP32S2_DATA_CACHE_8KB || ESP32S2_DATA_CACHE_16KB - bool "Use data cache rather than instruction cache to access read only data" - default "n" - help - If enabled, CPU will access rodata through data cache, which will reduce the overload - of instruction cache, however will increase the overload of data cache. - config ESP32S2_INSTRUCTION_CACHE_WRAP bool "Enable instruction cache wrap" default "n" @@ -184,6 +152,37 @@ menu "ESP32S2-specific" default 4194304 if SPIRAM_TYPE_ESPPSRAM32 default 8388608 if SPIRAM_TYPE_ESPPSRAM64 default 0 + menu "PSRAM clock and cs IO for ESP32S2" + depends on ESP32S2_SPIRAM_SUPPORT + config DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 30 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. + + config DEFAULT_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 26 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. + endmenu + config SPIRAM_SPIWP_SD3_PIN + int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)" + depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT + range 0 33 + default 28 + help + This value is ignored unless flash mode is set to DIO or DOUT and the SPI flash pins have been + overriden by setting the eFuses SPI_PAD_CONFIG_xxx. + + Different from esp32 chip, on esp32s2, the WP pin would also be defined in efuse. This value would only + be used if the WP pin recorded in efuse SPI_PAD_CONFIG_xxx is invalid. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set as the value configured in + bootloader. + config SPIRAM_FETCH_INSTRUCTIONS bool "Cache fetch instructions from SPI RAM" diff --git a/components/esp32s2beta/cache_err_int.c b/components/esp32s2beta/cache_err_int.c index 914be97b85..84ade820e4 100644 --- a/components/esp32s2beta/cache_err_int.c +++ b/components/esp32s2beta/cache_err_int.c @@ -27,6 +27,7 @@ #include "esp_err.h" #include "esp_intr_alloc.h" #include "esp_attr.h" +#include "soc/extmem_reg.h" #include "soc/dport_reg.h" #include "soc/periph_defs.h" #include "sdkconfig.h" @@ -52,17 +53,25 @@ void esp_cache_err_int_init(void) // interrupt is connected to PRO CPU and invalid access happens on the APP // CPU. - DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_IA_INT_EN_REG, - DPORT_MMU_ENTRY_FAULT_INT_ENA | - DPORT_DCACHE_REJECT_INT_ENA | - DPORT_DCACHE_WRITE_FLASH_INT_ENA | - DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA | - DPORT_DC_SYNC_SIZE_FAULT_INT_ENA | - DPORT_ICACHE_REJECT_INT_ENA | - DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA | - DPORT_IC_SYNC_SIZE_FAULT_INT_ENA | - DPORT_CACHE_DBG_INT_CLR | - DPORT_CACHE_DBG_EN); + DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_CLR_REG, + EXTMEM_MMU_ENTRY_FAULT_INT_CLR | + EXTMEM_DCACHE_REJECT_INT_CLR | + EXTMEM_DCACHE_WRITE_FLASH_INT_CLR | + EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR | + EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR | + EXTMEM_ICACHE_REJECT_INT_CLR | + EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR | + EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR); + DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_ENA_REG, + EXTMEM_MMU_ENTRY_FAULT_INT_ENA | + EXTMEM_DCACHE_REJECT_INT_ENA | + EXTMEM_DCACHE_WRITE_FLASH_INT_ENA | + EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA | + EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA | + EXTMEM_ICACHE_REJECT_INT_ENA | + EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA | + EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA | + EXTMEM_CACHE_DBG_EN); ESP_INTR_ENABLE(ETS_CACHEERR_INUM); } diff --git a/components/esp32s2beta/clk.c b/components/esp32s2beta/clk.c index 250c879d78..94e8578e26 100644 --- a/components/esp32s2beta/clk.c +++ b/components/esp32s2beta/clk.c @@ -48,8 +48,7 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk); // g_ticks_us defined in ROMs for PRO CPU extern uint32_t g_ticks_per_us_pro; - -static const char* TAG = "clk"; +static const char *TAG = "clk"; void esp_clk_init(void) @@ -89,20 +88,20 @@ void esp_clk_init(void) uint32_t freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ; rtc_cpu_freq_t freq = RTC_CPU_FREQ_80M; - switch(freq_mhz) { - case 240: - freq = RTC_CPU_FREQ_240M; - break; - case 160: - freq = RTC_CPU_FREQ_160M; - break; - case 80: - freq = RTC_CPU_FREQ_80M; - break; - default: - freq_mhz = 80; - freq = RTC_CPU_FREQ_80M; - break; + switch (freq_mhz) { + case 240: + freq = RTC_CPU_FREQ_240M; + break; + case 160: + freq = RTC_CPU_FREQ_160M; + break; + case 80: + freq = RTC_CPU_FREQ_80M; + break; + default: + freq_mhz = 80; + freq = RTC_CPU_FREQ_80M; + break; } // Wait for UART TX to finish, otherwise some UART output will be lost @@ -152,14 +151,14 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk) ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up"); rtc_clk_32k_enable(true); cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES); - if(cal_val == 0 || cal_val < 15000000L){ + if (cal_val == 0 || cal_val < 15000000L) { ESP_EARLY_LOGE(TAG, "RTC: Not found External 32 kHz XTAL. Switching to Internal 150 kHz RC chain"); slow_clk = RTC_SLOW_FREQ_RTC; changing_clock_to_150k = true; } } rtc_clk_slow_freq_set(slow_clk); - if (changing_clock_to_150k == true && wait > 1){ + if (changing_clock_to_150k == true && wait > 1) { // This helps when there are errors when switching the clock from External 32 kHz XTAL to Internal 150 kHz RC chain. rtc_clk_32k_enable(false); uint32_t min_bootstrap = 5; // Min bootstrapping for continue switching the clock. @@ -207,51 +206,50 @@ void esp_perip_clk_init(void) /* For reason that only reset CPU, do not disable the clocks * that have been enabled before reset. */ - if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET) - ) { + if (rst_reas[0] >= TG0WDT_CPU_RESET && + rst_reas[0] <= TG0WDT_CPU_RESET && + rst_reas[0] != RTCWDT_BROWN_OUT_RESET) { common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG); - hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG); + hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG); wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG); - } - else { + } else { common_perip_clk = DPORT_WDG_CLK_EN | - DPORT_I2S0_CLK_EN | + DPORT_I2S0_CLK_EN | #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - DPORT_UART_CLK_EN | + DPORT_UART_CLK_EN | #endif #if CONFIG_ESP_CONSOLE_UART_NUM != 1 - DPORT_UART1_CLK_EN | + DPORT_UART1_CLK_EN | #endif - DPORT_USB_CLK_EN | - DPORT_SPI2_CLK_EN | - DPORT_I2C_EXT0_CLK_EN | - DPORT_UHCI0_CLK_EN | - DPORT_RMT_CLK_EN | - DPORT_PCNT_CLK_EN | - DPORT_LEDC_CLK_EN | - DPORT_TIMERGROUP1_CLK_EN | - DPORT_SPI3_CLK_EN | - DPORT_SPI4_CLK_EN | - DPORT_PWM0_CLK_EN | - DPORT_CAN_CLK_EN | - DPORT_PWM1_CLK_EN | - DPORT_I2S1_CLK_EN | - DPORT_SPI2_DMA_CLK_EN | - DPORT_SPI3_DMA_CLK_EN | - DPORT_PWM2_CLK_EN | - DPORT_PWM3_CLK_EN; - common_perip_clk1 = DPORT_SPI_SHARED_DMA_CLK_EN; - hwcrypto_perip_clk = DPORT_PERI_EN_AES | - DPORT_PERI_EN_SHA | - DPORT_PERI_EN_RSA | - DPORT_PERI_EN_SECUREBOOT; + DPORT_USB_CLK_EN | + DPORT_SPI2_CLK_EN | + DPORT_I2C_EXT0_CLK_EN | + DPORT_UHCI0_CLK_EN | + DPORT_RMT_CLK_EN | + DPORT_PCNT_CLK_EN | + DPORT_LEDC_CLK_EN | + DPORT_TIMERGROUP1_CLK_EN | + DPORT_SPI3_CLK_EN | + DPORT_SPI4_CLK_EN | + DPORT_PWM0_CLK_EN | + DPORT_CAN_CLK_EN | + DPORT_PWM1_CLK_EN | + DPORT_I2S1_CLK_EN | + DPORT_SPI2_DMA_CLK_EN | + DPORT_SPI3_DMA_CLK_EN | + DPORT_PWM2_CLK_EN | + DPORT_PWM3_CLK_EN; + common_perip_clk1 = 0; + hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN | + DPORT_CRYPTO_SHA_CLK_EN | + DPORT_CRYPTO_RSA_CLK_EN; wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN | - DPORT_WIFI_CLK_BT_EN_M | - DPORT_WIFI_CLK_UNUSED_BIT5 | - DPORT_WIFI_CLK_UNUSED_BIT12 | - DPORT_WIFI_CLK_SDIOSLAVE_EN | - DPORT_WIFI_CLK_SDIO_HOST_EN | - DPORT_WIFI_CLK_EMAC_EN; + DPORT_WIFI_CLK_BT_EN_M | + DPORT_WIFI_CLK_UNUSED_BIT5 | + DPORT_WIFI_CLK_UNUSED_BIT12 | + DPORT_WIFI_CLK_SDIOSLAVE_EN | + DPORT_WIFI_CLK_SDIO_HOST_EN | + DPORT_WIFI_CLK_EMAC_EN; } //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. @@ -274,7 +272,7 @@ void esp_perip_clk_init(void) DPORT_I2S1_CLK_EN | DPORT_SPI2_DMA_CLK_EN | DPORT_SPI3_DMA_CLK_EN; - common_perip_clk1 = DPORT_SPI_SHARED_DMA_CLK_EN; + common_perip_clk1 = 0; /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, * the current is not reduced when disable I2S clock. @@ -290,8 +288,8 @@ void esp_perip_clk_init(void) DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1); /* Disable hardware crypto clocks. */ - DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk); - DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk); /* Disable WiFi/BT/SDIO clocks. */ DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); diff --git a/components/esp32s2beta/cpu_start.c b/components/esp32s2beta/cpu_start.c index 1c8a19607b..024793fc5c 100644 --- a/components/esp32s2beta/cpu_start.c +++ b/components/esp32s2beta/cpu_start.c @@ -78,7 +78,7 @@ void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attri void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn)); static void do_global_ctors(void); -static void main_task(void* args); +static void main_task(void *args); extern void app_main(void); extern esp_err_t esp_pthread_init(void); @@ -91,14 +91,16 @@ extern void (*__init_array_start)(void); extern void (*__init_array_end)(void); extern volatile int port_xSchedulerRunning[2]; -static const char* TAG = "cpu_start"; +static const char *TAG = "cpu_start"; -struct object { long placeholder[ 10 ]; }; +struct object { + long placeholder[ 10 ]; +}; void __register_frame_info (const void *begin, struct object *ob); extern char __eh_frame[]; //If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false. -static bool s_spiram_okay=true; +static bool s_spiram_okay = true; /* * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized, @@ -134,19 +136,14 @@ void IRAM_ATTR call_start_cpu0(void) } /* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */ -extern void esp_config_instruction_cache_mode(void); + extern void esp_config_instruction_cache_mode(void); esp_config_instruction_cache_mode(); - /* copy MMU table from ICache to DCache, so we can use DCache to access rodata later. */ -#if CONFIG_ESP32S2_RODATA_USE_DATA_CACHE - MMU_Drom0_I2D_Copy(); -#endif - /* If we need use SPIRAM, we should use data cache, or if we want to access rodata, we also should use data cache. Configure the mode of data : cache size, cache associated ways, cache line size. Enable data cache, so if we don't use SPIRAM, it just works. */ -#if CONFIG_SPIRAM_BOOT_INIT || CONFIG_ESP32S2_RODATA_USE_DATA_CACHE -extern void esp_config_data_cache_mode(void); +#if CONFIG_SPIRAM_BOOT_INIT + extern void esp_config_data_cache_mode(void); esp_config_data_cache_mode(); Cache_Enable_DCache(0); #endif @@ -167,18 +164,12 @@ extern void esp_config_data_cache_mode(void); } #endif - /* Start to use data cache to access rodata. */ -#if CONFIG_ESP32S2_RODATA_USE_DATA_CACHE -extern void esp_switch_rodata_to_dcache(void); - esp_switch_rodata_to_dcache(); -#endif - ESP_EARLY_LOGI(TAG, "Pro cpu up."); ESP_EARLY_LOGI(TAG, "Single core mode"); #if CONFIG_SPIRAM_MEMTEST if (s_spiram_okay) { - bool ext_ram_ok=esp_spiram_test(); + bool ext_ram_ok = esp_spiram_test(); if (!ext_ram_ok) { ESP_EARLY_LOGE(TAG, "External RAM failed memory test!"); abort(); @@ -187,23 +178,23 @@ extern void esp_switch_rodata_to_dcache(void); #endif #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS -extern void esp_spiram_enable_instruction_access(void); + extern void esp_spiram_enable_instruction_access(void); esp_spiram_enable_instruction_access(); #endif #if CONFIG_SPIRAM_RODATA -extern void esp_spiram_enable_rodata_access(void); + extern void esp_spiram_enable_rodata_access(void); esp_spiram_enable_rodata_access(); #endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP -uint32_t icache_wrap_enable = 0,dcache_wrap_enable = 0; + uint32_t icache_wrap_enable = 0, dcache_wrap_enable = 0; #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP icache_wrap_enable = 1; #endif #if CONFIG_ESP32S2_DATA_CACHE_WRAP dcache_wrap_enable = 1; #endif -extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable); + extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_wrap_enable); esp_enable_cache_wrap(icache_wrap_enable, dcache_wrap_enable); #endif @@ -236,13 +227,13 @@ void start_cpu0_default(void) if (s_spiram_okay) { #if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) - esp_err_t r=esp_spiram_add_to_heapalloc(); + esp_err_t r = esp_spiram_add_to_heapalloc(); if (r != ESP_OK) { ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!"); abort(); } #if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL - r=esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL); + r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL); if (r != ESP_OK) { ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool!"); abort(); @@ -284,14 +275,14 @@ void start_cpu0_default(void) esp_vfs_dev_uart_register(); esp_reent_init(_GLOBAL_REENT); #ifndef CONFIG_ESP_CONSOLE_UART_NONE - const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM); + const char *default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_ESP_CONSOLE_UART_NUM); _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r"); _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w"); _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w"); #else - _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin; - _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout; - _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr; + _GLOBAL_REENT->_stdin = (FILE *) &__sf_fake_stdin; + _GLOBAL_REENT->_stdout = (FILE *) &__sf_fake_stdout; + _GLOBAL_REENT->_stderr = (FILE *) &__sf_fake_stderr; #endif esp_timer_init(); esp_set_time_from_rtc(); @@ -330,8 +321,8 @@ void start_cpu0_default(void) rtc_cpu_freq_t max_freq; rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ, &max_freq); esp_pm_config_esp32_t cfg = { - .max_cpu_freq = max_freq, - .min_cpu_freq = RTC_CPU_FREQ_XTAL + .max_cpu_freq = max_freq, + .min_cpu_freq = RTC_CPU_FREQ_XTAL }; esp_pm_configure(&cfg); #endif //CONFIG_PM_DFS_INIT_AUTO @@ -342,8 +333,8 @@ void start_cpu0_default(void) #endif portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main", - ESP_TASK_MAIN_STACK, NULL, - ESP_TASK_MAIN_PRIO, NULL, 0); + ESP_TASK_MAIN_STACK, NULL, + ESP_TASK_MAIN_PRIO, NULL, 0); assert(res == pdTRUE); ESP_LOGI(TAG, "Starting scheduler on PRO CPU."); vTaskStartScheduler(); @@ -370,7 +361,7 @@ static void do_global_ctors(void) } } -static void main_task(void* args) +static void main_task(void *args) { //Enable allocation in region where the startup stacks were located. heap_caps_enable_nonos_stack_heaps(); @@ -385,7 +376,7 @@ static void main_task(void* args) //Add IDLE 0 to task wdt #ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0); - if(idle_0 != NULL){ + if (idle_0 != NULL) { ESP_ERROR_CHECK(esp_task_wdt_add(idle_0)); } #endif diff --git a/components/esp32s2beta/ld/esp32s2beta.ld b/components/esp32s2beta/ld/esp32s2beta.ld index c3f877f609..4b55693d17 100644 --- a/components/esp32s2beta/ld/esp32s2beta.ld +++ b/components/esp32s2beta/ld/esp32s2beta.ld @@ -1,18 +1,11 @@ -/* ESP32S2Beta Linker Script Memory Layout +/* ESP32S2 Linker Script Memory Layout - This file describes the memory layout (memory blocks) as virtual - memory addresses. + This file describes the memory layout (memory blocks) by virtual memory addresses. - esp32.common.ld contains output sections to link compiler output - into these memory blocks. + This linker script is passed through the C preprocessor to include configuration options. - *** - - This linker script is passed through the C preprocessor to include - configuration options. - - Please use preprocessor features sparingly! Restrict - to simple macros with numeric values, and/or #if/#endif blocks. + Please use preprocessor features sparingly! + Restrict to simple macros with numeric values, and/or #if/#endif blocks. */ #include "sdkconfig.h" @@ -33,7 +26,7 @@ #define RAM_IRAM_START 0x40020000 #define RAM_DRAM_START 0x3FFB0000 -#define DATA_RAM_END 0x3FFF2000 /* start address of bootloader */ +#define DATA_RAM_END 0x3FFF0000 /* start address of bootloader */ #define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + CONFIG_ESP32S2_DATA_CACHE_SIZE) @@ -55,7 +48,7 @@ MEMORY /* Even though the segment name is iram, it is actually mapped to flash */ - iram0_2_seg (RX) : org = 0x40080020, len = 0xb80000-0x20 + iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20 /* (0x20 offset above is a convenience for the app binary image generation. @@ -66,11 +59,7 @@ MEMORY */ - /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. - - Enabling Bluetooth & Trace Memory features in menuconfig will decrease - the amount of RAM available. - */ + /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */ dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE /* Flash mapped constant data */ diff --git a/components/esp32s2beta/ld/esp32s2beta.peripherals.ld b/components/esp32s2beta/ld/esp32s2beta.peripherals.ld index cb0ffaf361..1df103fb30 100644 --- a/components/esp32s2beta/ld/esp32s2beta.peripherals.ld +++ b/components/esp32s2beta/ld/esp32s2beta.peripherals.ld @@ -1,6 +1,6 @@ PROVIDE ( UART0 = 0x3f400000 ); -PROVIDE ( SPIMEM1 = 0x3f402000 ); -PROVIDE ( SPIMEM0 = 0x3f403000 ); +PROVIDE ( SPIMEM1 = 0x3f402000 ); +PROVIDE ( SPIMEM0 = 0x3f403000 ); PROVIDE ( GPIO = 0x3f404000 ); PROVIDE ( SIGMADELTA = 0x3f404f00 ); PROVIDE ( RTCCNTL = 0x3f408000 ); @@ -13,16 +13,17 @@ PROVIDE ( I2C0 = 0x3f413000 ); PROVIDE ( UHCI0 = 0x3f414000 ); PROVIDE ( HOST = 0x3f415000 ); PROVIDE ( RMT = 0x3f416000 ); -PROVIDE ( RMTMEM = 0x3f416400 ); +PROVIDE ( RMTMEM = 0x3f416800 ); PROVIDE ( PCNT = 0x3f417000 ); PROVIDE ( SLC = 0x3f418000 ); PROVIDE ( LEDC = 0x3f419000 ); +PROVIDE ( MCP = 0x3f4c3000 ); PROVIDE ( TIMERG0 = 0x3f41F000 ); -PROVIDE ( TIMERG1 = 0x3f420000 ); -PROVIDE ( GPSPI2 = 0x3f424000 ); -PROVIDE ( GPSPI3 = 0x3f425000 ); +PROVIDE ( TIMERG1 = 0x3f420000 ); +PROVIDE ( GPSPI2 = 0x3f424000 ); +PROVIDE ( GPSPI3 = 0x3f425000 ); PROVIDE ( SYSCON = 0x3f426000 ); PROVIDE ( I2C1 = 0x3f427000 ); -PROVIDE ( GPSPI4 = 0x3f437000 ); - +PROVIDE ( CAN = 0x3f42B000 ); +PROVIDE ( APB_SARADC = 0x3f440000 ); PROVIDE ( ToBeCleanedUpBelow = 0x00000000 ); diff --git a/components/esp32s2beta/panic.c b/components/esp32s2beta/panic.c index 512bcfeb1f..292aa2bbe9 100644 --- a/components/esp32s2beta/panic.c +++ b/components/esp32s2beta/panic.c @@ -25,6 +25,8 @@ #include "soc/uart_reg.h" #include "soc/io_mux_reg.h" #include "soc/dport_reg.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #include "soc/rtc_cntl_reg.h" #include "soc/timer_group_struct.h" #include "soc/timer_group_reg.h" @@ -214,35 +216,34 @@ static inline void printCacheError(void) { uint32_t vaddr = 0, size = 0; uint32_t status[2]; - status[0] = REG_READ(DPORT_CACHE_DBG_STATUS0_REG); - status[1] = REG_READ(DPORT_CACHE_DBG_STATUS1_REG); + status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG); + status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG); for (int i = 0; i < 32; i++) { - switch (status[0] & BIT(i)) - { - case DPORT_IC_SYNC_SIZE_FAULT_ST: - vaddr = REG_READ(DPORT_PRO_ICACHE_MEM_SYNC0_REG); - size = REG_READ(DPORT_PRO_ICACHE_MEM_SYNC1_REG); + switch (status[0] & BIT(i)) { + case EXTMEM_IC_SYNC_SIZE_FAULT_ST: + vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG); + size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG); panicPutStr("Icache sync parameter configuration error, the error address and size is 0x"); panicPutHex(vaddr); panicPutStr("(0x"); panicPutHex(size); panicPutStr(")\r\n"); break; - case DPORT_IC_PRELOAD_SIZE_FAULT_ST: - vaddr = REG_READ(DPORT_PRO_ICACHE_PRELOAD_ADDR_REG); - size = REG_READ(DPORT_PRO_ICACHE_PRELOAD_SIZE_REG); + case EXTMEM_IC_PRELOAD_SIZE_FAULT_ST: + vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG); + size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG); panicPutStr("Icache preload parameter configuration error, the error address and size is 0x"); panicPutHex(vaddr); panicPutStr("(0x"); panicPutHex(size); panicPutStr(")\r\n"); break; - case DPORT_ICACHE_REJECT_ST: - vaddr = REG_READ(DPORT_PRO_ICACHE_REJECT_VADDR_REG); + case EXTMEM_ICACHE_REJECT_ST: + vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG); panicPutStr("Icache reject error occurred while accessing the address 0x"); panicPutHex(vaddr); - if (REG_READ(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG) & DPORT_MMU_INVALID) { + if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) { panicPutStr(" (invalid mmu entry)"); } panicPutStr("\r\n"); @@ -250,45 +251,44 @@ static inline void printCacheError(void) default: break; } - switch (status[1] & BIT(i)) - { - case DPORT_DC_SYNC_SIZE_FAULT_ST: - vaddr = REG_READ(DPORT_PRO_DCACHE_MEM_SYNC0_REG); - size = REG_READ(DPORT_PRO_DCACHE_MEM_SYNC1_REG); + switch (status[1] & BIT(i)) { + case EXTMEM_DC_SYNC_SIZE_FAULT_ST: + vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG); + size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG); panicPutStr("Dcache sync parameter configuration error, the error address and size is 0x"); panicPutHex(vaddr); panicPutStr("(0x"); panicPutHex(size); panicPutStr(")\r\n"); break; - case DPORT_DC_PRELOAD_SIZE_FAULT_ST: - vaddr = REG_READ(DPORT_PRO_DCACHE_PRELOAD_ADDR_REG); - size = REG_READ(DPORT_PRO_DCACHE_PRELOAD_SIZE_REG); + case EXTMEM_DC_PRELOAD_SIZE_FAULT_ST: + vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG); + size = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG); panicPutStr("Dcache preload parameter configuration error, the error address and size is 0x"); panicPutHex(vaddr); panicPutStr("(0x"); panicPutHex(size); panicPutStr(")\r\n"); break; - case DPORT_DCACHE_WRITE_FLASH_ST: + case EXTMEM_DCACHE_WRITE_FLASH_ST: panicPutStr("Write back error occurred while dcache tries to write back to flash\r\n"); break; - case DPORT_DCACHE_REJECT_ST: - vaddr = REG_READ(DPORT_PRO_DCACHE_REJECT_VADDR_REG); + case EXTMEM_DCACHE_REJECT_ST: + vaddr = REG_READ(EXTMEM_PRO_DCACHE_REJECT_VADDR_REG); panicPutStr("Dcache reject error occurred while accessing the address 0x"); panicPutHex(vaddr); - if (REG_READ(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG) & DPORT_MMU_INVALID) { + if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) { panicPutStr(" (invalid mmu entry)"); } panicPutStr("\r\n"); break; - case DPORT_MMU_ENTRY_FAULT_ST: - vaddr = REG_READ(DPORT_PRO_CACHE_MMU_ERROR_VADDR_REG); + case EXTMEM_MMU_ENTRY_FAULT_ST: + vaddr = REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG); panicPutStr("MMU entry fault error occurred while accessing the address 0x"); panicPutHex(vaddr); - if (REG_READ(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG) & DPORT_MMU_INVALID) { + if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) { panicPutStr(" (invalid mmu entry)"); } panicPutStr("\r\n"); @@ -375,7 +375,7 @@ void panicHandler(XtExcFrame *frame) if (esp_cpu_in_ocd_debug_mode()) { disableAllWdts(); if (frame->exccause == PANIC_RSN_INTWDT_CPU0 || - frame->exccause == PANIC_RSN_INTWDT_CPU1) { + frame->exccause == PANIC_RSN_INTWDT_CPU1) { TIMERG1.int_clr.wdt = 1; } #if CONFIG_APPTRACE_ENABLE diff --git a/components/esp32s2beta/reset_reason.c b/components/esp32s2beta/reset_reason.c index 1ed5bb765c..d5eb92be30 100644 --- a/components/esp32s2beta/reset_reason.c +++ b/components/esp32s2beta/reset_reason.c @@ -57,9 +57,6 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re case RTCWDT_BROWN_OUT_RESET: return ESP_RST_BROWNOUT; - case SDIO_RESET: - return ESP_RST_SDIO; - case INTRUSION_RESET: /* unused */ default: return ESP_RST_UNKNOWN; diff --git a/components/esp32s2beta/sleep_modes.c b/components/esp32s2beta/sleep_modes.c index 8bae117841..f063ba2179 100644 --- a/components/esp32s2beta/sleep_modes.c +++ b/components/esp32s2beta/sleep_modes.c @@ -30,6 +30,7 @@ #include "soc/rtc.h" #include "soc/spi_periph.h" #include "soc/dport_reg.h" +#include "soc/extmem_reg.h" #include "soc/rtc_wdt.h" #include "soc/soc_memory_layout.h" #include "soc/uart_caps.h" @@ -128,8 +129,7 @@ void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub) void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) { /* Clear MMU for CPU 0 */ - _DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_INT_CLR); - _DPORT_REG_SET_BIT(DPORT_PRO_CACHE_IA_INT_EN_REG, DPORT_PRO_CACHE_DBG_EN); + REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN); } void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void); @@ -196,7 +196,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) s_config.sleep_duration > 0) { timer_wakeup_prepare(); } - uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0, 0); + uint32_t result = rtc_sleep_start(s_config.wakeup_triggers, 0, 1); // Restore CPU frequency rtc_clk_cpu_freq_set(cpu_freq); @@ -422,7 +422,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void) return TOUCH_PAD_MAX; } touch_pad_t pad_num; - esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); + esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero"); return pad_num; } diff --git a/components/esp32s2beta/spiram.c b/components/esp32s2beta/spiram.c index 3411102d2d..bdd45e86f0 100644 --- a/components/esp32s2beta/spiram.c +++ b/components/esp32s2beta/spiram.c @@ -33,17 +33,10 @@ we add more types of external RAM memory, this can be made into a more intellige #include "soc/soc_memory_layout.h" #include "soc/dport_reg.h" #include "esp32s2beta/rom/cache.h" +#include "soc/cache_memory.h" +#include "soc/extmem_reg.h" -#if CONFIG_FREERTOS_UNICORE #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL -#else -#warning "spiram.c: TODO: no even/odd mode for ESP32S2 PSRAM?" -#if 0 -#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD -#else -#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH -#endif -#endif #if CONFIG_SPIRAM @@ -131,45 +124,39 @@ void IRAM_ATTR esp_spiram_init_cache(void) Cache_Suspend_DCache(); /* map the address from SPIRAM end to the start, map the address in order: DRAM1, DRAM1, DPORT, DBUS3 */ #if CONFIG_SPIRAM_SIZE <= DRAM0_ONLY_CACHE_SIZE - /* cache size <= 3MB + 576 KB, only map DRAM0 bus */ - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0); - REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM0); + /* cache size <= 3MB + 512 KB, only map DRAM0 bus */ + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); + REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM0); #elif CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_CACHE_SIZE - /* cache size <= 7MB + 576KB, only map DRAM0 and DRAM1 bus */ - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0); - REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0); + /* cache size <= 7MB + 512KB, only map DRAM0 and DRAM1 bus */ + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); + REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0); #elif CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_CACHE_SIZE - /* cache size <= 10MB + 576KB, map DRAM0, DRAM1, DPORT bus */ - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0); - REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT); + /* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */ + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); + REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT); #else -#if CONFIG_SPIRAM_USE_AHB_DBUS3 +#if CONFIG_SPIRAM_USE_AHB_DBUS3// TODO Ready to remove this macro esp32s2 no AHB bus access cache #if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE - /* cache size <= 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0); + /* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0); #else - /* cache size > 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_BIG_SIZE_MAP_VADDR, SPIRAM_BIG_SIZE_MAP_PADDR, 64, SPIRAM_BIG_SIZE_MAP_SIZE >> 16, 0); + /* cache size > 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_BIG_SIZE_MAP_VADDR, SPIRAM_BIG_SIZE_MAP_PADDR, 64, SPIRAM_BIG_SIZE_MAP_SIZE >> 16, 0); #endif - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0); - REG_CLR_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0); - REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT | DPORT_PRO_DCACHE_MASK_BUS3); + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); + REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT | EXTMEM_PRO_DCACHE_MASK_BUS3); #else - /* cache size > 10MB + 576KB, map DRAM0, DRAM1, DPORT bus , only remap 0x3f500000 ~ 0x3ff90000*/ - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); - REG_SET_BIT(DPORT_CACHE_SOURCE_1_REG, DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT | DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0); - REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DRAM1 | DPORT_PRO_DCACHE_MASK_DRAM0 | DPORT_PRO_DCACHE_MASK_DPORT); + /* cache size > 10MB + 512KB, map DRAM0, DRAM1, DPORT bus , only remap 0x3f500000 ~ 0x3ff90000*/ + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); + REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT); #endif #endif } static uint32_t pages_for_flash = 0; static uint32_t page0_mapped = 0; -static uint32_t page0_page = 0xffff; +static uint32_t page0_page = INVALID_PHY_PAGE; static uint32_t instrcution_in_spiram = 0; static uint32_t rodata_in_spiram = 0; @@ -188,7 +175,6 @@ esp_err_t esp_spiram_enable_instruction_access(void) uint32_t pages_in_flash = 0; pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped); - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped); if ((pages_in_flash + pages_for_flash) > (CONFIG_SPIRAM_SIZE >> 16)) { ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (CONFIG_SPIRAM_SIZE >> 16), (pages_in_flash + pages_for_flash)); return ESP_FAIL; @@ -196,7 +182,6 @@ esp_err_t esp_spiram_enable_instruction_access(void) ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM"); pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, pages_for_flash, &page0_page); pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, pages_for_flash, &page0_page); - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, IROM0_ADDRESS_LOW, pages_for_flash, &page0_page); instrcution_in_spiram = 1; return ESP_OK; } @@ -204,11 +189,7 @@ esp_err_t esp_spiram_enable_instruction_access(void) esp_err_t esp_spiram_enable_rodata_access(void) { uint32_t pages_in_flash = 0; - if (Cache_Drom0_Using_ICache()) { - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS3, &page0_mapped); - } else { - pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS3, &page0_mapped); - } + pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS0, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped); @@ -219,11 +200,7 @@ esp_err_t esp_spiram_enable_rodata_access(void) } ESP_EARLY_LOGI(TAG, "Read only data copied and mapped to SPIRAM"); - if (Cache_Drom0_Using_ICache()) { - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS3, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page); - } else { - pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS3, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page); - } + pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, DROM0_ADDRESS_LOW, pages_for_flash, &page0_page); pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, pages_for_flash, &page0_page); pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, pages_for_flash, &page0_page); pages_for_flash = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, pages_for_flash, &page0_page); @@ -261,12 +238,12 @@ esp_err_t esp_spiram_add_to_heapalloc(void) //no need to explicitly specify them. #if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_CACHE_SIZE - /* cache size <= 10MB + 576KB, map DRAM0, DRAM1, DPORT bus */ + /* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */ return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1); #else -#if CONFIG_SPIRAM_USE_AHB_DBUS3 +#if CONFIG_SPIRAM_USE_AHB_DBUS3 //TODO #if CONFIG_SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE - /* cache size <= 14MB + 576KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ + /* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ if (size_for_flash <= SPIRAM_MID_SIZE_MAP_SIZE) { esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1); if (err) { @@ -294,7 +271,7 @@ esp_err_t esp_spiram_add_to_heapalloc(void) } #endif #else - Cache_Dbus_MMU_Set(DPORT_MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); + Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_BIG_SIZE_MAP_VADDR, SPIRAM_MID_BIG_SIZE_MAP_PADDR, 64, SPIRAM_MID_BIG_SIZE_MAP_SIZE >> 16, 0); if (size_for_flash <= SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) { return heap_caps_add_region((intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR, (intptr_t)SPIRAM_MID_BIG_SIZE_MAP_VADDR + SPIRAM_MID_BIG_SIZE_MAP_SIZE -1); } else { @@ -328,38 +305,9 @@ size_t esp_spiram_get_size(void) void IRAM_ATTR esp_spiram_writeback_cache(void) { extern void Cache_WriteBack_All(void); - int cache_was_disabled=0; - - if (!spiram_inited) return; - - //We need cache enabled for this to work. Re-enable it if needed; make sure we - //disable it again on exit as well. - if (DPORT_REG_GET_BIT(DPORT_PRO_DCACHE_CTRL_REG, DPORT_PRO_DCACHE_ENABLE)==0) { - cache_was_disabled|=(1<<0); - DPORT_SET_PERI_REG_BITS(DPORT_PRO_DCACHE_CTRL_REG, 1, 1, DPORT_PRO_DCACHE_ENABLE_S); - } - -#ifndef CONFIG_FREERTOS_UNICORE - if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) { - cache_was_disabled|=(1<<1); - DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S); - } -#endif - Cache_WriteBack_All(); - - if (cache_was_disabled&(1<<0)) { -#ifdef DPORT_CODE_COMPLETE - while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG2_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ; -#endif - DPORT_SET_PERI_REG_BITS(DPORT_PRO_DCACHE_CTRL_REG, 1, 0, DPORT_PRO_DCACHE_ENABLE_S); - } -#ifndef CONFIG_FREERTOS_UNICORE - if (cache_was_disabled&(1<<1)) { - while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG2_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) ; - DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S); - } -#endif } + + #endif diff --git a/components/esp32s2beta/spiram_psram.c b/components/esp32s2beta/spiram_psram.c index ae3af8f0c4..49501b094e 100644 --- a/components/esp32s2beta/spiram_psram.c +++ b/components/esp32s2beta/spiram_psram.c @@ -26,16 +26,23 @@ #include "spiram_psram.h" #include "esp32s2beta/rom/ets_sys.h" #include "esp32s2beta/rom/spi_flash.h" +#include "esp32s2beta/rom/opi_flash.h" #include "esp32s2beta/rom/gpio.h" #include "esp32s2beta/rom/cache.h" -#include "soc/io_mux_reg.h" +#include "esp32s2beta/rom/efuse.h" #include "soc/dport_reg.h" +#include "soc/efuse_periph.h" +#include "soc/spi_caps.h" +#include "soc/io_mux_reg.h" #include "soc/apb_ctrl_reg.h" #include "soc/gpio_sig_map.h" #include "soc/efuse_reg.h" +#include "soc/soc.h" #include "driver/gpio.h" +#include "driver/spi_common_internal.h" #include "driver/spi_common.h" #include "driver/periph_ctrl.h" +#include "bootloader_common.h" #if CONFIG_SPIRAM #include "soc/rtc.h" @@ -54,438 +61,228 @@ #define PSRAM_RESET 0x99 #define PSRAM_SET_BURST_LEN 0xC0 #define PSRAM_DEVICE_ID 0x9F - -typedef enum { - PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */ - PSRAM_CLK_MODE_DCLK = 1, /*!< Two extra clock cycles after CS is set high level */ -} psram_clk_mode_t; - +// ID #define PSRAM_ID_KGD_M 0xff #define PSRAM_ID_KGD_S 8 #define PSRAM_ID_KGD 0x5d #define PSRAM_ID_EID_M 0xff #define PSRAM_ID_EID_S 16 -#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) -#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) -#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) +// Use the [7:5](bit7~bit5) of EID to distinguish the psram size: +// +// BIT7 | BIT6 | BIT5 | SIZE(MBIT) +// ------------------------------------- +// 0 | 0 | 0 | 16 +// 0 | 0 | 1 | 32 +// 0 | 1 | 0 | 64 +#define PSRAM_EID_SIZE_M 0x07 +#define PSRAM_EID_SIZE_S 5 -// PSRAM_EID = 0x26 or 0x4x ----> 64MBit psram -// PSRAM_EID = 0x20 ------------> 32MBit psram -#define PSRAM_IS_64MBIT(id) ((PSRAM_EID(id) == 0x26) || ((PSRAM_EID(id) & 0xf0) == 0x40)) +#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) +#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) +#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) +#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) + +// For the old version 32Mbit psram, using the spicial driver */ #define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20) +#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) -// IO-pins for PSRAM. These need to be in the VDD_SIO power domain because all chips we -// currently support are 1.8V parts. +// IO-pins for PSRAM. // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines // hardcode the flash pins as well, making this code incompatible with either a setup // that has the flash on non-standard pins or ESP32s with built-in flash. -#define FLASH_CLK_IO SPI_CLK_GPIO_NUM //Psram clock is a delayed version of this in 40MHz mode -#define FLASH_CS_IO SPI_CS0_GPIO_NUM -#define PSRAM_CS_IO 26 -#define PSRAM_SPIQ_IO SPI_Q_GPIO_NUM -#define PSRAM_SPID_IO SPI_D_GPIO_NUM -#define PSRAM_SPIWP_IO SPI_WP_GPIO_NUM -#define PSRAM_SPIHD_IO SPI_HD_GPIO_NUM -#define PSRAM_INTERNAL_IO_28 28 -#define PSRAM_INTERNAL_IO_29 29 +#define FLASH_CLK_IO SPI_CLK_GPIO_NUM +#define FLASH_CS_IO SPI_CS0_GPIO_NUM +// PSRAM clock and cs IO should be configured based on hardware design. +#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 +#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 +#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM +#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM +#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM +#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM + +#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M +#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M + #define PSRAM_IO_MATRIX_DUMMY_20M 0 #define PSRAM_IO_MATRIX_DUMMY_40M 0 #define PSRAM_IO_MATRIX_DUMMY_80M 0 +#define _SPI_CACHE_PORT 0 +#define _SPI_FLASH_PORT 1 +#define _SPI_80M_CLK_DIV 1 +#define _SPI_40M_CLK_DIV 2 +#define _SPI_20M_CLK_DIV 4 -#define _SPI_CACHE_PORT 0 -#define _SPI_FLASH_PORT 1 -#define _SPI_80M_CLK_DIV 1 -#define _SPI_40M_CLK_DIV 2 -#define _SPI_20M_CLK_DIV 4 +typedef enum { + PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */ + PSRAM_CLK_MODE_A1C, /*!< ONE extra clock cycles after CS is set high level */ + PSRAM_CLK_MODE_A2C, /*!< Two extra clock cycles after CS is set high level */ + PSRAM_CLK_MODE_ALON, /*!< clock always on */ + PSRAM_CLK_MODE_MAX, +} psram_clk_mode_t; -static const char* TAG = "psram"; + +typedef enum { + PSRAM_EID_SIZE_16MBITS = 0, + PSRAM_EID_SIZE_32MBITS = 1, + PSRAM_EID_SIZE_64MBITS = 2, +} psram_eid_size_t; + +typedef struct { + uint8_t flash_clk_io; + uint8_t flash_cs_io; + uint8_t psram_clk_io; + uint8_t psram_cs_io; + uint8_t psram_spiq_sd0_io; + uint8_t psram_spid_sd1_io; + uint8_t psram_spiwp_sd3_io; + uint8_t psram_spihd_sd2_io; +} psram_io_t; + +#define PSRAM_IO_CONF_DEFAULT() { \ + .flash_clk_io = FLASH_CLK_IO, \ + .flash_cs_io = FLASH_CS_IO, \ + .psram_clk_io = PSRAM_CLK_IO, \ + .psram_cs_io = PSRAM_CS_IO, \ + .psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \ + .psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \ + .psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \ + .psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \ +} + +//static const char* TAG = "psram"; typedef enum { PSRAM_SPI_1 = 0x1, - PSRAM_SPI_2, - PSRAM_SPI_3, + /* PSRAM_SPI_2, */ + /* PSRAM_SPI_3, */ PSRAM_SPI_MAX , } psram_spi_num_t; -static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX; -static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK; -static uint32_t s_psram_id = 0; - -/* dummy_len_plus values defined in ROM for SPI flash configuration */ -extern uint8_t g_rom_spiflash_dummy_len_plus[]; -static int extra_dummy = 0; typedef enum { PSRAM_CMD_QPI, PSRAM_CMD_SPI, } psram_cmd_mode_t; -typedef struct { - uint16_t cmd; /*!< Command value */ - uint16_t cmdBitLen; /*!< Command byte length*/ - uint32_t *addr; /*!< Point to address value*/ - uint16_t addrBitLen; /*!< Address byte length*/ - uint32_t *txData; /*!< Point to send data buffer*/ - uint16_t txDataBitLen; /*!< Send data byte length.*/ - uint32_t *rxData; /*!< Point to recevie data buffer*/ - uint16_t rxDataBitLen; /*!< Recevie Data byte length.*/ - uint32_t dummyBitLen; -} psram_cmd_t; +typedef esp_rom_spi_cmd_t psram_cmd_t; +static uint32_t s_psram_id = 0; static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode); +extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); -static void psram_clear_spi_fifo(psram_spi_num_t spi_num) +static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode) { - int i; - for (i = 0; i < 16; i++) { - WRITE_PERI_REG(SPI_MEM_W0_REG(spi_num)+i*4, 0); + if (mode == PSRAM_CMD_QPI) { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE); + SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); + } else if (mode == PSRAM_CMD_SPI) { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE); } } - -//set basic SPI write mode -static void psram_set_basic_write_mode(psram_spi_num_t spi_num) +static void _psram_exec_cmd(int spi_num, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len) { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QIO); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DIO); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QUAD); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DUAL); + esp_rom_spi_cmd_t conf; + uint32_t _addr = addr; + conf.addr = &_addr; + conf.addrBitLen = addr_bit_len; + conf.cmd = cmd; + conf.cmdBitLen = cmd_bit_len; + conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723 + conf.txData = (uint32_t*) mosi_data; + conf.txDataBitLen = mosi_bit_len; + conf.rxData = (uint32_t*) miso_data; + conf.rxDataBitLen = miso_bit_len; + esp_rom_spi_cmd_config(spi_num, &conf); } -//set QPI write mode -static void psram_set_qio_write_mode(psram_spi_num_t spi_num) + +void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation) { - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QIO); - SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DIO); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_QUAD); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_FWRITE_DUAL); -} -//set QPI read mode -static void psram_set_qio_read_mode(psram_spi_num_t spi_num) -{ - SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QIO); - SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QUAD); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DUAL); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DIO); -} -//set SPI read mode -static void psram_set_basic_read_mode(psram_spi_num_t spi_num) -{ - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QIO); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_QUAD); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DUAL); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FREAD_DIO); + uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); + uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); + uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); + uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); + psram_set_op_mode(spi_num, mode); + _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len, + dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); + esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation); + + WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); + WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); + WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); + WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); } - -//start sending cmd/addr and optionally, receiving data -static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen, - psram_cmd_mode_t cmd_mode) -{ - //get cs1 - CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS1_DIS_M); - SET_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS0_DIS_M); - - uint32_t mode_backup = (READ_PERI_REG(SPI_MEM_USER_REG(spi_num)) >> SPI_MEM_FWRITE_DUAL_S) & 0xf; -#ifdef FAKE_QPI - uint32_t rd_mode_backup = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)) & (SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_QIO_M); -#else - uint32_t rd_mode_backup = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)) & (SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_QIO_M | SPI_MEM_FCMD_QUAD); -#endif - if (cmd_mode == PSRAM_CMD_SPI) { - psram_set_basic_write_mode(spi_num); - psram_set_basic_read_mode(spi_num); - } else if (cmd_mode == PSRAM_CMD_QPI) { - psram_set_qio_write_mode(spi_num); - psram_set_qio_read_mode(spi_num); - } - - // Start send data - SET_PERI_REG_MASK(SPI_MEM_CMD_REG(spi_num), SPI_MEM_USR); - while ((READ_PERI_REG(SPI_MEM_CMD_REG(spi_num)) & SPI_MEM_USR)); - - //recover spi mode - SET_PERI_REG_BITS(SPI_MEM_USER_REG(spi_num), (pRxData?SPI_MEM_FWRITE_DUAL_M:0xf), mode_backup, SPI_MEM_FWRITE_DUAL_S); -#ifdef FAKE_QPI - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), (SPI_MEM_FREAD_DIO_M|SPI_MEM_FREAD_DUAL_M|SPI_MEM_FREAD_QUAD_M|SPI_MEM_FREAD_QIO_M)); -#else - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), (SPI_MEM_FREAD_DIO_M|SPI_MEM_FREAD_DUAL_M|SPI_MEM_FREAD_QUAD_M|SPI_MEM_FREAD_QIO_M|SPI_MEM_FCMD_QUAD)); -#endif - SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), rd_mode_backup); - - //return cs to cs0 - SET_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS1_DIS_M); - CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(PSRAM_SPI_1), SPI_MEM_CS0_DIS_M); - - if (pRxData) { - int idx = 0; - // Read data out - do { - *pRxData++ = READ_PERI_REG(SPI_MEM_W0_REG(spi_num) + (idx << 2)); - } while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0))); - } -} - -static uint32_t backup_usr[3]; -static uint32_t backup_usr1[3]; -static uint32_t backup_usr2[3]; - - - -//setup spi command/addr/data/dummy in user mode -static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData) -{ - while (READ_PERI_REG(SPI_MEM_CMD_REG(spi_num)) & SPI_MEM_USR); - backup_usr[spi_num]=READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); - backup_usr1[spi_num]=READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); - backup_usr2[spi_num]=READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); - // Set command by user. - if (pInData->cmdBitLen != 0) { - // Max command length 16 bits. - SET_PERI_REG_BITS(SPI_MEM_USER2_REG(spi_num), SPI_MEM_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1, - SPI_MEM_USR_COMMAND_BITLEN_S); - // Enable command - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_COMMAND); - // Load command,bit15-0 is cmd value. - SET_PERI_REG_BITS(SPI_MEM_USER2_REG(spi_num), SPI_MEM_USR_COMMAND_VALUE, pInData->cmd, SPI_MEM_USR_COMMAND_VALUE_S); - } else { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_COMMAND); - SET_PERI_REG_BITS(SPI_MEM_USER2_REG(spi_num), SPI_MEM_USR_COMMAND_BITLEN, 0, SPI_MEM_USR_COMMAND_BITLEN_S); - } - // Set Address by user. - if (pInData->addrBitLen != 0) { - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_MEM_USR_ADDR_BITLEN_S); - // Enable address - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_ADDR); - // Set address - WRITE_PERI_REG(SPI_MEM_ADDR_REG(spi_num), *pInData->addr); - } else { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_ADDR); - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(spi_num), SPI_MEM_USR_ADDR_BITLEN, 0, SPI_MEM_USR_ADDR_BITLEN_S); - } - // Set data by user. - uint32_t* p_tx_val = pInData->txData; - if (pInData->txDataBitLen != 0) { - // Enable MOSI - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MOSI); - // Load send buffer - int len = (pInData->txDataBitLen + 31) / 32; - if (p_tx_val != NULL) { - memcpy((void*)SPI_MEM_W0_REG(spi_num), p_tx_val, len * 4); - } - // Set data send buffer length.Max data length 64 bytes. - SET_PERI_REG_BITS(SPI_MEM_MOSI_DLEN_REG(spi_num), SPI_MEM_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1), - SPI_MEM_USR_MOSI_DBITLEN_S); - } else { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MOSI); - SET_PERI_REG_BITS(SPI_MEM_MOSI_DLEN_REG(spi_num), SPI_MEM_USR_MOSI_DBITLEN, 0, SPI_MEM_USR_MOSI_DBITLEN_S); - } - // Set rx data by user. - if (pInData->rxDataBitLen != 0) { - // Enable MOSI - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MISO); - // Set data send buffer length.Max data length 64 bytes. - SET_PERI_REG_BITS(SPI_MEM_MISO_DLEN_REG(spi_num), SPI_MEM_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1), - SPI_MEM_USR_MISO_DBITLEN_S); - } else { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_MISO); - SET_PERI_REG_BITS(SPI_MEM_MISO_DLEN_REG(spi_num), SPI_MEM_USR_MISO_DBITLEN, 0, SPI_MEM_USR_MISO_DBITLEN_S); - } - if (pInData->dummyBitLen != 0) { - SET_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1, - SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - } else { - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(PSRAM_SPI_1), SPI_MEM_USR_DUMMY_CYCLELEN_V, 0, SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - } - return 0; -} - -void psram_cmd_end(int spi_num) { - while (READ_PERI_REG(SPI_MEM_CMD_REG(spi_num)) & SPI_MEM_USR); - WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr[spi_num]); - WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1[spi_num]); - WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2[spi_num]); -} - -#ifdef FAKE_QPI //exit QPI mode(set back to SPI mode) -static void psram_disable_qio_mode(psram_spi_num_t spi_num) +static void psram_disable_qio_mode(int spi_num) { - psram_cmd_t ps_cmd; - uint32_t cmd_exit_qpi; - cmd_exit_qpi = PSRAM_EXIT_QMODE; - ps_cmd.txDataBitLen = 8; - if (s_clk_mode == PSRAM_CLK_MODE_DCLK) { - switch (s_psram_mode) { - case PSRAM_CACHE_S80M: - break; - case PSRAM_CACHE_S40M: - default: - cmd_exit_qpi = PSRAM_EXIT_QMODE << 8; - ps_cmd.txDataBitLen = 16; - break; - } - } - ps_cmd.txData = &cmd_exit_qpi; - ps_cmd.cmd = 0; - ps_cmd.cmdBitLen = 0; - ps_cmd.addr = 0; - ps_cmd.addrBitLen = 0; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI); - psram_cmd_end(spi_num); + psram_exec_cmd(spi_num, PSRAM_CMD_QPI, + PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } -//read psram id -static void psram_read_id(uint32_t* dev_id) -{ - psram_spi_num_t spi_num = PSRAM_SPI_1; - psram_disable_qio_mode(spi_num); - uint32_t dummy_bits = 0 + extra_dummy; - psram_cmd_t ps_cmd; - - uint32_t addr = 0; - ps_cmd.addrBitLen = 3 * 8; - ps_cmd.cmd = PSRAM_DEVICE_ID; - ps_cmd.cmdBitLen = 8; - if (s_clk_mode == PSRAM_CLK_MODE_DCLK) { - switch (s_psram_mode) { - case PSRAM_CACHE_S80M: - break; - case PSRAM_CACHE_S40M: - default: - ps_cmd.cmdBitLen = 2; //this two bits is used to delay 2 clock cycle - ps_cmd.cmd = 0; - addr = (PSRAM_DEVICE_ID << 24) | 0; - ps_cmd.addrBitLen = 4 * 8; - break; - } - } - ps_cmd.addr = &addr; - ps_cmd.txDataBitLen = 0; - ps_cmd.txData = NULL; - ps_cmd.rxDataBitLen = 4 * 8; - ps_cmd.rxData = dev_id; - ps_cmd.dummyBitLen = dummy_bits; - - psram_cmd_config(spi_num, &ps_cmd); - psram_clear_spi_fifo(spi_num); - psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI); - psram_cmd_end(spi_num); -} - -//enter QPI mode -static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num) -{ - psram_cmd_t ps_cmd; - uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0; - - ps_cmd.cmdBitLen = 0; - if (s_clk_mode == PSRAM_CLK_MODE_DCLK) { - switch (s_psram_mode) { - case PSRAM_CACHE_S80M: - break; - case PSRAM_CACHE_S40M: - default: - ps_cmd.cmdBitLen = 2; - break; - } - } - ps_cmd.cmd = 0; - ps_cmd.addr = &addr; - ps_cmd.addrBitLen = 8; - ps_cmd.txData = NULL; - ps_cmd.txDataBitLen = 0; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); - psram_cmd_end(spi_num); - return ESP_OK; -} -#else /* FAKE_QPI */ -//exit QPI mode(set back to SPI mode) -static void psram_disable_qio_mode(psram_spi_num_t spi_num) -{ - psram_cmd_t ps_cmd; - ps_cmd.txData = NULL; - ps_cmd.txDataBitLen = 0; - ps_cmd.cmd = PSRAM_EXIT_QMODE; - ps_cmd.cmdBitLen = 8; - ps_cmd.addr = 0; - ps_cmd.addrBitLen = 0; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI); - psram_cmd_end(spi_num); -} - - //switch psram burst length(32 bytes or 1024 bytes) //datasheet says it should be 1024 bytes by default -static void psram_set_wrap_burst_length(psram_spi_num_t spi_num, psram_cmd_mode_t mode) +static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) { - psram_cmd_t ps_cmd; - ps_cmd.cmd = 0xC0; - ps_cmd.cmdBitLen = 8; - ps_cmd.addr = 0; - ps_cmd.addrBitLen = 0; - ps_cmd.txData = NULL; - ps_cmd.txDataBitLen = 0; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, mode); - psram_cmd_end(spi_num); + psram_exec_cmd(spi_num, mode, + PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //send reset command to psram, in spi mode -static void psram_reset_mode(psram_spi_num_t spi_num) +static void psram_reset_mode(int spi_num) { - psram_cmd_t ps_cmd; - ps_cmd.txData = NULL; - ps_cmd.txDataBitLen = 0; - ps_cmd.addr = NULL; - ps_cmd.addrBitLen = 0; - ps_cmd.cmd = PSRAM_RESET_EN; - ps_cmd.cmdBitLen = 8; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); - psram_cmd_end(spi_num); + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET_EN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ - memset(&ps_cmd, 0, sizeof(ps_cmd)); - ps_cmd.txData = NULL; - ps_cmd.txDataBitLen = 0; - ps_cmd.addr = NULL; - ps_cmd.addrBitLen = 0; - ps_cmd.cmd = PSRAM_RESET; - ps_cmd.cmdBitLen = 8; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); - psram_cmd_end(spi_num); + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } esp_err_t psram_enable_wrap(uint32_t wrap_size) { + static int current_wrap_size = 0; + if (current_wrap_size == wrap_size) { + return ESP_OK; + } switch (wrap_size) { case 32: + case 0: psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; return ESP_OK; case 16: case 64: @@ -508,282 +305,173 @@ bool psram_support_wrap_size(uint32_t wrap_size) } +//read psram id static void psram_read_id(uint32_t* dev_id) { - psram_spi_num_t spi_num = PSRAM_SPI_1; + int spi_num = PSRAM_SPI_1; psram_disable_qio_mode(spi_num); - uint32_t dummy_bits = 0; - uint32_t addr = 0; - psram_cmd_t ps_cmd; - switch (s_psram_mode) { - case PSRAM_CACHE_S80M: - dummy_bits = 0 + extra_dummy; - break; - case PSRAM_CACHE_S40M: - case PSRAM_CACHE_S26M: - case PSRAM_CACHE_S20M: - default: - dummy_bits = 0 + extra_dummy; - break; - } - ps_cmd.cmd = PSRAM_DEVICE_ID; - ps_cmd.cmdBitLen = 8; - ps_cmd.addr = &addr; - ps_cmd.addrBitLen = 24; - ps_cmd.txDataBitLen = 0; - ps_cmd.txData = NULL; - ps_cmd.rxDataBitLen = 3 * 8; - ps_cmd.rxData = dev_id; - ps_cmd.dummyBitLen = dummy_bits; - psram_cmd_config(spi_num, &ps_cmd); - psram_clear_spi_fifo(spi_num); - psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI); - psram_cmd_end(spi_num); + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_DEVICE_ID, 8, /* command and command bit len*/ + 0, 24, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //enter QPI mode -static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num) +static void IRAM_ATTR psram_enable_qio_mode(int spi_num) { - psram_cmd_t ps_cmd; - ps_cmd.cmd = PSRAM_ENTER_QMODE; - ps_cmd.cmdBitLen = 8; //this two bits is used to delay 2 clock cycle - ps_cmd.addr = NULL; - ps_cmd.addrBitLen = 0; - ps_cmd.txData = NULL; - ps_cmd.txDataBitLen = 0; - ps_cmd.rxData = NULL; - ps_cmd.rxDataBitLen = 0; - ps_cmd.dummyBitLen = 0; - psram_cmd_config(spi_num, &ps_cmd); - psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); - psram_cmd_end(spi_num); - return ESP_OK; + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } -#endif /* FAKE_QPI */ -//spi param init for psram -void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode) +static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode) { - uint8_t k; - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP); -#warning "psram_spi_init: part of configuration missing for esp32s2beta" -#if 0 - // SPI_CPOL & SPI_CPHA - CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(spi_num), SPI_MEM_CK_IDLE_EDGE); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CK_OUT_EDGE); - // SPI bit order - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_WR_BIT_ORDER); - CLEAR_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_RD_BIT_ORDER); - // SPI bit order - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_DOUTDIN); -#endif - // May be not must to do. - WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), 0); -#if 0 - // SPI mode type - CLEAR_PERI_REG_MASK(SPI_MEM_SLAVE_REG(spi_num), SPI_MEM_SLAVE_MODE); -#endif - // Set SPI speed for non-80M mode. (80M mode uses APB clock directly.) - if (mode!=PSRAM_CACHE_S80M) { - k = 2; //Main divider. Divide by 2 so we get 40MHz - //clear bit 31, set SPI clock div - CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK); - WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), - (((k - 1) & SPI_MEM_CLKCNT_N) << SPI_MEM_CLKCNT_N_S) | - ((((k + 1) / 2 - 1) & SPI_MEM_CLKCNT_H) << SPI_MEM_CLKCNT_H_S) | //50% duty cycle - (((k - 1) & SPI_MEM_CLKCNT_L) << SPI_MEM_CLKCNT_L_S)); + if (clk_mode == PSRAM_CLK_MODE_NORM) { + // SPI1 Flash Operation port + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } else { + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } +} + +static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode) +{ + if (clk_mode == PSRAM_CLK_MODE_NORM) { + // SPI0 SRAM Cache port + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); + // SPI0 Flash Cache port + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); + } else { + CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M); + } +} + +//psram gpio init , different working frequency we have different solutions +static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) +{ + psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT(); + const uint32_t spiconfig = ets_efuse_get_spiconfig(); + if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) { + /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */ + } else { + // FLASH pins are all configured via GPIO matrix in ROM. + psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig); + psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig); + psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig); + psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig); + psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig); + psram_io.psram_spiwp_sd3_io = ets_efuse_get_wp_pad(); + } + + #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT + // WP/HD already configured in bootloader. + psram_io.psram_spiwp_sd3_io = (psram_io.psram_spiwp_sd3_io <= MAX_PAD_GPIO_NUM ? psram_io.psram_spiwp_sd3_io : CONFIG_BOOTLOADER_SPI_WP_PIN); + #else + + psram_io.psram_spiwp_sd3_io = (psram_io.psram_spiwp_sd3_io <= MAX_PAD_GPIO_NUM ? psram_io.psram_spiwp_sd3_io : CONFIG_SPIRAM_SPIWP_SD3_PIN); + esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); + #endif +} + +psram_size_t psram_get_size(void) +{ + if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) { + return PSRAM_SIZE_64MBITS; + } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) { + return PSRAM_SIZE_32MBITS; + } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) { + return PSRAM_SIZE_16MBITS; + } else { + return PSRAM_SIZE_MAX; + } + return PSRAM_SIZE_MAX; +} + +//used in UT only +bool psram_is_32mbit_ver0(void) +{ + return PSRAM_IS_32MBIT_VER0(s_psram_id); +} + +static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode) +{ + if (spi_num == _SPI_CACHE_PORT) { + REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode); + } else if (spi_num == _SPI_FLASH_PORT) { + REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode); } - // Enable MOSI - SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP | SPI_MEM_CS_HOLD | SPI_MEM_USR_MOSI); - memset((void*)SPI_MEM_W0_REG(spi_num), 0, 16 * 4); } /* * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA. * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode. */ -static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) -{ - int spi_cache_dummy = 0; - uint32_t rd_mode_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0)); - if (rd_mode_reg & (SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_DIO_M)) { - spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; - } else if (rd_mode_reg & (SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DUAL_M)) { - spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; - } else { - spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; - } - // In bootloader, all the signals are already configured, - // We keep the following code in case the bootloader is some older version. - gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0); - gpio_matrix_out(PSRAM_SPIQ_IO, SPIQ_OUT_IDX, 0, 0); - gpio_matrix_in(PSRAM_SPIQ_IO, SPIQ_IN_IDX, 0); - gpio_matrix_out(PSRAM_SPID_IO, SPID_OUT_IDX, 0, 0); - gpio_matrix_in(PSRAM_SPID_IO, SPID_IN_IDX, 0); - gpio_matrix_out(PSRAM_SPIWP_IO, SPIWP_OUT_IDX, 0, 0); - gpio_matrix_in(PSRAM_SPIWP_IO, SPIWP_IN_IDX, 0); - gpio_matrix_out(PSRAM_SPIHD_IO, SPIHD_OUT_IDX, 0, 0); - gpio_matrix_in(PSRAM_SPIHD_IO, SPIHD_IN_IDX, 0); - -#warning "psram_gpio_config: parts not implemented for esp32s2beta" - - switch (mode) { - case PSRAM_CACHE_S40M: - extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M; -#if CONFIG_ESPTOOLPY_FLASHFREQ_80M - g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M; - g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M; - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT); - esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT); -#endif - break; - case PSRAM_CACHE_S80M: - extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M; -#if 0 - g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M; - g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_80M; - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - - CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE); - esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT); - CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE); - esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_FLASH_PORT); - -#endif - break; - case PSRAM_CACHE_S26M: - case PSRAM_CACHE_S20M: - extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; -#if 0 - g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_20M; - g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_20M; - SET_PERI_REG_BITS(SPI_MEM_USER1_REG(_SPI_CACHE_PORT), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_20M, SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY - - CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE); - esp_rom_spiflash_config_clk(_SPI_20M_CLK_DIV, _SPI_CACHE_PORT); - CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE); - esp_rom_spiflash_config_clk(_SPI_20M_CLK_DIV, _SPI_FLASH_PORT); -#endif - - default: - break; - } - SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY); // dummy en - //select pin function gpio - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIHD_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIWP_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICS0_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPIQ_U, PIN_FUNC_GPIO); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPID_U, PIN_FUNC_GPIO); - // flash clock signal should come from IO MUX. - // set drive ability for clock - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SPICLK_U, FUNC_SPICLK_SPICLK); -} - -psram_size_t psram_get_size(void) -{ - if (PSRAM_IS_32MBIT_VER0(s_psram_id)) { - return PSRAM_SIZE_32MBITS; - } else if (PSRAM_IS_64MBIT(s_psram_id)) { - return PSRAM_SIZE_64MBITS; - } else { - return PSRAM_SIZE_MAX; - } -} - -//psram gpio init , different working frequency we have different solutions esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init { - assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now."); - s_psram_mode = mode; - - periph_module_enable(PERIPH_SPI_MODULE); - -#warning "psram_enable: some code disabled for esp32s2beta" -#if 0 - WRITE_PERI_REG(SPI_MEM_EXT3_REG(0), 0x1); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_USR_PREP_HOLD_M); -#endif - - - switch (mode) { - case PSRAM_CACHE_S80M: - case PSRAM_CACHE_S40M: - case PSRAM_CACHE_S26M: - case PSRAM_CACHE_S20M: - default: - psram_spi_init(PSRAM_SPI_1, mode); - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_CS_HOLD); - gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0); -#ifdef FAKE_QPI - /* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral. - We do this by routing it signal to signal 220/221, which are used as a loopback; the extra run through - the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in - silicon) as a temporary pad for this. So the signal path is: - SPI CLK --> GPIO28 --> signal220(in then out) --> internal GPIO29 --> signal221(in then out) --> GPIO17(PSRAM CLK) - */ - gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0); - gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC220_IDX, 0); - gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC220_IDX, 0, 0); - gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC221_IDX, 0); - gpio_matrix_out(PSRAM_CLK_IO, SIG_IN_FUNC221_IDX, 0, 0); -#else - REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, 1); - REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, 1); -#endif - - break; - } - - #if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V - // For flash 80Mhz, we must update ldo voltage in case older version of bootloader didn't do this. - rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config(); - if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) { // VDDSDIO regulator is enabled @ 1.8V - cfg.drefh = 3; - cfg.drefm = 3; - cfg.drefl = 3; - cfg.force = 1; - rtc_vddsdio_set_config(cfg); - ets_delay_us(10); // wait for regulator to become stable - } - #endif - CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(PSRAM_SPI_1), SPI_MEM_CS_SETUP_M); + // GPIO related settings psram_gpio_config(mode); - PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], PIN_FUNC_GPIO); - psram_read_id(&s_psram_id); + + /* SPI1: set spi1 clk mode, in order to send commands on SPI1 */ + /* SPI1: set cs timing(hold time) in order to send commands on SPI1 */ + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C); + psram_read_id(&s_psram_id); if (!PSRAM_IS_VALID(s_psram_id)) { return ESP_FAIL; } - uint32_t flash_id = g_rom_flashchip.device_id; - if (flash_id == FLASH_ID_GD25LQ32C) { - // Set drive ability for 1.8v flash in 80Mhz. - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIHD_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIWP_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICS0_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPICLK_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPIQ_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SPID_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CS_IO], FUN_DRV, 3, FUN_DRV_S); + + psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX; + if (psram_is_32mbit_ver0()) { + clk_mode = PSRAM_CLK_MODE_A1C; + // SPI1: keep clock mode and cs timing for spi1 + } else { + // For other psram, we don't need any extra clock cycles after cs get back to high level + clk_mode = PSRAM_CLK_MODE_NORM; + // SPI1: set clock mode and cs timing to normal mode + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); } - if (PSRAM_IS_64MBIT(s_psram_id)) { - // For this psram, we don't need any extra clock cycles after cs get back to high level - s_clk_mode = PSRAM_CLK_MODE_NORM; - REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, 0); - REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, 0); - } else if (PSRAM_IS_32MBIT_VER0(s_psram_id)) { - s_clk_mode = PSRAM_CLK_MODE_DCLK; - if (mode == PSRAM_CACHE_S80M) { - } - } - psram_reset_mode(PSRAM_SPI_1); + + /* SPI1: send psram reset command */ + /* SPI1: send QPI enable command */ + psram_reset_mode(PSRAM_SPI_1); psram_enable_qio_mode(PSRAM_SPI_1); + + // after sending commands, set spi1 clock mode and cs timing to normal mode. + // since all the operations are sent via SPI0 Cache + /* SPI1: set clock mode to normal mode. */ + /* SPI1: set cs timing to normal */ + psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); + psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); + + /* SPI0: set spi0 clock mode */ + /* SPI0: set spi0 flash/cache cs timing */ + psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode); + psram_set_spi0_cache_cs_timing(clk_mode); + + // SPI0: init SPI commands for Cache psram_cache_init(mode, vaddrmode); + return ESP_OK; } -static void IRAM_ATTR psram_clock_set(psram_spi_num_t spi_num, int8_t freqdiv) +static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv) { uint32_t freqbits; if (1 >= freqdiv) { @@ -797,8 +485,37 @@ static void IRAM_ATTR psram_clock_set(psram_spi_num_t spi_num, int8_t freqdiv) //register initialization for sram cache params and r/w commands static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode) { - SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy - SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command + int extra_dummy = 0; + switch (psram_cache_mode) { + case PSRAM_CACHE_S80M: + psram_clock_set(0, 1); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M; + break; + case PSRAM_CACHE_S40M: + psram_clock_set(0, 2); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M; + break; + case PSRAM_CACHE_S26M: + psram_clock_set(0, 3); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; + break; + case PSRAM_CACHE_S20M: + psram_clock_set(0, 4); + extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; + break; + default: + psram_clock_set(0, 2); + break; + } + + CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S); //write address for cache command. + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy + + //config sram cache r/w command SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, @@ -810,58 +527,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy, SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy - switch (psram_cache_mode) { - case PSRAM_CACHE_S80M: - psram_clock_set(0, 1); - break; - case PSRAM_CACHE_S40M: - psram_clock_set(0, 2); - break; - case PSRAM_CACHE_S26M: - psram_clock_set(0, 3); - break; - case PSRAM_CACHE_S20M: - psram_clock_set(0, 4); - break; - default: - psram_clock_set(0, 2); - break; - } - SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); // cache write command enable - SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S); //write address for cache command. - SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command - CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command - - //config sram cache r/w command - switch (psram_cache_mode) { - case PSRAM_CACHE_S80M: //in this mode , no delay is needed - break; - case PSRAM_CACHE_S40M: //is sram is @40M, need 2 cycles of delay - case PSRAM_CACHE_S26M: - case PSRAM_CACHE_S20M: - default: -#ifdef FAKE_QPI - SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15, - SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache - SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ_QUAD) << 8), - SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd) - SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 15, - SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache) - SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8), - SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay) -#else - SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, - SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache - SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, - SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd) - SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, - SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache) - SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, - SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay) -#endif - break; - } - #if !CONFIG_FREERTOS_UNICORE DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT); DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT); @@ -875,15 +540,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra #endif Cache_Resume_DCache(0); - CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) - if (s_clk_mode == PSRAM_CLK_MODE_NORM) { //different - REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, 0); - REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, 0); - - SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD); - // Set cs time. - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); - } } #endif // CONFIG_SPIRAM diff --git a/components/esp32s2beta/spiram_psram.h b/components/esp32s2beta/spiram_psram.h index b357b8807e..ea7908f030 100644 --- a/components/esp32s2beta/spiram_psram.h +++ b/components/esp32s2beta/spiram_psram.h @@ -28,8 +28,9 @@ typedef enum { } psram_cache_mode_t; typedef enum { - PSRAM_SIZE_32MBITS = 0, - PSRAM_SIZE_64MBITS = 1, + PSRAM_SIZE_16MBITS = 0, + PSRAM_SIZE_32MBITS = 1, + PSRAM_SIZE_64MBITS = 2, PSRAM_SIZE_MAX, } psram_size_t; diff --git a/components/esp32s2beta/system_api_esp32s2beta.c b/components/esp32s2beta/system_api_esp32s2beta.c index 366454072b..f69f88dc70 100644 --- a/components/esp32s2beta/system_api_esp32s2beta.c +++ b/components/esp32s2beta/system_api_esp32s2beta.c @@ -13,12 +13,12 @@ // limitations under the License. #include +#include "sdkconfig.h" #include "esp_system.h" #include "esp_private/system_internal.h" #include "esp_attr.h" #include "esp_wifi.h" #include "esp_log.h" -#include "sdkconfig.h" #include "esp32s2beta/rom/cache.h" #include "esp32s2beta/rom/uart.h" #include "soc/dport_reg.h" @@ -56,19 +56,13 @@ void IRAM_ATTR esp_restart_noos(void) // instruction. This would cause memory pool to be locked by arbiter // to the stalled CPU, preventing current CPU from accessing this pool. const uint32_t core_id = xPortGetCoreID(); -#if !CONFIG_FREERTOS_UNICORE - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - esp_cpu_reset(other_core_id); - esp_cpu_stall(other_core_id); -#endif - // Disable TG0/TG1 watchdogs - TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE; + TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE; TIMERG0.wdt_config0.en = 0; - TIMERG0.wdt_wprotect=0; - TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE; + TIMERG0.wdt_wprotect = 0; + TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE; TIMERG1.wdt_config0.en = 0; - TIMERG1.wdt_wprotect=0; + TIMERG1.wdt_wprotect = 0; // Flush any data left in UART FIFOs uart_tx_wait_idle(0); @@ -88,54 +82,34 @@ void IRAM_ATTR esp_restart_noos(void) // Reset wifi/bluetooth/ethernet/sdio (bb/mac) DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | - DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | + DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | + DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | + DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); // Reset timer/spi/uart DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST); + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST); DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); -#if !CONFIG_FREERTOS_UNICORE - // Clear entry point for APP CPU - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); -#endif - // Reset CPUs if (core_id == 0) { - // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. -#if !CONFIG_FREERTOS_UNICORE - esp_cpu_reset(1); -#endif esp_cpu_reset(0); } -#if !CONFIG_FREERTOS_UNICORE - else { - // Running on APP CPU: need to reset PRO CPU and unstall it, - // then reset APP CPU - esp_cpu_reset(0); - esp_cpu_unstall(0); - esp_cpu_reset(1); - } -#endif - while(true) { + while (true) { ; } } -void esp_chip_info(esp_chip_info_t* out_info) +void esp_chip_info(esp_chip_info_t *out_info) { memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32S2BETA; out_info->cores = 1; out_info->features = CHIP_FEATURE_WIFI_BGN; - - // FIXME: other features? } diff --git a/components/esp_adc_cal/CMakeLists.txt b/components/esp_adc_cal/CMakeLists.txt index 9a925bcd41..d823c3b631 100644 --- a/components/esp_adc_cal/CMakeLists.txt +++ b/components/esp_adc_cal/CMakeLists.txt @@ -1,5 +1,6 @@ -# TODO esp32s2beta: Use require_idf_targets here -if(IDF_TARGET STREQUAL "esp32s2beta") +idf_build_get_property(target IDF_TARGET) +# ToDo: re-enable adc-cal for other target +if(NOT ${target} STREQUAL "esp32") return() endif() diff --git a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.ld b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.ld index ee0b7332f6..2405e2f054 100644 --- a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.ld +++ b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.ld @@ -1,478 +1,405 @@ /* -ESP32C ROM address table +ESP32S2 ROM address table Generated for ROM with MD5sum: -f054d40c5f6b9207d3827460a6f5748c /home/jack/esp-rom/rom//.output/eagle/release/image/eagle.pro.rom.out +0a2c7ec5109c17884606d23b47045796 /home/jack/esp-rom/rom//.output/eagle/release/image/eagle.pro.rom.out */ -PROVIDE ( abs = 0x4000073c ); -PROVIDE ( acm_config_descr = 0x3ffae859 ); -PROVIDE ( acm_usb_descriptors = 0x3ffae7b0 ); -PROVIDE ( app_gpio_arg = 0x3fffc9b4 ); -PROVIDE ( app_gpio_handler = 0x3fffc9b8 ); -PROVIDE ( __ascii_mbtowc = 0x40007de0 ); -PROVIDE ( __ascii_wctomb = 0x40001cac ); -PROVIDE ( __assert = 0x4001565c ); -PROVIDE ( __assert_func = 0x40015634 ); -PROVIDE ( atoi = 0x40000adc ); -PROVIDE ( _atoi_r = 0x40000aec ); -PROVIDE ( atol = 0x40000b04 ); -PROVIDE ( _atol_r = 0x40000b14 ); -PROVIDE ( boot_prepare = 0x4000c020 ); -PROVIDE ( bzero = 0x40007ca4 ); -PROVIDE ( Cache_Address_Through_DCache = 0x40013b50 ); -PROVIDE ( Cache_Address_Through_ICache = 0x40013b10 ); -PROVIDE ( Cache_Allocate_SRAM = 0x4001399c ); -PROVIDE ( Cache_Clean_Addr = 0x40013d80 ); -PROVIDE ( Cache_Clean_All = 0x40013e08 ); -PROVIDE ( Cache_Clean_Items = 0x40013c8c ); -PROVIDE ( Cache_Config_DCache_Autoload = 0x40014148 ); -PROVIDE ( Cache_Config_ICache_Autoload = 0x4001401c ); -PROVIDE ( Cache_Count_Flash_Pages = 0x400147c0 ); -PROVIDE ( Cache_Dbus_MMU_Set = 0x4001468c ); -PROVIDE ( Cache_DCache_Preload_Done = 0x40013fe8 ); -PROVIDE ( Cache_Disable_DCache = 0x40014474 ); -PROVIDE ( Cache_Disable_DCache_Autoload = 0x40014240 ); -PROVIDE ( Cache_Disable_DCache_Lock = 0x400143c8 ); -PROVIDE ( Cache_Disable_ICache = 0x40014438 ); -PROVIDE ( Cache_Disable_ICache_Autoload = 0x40014114 ); -PROVIDE ( Cache_Disable_ICache_Lock = 0x400142e0 ); -PROVIDE ( Cache_Drom0_Source_DCache = 0x400138f8 ); -PROVIDE ( Cache_Drom0_Source_ICache = 0x400138d0 ); -PROVIDE ( Cache_Drom0_Using_DCache = 0x40013940 ); -PROVIDE ( Cache_Drom0_Using_ICache = 0x40013920 ); -PROVIDE ( Cache_Enable_DCache = 0x40014564 ); -PROVIDE ( Cache_Enable_DCache_Autoload = 0x40014228 ); -PROVIDE ( Cache_Enable_DCache_Lock = 0x4001435c ); -PROVIDE ( Cache_Enable_ICache = 0x40014504 ); -PROVIDE ( Cache_Enable_ICache_Autoload = 0x400140fc ); -PROVIDE ( Cache_Enable_ICache_Lock = 0x40014274 ); -PROVIDE ( Cache_End_DCache_Preload = 0x40013ffc ); -PROVIDE ( Cache_End_ICache_Preload = 0x40013f7c ); -PROVIDE ( Cache_Flash_To_SPIRAM_Copy = 0x40014814 ); -PROVIDE ( Cache_Get_DCache_Line_Size = 0x4001397c ); -PROVIDE ( Cache_Get_ICache_Line_Size = 0x40013960 ); -PROVIDE ( Cache_Get_Memory_Addr = 0x40014b14 ); -PROVIDE ( Cache_Get_Memory_BaseAddr = 0x40014abc ); -PROVIDE ( Cache_Get_Memory_value = 0x40014b50 ); -PROVIDE ( Cache_Get_Mode = 0x40013a00 ); -PROVIDE ( Cache_Get_Virtual_Addr = 0x40014a1c ); -PROVIDE ( Cache_Ibus_MMU_Set = 0x4001459c ); -PROVIDE ( Cache_ICache_Preload_Done = 0x40013f68 ); -PROVIDE ( Cache_Invalidate_Addr = 0x40013d20 ); -PROVIDE ( Cache_Invalidate_DCache_All = 0x40013dfc ); -PROVIDE ( Cache_Invalidate_DCache_Items = 0x40013c44 ); -PROVIDE ( Cache_Invalidate_ICache_All = 0x40013df0 ); -PROVIDE ( Cache_Invalidate_ICache_Items = 0x40013bf4 ); -PROVIDE ( Cache_Mask_All = 0x40013e28 ); -PROVIDE ( cache_memory_baseaddrs = 0x3ffae8c8 ); -PROVIDE ( Cache_MMU_Init = 0x40014578 ); -PROVIDE ( Cache_Resume_DCache = 0x40014548 ); -PROVIDE ( Cache_Resume_DCache_Autoload = 0x40013ee8 ); -PROVIDE ( Cache_Resume_ICache = 0x400144e8 ); -PROVIDE ( Cache_Resume_ICache_Autoload = 0x40013ea0 ); -PROVIDE ( Cache_Set_DCache_Mode = 0x40013aa8 ); -PROVIDE ( Cache_Set_Default_Mode = 0x40013b8c ); -PROVIDE ( Cache_Set_ICache_Mode = 0x40013a58 ); -PROVIDE ( Cache_Start_DCache_Preload = 0x40013f90 ); -PROVIDE ( Cache_Start_ICache_Preload = 0x40013f10 ); -PROVIDE ( Cache_Suspend_DCache = 0x40014510 ); -PROVIDE ( Cache_Suspend_DCache_Autoload = 0x40013ebc ); -PROVIDE ( Cache_Suspend_ICache = 0x400144b0 ); -PROVIDE ( Cache_Suspend_ICache_Autoload = 0x40013e74 ); -PROVIDE ( Cache_Travel_Tag_Memory = 0x400148d0 ); -PROVIDE ( Cache_Unlock_DCache = 0x400143ec ); -PROVIDE ( Cache_Unlock_ICache = 0x40014304 ); -PROVIDE ( Cache_UnMask_Drom0 = 0x40013e50 ); -PROVIDE ( Cache_WriteBack_Addr = 0x40013db8 ); -PROVIDE ( Cache_WriteBack_All = 0x40013e14 ); -PROVIDE ( Cache_WriteBack_Items = 0x40013cd4 ); -PROVIDE ( cacl_rtc_memory_crc = 0x4000cc9c ); -PROVIDE ( calloc = 0x40015520 ); -PROVIDE ( _calloc_r = 0x40015234 ); -PROVIDE ( cdc_acm_class_handle_req = 0x4000fc74 ); -PROVIDE ( cdc_acm_config = 0x3fffc260 ); -PROVIDE ( cdc_acm_dev = 0x3fffc52c ); -PROVIDE ( cdc_acm_fifo_fill = 0x4000fd8c ); -PROVIDE ( cdc_acm_fifo_read = 0x4000fdcc ); -PROVIDE ( cdc_acm_init = 0x4000fd48 ); -PROVIDE ( cdc_acm_irq_callback_set = 0x4000fea0 ); -PROVIDE ( cdc_acm_irq_is_pending = 0x4000fe7c ); -PROVIDE ( cdc_acm_irq_rx_disable = 0x4000fe5c ); -PROVIDE ( cdc_acm_irq_rx_enable = 0x4000fe50 ); -PROVIDE ( cdc_acm_irq_rx_ready = 0x4000fe68 ); -PROVIDE ( cdc_acm_irq_state_disable = 0x4000fe30 ); -PROVIDE ( cdc_acm_irq_state_enable = 0x4000fe24 ); -PROVIDE ( cdc_acm_irq_tx_disable = 0x4000fe18 ); -PROVIDE ( cdc_acm_irq_tx_enable = 0x4000fe0c ); -PROVIDE ( cdc_acm_irq_tx_ready = 0x4000fe3c ); -PROVIDE ( cdc_acm_line_ctrl_get = 0x4000fefc ); -PROVIDE ( cdc_acm_line_ctrl_set = 0x4000fea8 ); -PROVIDE ( cdc_acm_poll_out = 0x4000ff2c ); -PROVIDE ( cdc_acm_rx_fifo_cnt = 0x4000fdb8 ); -PROVIDE ( chip_usb_dw_init = 0x40011be0 ); -PROVIDE ( _cleanup = 0x40015724 ); -PROVIDE ( _cleanup_r = 0x400156ac ); -PROVIDE ( __clear_cache = 0x40005e98 ); -PROVIDE ( close = 0x4000848c ); -PROVIDE ( _close_r = 0x40015378 ); -PROVIDE ( cpio_destroy = 0x40012088 ); -PROVIDE ( cpio_done = 0x40012054 ); -PROVIDE ( cpio_feed = 0x40011d5c ); -PROVIDE ( cpio_start = 0x40011d10 ); -PROVIDE ( crc16_be = 0x4000e744 ); -PROVIDE ( crc16_le = 0x4000e708 ); -PROVIDE ( crc32_be = 0x4000e6d4 ); -PROVIDE ( crc32_le = 0x4000e6a0 ); -PROVIDE ( crc8_be = 0x4000e7b4 ); -PROVIDE ( crc8_le = 0x4000e784 ); -PROVIDE ( creat = 0x40007c68 ); -PROVIDE ( _ctype_ = 0x3ffab96c ); -PROVIDE ( _cvt = 0x4000c6d8 ); -PROVIDE ( _data_end_all_pro = 0x3fffdd10 ); -PROVIDE ( _data_end_c = 0x3fffc040 ); -PROVIDE ( _data_end_cache = 0x3fffc020 ); -PROVIDE ( _data_end_ets = 0x3fffc010 ); -PROVIDE ( _data_end_etsc = 0x3fffcb10 ); -PROVIDE ( _data_end_gpio = 0x3fffc980 ); -PROVIDE ( _data_end_hal = 0x3fffc010 ); -PROVIDE ( _data_end_newlib = 0x3fffc020 ); -PROVIDE ( _data_end_phyrom = 0x3fffc230 ); -PROVIDE ( _data_end_sip = 0x3fffc690 ); -PROVIDE ( _data_end_slc = 0x3fffc540 ); -PROVIDE ( _data_end_spi_flash = 0x3fffc250 ); -PROVIDE ( _data_end_uart = 0x3fffc9c0 ); -PROVIDE ( _data_end_usbdev = 0x3fffc2c0 ); -PROVIDE ( _data_end_xtos = 0x3fffd1c0 ); -PROVIDE ( _data_start_all_pro = 0x3fffdd10 ); -PROVIDE ( _data_start_c = 0x3fffc030 ); -PROVIDE ( _data_start_cache = 0x3fffc020 ); -PROVIDE ( _data_start_ets = 0x3fffc010 ); -PROVIDE ( _data_start_etsc = 0x3fffcb00 ); -PROVIDE ( _data_start_gpio = 0x3fffc980 ); -PROVIDE ( _data_start_hal = 0x3fffc010 ); -PROVIDE ( _data_start_newlib = 0x3fffc020 ); -PROVIDE ( _data_start_phyrom = 0x3fffc050 ); -PROVIDE ( _data_start_sip = 0x3fffc690 ); -PROVIDE ( _data_start_slc = 0x3fffc540 ); -PROVIDE ( _data_start_spi_flash = 0x3fffc230 ); -PROVIDE ( _data_start_uart = 0x3fffc9c0 ); -PROVIDE ( _data_start_usbdev = 0x3fffc260 ); -PROVIDE ( _data_start_xtos = 0x3fffcda0 ); -PROVIDE ( dbus_ahb_baseaddrs = 0x3ffae8d8 ); -PROVIDE ( dbus_baseaddrs = 0x3ffae8e8 ); +PROVIDE ( abort = 0x40019fb4 ); +PROVIDE ( acm_config_descr = 0x3ffaef0f ); +PROVIDE ( acm_usb_descriptors = 0x3ffaee68 ); +PROVIDE ( boot_prepare = 0x4000f348 ); +PROVIDE ( Cache_Address_Through_DCache = 0x400180f0 ); +PROVIDE ( Cache_Address_Through_ICache = 0x400180bc ); +PROVIDE ( Cache_Allocate_SRAM = 0x40018d6c ); +PROVIDE ( Cache_Clean_Addr = 0x40018370 ); +PROVIDE ( Cache_Clean_All = 0x40018438 ); +PROVIDE ( Cache_Clean_Items = 0x40018250 ); +PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 ); +PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 ); +PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 ); +PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 ); +PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 ); +PROVIDE ( Cache_Disable_DCache = 0x40018c68 ); +PROVIDE ( Cache_Disable_DCache_Autoload = 0x4001888c ); +PROVIDE ( Cache_Disable_DCache_PreLock = 0x40018a5c ); +PROVIDE ( Cache_Disable_ICache = 0x40018c2c ); +PROVIDE ( Cache_Disable_ICache_Autoload = 0x4001875c ); +PROVIDE ( Cache_Disable_ICache_PreLock = 0x4001892c ); +PROVIDE ( Cache_Enable_DCache = 0x40018d58 ); +PROVIDE ( Cache_Enable_DCache_Autoload = 0x40018874 ); +PROVIDE ( Cache_Enable_DCache_PreLock = 0x400189f0 ); +PROVIDE ( Cache_Enable_Defalut_DCache_Mode = 0x40018170 ); +PROVIDE ( Cache_Enable_ICache = 0x40018cf8 ); +PROVIDE ( Cache_Enable_ICache_Autoload = 0x40018744 ); +PROVIDE ( Cache_Enable_ICache_PreLock = 0x400188c0 ); +PROVIDE ( Cache_End_DCache_Preload = 0x40018644 ); +PROVIDE ( Cache_End_ICache_Preload = 0x400185b0 ); +PROVIDE ( Cache_Flash_To_SPIRAM_Copy = 0x40018fc4 ); +PROVIDE ( Cache_Get_DCache_Line_Size = 0x40017fd8 ); +PROVIDE ( Cache_Get_ICache_Line_Size = 0x40017fbc ); +PROVIDE ( Cache_Get_Memory_Addr = 0x4001929c ); +PROVIDE ( Cache_Get_Memory_BaseAddr = 0x40019244 ); +PROVIDE ( Cache_Get_Memory_value = 0x400192d8 ); +PROVIDE ( Cache_Get_Mode = 0x40017ff0 ); +PROVIDE ( Cache_Get_Virtual_Addr = 0x40019210 ); +PROVIDE ( Cache_Ibus_MMU_Set = 0x40018df4 ); +PROVIDE ( Cache_ICache_Preload_Done = 0x4001859c ); +PROVIDE ( Cache_Invalidate_Addr = 0x400182e4 ); +PROVIDE ( Cache_Invalidate_DCache_All = 0x4001842c ); +PROVIDE ( Cache_Invalidate_DCache_Items = 0x40018208 ); +PROVIDE ( Cache_Invalidate_ICache_All = 0x40018420 ); +PROVIDE ( Cache_Invalidate_ICache_Items = 0x400181b8 ); +PROVIDE ( Cache_Lock_Addr = 0x40018b10 ); +PROVIDE ( Cache_Lock_DCache_Items = 0x40018a80 ); +PROVIDE ( Cache_Lock_ICache_Items = 0x40018950 ); +PROVIDE ( Cache_Mask_All = 0x40018458 ); +PROVIDE ( cache_memory_baseaddrs = 0x3ffaf020 ); +PROVIDE ( Cache_MMU_Init = 0x40018dd8 ); +PROVIDE ( Cache_Resume_DCache = 0x40018d3c ); +PROVIDE ( Cache_Resume_DCache_Autoload = 0x4001850c ); +PROVIDE ( Cache_Resume_ICache = 0x40018cdc ); +PROVIDE ( Cache_Resume_ICache_Autoload = 0x400184c4 ); +PROVIDE ( Cache_Set_DCache_Mode = 0x40018074 ); +PROVIDE ( Cache_Set_Default_Mode = 0x4001810c ); +PROVIDE ( Cache_Set_ICache_Mode = 0x4001803c ); +PROVIDE ( Cache_Start_DCache_Preload = 0x400185c4 ); +PROVIDE ( Cache_Start_ICache_Preload = 0x40018530 ); +PROVIDE ( Cache_Suspend_DCache = 0x40018d04 ); +PROVIDE ( Cache_Suspend_DCache_Autoload = 0x400184e0 ); +PROVIDE ( Cache_Suspend_ICache = 0x40018ca4 ); +PROVIDE ( Cache_Suspend_ICache_Autoload = 0x40018498 ); +PROVIDE ( Cache_Travel_Tag_Memory = 0x4001908c ); +PROVIDE ( Cache_Unlock_Addr = 0x40018b9c ); +PROVIDE ( Cache_Unlock_DCache_Items = 0x40018ac8 ); +PROVIDE ( Cache_Unlock_ICache_Items = 0x40018998 ); +PROVIDE ( Cache_UnMask_Drom0 = 0x40018480 ); +PROVIDE ( Cache_WriteBack_Addr = 0x400183c8 ); +PROVIDE ( Cache_WriteBack_All = 0x40018444 ); +PROVIDE ( Cache_WriteBack_Items = 0x40018298 ); +PROVIDE ( cacl_rtc_memory_crc = 0x4000ffa0 ); +PROVIDE ( cdc_acm_class_handle_req = 0x40013050 ); +PROVIDE ( cdc_acm_config = 0x3ffffa10 ); +PROVIDE ( cdc_acm_dev = 0x3ffffce8 ); +PROVIDE ( cdc_acm_fifo_fill = 0x4001318c ); +PROVIDE ( cdc_acm_fifo_read = 0x40013200 ); +PROVIDE ( cdc_acm_init = 0x40013144 ); +PROVIDE ( cdc_acm_irq_callback_set = 0x400132d4 ); +PROVIDE ( cdc_acm_irq_is_pending = 0x400132b0 ); +PROVIDE ( cdc_acm_irq_rx_disable = 0x40013290 ); +PROVIDE ( cdc_acm_irq_rx_enable = 0x40013284 ); +PROVIDE ( cdc_acm_irq_rx_ready = 0x4001329c ); +PROVIDE ( cdc_acm_irq_state_disable = 0x40013264 ); +PROVIDE ( cdc_acm_irq_state_enable = 0x40013258 ); +PROVIDE ( cdc_acm_irq_tx_disable = 0x4001324c ); +PROVIDE ( cdc_acm_irq_tx_enable = 0x40013240 ); +PROVIDE ( cdc_acm_irq_tx_ready = 0x40013270 ); +PROVIDE ( cdc_acm_line_ctrl_get = 0x40013330 ); +PROVIDE ( cdc_acm_line_ctrl_set = 0x400132dc ); +PROVIDE ( cdc_acm_poll_out = 0x40013360 ); +PROVIDE ( cdc_acm_rx_fifo_cnt = 0x400131ec ); +PROVIDE ( chip723_phyrom_version = 0x4000a8a8 ); +PROVIDE ( chip_usb_detach = 0x40013508 ); +PROVIDE ( chip_usb_dw_did_persist = 0x4001337c ); +PROVIDE ( chip_usb_dw_init = 0x400133bc ); +PROVIDE ( chip_usb_dw_prepare_persist = 0x40013588 ); +PROVIDE ( chip_usb_get_persist_flags = 0x400135d8 ); +PROVIDE ( chip_usb_set_persist_flags = 0x400135e8 ); +PROVIDE ( __clear_cache = 0x40005abc ); +PROVIDE ( context = 0x3fffeb34 ); +PROVIDE ( cpio_destroy = 0x4001599c ); +PROVIDE ( cpio_done = 0x40015968 ); +PROVIDE ( cpio_feed = 0x40015668 ); +PROVIDE ( cpio_start = 0x4001561c ); +PROVIDE ( crc16_le = 0x40011a10 ); +PROVIDE ( crc32_le = 0x400119dc ); +PROVIDE ( crc8_le = 0x40011a4c ); +PROVIDE ( _data_end_all_pro = 0x3fffff98 ); +PROVIDE ( _data_end_c = 0x3ffffd80 ); +PROVIDE ( _data_end_ets = 0x3fffe710 ); +PROVIDE ( _data_end_ets_delay = 0x3ffffd74 ); +PROVIDE ( _data_end_ets_printf = 0x3ffffd5c ); +PROVIDE ( _data_end_newlib = 0x3ffffd74 ); +PROVIDE ( _data_end_phyrom = 0x3fffff98 ); +PROVIDE ( _data_end_sip = 0x3fffeb70 ); +PROVIDE ( _data_end_slc = 0x3fffeb70 ); +PROVIDE ( _data_end_spi_flash = 0x3ffffd54 ); +PROVIDE ( _data_end_spi_slave = 0x3fffeb30 ); +PROVIDE ( _data_end_uart = 0x3ffffcf4 ); +PROVIDE ( _data_end_usbdev = 0x3ffffa6c ); +PROVIDE ( _data_end_xtos = 0x3fffef88 ); +PROVIDE ( _data_start_all_pro = 0x3fffff98 ); +PROVIDE ( _data_start_c = 0x3ffffd7c ); +PROVIDE ( _data_start_ets = 0x3fffe710 ); +PROVIDE ( _data_start_ets_delay = 0x3ffffd70 ); +PROVIDE ( _data_start_ets_printf = 0x3ffffd5c ); +PROVIDE ( _data_start_newlib = 0x3ffffd74 ); +PROVIDE ( _data_start_phyrom = 0x3ffffd90 ); +PROVIDE ( _data_start_sip = 0x3fffeb70 ); +PROVIDE ( _data_start_slc = 0x3fffeb70 ); +PROVIDE ( _data_start_spi_flash = 0x3ffffd38 ); +PROVIDE ( _data_start_spi_slave = 0x3fffeb30 ); +PROVIDE ( _data_start_uart = 0x3ffffcf4 ); +PROVIDE ( _data_start_usbdev = 0x3ffffa10 ); +PROVIDE ( _data_start_xtos = 0x3fffeb70 ); +PROVIDE ( dbus_baseaddrs = 0x3ffaf030 ); PROVIDE ( _DebugExceptionVector = 0x40000280 ); PROVIDE ( _DebugExceptionVector_text_end = 0x4000028b ); PROVIDE ( _DebugExceptionVector_text_start = 0x40000280 ); -PROVIDE ( debug_timer = 0x3fffcd90 ); -PROVIDE ( debug_timerfn = 0x3fffcd94 ); -PROVIDE ( __default_global_locale = 0x3ffab800 ); -PROVIDE ( dfu_class_handle_req = 0x40011978 ); -PROVIDE ( dfu_config_descr = 0x3ffae778 ); -PROVIDE ( dfu_config_descr_dummy = 0x3ffae793 ); -PROVIDE ( dfu_cpio_callback = 0x4000ff58 ); -PROVIDE ( dfu_custom_handle_req = 0x40011b8c ); -PROVIDE ( dfu_flash_attach = 0x400120d8 ); -PROVIDE ( dfu_flash_deinit = 0x400120a0 ); -PROVIDE ( dfu_flash_erase = 0x400120a8 ); -PROVIDE ( dfu_flash_init = 0x40012090 ); -PROVIDE ( dfu_flash_program = 0x400120b8 ); -PROVIDE ( dfu_flash_read = 0x400120c8 ); -PROVIDE ( dfu_runtime_config_descr = 0x3ffae83e ); -PROVIDE ( dfu_status_cb = 0x40011b58 ); -PROVIDE ( dfu_updater_begin = 0x400101a4 ); -PROVIDE ( dfu_updater_clear_err = 0x4001015c ); -PROVIDE ( dfu_updater_enable = 0x40010174 ); -PROVIDE ( dfu_updater_end = 0x40010248 ); -PROVIDE ( dfu_updater_feed = 0x400101fc ); -PROVIDE ( dfu_updater_flash_read = 0x40010330 ); -PROVIDE ( dfu_updater_get_err = 0x40010148 ); -PROVIDE ( dfu_updater_set_raw_addr = 0x4001031c ); -PROVIDE ( dfu_usb_descriptors = 0x3ffae758 ); -PROVIDE ( dh_group14_generator = 0x3ffad898 ); -PROVIDE ( dh_group14_prime = 0x3ffad798 ); -PROVIDE ( dh_group15_generator = 0x3ffad797 ); -PROVIDE ( dh_group15_prime = 0x3ffad617 ); -PROVIDE ( dh_group16_generator = 0x3ffad616 ); -PROVIDE ( dh_group16_prime = 0x3ffad416 ); -PROVIDE ( dh_group17_generator = 0x3ffad415 ); -PROVIDE ( dh_group17_prime = 0x3ffad115 ); -PROVIDE ( dh_group18_generator = 0x3ffad114 ); -PROVIDE ( dh_group18_prime = 0x3ffacd14 ); -PROVIDE ( dh_group1_generator = 0x3ffada3b ); -PROVIDE ( dh_group1_prime = 0x3ffad9db ); -PROVIDE ( dh_group2_generator = 0x3ffad9da ); -PROVIDE ( dh_group2_prime = 0x3ffad95a ); -PROVIDE ( dh_group5_generator = 0x3ffad959 ); -PROVIDE ( dh_group5_prime = 0x3ffad899 ); -PROVIDE ( disable_default_watchdog = 0x4000bf84 ); -PROVIDE ( Disable_QMode = 0x40012d24 ); -PROVIDE ( div = 0x40000744 ); +PROVIDE ( dfu_class_handle_req = 0x400152f0 ); +PROVIDE ( dfu_config_descr = 0x3ffaeeb2 ); +PROVIDE ( dfu_cpio_callback = 0x4001360c ); +PROVIDE ( dfu_custom_handle_req = 0x40015568 ); +PROVIDE ( dfu_flash_attach = 0x40015a34 ); +PROVIDE ( dfu_flash_deinit = 0x400159b4 ); +PROVIDE ( dfu_flash_erase = 0x400159bc ); +PROVIDE ( dfu_flash_init = 0x400159a4 ); +PROVIDE ( dfu_flash_program = 0x400159d0 ); +PROVIDE ( dfu_flash_read = 0x40015a24 ); +PROVIDE ( dfu_status_cb = 0x40015514 ); +PROVIDE ( dfu_updater_begin = 0x40013858 ); +PROVIDE ( dfu_updater_clear_err = 0x40013810 ); +PROVIDE ( dfu_updater_enable = 0x40013828 ); +PROVIDE ( dfu_updater_end = 0x40013900 ); +PROVIDE ( dfu_updater_feed = 0x400138b4 ); +PROVIDE ( dfu_updater_flash_read = 0x400139e8 ); +PROVIDE ( dfu_updater_get_err = 0x400137fc ); +PROVIDE ( dfu_updater_set_raw_addr = 0x400139d4 ); +PROVIDE ( dfu_usb_descriptors = 0x3ffaee4c ); +PROVIDE ( dh_group14_generator = 0x3ffadfec ); +PROVIDE ( dh_group14_prime = 0x3ffadeec ); +PROVIDE ( dh_group15_generator = 0x3ffadeeb ); +PROVIDE ( dh_group15_prime = 0x3ffadd6b ); +PROVIDE ( dh_group16_generator = 0x3ffadd6a ); +PROVIDE ( dh_group16_prime = 0x3ffadb6a ); +PROVIDE ( dh_group17_generator = 0x3ffadb69 ); +PROVIDE ( dh_group17_prime = 0x3ffad869 ); +PROVIDE ( dh_group18_generator = 0x3ffad868 ); +PROVIDE ( dh_group18_prime = 0x3ffad468 ); +PROVIDE ( dh_group1_generator = 0x3ffae18f ); +PROVIDE ( dh_group1_prime = 0x3ffae12f ); +PROVIDE ( dh_group2_generator = 0x3ffae12e ); +PROVIDE ( dh_group2_prime = 0x3ffae0ae ); +PROVIDE ( dh_group5_generator = 0x3ffae0ad ); +PROVIDE ( dh_group5_prime = 0x3ffadfed ); +PROVIDE ( disable_default_watchdog = 0x4000f270 ); +PROVIDE ( Disable_QMode = 0x400166e0 ); +PROVIDE ( dmadesc_rx = 0x3fffeb4c ); +PROVIDE ( dmadesc_tx = 0x3fffeb40 ); PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); PROVIDE ( _DoubleExceptionVector_text_end = 0x400003c6 ); PROVIDE ( _DoubleExceptionVector_text_start = 0x400003c0 ); -PROVIDE ( _dram0_0_start = 0x3fffc000 ); -PROVIDE ( _dram0_1_start = 0x3fffdd00 ); -PROVIDE ( dummy_len_plus = 0x3fffc250 ); -PROVIDE ( Enable_QMode = 0x40012cd4 ); -PROVIDE ( esp_crc8 = 0x4000e7e0 ); -PROVIDE ( _etext = 0x400170fc ); -PROVIDE ( ets_aes_block = 0x4000aa2c ); -PROVIDE ( ets_aes_disable = 0x4000a914 ); -PROVIDE ( ets_aes_enable = 0x4000a8e8 ); -PROVIDE ( ets_aes_set_endian = 0x4000a944 ); -PROVIDE ( ets_aes_setkey = 0x4000a9b0 ); -PROVIDE ( ets_aes_setkey_dec = 0x4000aa0c ); -PROVIDE ( ets_aes_setkey_enc = 0x4000a9fc ); -PROVIDE ( ets_bigint_disable = 0x4000ab6c ); -PROVIDE ( ets_bigint_enable = 0x4000ab24 ); -PROVIDE ( ets_bigint_getz = 0x4000ac74 ); -PROVIDE ( ets_bigint_modexp = 0x4000ac34 ); -PROVIDE ( ets_bigint_modmult = 0x4000ac10 ); -PROVIDE ( ets_bigint_multiply = 0x4000abac ); -PROVIDE ( ets_bigint_wait_finish = 0x4000ac5c ); -PROVIDE ( ets_config_flash_by_image_hdr = 0x4000db10 ); -PROVIDE ( ets_delay_us = 0x4000d938 ); -PROVIDE ( ets_efuse_clear_program_registers = 0x4000aec4 ); -PROVIDE ( ets_efuse_count_unused_key_blocks = 0x4000b088 ); -PROVIDE ( ets_efuse_download_modes_disabled = 0x4000b328 ); -PROVIDE ( ets_efuse_find_purpose = 0x4000afe0 ); -PROVIDE ( ets_efuse_find_unused_key_block = 0x4000b070 ); -PROVIDE ( ets_efuse_get_8M_clock = 0x4000b2b8 ); -PROVIDE ( ets_efuse_get_flash_delay_us = 0x4000b414 ); -PROVIDE ( ets_efuse_get_key_purpose = 0x4000af6c ); -PROVIDE ( ets_efuse_get_read_register_address = 0x4000af48 ); -PROVIDE ( ets_efuse_get_spiconfig = 0x4000b264 ); -PROVIDE ( ets_efuse_get_uart_print_channel = 0x4000b358 ); -PROVIDE ( ets_efuse_get_uart_print_control = 0x4000b348 ); -PROVIDE ( ets_efuse_get_wp_pad = 0x4000b208 ); -PROVIDE ( ets_efuse_get_xtal_freq = 0x4000b2c8 ); -PROVIDE ( ets_efuse_key_block_unused = 0x4000b00c ); -PROVIDE ( ets_efuse_legacy_spi_boot_mode_disabled = 0x4000b338 ); -PROVIDE ( ets_efuse_program = 0x4000af34 ); -PROVIDE ( ets_efuse_read = 0x4000ae94 ); -PROVIDE ( ets_efuse_rs_calculate = 0x4000b438 ); -PROVIDE ( ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000b404 ); -PROVIDE ( ets_efuse_secure_boot_enabled = 0x4000b3f4 ); -PROVIDE ( ets_efuse_security_download_modes_enabled = 0x4000b388 ); -PROVIDE ( ets_efuse_start = 0x4000ae28 ); -PROVIDE ( ets_efuse_tiny_basic_mode_disabled = 0x4000b368 ); -PROVIDE ( ets_efuse_usb_download_mode_disabled = 0x4000b3a8 ); -PROVIDE ( ets_efuse_usb_force_b = 0x4000b3e4 ); -PROVIDE ( ets_efuse_usb_module_disabled = 0x4000b378 ); -PROVIDE ( ets_efuse_usb_use_ext_phy = 0x4000b3d4 ); -PROVIDE ( ets_efuse_write_key = 0x4000b0c8 ); -PROVIDE ( ets_emsa_pss_verify = 0x4000e508 ); -PROVIDE ( ets_get_apb_freq = 0x4000d9cc ); -PROVIDE ( ets_get_cpu_frequency = 0x4000d960 ); -PROVIDE ( ets_get_xtal_freq = 0x4000d988 ); -PROVIDE ( ets_get_xtal_scale = 0x4000d970 ); -PROVIDE ( ets_hmac_calculate_downstream = 0x4000be1c ); -PROVIDE ( ets_hmac_calculate_message = 0x4000bd38 ); -PROVIDE ( ets_hmac_disable = 0x4000bd0c ); -PROVIDE ( ets_hmac_enable = 0x4000bcf0 ); -PROVIDE ( ets_hmac_invalidate_downstream = 0x4000be3c ); -PROVIDE ( ets_install_lock = 0x4000cbc0 ); -PROVIDE ( ets_install_putc1 = 0x4000cbd0 ); -PROVIDE ( ets_install_putc2 = 0x4000cbf0 ); -PROVIDE ( ets_install_uart_printf = 0x4000cbe0 ); -PROVIDE ( ets_intr_count = 0x3fffcd1c ); -PROVIDE ( ets_intr_lock = 0x4000be64 ); -PROVIDE ( ets_intr_unlock = 0x4000be78 ); -PROVIDE ( ets_isr_attach = 0x4000bea0 ); -PROVIDE ( ets_isr_mask = 0x4000beb0 ); -PROVIDE ( ets_isr_unmask = 0x4000bebc ); -PROVIDE ( ets_jtag_enable_temporarily = 0x4000b2dc ); -PROVIDE ( ets_loader_map_range = 0x4000da5c ); -PROVIDE ( ets_mgf1_sha256 = 0x4000e4a0 ); -PROVIDE ( ets_post = 0x4000ad78 ); -PROVIDE ( ets_printf = 0x4000cc00 ); -PROVIDE ( ets_printf_lock = 0x3fffc014 ); -PROVIDE ( ets_printf_unlock = 0x3fffc010 ); -PROVIDE ( ets_readySet_ = 0x3fffcb10 ); -PROVIDE ( ets_rsa_pss_verify = 0x4000e5e4 ); -PROVIDE ( ets_run = 0x4000acf0 ); -PROVIDE ( ets_run_flash_bootloader = 0x4000dc08 ); -PROVIDE ( ets_secure_boot_read_key_digests = 0x4000cdcc ); -PROVIDE ( ets_secure_boot_revoke_public_key_digest = 0x4000ce4c ); -PROVIDE ( ets_secure_boot_verify_bootloader = 0x4000d184 ); -PROVIDE ( ets_secure_boot_verify_bootloader_with_keys = 0x4000cff8 ); -PROVIDE ( ets_secure_boot_verify_signature = 0x4000ceb4 ); -PROVIDE ( ets_set_appcpu_boot_addr = 0x4000bf74 ); -PROVIDE ( ets_set_idle_cb = 0x4000aca8 ); -PROVIDE ( ets_set_startup_callback = 0x4000bf68 ); -PROVIDE ( ets_set_user_start = 0x4000bf58 ); -PROVIDE ( ets_sha_clone = 0x4000d3b0 ); -PROVIDE ( ets_sha_disable = 0x4000d208 ); -PROVIDE ( ets_sha_enable = 0x4000d1dc ); -PROVIDE ( ets_sha_finish = 0x4000d544 ); -PROVIDE ( ets_sha_get_state = 0x4000d388 ); -PROVIDE ( ets_sha_init = 0x4000d234 ); -PROVIDE ( ets_sha_process = 0x4000d3dc ); -PROVIDE ( ets_sha_starts = 0x4000d27c ); -PROVIDE ( ets_sha_update = 0x4000d484 ); -PROVIDE ( ets_startup_callback = 0x3fffcd24 ); -PROVIDE ( ets_task = 0x4000acbc ); -PROVIDE ( ets_unpack_flash_code_legacy = 0x4000e138 ); -PROVIDE ( ets_update_cpu_frequency = 0x4000d954 ); -PROVIDE ( ets_vprintf = 0x4000c75c ); -PROVIDE ( ets_waiti0 = 0x4000be8c ); -PROVIDE ( ets_wdt_reset_cpu = 0x40015a58 ); -PROVIDE ( ets_write_char = 0x4000c694 ); -PROVIDE ( ets_write_char_uart = 0x4000c6b8 ); -PROVIDE ( exc_cause_table = 0x3ffabda8 ); -PROVIDE ( _exit_r = 0x40015364 ); -PROVIDE ( fclose = 0x40015a30 ); -PROVIDE ( _fclose_r = 0x40015940 ); -PROVIDE ( fflush = 0x40001f94 ); -PROVIDE ( _fflush_r = 0x40001f0c ); -PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x4000ec20 ); -PROVIDE ( FilePacketSendReqMsgProc = 0x4000e920 ); -PROVIDE ( fiprintf = 0x40000e18 ); -PROVIDE ( _fiprintf_r = 0x40000df4 ); -PROVIDE ( flashchip = 0x3fffc230 ); -PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x4000ebc8 ); -PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000ea08 ); -PROVIDE ( FlashDwnLdStartMsgProc = 0x4000e8bc ); -PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x4000ed20 ); -PROVIDE ( FlashDwnLdStopReqMsgProc = 0x4000e9d8 ); -PROVIDE ( __fp_lock_all = 0x40015864 ); -PROVIDE ( fprintf = 0x40000e18 ); -PROVIDE ( _fprintf_r = 0x40000df4 ); -PROVIDE ( __fp_unlock_all = 0x40015878 ); -PROVIDE ( fputwc = 0x40001c40 ); -PROVIDE ( __fputwc = 0x40001b4c ); -PROVIDE ( _fputwc_r = 0x40001bd4 ); -PROVIDE ( free = 0x400154f4 ); -PROVIDE ( _free_r = 0x40015208 ); -PROVIDE ( _fstat_r = 0x40015308 ); -PROVIDE ( _fwalk = 0x40016efc ); -PROVIDE ( _fwalk_reent = 0x40016f34 ); -PROVIDE ( general_device_descr = 0x3fffc2a8 ); -PROVIDE ( _GeneralException = 0x400077ab ); -PROVIDE ( get_id = 0x4001272c ); -PROVIDE ( _getpid_r = 0x40015338 ); -PROVIDE ( __getreent = 0x400154c8 ); -PROVIDE ( GetSecurityInfoProc = 0x4000ede0 ); -PROVIDE ( _gettimeofday_r = 0x40015294 ); -PROVIDE ( GetUartDevice = 0x4000fbb0 ); -PROVIDE ( _global_impure_ptr = 0x3fffc04c ); -PROVIDE ( __global_locale_ptr = 0x3fffc030 ); -PROVIDE ( g_phyFuns_instance = 0x3fffc054 ); -PROVIDE ( gpio_init = 0x40014cbc ); -PROVIDE ( gpio_input_get = 0x40014c20 ); -PROVIDE ( gpio_input_get_high = 0x40014c34 ); -PROVIDE ( gpio_intr_ack = 0x40014e70 ); -PROVIDE ( gpio_intr_ack_high = 0x40014eb8 ); -PROVIDE ( gpio_intr_handler_register = 0x40014f04 ); -PROVIDE ( gpio_intr_pending = 0x40014d88 ); -PROVIDE ( gpio_intr_pending_high = 0x40014d94 ); -PROVIDE ( gpio_matrix_in = 0x40014f74 ); -PROVIDE ( gpio_matrix_out = 0x40014fa4 ); -PROVIDE ( gpio_output_disable = 0x40015020 ); -PROVIDE ( gpio_output_enable = 0x40014ff4 ); -PROVIDE ( gpio_output_set = 0x40014bbc ); -PROVIDE ( gpio_output_set_high = 0x40014bf4 ); -PROVIDE ( gpio_pad_hold = 0x4001519c ); -PROVIDE ( gpio_pad_input_disable = 0x40015138 ); -PROVIDE ( gpio_pad_input_enable = 0x40015114 ); -PROVIDE ( gpio_pad_pulldown = 0x400150e0 ); -PROVIDE ( gpio_pad_pullup = 0x400150ac ); -PROVIDE ( gpio_pad_select_gpio = 0x40015054 ); -PROVIDE ( gpio_pad_set_drv = 0x40015080 ); -PROVIDE ( gpio_pad_unhold = 0x40015164 ); -PROVIDE ( gpio_pending_mask = 0x3fffc9b0 ); -PROVIDE ( gpio_pending_mask_high = 0x3fffc9bc ); -PROVIDE ( gpio_pin_intr_state_set = 0x40014da0 ); -PROVIDE ( gpio_pin_wakeup_disable = 0x40014f48 ); -PROVIDE ( gpio_pin_wakeup_enable = 0x40014f14 ); -PROVIDE ( gpio_register_get = 0x40014d58 ); -PROVIDE ( gpio_register_set = 0x40014c54 ); -PROVIDE ( g_ticks_per_us = 0x3fffcb00 ); -PROVIDE ( hmac_md5 = 0x4000586c ); -PROVIDE ( hmac_md5_vector = 0x4000577c ); -PROVIDE ( ibus_ahb_baseaddrs = 0x3ffae8f8 ); -PROVIDE ( ibus_baseaddrs = 0x3ffae908 ); -PROVIDE ( intr_matrix_set = 0x4000becc ); +PROVIDE ( _dram0_0_start = 0x3ffeab00 ); +PROVIDE ( _dram0_rtos_reserved_start = 0x3ffffa10 ); +PROVIDE ( dummy_len_plus = 0x3ffffd54 ); +PROVIDE ( Enable_QMode = 0x40016690 ); +PROVIDE ( esp_crc8 = 0x40011a78 ); +PROVIDE ( esp_rom_config_pad_power_select = 0x40016e58 ); +PROVIDE ( esp_rom_opiflash_cache_mode_config = 0x40016754 ); +PROVIDE ( esp_rom_opiflash_exec_cmd = 0x40017e30 ); +PROVIDE ( esp_rom_opiflash_exit_continuous_read_mode = 0x40017ee8 ); +PROVIDE ( esp_rom_opiflash_mode_reset = 0x40017f90 ); +PROVIDE ( esp_rom_opiflash_pin_config = 0x400177f8 ); +PROVIDE ( esp_rom_opiflash_soft_reset = 0x40017f24 ); +PROVIDE ( esp_rom_spi_cmd_config = 0x40017c58 ); +PROVIDE ( esp_rom_spi_cmd_start = 0x40017ba8 ); +PROVIDE ( esp_rom_spi_flash_auto_sus_res = 0x400175e0 ); +PROVIDE ( esp_rom_spi_flash_auto_wait_idle = 0x4001751c ); +PROVIDE ( esp_rom_spi_flash_send_resume = 0x40017570 ); +PROVIDE ( esp_rom_spi_flash_update_id = 0x40016e44 ); +PROVIDE ( esp_rom_spi_reset_rw_mode = 0x40017984 ); +PROVIDE ( esp_rom_spi_set_dtr_swap_mode = 0x40017b60 ); +PROVIDE ( esp_rom_spi_set_op_mode = 0x400179e8 ); +PROVIDE ( _etext = 0x4001bed0 ); +PROVIDE ( ets_aes_block = 0x4000d610 ); +PROVIDE ( ets_aes_disable = 0x4000d4f8 ); +PROVIDE ( ets_aes_enable = 0x4000d4cc ); +PROVIDE ( ets_aes_set_endian = 0x4000d528 ); +PROVIDE ( ets_aes_setkey = 0x4000d594 ); +PROVIDE ( ets_aes_setkey_dec = 0x4000d5f0 ); +PROVIDE ( ets_aes_setkey_enc = 0x4000d5e0 ); +PROVIDE ( ets_bigint_disable = 0x4000d750 ); +PROVIDE ( ets_bigint_enable = 0x4000d708 ); +PROVIDE ( ets_bigint_getz = 0x4000d858 ); +PROVIDE ( ets_bigint_modexp = 0x4000d818 ); +PROVIDE ( ets_bigint_modmult = 0x4000d7f4 ); +PROVIDE ( ets_bigint_multiply = 0x4000d790 ); +PROVIDE ( ets_bigint_wait_finish = 0x4000d840 ); +PROVIDE ( ets_config_flash_by_image_hdr = 0x40010e40 ); +PROVIDE ( ets_delay_us = 0x4000d888 ); +PROVIDE ( ets_ds_disable = 0x4000d910 ); +PROVIDE ( ets_ds_enable = 0x4000d8e4 ); +PROVIDE ( ets_ds_encrypt_params = 0x4000da90 ); +PROVIDE ( ets_ds_finish_sign = 0x4000d9f8 ); +PROVIDE ( ets_ds_is_busy = 0x4000d93c ); +PROVIDE ( ets_ds_start_sign = 0x4000d96c ); +PROVIDE ( ets_efuse_cache_encryption_enabled = 0x4000e690 ); +PROVIDE ( ets_efuse_clear_program_registers = 0x4000e100 ); +PROVIDE ( ets_efuse_count_unused_key_blocks = 0x4000e2c4 ); +PROVIDE ( ets_efuse_download_modes_disabled = 0x4000e594 ); +PROVIDE ( ets_efuse_find_purpose = 0x4000e224 ); +PROVIDE ( ets_efuse_find_unused_key_block = 0x4000e2ac ); +PROVIDE ( ets_efuse_flash_opi_5pads_power_sel_vddspi = 0x4000e640 ); +PROVIDE ( ets_efuse_flash_opi_mode = 0x4000e650 ); +PROVIDE ( ets_efuse_force_send_resume = 0x4000e660 ); +PROVIDE ( ets_efuse_get_flash_delay_us = 0x4000e6d4 ); +PROVIDE ( ets_efuse_get_key_purpose = 0x4000e1b0 ); +PROVIDE ( ets_efuse_get_opiconfig = 0x4000e4fc ); +PROVIDE ( ets_efuse_get_read_register_address = 0x4000e18c ); +PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 ); +PROVIDE ( ets_efuse_get_uart_print_channel = 0x4000e5b4 ); +PROVIDE ( ets_efuse_get_uart_print_control = 0x4000e5a4 ); +PROVIDE ( ets_efuse_get_wp_pad = 0x4000e444 ); +PROVIDE ( ets_efuse_key_block_unused = 0x4000e250 ); +PROVIDE ( ets_efuse_legacy_spi_boot_mode_disabled = 0x4000e6b0 ); +PROVIDE ( ets_efuse_program = 0x4000e134 ); +PROVIDE ( ets_efuse_read = 0x4000e0c0 ); +PROVIDE ( ets_efuse_rs_calculate = 0x4000e6f8 ); +PROVIDE ( ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000e680 ); +PROVIDE ( ets_efuse_secure_boot_enabled = 0x4000e670 ); +PROVIDE ( ets_efuse_security_download_modes_enabled = 0x4000e5d4 ); +PROVIDE ( ets_efuse_set_timing = 0x4000df3c ); +PROVIDE ( ets_efuse_start = 0x4000e084 ); +PROVIDE ( ets_efuse_usb_download_mode_disabled = 0x4000e5f4 ); +PROVIDE ( ets_efuse_usb_force_nopersist = 0x4000e630 ); +PROVIDE ( ets_efuse_usb_module_disabled = 0x4000e5c4 ); +PROVIDE ( ets_efuse_usb_use_ext_phy = 0x4000e620 ); +PROVIDE ( ets_efuse_write_key = 0x4000e2f4 ); +PROVIDE ( ets_emsa_pss_verify = 0x40011818 ); +PROVIDE ( ets_get_apb_freq = 0x40010c58 ); +PROVIDE ( ets_get_cpu_frequency = 0x4000d8b0 ); +PROVIDE ( ets_get_printf_channel = 0x4000ff48 ); +PROVIDE ( ets_get_xtal_div = 0x40010bfc ); +PROVIDE ( ets_get_xtal_freq = 0x40010c38 ); +PROVIDE ( ets_hmac_calculate_downstream = 0x4000f120 ); +PROVIDE ( ets_hmac_calculate_message = 0x4000f020 ); +PROVIDE ( ets_hmac_disable = 0x4000eff4 ); +PROVIDE ( ets_hmac_enable = 0x4000efd8 ); +PROVIDE ( ets_hmac_invalidate_downstream = 0x4000f140 ); +PROVIDE ( ets_install_lock = 0x4000fea0 ); +PROVIDE ( ets_install_putc1 = 0x4000feb0 ); +PROVIDE ( ets_install_putc2 = 0x4000fed0 ); +PROVIDE ( ets_install_uart_printf = 0x4000fec0 ); +PROVIDE ( ets_intr_count = 0x3fffe710 ); +PROVIDE ( ets_intr_lock = 0x4000f168 ); +PROVIDE ( ets_intr_unlock = 0x4000f17c ); +PROVIDE ( ets_is_print_boot = 0x4000f2a0 ); +PROVIDE ( ets_isr_attach = 0x4000f1a4 ); +PROVIDE ( ets_isr_mask = 0x4000f1b4 ); +PROVIDE ( ets_isr_unmask = 0x4000f1c0 ); +PROVIDE ( ets_jtag_enable_temporarily = 0x4000e548 ); +PROVIDE ( ets_loader_map_range = 0x40010d4c ); +PROVIDE ( ets_mgf1_sha256 = 0x400117b0 ); +PROVIDE ( ets_printf = 0x4000fee0 ); +PROVIDE ( ets_printf_lock = 0x3ffffd64 ); +PROVIDE ( ets_printf_uart = 0x3ffffd5c ); +PROVIDE ( ets_printf_unlock = 0x3ffffd60 ); +PROVIDE ( ets_rsa_pss_verify = 0x4001191c ); +PROVIDE ( ets_run_flash_bootloader = 0x40010f58 ); +PROVIDE ( ets_secure_boot_read_key_digests = 0x400101ac ); +PROVIDE ( ets_secure_boot_revoke_public_key_digest = 0x4001025c ); +PROVIDE ( ets_secure_boot_verify_bootloader_with_keys = 0x40010444 ); +PROVIDE ( ets_secure_boot_verify_signature = 0x400102cc ); +PROVIDE ( ets_secure_boot_verify_stage_bootloader = 0x40010720 ); +PROVIDE ( ets_set_printf_channel = 0x4000ff3c ); +PROVIDE ( ets_set_user_start = 0x4000f25c ); +PROVIDE ( ets_set_xtal_div = 0x40010c18 ); +PROVIDE ( ets_sha_clone = 0x4001095c ); +PROVIDE ( ets_sha_disable = 0x400107b4 ); +PROVIDE ( ets_sha_enable = 0x40010788 ); +PROVIDE ( ets_sha_finish = 0x40010ab8 ); +PROVIDE ( ets_sha_get_state = 0x40010934 ); +PROVIDE ( ets_sha_init = 0x400107e0 ); +PROVIDE ( ets_sha_process = 0x40010988 ); +PROVIDE ( ets_sha_starts = 0x40010828 ); +PROVIDE ( ets_sha_update = 0x400109f8 ); +PROVIDE ( ets_startup_callback = 0x3fffe718 ); +PROVIDE ( ets_unpack_flash_code_legacy = 0x40011430 ); +PROVIDE ( ets_update_cpu_frequency = 0x4000d8a4 ); +PROVIDE ( ets_vprintf = 0x4000fa3c ); +PROVIDE ( ets_waiti0 = 0x4000f190 ); +PROVIDE ( ets_wdt_reset_cpu = 0x4001a82c ); +PROVIDE ( ets_write_char = 0x4000f974 ); +PROVIDE ( ets_write_char_uart = 0x4000f998 ); +PROVIDE ( exc_cause_table = 0x3ffacbe8 ); +PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40011ed8 ); +PROVIDE ( FilePacketSendReqMsgProc = 0x40011bd8 ); +PROVIDE ( flashchip = 0x3ffffd38 ); +PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40011e80 ); +PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x40011cc0 ); +PROVIDE ( FlashDwnLdStartMsgProc = 0x40011b74 ); +PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40011fd8 ); +PROVIDE ( FlashDwnLdStopReqMsgProc = 0x40011c90 ); +PROVIDE ( general_device_descr = 0x3ffffa58 ); +PROVIDE ( _GeneralException = 0x400073cf ); +PROVIDE ( get_id = 0x4001610c ); +PROVIDE ( GetSecurityInfoProc = 0x40012098 ); +PROVIDE ( GetUartDevice = 0x40012f60 ); +PROVIDE ( g_phyFuns = 0x3ffffd90 ); +PROVIDE ( g_phyFuns_instance = 0x3ffffd94 ); +PROVIDE ( gpio_input_get = 0x400193a0 ); +PROVIDE ( gpio_input_get_high = 0x400193b4 ); +PROVIDE ( gpio_matrix_in = 0x40019430 ); +PROVIDE ( gpio_matrix_out = 0x40019460 ); +PROVIDE ( gpio_output_disable = 0x400194dc ); +PROVIDE ( gpio_output_enable = 0x400194b0 ); +PROVIDE ( gpio_output_set = 0x4001933c ); +PROVIDE ( gpio_output_set_high = 0x40019374 ); +PROVIDE ( gpio_pad_hold = 0x40019654 ); +PROVIDE ( gpio_pad_input_disable = 0x400195f0 ); +PROVIDE ( gpio_pad_input_enable = 0x400195cc ); +PROVIDE ( gpio_pad_pulldown = 0x40019598 ); +PROVIDE ( gpio_pad_pullup = 0x40019564 ); +PROVIDE ( gpio_pad_select_gpio = 0x40019510 ); +PROVIDE ( gpio_pad_set_drv = 0x40019538 ); +PROVIDE ( gpio_pad_unhold = 0x4001961c ); +PROVIDE ( gpio_pin_wakeup_disable = 0x40019404 ); +PROVIDE ( gpio_pin_wakeup_enable = 0x400193c8 ); +PROVIDE ( g_shared_buffers = 0x3ffeab04 ); +PROVIDE ( g_ticks_per_us = 0x3ffffd70 ); +PROVIDE ( hmac_md5 = 0x40005490 ); +PROVIDE ( hmac_md5_vector = 0x400053a0 ); +PROVIDE ( ibus_baseaddrs = 0x3ffaf03c ); +PROVIDE ( intr_matrix_set = 0x4000f1d0 ); PROVIDE ( _iram0_text_end = 0x40000540 ); PROVIDE ( _iram0_text_start = 0x40000540 ); PROVIDE ( _iram1_text_end = 0x60021100 ); PROVIDE ( _iram1_text_start = 0x60021100 ); -PROVIDE ( isalnum = 0x40007cb4 ); -PROVIDE ( isalpha = 0x40007cc4 ); -PROVIDE ( isascii = 0x40015d18 ); -PROVIDE ( _isatty_r = 0x40007c7c ); -PROVIDE ( isblank = 0x40007cd4 ); -PROVIDE ( iscntrl = 0x40007cf4 ); -PROVIDE ( isdigit = 0x40007d0c ); -PROVIDE ( isgraph = 0x40007d44 ); -PROVIDE ( islower = 0x40007d24 ); -PROVIDE ( isprint = 0x40007d5c ); -PROVIDE ( ispunct = 0x40007d70 ); -PROVIDE ( isspace = 0x40007d88 ); -PROVIDE ( isupper = 0x40007da0 ); -PROVIDE ( itoa = 0x40000acc ); -PROVIDE ( __itoa = 0x40000a90 ); PROVIDE ( _KernelExceptionVector = 0x40000300 ); PROVIDE ( _KernelExceptionVector_text_end = 0x40000306 ); PROVIDE ( _KernelExceptionVector_text_start = 0x40000300 ); -PROVIDE ( _kill_r = 0x4001534c ); -PROVIDE ( labs = 0x4000076c ); -PROVIDE ( ldiv = 0x40000774 ); -PROVIDE ( _Level2FromVector = 0x400078d4 ); +PROVIDE ( _Level2FromVector = 0x400074f8 ); PROVIDE ( _Level2HandlerLabel = 0x00000000 ); PROVIDE ( _Level2InterruptVector_text_end = 0x40000186 ); PROVIDE ( _Level2InterruptVector_text_start = 0x40000180 ); PROVIDE ( _Level2Vector = 0x40000180 ); -PROVIDE ( _Level3FromVector = 0x40007970 ); +PROVIDE ( _Level3FromVector = 0x40007594 ); PROVIDE ( _Level3HandlerLabel = 0x00000000 ); PROVIDE ( _Level3InterruptVector_text_end = 0x400001c6 ); PROVIDE ( _Level3InterruptVector_text_start = 0x400001c0 ); PROVIDE ( _Level3Vector = 0x400001c0 ); -PROVIDE ( _Level4FromVector = 0x40007a08 ); +PROVIDE ( _Level4FromVector = 0x4000762c ); PROVIDE ( _Level4HandlerLabel = 0x00000000 ); PROVIDE ( _Level4InterruptVector_text_end = 0x40000206 ); PROVIDE ( _Level4InterruptVector_text_start = 0x40000200 ); PROVIDE ( _Level4Vector = 0x40000200 ); -PROVIDE ( _Level5FromVector = 0x40007b38 ); +PROVIDE ( _Level5FromVector = 0x4000775c ); PROVIDE ( _Level5HandlerLabel = 0x00000000 ); PROVIDE ( _Level5InterruptVector_text_end = 0x40000246 ); PROVIDE ( _Level5InterruptVector_text_start = 0x40000240 ); PROVIDE ( _Level5Vector = 0x40000240 ); -PROVIDE ( _LevelOneInterrupt = 0x400077e6 ); -PROVIDE ( _link_r = 0x400152d8 ); +PROVIDE ( _LevelOneInterrupt = 0x4000740a ); PROVIDE ( _lit4_end = 0x40000540 ); PROVIDE ( _lit4_start = 0x40000540 ); -PROVIDE ( lldesc_build_chain = 0x4000a784 ); -PROVIDE ( lldesc_num2link = 0x4000a874 ); -PROVIDE ( lldesc_set_owner = 0x4000a8a0 ); -PROVIDE ( __locale_ctype_ptr = 0x40002008 ); -PROVIDE ( __locale_ctype_ptr_l = 0x40002000 ); -PROVIDE ( __locale_mb_cur_max = 0x40001fe8 ); -PROVIDE ( _lock_acquire = 0x40015450 ); -PROVIDE ( _lock_acquire_recursive = 0x40015464 ); -PROVIDE ( _lock_close = 0x40015428 ); -PROVIDE ( _lock_close_recursive = 0x4001543c ); -PROVIDE ( _lock_init = 0x40015400 ); -PROVIDE ( _lock_init_recursive = 0x40015414 ); -PROVIDE ( _lock_release = 0x400154a0 ); -PROVIDE ( _lock_release_recursive = 0x400154b4 ); -PROVIDE ( _lock_try_acquire = 0x40015478 ); -PROVIDE ( _lock_try_acquire_recursive = 0x4001548c ); -PROVIDE ( longjmp = 0x400006c8 ); -PROVIDE ( _lseek_r = 0x400153c8 ); -PROVIDE ( main = 0x4000c390 ); -PROVIDE ( malloc = 0x400154dc ); -PROVIDE ( _malloc_r = 0x400151f0 ); -PROVIDE ( _mbtowc_r = 0x40007dbc ); -PROVIDE ( MD5Final = 0x400056e8 ); -PROVIDE ( MD5Init = 0x40005648 ); -PROVIDE ( MD5Update = 0x40005668 ); -PROVIDE ( md5_vector = 0x40005750 ); -PROVIDE ( memccpy = 0x40015d2c ); -PROVIDE ( memchr = 0x40015d50 ); -PROVIDE ( memcmp = 0x40015d6c ); -PROVIDE ( memcpy = 0x40015dd4 ); -PROVIDE ( MemDwnLdStartMsgProc = 0x4000ea34 ); -PROVIDE ( MemDwnLdStopReqMsgProc = 0x4000eac8 ); +PROVIDE ( lldesc_build_chain = 0x4000907c ); +PROVIDE ( lldesc_num2link = 0x4000916c ); +PROVIDE ( lldesc_set_owner = 0x40009198 ); +PROVIDE ( lldesc_setup = 0x40019ed8 ); +PROVIDE ( main = 0x4000f6c4 ); +PROVIDE ( MD5Final = 0x4000530c ); +PROVIDE ( MD5Init = 0x4000526c ); +PROVIDE ( MD5Update = 0x4000528c ); +PROVIDE ( md5_vector = 0x40005374 ); +PROVIDE ( MemDwnLdStartMsgProc = 0x40011cec ); +PROVIDE ( MemDwnLdStopReqMsgProc = 0x40011d80 ); PROVIDE ( _memmap_cacheattr_bp_allvalid = 0x22222222 ); PROVIDE ( _memmap_cacheattr_bp_base = 0x00000220 ); PROVIDE ( _memmap_cacheattr_bp_strict = 0xfffff22f ); @@ -490,430 +417,333 @@ PROVIDE ( _memmap_cacheattr_wt_base = 0x00000110 ); PROVIDE ( _memmap_cacheattr_wt_strict = 0xfffff11f ); PROVIDE ( _memmap_cacheattr_wt_trapnull = 0x2222211f ); PROVIDE ( _memmap_vecbase_reset = 0x40000000 ); -PROVIDE ( memmove = 0x40015edc ); -PROVIDE ( MemPacketSendReqMsgProc = 0x4000ea64 ); -PROVIDE ( memrchr = 0x40015f18 ); -PROVIDE ( memset = 0x40015f68 ); -PROVIDE ( MMU_Drom0_I2D_Copy = 0x40014788 ); -PROVIDE ( MMU_Drom_ICache_Unmap = 0x400147a0 ); -PROVIDE ( multofup = 0x40009d90 ); -PROVIDE ( mz_adler32 = 0x4000326c ); -PROVIDE ( mz_crc32 = 0x40003334 ); -PROVIDE ( mz_free = 0x40003380 ); +PROVIDE ( MemPacketSendReqMsgProc = 0x40011d1c ); +PROVIDE ( multofup = 0x4001bce0 ); +PROVIDE ( must_reset = 0x3ffffcf4 ); +PROVIDE ( mz_adler32 = 0x40002e90 ); +PROVIDE ( mz_crc32 = 0x40002f58 ); +PROVIDE ( mz_free = 0x40002fa4 ); PROVIDE ( _NMIExceptionVector = 0x400002c0 ); PROVIDE ( _NMIExceptionVector_text_end = 0x400002c3 ); PROVIDE ( _NMIExceptionVector_text_start = 0x400002c0 ); -PROVIDE ( open = 0x400084a0 ); -PROVIDE ( _open_r = 0x40015390 ); -PROVIDE ( __packed = 0x3fffc530 ); -PROVIDE ( _PathLocale = 0x3fffc040 ); -PROVIDE ( phy_get_romfuncs = 0x4000a8d4 ); -PROVIDE ( _Pri_4_HandlerAddress = 0x3fffcfa8 ); -PROVIDE ( _Pri_5_HandlerAddress = 0x3fffcfac ); -PROVIDE ( _printf_common = 0x4000123c ); -PROVIDE ( _printf_float = 0x40015538 ); -PROVIDE ( _printf_i = 0x40001308 ); -PROVIDE ( pthread_setcancelstate = 0x400151d4 ); -PROVIDE ( _putc1 = 0x3fffc01c ); -PROVIDE ( _putc2 = 0x3fffc018 ); -PROVIDE ( qsort = 0x40000818 ); -PROVIDE ( _raise_r = 0x400152ac ); -PROVIDE ( rand = 0x40007e54 ); -PROVIDE ( rand_r = 0x40007ed0 ); -PROVIDE ( RcvMsg = 0x4000fb60 ); -PROVIDE ( read = 0x400084f0 ); -PROVIDE ( _read_r = 0x400153e4 ); -PROVIDE ( realloc = 0x40015508 ); -PROVIDE ( _realloc_r = 0x4001521c ); -PROVIDE ( RecvBuff = 0x3fffc9c8 ); -PROVIDE ( recv_packet = 0x4000fa34 ); -PROVIDE ( _rename_r = 0x40015264 ); +PROVIDE ( phy_get_romfuncs = 0x4000a88c ); +PROVIDE ( _Pri_4_HandlerAddress = 0x3fffed78 ); +PROVIDE ( _Pri_5_HandlerAddress = 0x3fffed7c ); +PROVIDE ( _putc1 = 0x3ffffd6c ); +PROVIDE ( _putc2 = 0x3ffffd68 ); +PROVIDE ( RcvMsg = 0x40012f10 ); +PROVIDE ( recv_packet = 0x40012de8 ); PROVIDE ( _ResetHandler = 0x4000044c ); PROVIDE ( _ResetVector = 0x40000400 ); PROVIDE ( _ResetVector_literal_end = 0x40000540 ); PROVIDE ( _ResetVector_literal_start = 0x40000540 ); PROVIDE ( _ResetVector_text_end = 0x4000053d ); PROVIDE ( _ResetVector_text_start = 0x40000400 ); -PROVIDE ( _rodata_end = 0x3ffaf840 ); -PROVIDE ( _rodata_start = 0x3ffab800 ); -PROVIDE ( rom_abs_temp = 0x40019428 ); -PROVIDE ( rom_bb_bss_bw_40_en = 0x40017ec8 ); -PROVIDE ( rom_bb_bss_cbw40_dig = 0x40017968 ); -PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40017580 ); -PROVIDE ( rom_bb_tx_ht20_cen = 0x400175ac ); -PROVIDE ( rom_bb_wdg_test_en = 0x40017900 ); -PROVIDE ( rom_bb_wdt_get_status = 0x40017c00 ); -PROVIDE ( rom_bb_wdt_int_enable = 0x40017bc0 ); -PROVIDE ( rom_bb_wdt_rst_enable = 0x40017b9c ); -PROVIDE ( rom_bb_wdt_timeout_clear = 0x40017be4 ); -PROVIDE ( rom_cbw2040_cfg = 0x40017fb4 ); -PROVIDE ( rom_check_noise_floor = 0x40017a30 ); -PROVIDE ( rom_chip_i2c_readReg = 0x40018120 ); -PROVIDE ( rom_chip_i2c_writeReg = 0x4001819c ); -PROVIDE ( rom_chip_sleep_prot_dis = 0x40017940 ); -PROVIDE ( rom_chip_sleep_prot_en = 0x40017e0c ); -PROVIDE ( rom_clk_force_on_vit = 0x4001755c ); -PROVIDE ( rom_correct_rf_ana_gain = 0x40019eb4 ); -PROVIDE ( rom_dc_iq_est = 0x40019504 ); -PROVIDE ( rom_disable_agc = 0x40017138 ); -PROVIDE ( rom_enable_agc = 0x40017150 ); -PROVIDE ( rom_en_pwdet = 0x40019014 ); -PROVIDE ( rom_gen_rx_gain_table = 0x40017cec ); -PROVIDE ( rom_get_bbgain_db = 0x400172f4 ); -PROVIDE ( rom_get_data_sat = 0x400172a4 ); -PROVIDE ( rom_get_fm_sar_dout = 0x40019148 ); -PROVIDE ( rom_get_i2c_read_mask = 0x400180fc ); -PROVIDE ( rom_get_power_db = 0x40019c04 ); -PROVIDE ( rom_get_pwctrl_correct = 0x4001a070 ); -PROVIDE ( rom_get_rfcal_rxiq_data = 0x40019860 ); -PROVIDE ( rom_get_rf_gain_qdb = 0x40019e9c ); -PROVIDE ( rom_get_sar_dout = 0x4001a000 ); -PROVIDE ( rom_i2c_readReg = 0x4001817c ); -PROVIDE ( rom_i2c_readReg_Mask = 0x40018200 ); -PROVIDE ( rom_i2c_writeReg = 0x400181e4 ); -PROVIDE ( rom_i2c_writeReg_Mask = 0x4001823c ); -PROVIDE ( rom_index_to_txbbgain = 0x40018d20 ); -PROVIDE ( rom_iq_est_disable = 0x400194c8 ); -PROVIDE ( rom_iq_est_enable = 0x4001944c ); -PROVIDE ( rom_linear_to_db = 0x40019b98 ); -PROVIDE ( rom_loopback_mode_en = 0x40017270 ); -PROVIDE ( rom_meas_tone_pwr_db = 0x40019c40 ); -PROVIDE ( rom_mhz2ieee = 0x40017f54 ); -PROVIDE ( rom_noise_floor_auto_set = 0x40017998 ); -PROVIDE ( rom_pbus_debugmode = 0x4001849c ); -PROVIDE ( rom_pbus_force_mode = 0x400182ac ); -PROVIDE ( rom_pbus_force_test = 0x400183fc ); -PROVIDE ( rom_pbus_rd = 0x40018458 ); -PROVIDE ( rom_pbus_rd_addr = 0x40018374 ); -PROVIDE ( rom_pbus_rd_shift = 0x400183b4 ); -PROVIDE ( rom_pbus_set_dco = 0x4001867c ); -PROVIDE ( rom_pbus_set_rxgain = 0x400184c4 ); -PROVIDE ( rom_pbus_workmode = 0x400184b0 ); -PROVIDE ( rom_pbus_xpd_rx_off = 0x4001854c ); -PROVIDE ( rom_pbus_xpd_rx_on = 0x40018580 ); -PROVIDE ( rom_pbus_xpd_tx_off = 0x400185d4 ); -PROVIDE ( rom_pbus_xpd_tx_on = 0x40018624 ); -PROVIDE ( rom_phy_byte_to_word = 0x40017cbc ); -PROVIDE ( rom_phy_chan_filt_set = 0x4001801c ); -PROVIDE ( rom_phy_disable_agc = 0x40017104 ); -PROVIDE ( rom_phy_disable_cca = 0x40017174 ); -PROVIDE ( rom_phy_enable_agc = 0x40017120 ); -PROVIDE ( rom_phy_enable_cca = 0x400171a0 ); -PROVIDE ( rom_phy_freq_correct = 0x40018a84 ); -PROVIDE ( rom_phyFuns = 0x3fffc050 ); -PROVIDE ( rom_phy_get_noisefloor = 0x400179e8 ); -PROVIDE ( rom_phy_get_rx_freq = 0x400180b4 ); -PROVIDE ( rom_phy_get_tx_rate = 0x40017c38 ); -PROVIDE ( rom_phy_rx11blr_cfg = 0x40017b40 ); -PROVIDE ( rom_phy_set_bbfreq_init = 0x40019fd0 ); -PROVIDE ( rom_pow_usr = 0x400171b8 ); -PROVIDE ( rom_pwdet_sar2_init = 0x40018f68 ); -PROVIDE ( rom_read_hw_noisefloor = 0x40017b1c ); -PROVIDE ( rom_read_sar_dout = 0x40019120 ); -PROVIDE ( rom_restart_cal = 0x400186c4 ); -PROVIDE ( rom_rfbt_init = 0x40018cbc ); -PROVIDE ( rom_rfcal_pwrctrl = 0x40019c98 ); -PROVIDE ( rom_rfcal_rxiq = 0x400197ec ); -PROVIDE ( rom_rfcal_txcap = 0x40019a68 ); -PROVIDE ( rom_rfpll_set_freq = 0x400187d0 ); -PROVIDE ( rom_rfrx_init = 0x40018c1c ); -PROVIDE ( rom_rftx_init = 0x40018c48 ); -PROVIDE ( rom_rtc_mem_backup = 0x40017c4c ); -PROVIDE ( rom_rtc_mem_recovery = 0x40017c84 ); -PROVIDE ( rom_rx_gain_force = 0x40017364 ); -PROVIDE ( rom_rxiq_cover_mg_mp = 0x40019708 ); -PROVIDE ( rom_rxiq_get_mis = 0x4001958c ); -PROVIDE ( rom_rxiq_set_reg = 0x400196a0 ); -PROVIDE ( rom_set_cal_rxdc = 0x40017230 ); -PROVIDE ( rom_set_chan_cal_interp = 0x40019954 ); -PROVIDE ( rom_set_channel_freq = 0x40018840 ); -PROVIDE ( rom_set_loopback_gain = 0x400171d4 ); -PROVIDE ( rom_set_noise_floor = 0x40017ad8 ); -PROVIDE ( rom_set_rf_freq_offset = 0x40018be4 ); -PROVIDE ( rom_set_rxclk_en = 0x400173dc ); -PROVIDE ( rom_set_txcap_reg = 0x400199e4 ); -PROVIDE ( rom_set_txclk_en = 0x400173ac ); -PROVIDE ( rom_set_tx_dig_gain = 0x4001731c ); -PROVIDE ( rom_spur_cal = 0x40017ee8 ); -PROVIDE ( rom_spur_reg_write_one_tone = 0x4001763c ); -PROVIDE ( rom_start_tx_tone = 0x40017500 ); -PROVIDE ( rom_start_tx_tone_step = 0x40017418 ); -PROVIDE ( rom_stop_tx_tone = 0x40017e74 ); -PROVIDE ( _rom_store = 0x400170fc ); -PROVIDE ( _rom_store_table = 0x40016f74 ); -PROVIDE ( rom_target_power_add_backoff = 0x40019e78 ); -PROVIDE ( rom_txbbgain_to_index = 0x40018cf0 ); -PROVIDE ( rom_txcal_work_mode = 0x4001907c ); -PROVIDE ( rom_txdc_cal_init = 0x40018d3c ); -PROVIDE ( rom_txdc_cal_v70 = 0x40018dd4 ); -PROVIDE ( rom_txiq_cover = 0x400192d8 ); -PROVIDE ( rom_txiq_get_mis_pwr = 0x40019224 ); -PROVIDE ( rom_txiq_set_reg = 0x400190b0 ); -PROVIDE ( rom_tx_pwctrl_bg_init = 0x4001a0c4 ); -PROVIDE ( rom_txtone_linear_pwr = 0x400191d8 ); -PROVIDE ( rom_wait_rfpll_cal_end = 0x4001878c ); -PROVIDE ( rom_wifi_11g_rate_chg = 0x40019e60 ); -PROVIDE ( rom_wifi_rifs_mode_en = 0x40017c14 ); -PROVIDE ( rom_write_gain_mem = 0x400172c4 ); -PROVIDE ( rom_write_rfpll_sdm = 0x40018724 ); -PROVIDE ( roundup2 = 0x40009d80 ); -PROVIDE ( rtc_boot_control = 0x4000cd28 ); -PROVIDE ( rtc_get_reset_reason = 0x4000cc5c ); -PROVIDE ( rtc_get_wakeup_cause = 0x4000cc7c ); -PROVIDE ( rtc_select_apb_bridge = 0x4000cda0 ); -PROVIDE ( sbrk = 0x40008508 ); -PROVIDE ( _sbrk_r = 0x40015320 ); -PROVIDE ( _scanf_float = 0x40015554 ); -PROVIDE ( s_cdcacm_old_dtr = 0x3fffc9c4 ); -PROVIDE ( __sclose = 0x4001592c ); -PROVIDE ( sdio_slave_mode_init = 0x40009614 ); -PROVIDE ( sdio_slave_pads_init = 0x40009554 ); -PROVIDE ( SelectSpiFunction = 0x40012434 ); -PROVIDE ( SelectSpiQIO = 0x400122b8 ); -PROVIDE ( SendMsg = 0x4000f958 ); -PROVIDE ( send_packet = 0x4000f914 ); -PROVIDE ( __seofread = 0x400158bc ); -PROVIDE ( setjmp = 0x40000664 ); -PROVIDE ( setlocale = 0x40002020 ); -PROVIDE ( _setlocale_r = 0x40001fb8 ); -PROVIDE ( set_rtc_memory_crc = 0x4000cd0c ); -PROVIDE ( SetSpiDrvs = 0x40012348 ); -PROVIDE ( __sf_fake_stderr = 0x3ffae938 ); -PROVIDE ( __sf_fake_stdin = 0x3ffae978 ); -PROVIDE ( __sf_fake_stdout = 0x3ffae958 ); -PROVIDE ( __sflush_r = 0x40001db8 ); -PROVIDE ( __sfmoreglue = 0x400156f4 ); -PROVIDE ( __sfp = 0x400157bc ); -PROVIDE ( __sfp_lock_acquire = 0x40015734 ); -PROVIDE ( __sfp_lock_release = 0x40015740 ); -PROVIDE ( __sfputs_r = 0x40000e7c ); -PROVIDE ( __sfvwrite_r = 0x400016ec ); -PROVIDE ( sig_matrix = 0x3fffc253 ); -PROVIDE ( __sinit = 0x40015764 ); -PROVIDE ( __sinit_lock_acquire = 0x4001574c ); -PROVIDE ( __sinit_lock_release = 0x40015758 ); -PROVIDE ( sip_after_tx_complete = 0x4000a57c ); -PROVIDE ( sip_alloc_to_host_evt = 0x40009da4 ); -PROVIDE ( sip_download_begin = 0x4000a03c ); -PROVIDE ( sip_get_ptr = 0x4000a570 ); -PROVIDE ( sip_get_state = 0x4000a050 ); -PROVIDE ( sip_init_attach = 0x4000a07c ); -PROVIDE ( sip_install_rx_ctrl_cb = 0x4000a020 ); -PROVIDE ( sip_install_rx_data_cb = 0x4000a030 ); -PROVIDE ( sip_is_active = 0x4000a5e4 ); -PROVIDE ( sip_post_init = 0x4000a0fc ); -PROVIDE ( sip_reclaim_from_host_cmd = 0x40009fcc ); -PROVIDE ( sip_reclaim_tx_data_pkt = 0x40009f70 ); -PROVIDE ( sip_send = 0x4000a178 ); -PROVIDE ( sip_to_host_chain_append = 0x4000a11c ); -PROVIDE ( sip_to_host_evt_send_done = 0x40009e10 ); -PROVIDE ( slc_add_credits = 0x40009b00 ); -PROVIDE ( slc_enable = 0x4000967c ); -PROVIDE ( slc_from_host_chain_fetch = 0x40009830 ); -PROVIDE ( slc_from_host_chain_recycle = 0x40009b20 ); -PROVIDE ( slc_has_pkt_to_host = 0x400094f0 ); -PROVIDE ( slc_init_attach = 0x40009950 ); -PROVIDE ( slc_init_credit = 0x40009ae4 ); -PROVIDE ( slc_reattach = 0x40009528 ); -PROVIDE ( slc_send_to_host_chain = 0x400096d8 ); -PROVIDE ( slc_set_host_io_max_window = 0x400098e4 ); -PROVIDE ( slc_to_host_chain_recycle = 0x4000979c ); -PROVIDE ( __smakebuf_r = 0x40001d30 ); -PROVIDE ( software_reset = 0x4000cd64 ); -PROVIDE ( software_reset_cpu = 0x4000cd7c ); -PROVIDE ( SPI_block_erase = 0x400127fc ); -PROVIDE ( spi_cache_mode_switch = 0x40012d94 ); -PROVIDE ( SPI_chip_erase = 0x40012794 ); -PROVIDE ( SPIClkConfig = 0x40013294 ); -PROVIDE ( SPI_Common_Command = 0x40012950 ); -PROVIDE ( spi_dummy_len_fix = 0x40012280 ); -PROVIDE ( SPI_Encrypt_Write = 0x400138b8 ); -PROVIDE ( SPI_Encrypt_Write_Dest = 0x400137a4 ); -PROVIDE ( SPIEraseArea = 0x400136a0 ); -PROVIDE ( SPIEraseBlock = 0x40013300 ); -PROVIDE ( SPIEraseChip = 0x400132e0 ); -PROVIDE ( SPIEraseSector = 0x40013360 ); -PROVIDE ( spi_flash_attach = 0x40013214 ); -PROVIDE ( SPI_flashchip_data = 0x3fffc234 ); -PROVIDE ( SPI_init = 0x40012fb4 ); -PROVIDE ( SPILock = 0x40013134 ); -PROVIDE ( SPIMasterReadModeCnfig = 0x40013230 ); -PROVIDE ( SPI_page_program = 0x40012c00 ); -PROVIDE ( SPIParamCfg = 0x40013730 ); -PROVIDE ( SPIRead = 0x40013484 ); -PROVIDE ( SPI_read_data = 0x40012834 ); -PROVIDE ( SPIReadModeCnfig = 0x4001317c ); -PROVIDE ( SPI_read_status = 0x400126b8 ); -PROVIDE ( SPI_read_status_high = 0x400128fc ); -PROVIDE ( SPI_sector_erase = 0x400127bc ); -PROVIDE ( SPIUnlock = 0x400130e8 ); -PROVIDE ( SPI_user_command_read = 0x400125fc ); -PROVIDE ( SPI_Wait_Idle = 0x40012cc4 ); -PROVIDE ( SPI_WakeUp = 0x40012714 ); -PROVIDE ( SPIWrite = 0x400133c0 ); -PROVIDE ( SPI_write_enable = 0x40012bc4 ); -PROVIDE ( SPI_Write_Encrypt_Disable = 0x40013768 ); -PROVIDE ( SPI_Write_Encrypt_Enable = 0x4001374c ); -PROVIDE ( SPI_write_status = 0x4001291c ); -PROVIDE ( __sprint_r = 0x40000ec8 ); -PROVIDE ( srand = 0x40007e00 ); -PROVIDE ( __sread = 0x4001588c ); -PROVIDE ( __sseek = 0x400158f8 ); -PROVIDE ( __stack = 0x40000000 ); -PROVIDE ( _stack_sentry = 0x3fffdd10 ); -PROVIDE ( _start = 0x40007648 ); -PROVIDE ( _stat_r = 0x400152f0 ); -PROVIDE ( _stext = 0x400074f4 ); -PROVIDE ( strcasecmp = 0x40007f14 ); -PROVIDE ( strcasestr = 0x40007f58 ); -PROVIDE ( strcat = 0x40015fbc ); -PROVIDE ( strchr = 0x40015fdc ); -PROVIDE ( strcmp = 0x40007fc0 ); -PROVIDE ( strcoll = 0x400080c4 ); -PROVIDE ( strcpy = 0x400080d8 ); -PROVIDE ( strcspn = 0x40015ff8 ); -PROVIDE ( strdup = 0x40008160 ); -PROVIDE ( _strdup_r = 0x40008174 ); -PROVIDE ( string0_descr = 0x3ffae83a ); -PROVIDE ( strlcat = 0x40008194 ); -PROVIDE ( strlcpy = 0x40016024 ); -PROVIDE ( strlen = 0x400081e4 ); -PROVIDE ( strlwr = 0x40008244 ); -PROVIDE ( str_manu_descr = 0x3ffae826 ); -PROVIDE ( strncasecmp = 0x40008270 ); -PROVIDE ( strncat = 0x40016060 ); -PROVIDE ( strncmp = 0x40016090 ); -PROVIDE ( strncpy = 0x400082fc ); -PROVIDE ( strndup = 0x400083c4 ); -PROVIDE ( _strndup_r = 0x400083d8 ); -PROVIDE ( strnlen = 0x400160c8 ); -PROVIDE ( str_prod_descr = 0x3ffae7ec ); -PROVIDE ( str_prod_dfu_descr = 0x3ffae7d0 ); -PROVIDE ( strrchr = 0x4000841c ); -PROVIDE ( strsep = 0x40008448 ); -PROVIDE ( str_serial_descr = 0x3ffae7e8 ); -PROVIDE ( strspn = 0x400160e8 ); -PROVIDE ( strstr = 0x40016114 ); -PROVIDE ( __strtok_r = 0x40016144 ); -PROVIDE ( strtok_r = 0x400161a8 ); -PROVIDE ( strtol = 0x40000c70 ); -PROVIDE ( strtol_l = 0x40000c58 ); -PROVIDE ( _strtol_r = 0x40000c34 ); -PROVIDE ( strtoul = 0x40000dcc ); -PROVIDE ( strtoul_l = 0x40000db4 ); -PROVIDE ( _strtoul_r = 0x40000d90 ); -PROVIDE ( strupr = 0x40008460 ); -PROVIDE ( s_usb_osglue = 0x3fffc520 ); -PROVIDE ( __swbuf = 0x40001a58 ); -PROVIDE ( __swbuf_r = 0x40001998 ); -PROVIDE ( __swhatbuf_r = 0x40001cd4 ); -PROVIDE ( __swrite = 0x400158c4 ); -PROVIDE ( __swsetup_r = 0x40001a6c ); -PROVIDE ( _SyscallException = 0x40007706 ); -PROVIDE ( syscall_table_ptr_app = 0x3fffc020 ); -PROVIDE ( syscall_table_ptr_pro = 0x3fffc024 ); -PROVIDE ( _system_r = 0x4001524c ); -PROVIDE ( tdefl_compress = 0x400045b8 ); -PROVIDE ( tdefl_compress_buffer = 0x40004d14 ); -PROVIDE ( tdefl_compress_mem_to_mem = 0x40004e2c ); -PROVIDE ( tdefl_compress_mem_to_output = 0x40004e0c ); -PROVIDE ( tdefl_get_adler32 = 0x40004e04 ); -PROVIDE ( tdefl_get_prev_return_status = 0x40004dfc ); -PROVIDE ( tdefl_init = 0x40004d30 ); -PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x40004e40 ); -PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40004e34 ); -PROVIDE ( _text_end = 0x400170fc ); -PROVIDE ( _text_start = 0x400074f4 ); -PROVIDE ( _times_r = 0x4001527c ); -PROVIDE ( tinfl_decompress = 0x400033dc ); -PROVIDE ( tinfl_decompress_mem_to_callback = 0x40004584 ); -PROVIDE ( tinfl_decompress_mem_to_mem = 0x40004544 ); -PROVIDE ( toascii = 0x400161bc ); -PROVIDE ( tolower = 0x40008534 ); -PROVIDE ( toupper = 0x40008550 ); -PROVIDE ( uart_acm_dev = 0x3fffc9c0 ); -PROVIDE ( uartAttach = 0x4000f524 ); -PROVIDE ( uart_baudrate_detect = 0x4000f588 ); -PROVIDE ( uart_buff_switch = 0x4000f9b0 ); -PROVIDE ( UartConnCheck = 0x4000e824 ); -PROVIDE ( UartConnectProc = 0x4000eaf0 ); -PROVIDE ( UartDev = 0x3fffcac8 ); -PROVIDE ( uart_div_modify = 0x4000f628 ); -PROVIDE ( UartDwnLdProc = 0x4000eef8 ); -PROVIDE ( UartGetCmdLn = 0x4000fb78 ); -PROVIDE ( Uart_Init = 0x4000f68c ); -PROVIDE ( Uart_Init_USB = 0x4000f4c8 ); -PROVIDE ( UartRegReadProc = 0x4000eb40 ); -PROVIDE ( UartRegWriteProc = 0x4000eb00 ); -PROVIDE ( uart_rx_intr_handler = 0x4000f3d0 ); -PROVIDE ( uart_rx_one_char = 0x4000f874 ); -PROVIDE ( uart_rx_one_char_block = 0x4000f824 ); -PROVIDE ( uart_rx_readbuff = 0x4000f968 ); -PROVIDE ( UartRxString = 0x4000f8d0 ); -PROVIDE ( UartSecureDwnLdProc = 0x4000f1a4 ); -PROVIDE ( UartSetBaudProc = 0x4000eb9c ); -PROVIDE ( UartSpiAttachProc = 0x4000eb54 ); -PROVIDE ( UartSpiReadProc = 0x4000eb70 ); -PROVIDE ( uart_tx_flush = 0x4000f7c8 ); -PROVIDE ( uart_tx_one_char = 0x4000f79c ); -PROVIDE ( uart_tx_one_char2 = 0x4000f7b0 ); -PROVIDE ( uart_tx_switch = 0x4000f57c ); -PROVIDE ( uart_tx_wait_idle = 0x4000f7f4 ); -PROVIDE ( uart_usb_enable_reset_on_rts = 0x4000f4e8 ); -PROVIDE ( _unlink_r = 0x400152c0 ); -PROVIDE ( usb_cancel_transfer = 0x4001189c ); -PROVIDE ( usb_data_stuff = 0x3ffabe48 ); -PROVIDE ( usb_dc_attach = 0x400104f8 ); -PROVIDE ( usb_dc_check_poll_for_interrupts = 0x40010ef0 ); -PROVIDE ( usb_dc_detach = 0x400105b8 ); -PROVIDE ( usb_dc_ep_check_cap = 0x40010634 ); -PROVIDE ( usb_dc_ep_clear_stall = 0x40010890 ); -PROVIDE ( usb_dc_ep_configure = 0x40010678 ); -PROVIDE ( usb_dc_ep_disable = 0x40010a90 ); -PROVIDE ( usb_dc_ep_enable = 0x400109d0 ); -PROVIDE ( usb_dc_ep_flush = 0x40010b60 ); -PROVIDE ( usb_dc_ep_halt = 0x400108fc ); -PROVIDE ( usb_dc_ep_is_stalled = 0x4001095c ); -PROVIDE ( usb_dc_ep_mps = 0x40010ebc ); -PROVIDE ( usb_dc_ep_read = 0x40010e3c ); -PROVIDE ( usb_dc_ep_read_continue = 0x40010dfc ); -PROVIDE ( usb_dc_ep_read_wait = 0x40010d1c ); -PROVIDE ( usb_dc_ep_set_callback = 0x40010e74 ); -PROVIDE ( usb_dc_ep_set_stall = 0x40010830 ); -PROVIDE ( usb_dc_ep_write = 0x40010bd8 ); -PROVIDE ( usb_dc_reset = 0x400105e4 ); -PROVIDE ( usb_dc_set_address = 0x400105fc ); -PROVIDE ( usb_dc_set_status_callback = 0x40010eb0 ); -PROVIDE ( usb_deconfig = 0x40011654 ); -PROVIDE ( usb_disable = 0x40011704 ); -PROVIDE ( usb_enable = 0x40011674 ); -PROVIDE ( usb_ep_clear_stall = 0x40011764 ); -PROVIDE ( usb_ep_read_continue = 0x4001178c ); -PROVIDE ( usb_ep_read_wait = 0x40011774 ); -PROVIDE ( usb_ep_set_stall = 0x40011754 ); -PROVIDE ( usb_get_descriptor = 0x40012200 ); -PROVIDE ( usb_read = 0x4001173c ); -PROVIDE ( usb_set_config = 0x40011610 ); -PROVIDE ( usb_set_current_descriptor = 0x400121e8 ); -PROVIDE ( usb_transfer = 0x400117ec ); -PROVIDE ( usb_transfer_ep_callback = 0x4001179c ); -PROVIDE ( usb_transfer_sync = 0x400118ec ); -PROVIDE ( usb_write = 0x40011724 ); -PROVIDE ( user_code_start = 0x3fffcd20 ); +PROVIDE ( _rodata_end = 0x3ffaff2c ); +PROVIDE ( _rodata_start = 0x3ffac600 ); +PROVIDE ( rom_abs_temp = 0x4000c330 ); +PROVIDE ( rom_ant_btrx_cfg = 0x4000a0fc ); +PROVIDE ( rom_ant_bttx_cfg = 0x4000a0c0 ); +PROVIDE ( rom_ant_dft_cfg = 0x40009fc8 ); +PROVIDE ( rom_ant_wifirx_cfg = 0x4000a03c ); +PROVIDE ( rom_ant_wifitx_cfg = 0x40009ff8 ); +PROVIDE ( rom_bb_bss_cbw40_dig = 0x40009a84 ); +PROVIDE ( rom_bb_wdg_cfg = 0x40009eb8 ); +PROVIDE ( rom_bb_wdg_test_en = 0x40009a48 ); +PROVIDE ( rom_bb_wdt_get_status = 0x40009d18 ); +PROVIDE ( rom_bb_wdt_int_enable = 0x40009cd4 ); +PROVIDE ( rom_bb_wdt_rst_enable = 0x40009cb4 ); +PROVIDE ( rom_bb_wdt_timeout_clear = 0x40009cfc ); +PROVIDE ( rom_cbw2040_cfg = 0x4000a550 ); +PROVIDE ( rom_check_noise_floor = 0x40009b4c ); +PROVIDE ( rom_chip_i2c_readReg = 0x4000a8e4 ); +PROVIDE ( rom_chip_i2c_writeReg = 0x4000a960 ); +PROVIDE ( rom_correct_rf_ana_gain = 0x4000d2b4 ); +PROVIDE ( rom_dc_iq_est = 0x4000c414 ); +PROVIDE ( rom_disable_agc = 0x400091cc ); +PROVIDE ( rom_enable_agc = 0x400091e4 ); +PROVIDE ( rom_freq_get_i2c_data = 0x4000bb84 ); +PROVIDE ( rom_freq_i2c_set_wifi_data = 0x4000b948 ); +PROVIDE ( rom_freq_i2c_write_set = 0x4000b3bc ); +PROVIDE ( rom_gen_rx_gain_table = 0x4000a300 ); +PROVIDE ( rom_get_bbgain_db = 0x400094ec ); +PROVIDE ( rom_get_data_sat = 0x40009338 ); +PROVIDE ( rom_get_fm_sar_dout = 0x4000c024 ); +PROVIDE ( rom_get_i2c_read_mask = 0x4000a8c0 ); +PROVIDE ( rom_get_power_db = 0x4000ce28 ); +PROVIDE ( rom_get_pwctrl_correct = 0x4000d470 ); +PROVIDE ( rom_get_rfcal_rxiq_data = 0x4000cab0 ); +PROVIDE ( rom_get_rf_gain_qdb = 0x4000d29c ); +PROVIDE ( rom_get_sar_dout = 0x4000d400 ); +PROVIDE ( rom_i2c_clk_sel = 0x4000a788 ); +PROVIDE ( rom_i2c_readReg = 0x4000a940 ); +PROVIDE ( rom_i2c_readReg_Mask = 0x4000a9c4 ); +PROVIDE ( rom_i2c_writeReg = 0x4000a9a8 ); +PROVIDE ( rom_i2c_writeReg_Mask = 0x4000aa00 ); +PROVIDE ( rom_index_to_txbbgain = 0x4000bd10 ); +PROVIDE ( rom_iq_est_disable = 0x4000c3d8 ); +PROVIDE ( rom_iq_est_enable = 0x4000c358 ); +PROVIDE ( rom_linear_to_db = 0x4000cdbc ); +PROVIDE ( rom_loopback_mode_en = 0x40009304 ); +PROVIDE ( rom_mac_enable_bb = 0x40009e48 ); +PROVIDE ( rom_meas_tone_pwr_db = 0x4000ce64 ); +PROVIDE ( rom_mhz2ieee = 0x4000a4e8 ); +PROVIDE ( rom_noise_floor_auto_set = 0x40009ab4 ); +PROVIDE ( rom_pbus_debugmode = 0x4000ac70 ); +PROVIDE ( rom_pbus_force_mode = 0x4000aa6c ); +PROVIDE ( rom_pbus_force_test = 0x4000abd0 ); +PROVIDE ( rom_pbus_rd = 0x4000ac2c ); +PROVIDE ( rom_pbus_rd_addr = 0x4000ab34 ); +PROVIDE ( rom_pbus_rd_shift = 0x4000ab80 ); +PROVIDE ( rom_pbus_rx_dco_cal = 0x4000c49c ); +PROVIDE ( rom_pbus_set_dco = 0x4000ae2c ); +PROVIDE ( rom_pbus_set_rxgain = 0x4000ac98 ); +PROVIDE ( rom_pbus_workmode = 0x4000ac84 ); +PROVIDE ( rom_pbus_xpd_rx_off = 0x4000acfc ); +PROVIDE ( rom_pbus_xpd_rx_on = 0x4000ad30 ); +PROVIDE ( rom_pbus_xpd_tx_off = 0x4000ad84 ); +PROVIDE ( rom_pbus_xpd_tx_on = 0x4000add4 ); +PROVIDE ( rom_phy_ant_init = 0x40009f48 ); +PROVIDE ( rom_phy_byte_to_word = 0x40009d60 ); +PROVIDE ( rom_phy_chan_dump_cfg = 0x4000a180 ); +PROVIDE ( rom_phy_chan_filt_set = 0x4000a614 ); +PROVIDE ( rom_phy_close_pa = 0x4000a810 ); +PROVIDE ( rom_phy_disable_cca = 0x40009208 ); +PROVIDE ( rom_phy_disable_low_rate = 0x4000a2b8 ); +PROVIDE ( rom_phy_enable_cca = 0x40009234 ); +PROVIDE ( rom_phy_enable_low_rate = 0x4000a280 ); +PROVIDE ( rom_phy_freq_correct = 0x4000b0b4 ); +PROVIDE ( rom_phy_get_noisefloor = 0x40009b04 ); +PROVIDE ( rom_phy_get_rx_freq = 0x4000a6ac ); +PROVIDE ( rom_phy_get_tx_rate = 0x40009d50 ); +PROVIDE ( rom_phy_rx11blr_cfg = 0x40009c5c ); +PROVIDE ( rom_phy_rx_sense_set = 0x4000a704 ); +PROVIDE ( rom_phy_set_bbfreq_init = 0x4000d3d0 ); +PROVIDE ( rom_pll_correct_dcap = 0x4000bad4 ); +PROVIDE ( rom_pow_usr = 0x4000924c ); +PROVIDE ( rom_read_hw_noisefloor = 0x40009c38 ); +PROVIDE ( rom_read_sar_dout = 0x4000bfd4 ); +PROVIDE ( rom_restart_cal = 0x4000ae74 ); +PROVIDE ( rom_rfcal_pwrctrl = 0x4000d098 ); +PROVIDE ( rom_rfcal_rxiq = 0x4000ca3c ); +PROVIDE ( rom_rfcal_txcap = 0x4000ccac ); +PROVIDE ( rom_rfpll_set_freq = 0x4000afa4 ); +PROVIDE ( rom_rftx_init = 0x4000b24c ); +PROVIDE ( rom_rx_gain_force = 0x40009558 ); +PROVIDE ( rom_rxiq_cover_mg_mp = 0x4000c954 ); +PROVIDE ( rom_rxiq_get_mis = 0x4000c7d8 ); +PROVIDE ( rom_rxiq_set_reg = 0x4000c8ec ); +PROVIDE ( rom_set_cal_rxdc = 0x400092c4 ); +PROVIDE ( rom_set_cca = 0x4000a59c ); +PROVIDE ( rom_set_chan_cal_interp = 0x4000cba4 ); +PROVIDE ( rom_set_channel_freq = 0x4000b00c ); +PROVIDE ( rom_set_loopback_gain = 0x40009268 ); +PROVIDE ( rom_set_noise_floor = 0x40009bf4 ); +PROVIDE ( rom_set_pbus_mem = 0x40009380 ); +PROVIDE ( rom_set_rf_freq_offset = 0x4000b214 ); +PROVIDE ( rom_set_rxclk_en = 0x400095cc ); +PROVIDE ( rom_set_txcap_reg = 0x4000cc34 ); +PROVIDE ( rom_set_txclk_en = 0x4000959c ); +PROVIDE ( rom_set_tx_dig_gain = 0x40009514 ); +PROVIDE ( rom_set_xpd_sar = 0x40009f08 ); +PROVIDE ( rom_spur_cal = 0x4000a47c ); +PROVIDE ( rom_spur_reg_write_one_tone = 0x400097c4 ); +PROVIDE ( rom_start_tx_tone = 0x400096f0 ); +PROVIDE ( rom_start_tx_tone_step = 0x40009608 ); +PROVIDE ( rom_stop_tx_tone = 0x4000a428 ); +PROVIDE ( _rom_store = 0x4001bed0 ); +PROVIDE ( _rom_store_table = 0x4001bd64 ); +PROVIDE ( rom_target_power_add_backoff = 0x4000d278 ); +PROVIDE ( rom_txbbgain_to_index = 0x4000bce0 ); +PROVIDE ( rom_txcal_work_mode = 0x4000bf30 ); +PROVIDE ( rom_txdc_cal_init = 0x4000bd2c ); +PROVIDE ( rom_txdc_cal_v70 = 0x4000bdc0 ); +PROVIDE ( rom_txiq_cover = 0x4000c1ac ); +PROVIDE ( rom_txiq_get_mis_pwr = 0x4000c0f8 ); +PROVIDE ( rom_txiq_set_reg = 0x4000bf64 ); +PROVIDE ( rom_tx_paon_set = 0x40009db8 ); +PROVIDE ( rom_tx_pwr_backoff = 0x4000ceb8 ); +PROVIDE ( rom_txtone_linear_pwr = 0x4000c0b0 ); +PROVIDE ( rom_wait_rfpll_cal_end = 0x4000af3c ); +PROVIDE ( rom_wifi_11g_rate_chg = 0x4000d260 ); +PROVIDE ( rom_wifi_rifs_mode_en = 0x40009d2c ); +PROVIDE ( rom_write_dac_gain2 = 0x4000a210 ); +PROVIDE ( rom_write_gain_mem = 0x400094bc ); +PROVIDE ( rom_write_pll_cap_mem = 0x4000ba58 ); +PROVIDE ( rom_write_rfpll_sdm = 0x4000aed4 ); +PROVIDE ( rom_wr_rf_freq_mem = 0x4000b2f0 ); +PROVIDE ( roundup2 = 0x4001bcd0 ); +PROVIDE ( rtc_boot_control = 0x4001002c ); +PROVIDE ( rtc_get_reset_reason = 0x4000ff58 ); +PROVIDE ( rtc_get_wakeup_cause = 0x4000ff7c ); +PROVIDE ( rtc_select_apb_bridge = 0x400100a0 ); +PROVIDE ( s_cdcacm_old_rts = 0x3ffffd34 ); +PROVIDE ( SelectSpiFunction = 0x40015d08 ); +PROVIDE ( SelectSpiQIO = 0x40015b88 ); +PROVIDE ( SendMsg = 0x40012d0c ); +PROVIDE ( send_packet = 0x40012cc8 ); +PROVIDE ( setlocale = 0x40001c44 ); +PROVIDE ( _setlocale_r = 0x40001bdc ); +PROVIDE ( set_rtc_memory_crc = 0x40010010 ); +PROVIDE ( SetSpiDrvs = 0x40015c18 ); +PROVIDE ( sig_matrix = 0x3ffffd57 ); +PROVIDE ( software_reset = 0x40010068 ); +PROVIDE ( software_reset_cpu = 0x40010080 ); +PROVIDE ( SPI_block_erase = 0x4001623c ); +PROVIDE ( spi_cache_mode_switch = 0x40016a00 ); +PROVIDE ( SPI_chip_erase = 0x400161b8 ); +PROVIDE ( SPIClkConfig = 0x400170a0 ); +PROVIDE ( SPI_Common_Command = 0x400162e8 ); +PROVIDE ( spi_common_set_flash_cs_timing = 0x40016c0c ); +PROVIDE ( spi_dummy_len_fix = 0x40015b50 ); +PROVIDE ( SPI_Encrypt_Write = 0x400177e0 ); +PROVIDE ( SPI_Encrypt_Write_Dest = 0x400176cc ); +PROVIDE ( SPIEraseArea = 0x40017470 ); +PROVIDE ( SPIEraseBlock = 0x4001710c ); +PROVIDE ( SPIEraseChip = 0x400170ec ); +PROVIDE ( SPIEraseSector = 0x4001716c ); +PROVIDE ( spi_flash_attach = 0x40017004 ); +PROVIDE ( spi_flash_boot_attach = 0x40016fc0 ); +PROVIDE ( spi_flash_check_suspend_cb = 0x3ffffd58 ); +PROVIDE ( SPI_flashchip_data = 0x3ffffd3c ); +PROVIDE ( spi_flash_set_check_suspend_cb = 0x40015b3c ); +PROVIDE ( SPI_init = 0x40016ce8 ); +PROVIDE ( SPILock = 0x40016ed4 ); +PROVIDE ( SPIMasterReadModeCnfig = 0x40017014 ); +PROVIDE ( SPI_page_program = 0x400165a8 ); +PROVIDE ( SPIParamCfg = 0x40017500 ); +PROVIDE ( SPIRead = 0x4001728c ); +PROVIDE ( SPI_read_data = 0x40015ed8 ); +PROVIDE ( SPIReadModeCnfig = 0x40016f1c ); +PROVIDE ( SPI_read_status = 0x40016084 ); +PROVIDE ( SPI_read_status_high = 0x40016284 ); +PROVIDE ( SPI_sector_erase = 0x400161ec ); +PROVIDE ( spi_slave_download = 0x4001998c ); +PROVIDE ( spi_slave_rom_check_conn = 0x40019724 ); +PROVIDE ( spi_slave_rom_init = 0x40019774 ); +PROVIDE ( spi_slave_rom_init_hw = 0x40019b5c ); +PROVIDE ( spi_slave_rom_intr_enable = 0x40019b3c ); +PROVIDE ( spi_slave_rom_rxdma_load = 0x40019da8 ); +PROVIDE ( spi_slave_rom_txdma_load = 0x40019e3c ); +PROVIDE ( SPIUnlock = 0x40016e88 ); +PROVIDE ( SPI_user_command_read = 0x40015fc8 ); +PROVIDE ( SPI_Wait_Idle = 0x40016680 ); +PROVIDE ( SPI_WakeUp = 0x400160f4 ); +PROVIDE ( SPIWrite = 0x400171cc ); +PROVIDE ( SPI_write_enable = 0x4001655c ); +PROVIDE ( SPI_Write_Encrypt_Disable = 0x40017694 ); +PROVIDE ( SPI_Write_Encrypt_Enable = 0x40017678 ); +PROVIDE ( SPI_write_status = 0x400162a4 ); +PROVIDE ( __stack = 0x3fffe710 ); +PROVIDE ( _stack_sentry = 0x3fffc410 ); +PROVIDE ( _start = 0x4000726c ); +PROVIDE ( _stext = 0x40007118 ); +PROVIDE ( string0_descr = 0x3ffaeeae ); +PROVIDE ( str_manu_descr = 0x3ffaee9a ); +PROVIDE ( str_prod_descr = 0x3ffaee88 ); +PROVIDE ( str_serial_descr = 0x3ffaee84 ); +PROVIDE ( s_usb_osglue = 0x3ffffcdc ); +PROVIDE ( _SyscallException = 0x4000732a ); +PROVIDE ( syscall_table_ptr_app = 0x3ffffd74 ); +PROVIDE ( syscall_table_ptr_pro = 0x3ffffd78 ); +PROVIDE ( tdefl_compress = 0x400041dc ); +PROVIDE ( tdefl_compress_buffer = 0x40004938 ); +PROVIDE ( tdefl_compress_mem_to_mem = 0x40004a50 ); +PROVIDE ( tdefl_compress_mem_to_output = 0x40004a30 ); +PROVIDE ( tdefl_get_adler32 = 0x40004a28 ); +PROVIDE ( tdefl_get_prev_return_status = 0x40004a20 ); +PROVIDE ( tdefl_init = 0x40004954 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x40004a64 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40004a58 ); +PROVIDE ( _text_end = 0x4001bed0 ); +PROVIDE ( _text_start = 0x40007118 ); +PROVIDE ( tinfl_decompress = 0x40003000 ); +PROVIDE ( tinfl_decompress_mem_to_callback = 0x400041a8 ); +PROVIDE ( tinfl_decompress_mem_to_mem = 0x40004168 ); +PROVIDE ( uart_acm_dev = 0x3ffffcf8 ); +PROVIDE ( uartAttach = 0x40012890 ); +PROVIDE ( uart_baudrate_detect = 0x400128f0 ); +PROVIDE ( uart_buff_switch = 0x40012d64 ); +PROVIDE ( UartConnCheck = 0x40011ab4 ); +PROVIDE ( UartConnectProc = 0x40011da8 ); +PROVIDE ( UartDev = 0x3ffffcfc ); +PROVIDE ( uart_div_modify = 0x40012984 ); +PROVIDE ( uart_div_reinit = 0x400129d0 ); +PROVIDE ( UartDwnLdProc = 0x400121ac ); +PROVIDE ( UartGetCmdLn = 0x40012f28 ); +PROVIDE ( Uart_Init = 0x40012a04 ); +PROVIDE ( Uart_Init_USB = 0x40012818 ); +PROVIDE ( UartRegReadProc = 0x40011df8 ); +PROVIDE ( UartRegWriteProc = 0x40011db8 ); +PROVIDE ( uart_rx_intr_handler = 0x40012690 ); +PROVIDE ( uart_rx_one_char = 0x40012bf0 ); +PROVIDE ( uart_rx_one_char_block = 0x40012b9c ); +PROVIDE ( uart_rx_readbuff = 0x40012d1c ); +PROVIDE ( UartRxString = 0x40012c84 ); +PROVIDE ( UartSecureDwnLdProc = 0x40012464 ); +PROVIDE ( UartSetBaudProc = 0x40011e54 ); +PROVIDE ( UartSpiAttachProc = 0x40011e0c ); +PROVIDE ( UartSpiReadProc = 0x40011e28 ); +PROVIDE ( uart_tx_flush = 0x40012b40 ); +PROVIDE ( uart_tx_one_char = 0x40012b10 ); +PROVIDE ( uart_tx_one_char2 = 0x40012b28 ); +PROVIDE ( uart_tx_switch = 0x400128e4 ); +PROVIDE ( uart_tx_wait_idle = 0x40012b6c ); +PROVIDE ( uart_usb_enable_reset_on_rts = 0x40012858 ); +PROVIDE ( Uart_USB_Send_Testament = 0x400127d8 ); +PROVIDE ( usb_cancel_transfer = 0x40015200 ); +PROVIDE ( usb_data_stuff = 0x3ffacc88 ); +PROVIDE ( usb_dc_attach = 0x40013ecc ); +PROVIDE ( usb_dc_check_poll_for_interrupts = 0x40014980 ); +PROVIDE ( usb_dc_detach = 0x40014010 ); +PROVIDE ( usb_dc_ep_check_cap = 0x40014094 ); +PROVIDE ( usb_dc_ep_clear_stall = 0x400142f0 ); +PROVIDE ( usb_dc_ep_configure = 0x400140d8 ); +PROVIDE ( usb_dc_ep_disable = 0x400144ec ); +PROVIDE ( usb_dc_ep_enable = 0x4001442c ); +PROVIDE ( usb_dc_ep_flush = 0x400145b8 ); +PROVIDE ( usb_dc_ep_halt = 0x4001435c ); +PROVIDE ( usb_dc_ep_is_stalled = 0x400143bc ); +PROVIDE ( usb_dc_ep_mps = 0x40014958 ); +PROVIDE ( usb_dc_ep_read = 0x400148d8 ); +PROVIDE ( usb_dc_ep_read_continue = 0x40014898 ); +PROVIDE ( usb_dc_ep_read_wait = 0x400147bc ); +PROVIDE ( usb_dc_ep_set_callback = 0x40014910 ); +PROVIDE ( usb_dc_ep_set_stall = 0x40014290 ); +PROVIDE ( usb_dc_ep_write = 0x40014684 ); +PROVIDE ( usb_dc_ep_write_would_block = 0x40014624 ); +PROVIDE ( usb_dc_prepare_persist = 0x40013bec ); +PROVIDE ( usb_dc_reset = 0x40014044 ); +PROVIDE ( usb_dc_set_address = 0x4001405c ); +PROVIDE ( usb_dc_set_status_callback = 0x4001494c ); +PROVIDE ( usb_deconfig = 0x40014fa8 ); +PROVIDE ( usb_dev_get_configuration = 0x40014f4c ); +PROVIDE ( usb_dev_resume = 0x40014f38 ); +PROVIDE ( usb_dfu_force_detach = 0x400155b0 ); +PROVIDE ( usb_dfu_init = 0x40015598 ); +PROVIDE ( usb_dfu_set_detach_cb = 0x400152dc ); +PROVIDE ( usb_disable = 0x40015058 ); +PROVIDE ( usb_dw_isr_handler = 0x40013c48 ); +PROVIDE ( usb_enable = 0x40014fc8 ); +PROVIDE ( usb_ep_clear_stall = 0x400150c8 ); +PROVIDE ( usb_ep_read_continue = 0x400150f0 ); +PROVIDE ( usb_ep_read_wait = 0x400150d8 ); +PROVIDE ( usb_ep_set_stall = 0x400150b8 ); +PROVIDE ( usb_get_descriptor = 0x400149c0 ); +PROVIDE ( usb_read = 0x400150a0 ); +PROVIDE ( usb_set_config = 0x40014f64 ); +PROVIDE ( usb_set_current_descriptor = 0x400149a8 ); +PROVIDE ( usb_transfer = 0x40015150 ); +PROVIDE ( usb_transfer_ep_callback = 0x40015100 ); +PROVIDE ( usb_transfer_sync = 0x40015250 ); +PROVIDE ( usb_write = 0x40015088 ); +PROVIDE ( usb_write_would_block = 0x40015078 ); +PROVIDE ( user_code_start = 0x3fffe714 ); PROVIDE ( _UserExceptionVector = 0x40000340 ); PROVIDE ( _UserExceptionVector_text_end = 0x40000357 ); PROVIDE ( _UserExceptionVector_text_start = 0x40000340 ); -PROVIDE ( utoa = 0x40000654 ); -PROVIDE ( __utoa = 0x400005f0 ); -PROVIDE ( VerifyFlashMd5Proc = 0x4000ed4c ); -PROVIDE ( vfiprintf = 0x4000121c ); -PROVIDE ( _vfiprintf_r = 0x40000f34 ); -PROVIDE ( vfprintf = 0x4000121c ); -PROVIDE ( _vfprintf_r = 0x40000f34 ); -PROVIDE ( Wait_SPI_Idle = 0x40012764 ); -PROVIDE ( wcrtomb = 0x400016d0 ); -PROVIDE ( _wcrtomb_r = 0x4000167c ); -PROVIDE ( _wctomb_r = 0x40001c88 ); +PROVIDE ( VerifyFlashMd5Proc = 0x40012004 ); +PROVIDE ( Wait_SPI_Idle = 0x40016188 ); PROVIDE ( _WindowOverflow12 = 0x40000100 ); PROVIDE ( _WindowOverflow4 = 0x40000000 ); PROVIDE ( _WindowOverflow8 = 0x40000080 ); @@ -922,47 +752,45 @@ PROVIDE ( _WindowUnderflow4 = 0x40000040 ); PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); PROVIDE ( _WindowVectors_text_end = 0x40000170 ); PROVIDE ( _WindowVectors_text_start = 0x40000000 ); -PROVIDE ( write = 0x4000851c ); -PROVIDE ( _write_r = 0x400153ac ); -PROVIDE ( __XT_EXCEPTION_DESCS__ = 0x3ffaf840 ); -PROVIDE ( __XT_EXCEPTION_DESCS_END__ = 0x3ffaf840 ); -PROVIDE ( __XT_EXCEPTION_TABLE__ = 0x3ffaf74d ); -PROVIDE ( xthal_bcopy = 0x40015b44 ); -PROVIDE ( xthal_copy123 = 0x40015bd8 ); -PROVIDE ( xthal_get_ccompare = 0x40015ce8 ); -PROVIDE ( xthal_get_ccount = 0x40015cbc ); -PROVIDE ( xthal_get_interrupt = 0x40015d08 ); -PROVIDE ( Xthal_intlevel = 0x3ffae918 ); -PROVIDE ( xthal_memcpy = 0x40015b68 ); -PROVIDE ( xthal_set_ccompare = 0x40015cc4 ); -PROVIDE ( xthal_set_intclear = 0x40015d10 ); +PROVIDE ( __XT_EXCEPTION_DESCS__ = 0x3ffaff2c ); +PROVIDE ( __XT_EXCEPTION_DESCS_END__ = 0x3ffaff2c ); +PROVIDE ( __XT_EXCEPTION_TABLE__ = 0x3ffafe3a ); +PROVIDE ( xthal_bcopy = 0x4001a918 ); +PROVIDE ( xthal_copy123 = 0x4001a9ac ); +PROVIDE ( xthal_get_ccompare = 0x4001aabc ); +PROVIDE ( xthal_get_ccount = 0x4001aa90 ); +PROVIDE ( xthal_get_interrupt = 0x4001aadc ); +PROVIDE ( Xthal_intlevel = 0x3ffaf06c ); +PROVIDE ( xthal_memcpy = 0x4001a93c ); +PROVIDE ( xthal_set_ccompare = 0x4001aa98 ); +PROVIDE ( xthal_set_intclear = 0x4001aae4 ); PROVIDE ( xthals_hw_configid0 = 0xc2ecfafe ); PROVIDE ( xthals_hw_configid1 = 0x224787b1 ); PROVIDE ( xthals_release_major = 0x00002ee0 ); PROVIDE ( xthals_release_minor = 0x00000009 ); PROVIDE ( _xtos_alloca_handler = 0x40000010 ); -PROVIDE ( xtos_cause3_handler = 0x4000774c ); -PROVIDE ( xtos_c_handler_table = 0x3fffcea8 ); -PROVIDE ( xtos_c_wrapper_handler = 0x4000775c ); -PROVIDE ( _xtos_enabled = 0x3fffcfb0 ); -PROVIDE ( xtos_exc_handler_table = 0x3fffcda8 ); -PROVIDE ( xtos_interrupt_mask_table = 0x3fffd0b8 ); -PROVIDE ( xtos_interrupt_table = 0x3fffcfb8 ); -PROVIDE ( _xtos_ints_off = 0x4001560c ); -PROVIDE ( _xtos_ints_on = 0x400155e8 ); -PROVIDE ( _xtos_intstruct = 0x3fffcfb0 ); -PROVIDE ( _xtos_l1int_handler = 0x400077c8 ); -PROVIDE ( xtos_p_none = 0x40015acc ); -PROVIDE ( _xtos_restore_intlevel = 0x400078a8 ); -PROVIDE ( _xtos_return_from_exc = 0x40015ad4 ); -PROVIDE ( _xtos_set_exception_handler = 0x40007690 ); -PROVIDE ( _xtos_set_interrupt_handler = 0x400155ac ); -PROVIDE ( _xtos_set_interrupt_handler_arg = 0x40015570 ); -PROVIDE ( _xtos_set_intlevel = 0x40015aec ); -PROVIDE ( _xtos_set_min_intlevel = 0x40015b08 ); -PROVIDE ( _xtos_set_vpri = 0x400078b4 ); -PROVIDE ( _xtos_syscall_handler = 0x400076d8 ); -PROVIDE ( xtos_unhandled_exception = 0x40015b2c ); -PROVIDE ( xtos_unhandled_interrupt = 0x40015b3c ); +PROVIDE ( xtos_cause3_handler = 0x40007370 ); +PROVIDE ( xtos_c_handler_table = 0x3fffec78 ); +PROVIDE ( xtos_c_wrapper_handler = 0x40007380 ); +PROVIDE ( _xtos_enabled = 0x3fffed80 ); +PROVIDE ( xtos_exc_handler_table = 0x3fffeb78 ); +PROVIDE ( xtos_interrupt_mask_table = 0x3fffee88 ); +PROVIDE ( xtos_interrupt_table = 0x3fffed88 ); +PROVIDE ( _xtos_ints_off = 0x4001a3e0 ); +PROVIDE ( _xtos_ints_on = 0x4001a3bc ); +PROVIDE ( _xtos_intstruct = 0x3fffed80 ); +PROVIDE ( _xtos_l1int_handler = 0x400073ec ); +PROVIDE ( xtos_p_none = 0x4001a8a0 ); +PROVIDE ( _xtos_restore_intlevel = 0x400074cc ); +PROVIDE ( _xtos_return_from_exc = 0x4001a8a8 ); +PROVIDE ( _xtos_set_exception_handler = 0x400072b4 ); +PROVIDE ( _xtos_set_interrupt_handler = 0x4001a380 ); +PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4001a344 ); +PROVIDE ( _xtos_set_intlevel = 0x4001a8c0 ); +PROVIDE ( _xtos_set_min_intlevel = 0x4001a8dc ); +PROVIDE ( _xtos_set_vpri = 0x400074d8 ); +PROVIDE ( _xtos_syscall_handler = 0x400072fc ); +PROVIDE ( xtos_unhandled_exception = 0x4001a900 ); +PROVIDE ( xtos_unhandled_interrupt = 0x4001a910 ); PROVIDE ( _xtos_vectors_ref_ = 0x00000000 ); -PROVIDE ( _xtos_vpri_enabled = 0x3fffcfb4 ); +PROVIDE ( _xtos_vpri_enabled = 0x3fffed84 ); diff --git a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.libgcc.ld b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.libgcc.ld index d53bd27e43..d714ff7da1 100644 --- a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.libgcc.ld +++ b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.libgcc.ld @@ -1,98 +1,92 @@ -/* Unlike other ROM functions which are exported using PROVIDE, which declares - weak symbols, these libgcc functions are exported using assignment, - which declares strong symbols. This is done so that ROM functions are always - used instead of the ones provided by libgcc.a. -*/ - -__absvdi2 = 0x40005eb4; -__absvsi2 = 0x40005ea0; -__adddf3 = 0x40008a3c; -__addsf3 = 0x40008594; -__addvdi3 = 0x4000916c; -__addvsi3 = 0x40009148; -__ashldi3 = 0x4001622c; -__ashrdi3 = 0x40016244; -__bswapdi2 = 0x40007110; -__bswapsi2 = 0x400070e8; -__clrsbdi2 = 0x40007184; -__clrsbsi2 = 0x4000716c; -__clzdi2 = 0x40016464; -__clzsi2 = 0x400161fc; -__cmpdi2 = 0x40005e58; -__ctzdi2 = 0x40016478; -__ctzsi2 = 0x40016204; -__divdc3 = 0x40006c30; -__divdf3 = 0x40008e00; -__divdi3 = 0x40016498; -__divsc3 = 0x40006920; -__divsf3 = 0x400087f8; -__divsi3 = 0x400161cc; -__eqdf2 = 0x40005ce0; -__eqsf2 = 0x400059ac; -__extendsfdf2 = 0x400090e4; -__ffsdi2 = 0x40016440; -__ffssi2 = 0x40016218; -__fixdfdi = 0x40008f74; -__fixdfsi = 0x40008f28; -__fixsfdi = 0x400088f8; -__fixsfsi = 0x400088b8; -__fixunsdfsi = 0x40008fe0; -__fixunssfdi = 0x400089b0; -__fixunssfsi = 0x40008958; -__floatdidf = 0x4001639c; -__floatdisf = 0x400162d4; -__floatsidf = 0x40016358; -__floatsisf = 0x40016284; -__floatundidf = 0x4001638c; -__floatundisf = 0x400162c4; -__floatunsidf = 0x4001634c; -__floatunsisf = 0x40016278; -__gcc_bcmp = 0x400071bc; -__gedf2 = 0x40005da0; -__gesf2 = 0x40005a44; -__gtdf2 = 0x40005d14; -__gtsf2 = 0x400059d8; -__ledf2 = 0x40005d3c; -__lesf2 = 0x400059f8; -__lshrdi3 = 0x40016260; -__ltdf2 = 0x40005dc8; -__ltsf2 = 0x40005a64; -__moddi3 = 0x40016760; -__modsi3 = 0x400161d4; -__muldc3 = 0x400062e8; -__muldf3 = 0x40005bc4; -__muldi3 = 0x40016410; -__mulsc3 = 0x40005f80; -__mulsf3 = 0x40005900; -__mulsi3 = 0x400161c4; -__mulvdi3 = 0x4000922c; -__mulvsi3 = 0x40009214; -__nedf2 = 0x40005ce0; -__negdf2 = 0x40005ad8; -__negdi2 = 0x40016428; -__negsf2 = 0x4000856c; -__negvdi2 = 0x40009348; -__negvsi2 = 0x40009328; -__nesf2 = 0x400059ac; -__nsau_data = 0x3ffaba70; -__paritysi2 = 0x40009414; -__popcountdi2 = 0x400093bc; -__popcountsi2 = 0x40009384; -__popcount_tab = 0x3ffaba70; -__powidf2 = 0x40005f1c; -__powisf2 = 0x40005ed4; -__subdf3 = 0x40008b90; -__subsf3 = 0x4000867c; -__subvdi3 = 0x400091d0; -__subvsi3 = 0x400091ac; -__truncdfsf2 = 0x40009040; -__ucmpdi2 = 0x40005e78; -__udivdi3 = 0x40016a08; -__udivmoddi4 = 0x400071fc; -__udivsi3 = 0x400161dc; -__udiv_w_sdiv = 0x400071f4; -__umoddi3 = 0x40016c8c; -__umodsi3 = 0x400161e4; -__umulsidi3 = 0x400161ec; -__unorddf2 = 0x40005e2c; -__unordsf2 = 0x40005ab0; +__absvdi2 = 0x40005ad8; +__absvsi2 = 0x40005ac4; +__adddf3 = 0x40008660; +__addsf3 = 0x400081b8; +__addvdi3 = 0x40008d90; +__addvsi3 = 0x40008d6c; +__ashldi3 = 0x4001b000; +__ashrdi3 = 0x4001b018; +__bswapdi2 = 0x40006d34; +__bswapsi2 = 0x40006d0c; +__clrsbdi2 = 0x40006da8; +__clrsbsi2 = 0x40006d90; +__clzdi2 = 0x4001b238; +__clzsi2 = 0x4001afd0; +__cmpdi2 = 0x40005a7c; +__ctzdi2 = 0x4001b24c; +__ctzsi2 = 0x4001afd8; +__divdc3 = 0x40006854; +__divdf3 = 0x40008a24; +__divdi3 = 0x4001b26c; +__divsc3 = 0x40006544; +__divsf3 = 0x4000841c; +__divsi3 = 0x4001afa0; +__eqdf2 = 0x40005904; +__eqsf2 = 0x400055d0; +__extendsfdf2 = 0x40008d08; +__ffsdi2 = 0x4001b214; +__ffssi2 = 0x4001afec; +__fixdfdi = 0x40008b98; +__fixdfsi = 0x40008b4c; +__fixsfdi = 0x4000851c; +__fixsfsi = 0x400084dc; +__fixunsdfsi = 0x40008c04; +__fixunssfdi = 0x400085d4; +__fixunssfsi = 0x4000857c; +__floatdidf = 0x4001b170; +__floatdisf = 0x4001b0a8; +__floatsidf = 0x4001b12c; +__floatsisf = 0x4001b058; +__floatundidf = 0x4001b160; +__floatundisf = 0x4001b098; +__floatunsidf = 0x4001b120; +__floatunsisf = 0x4001b04c; +__gcc_bcmp = 0x40006de0; +__gedf2 = 0x400059c4; +__gesf2 = 0x40005668; +__gtdf2 = 0x40005938; +__gtsf2 = 0x400055fc; +__ledf2 = 0x40005960; +__lesf2 = 0x4000561c; +__lshrdi3 = 0x4001b034; +__ltdf2 = 0x400059ec; +__ltsf2 = 0x40005688; +__moddi3 = 0x4001b534; +__modsi3 = 0x4001afa8; +__muldc3 = 0x40005f0c; +__muldf3 = 0x400057e8; +__muldi3 = 0x4001b1e4; +__mulsc3 = 0x40005ba4; +__mulsf3 = 0x40005524; +__mulsi3 = 0x4001af98; +__mulvdi3 = 0x40008e50; +__mulvsi3 = 0x40008e38; +__nedf2 = 0x40005904; +__negdf2 = 0x400056fc; +__negdi2 = 0x4001b1fc; +__negsf2 = 0x40008190; +__negvdi2 = 0x40008f6c; +__negvsi2 = 0x40008f4c; +__nesf2 = 0x400055d0; +__nsau_data = 0x3ffac870; +__paritysi2 = 0x40009038; +__popcountdi2 = 0x40008fe0; +__popcountsi2 = 0x40008fa8; +__popcount_tab = 0x3ffac870; +__powidf2 = 0x40005b40; +__powisf2 = 0x40005af8; +__subdf3 = 0x400087b4; +__subsf3 = 0x400082a0; +__subvdi3 = 0x40008df4; +__subvsi3 = 0x40008dd0; +__truncdfsf2 = 0x40008c64; +__ucmpdi2 = 0x40005a9c; +__udivdi3 = 0x4001b7dc; +__udivmoddi4 = 0x40006e20; +__udivsi3 = 0x4001afb0; +__udiv_w_sdiv = 0x40006e18; +__umoddi3 = 0x4001ba60; +__umodsi3 = 0x4001afb8; +__umulsidi3 = 0x4001afc0; +__unorddf2 = 0x40005a50; +__unordsf2 = 0x400056d4; diff --git a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-data.ld b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-data.ld index dd4d696503..56642969ba 100644 --- a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-data.ld +++ b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-data.ld @@ -1,19 +1,9 @@ -/* These are the .bss/.data symbols used by newlib functions present in ESP32S2beta ROM. - See also esp32s2beta.rom.newlib-funcs.ld for the list of general newlib functions, - and esp32s2beta.rom.newlib-stdio.ld for stdio related newlib functions. - - Unlike other ROM functions and data which are exported using PROVIDE, which declares - weak symbols, newlib related functions are exported using assignment, - which declares strong symbols. This is done so that ROM functions are always - used instead of the ones provided by libc.a. - */ - -_ctype_ = 0x3ffab96c; -__default_global_locale = 0x3ffab800; -_global_impure_ptr = 0x3fffc04c; -__global_locale_ptr = 0x3fffc030; -__locale_ctype_ptr = 0x40002008; -__locale_ctype_ptr_l = 0x40002000; -__locale_mb_cur_max = 0x40001fe8; -__packed = 0x3fffc530; -_PathLocale = 0x3fffc040; +_ctype_ = 0x3ffac76c; +__default_global_locale = 0x3ffac600; +_global_impure_ptr = 0x3ffffd8c; +__global_locale_ptr = 0x3ffffd7c; +__locale_ctype_ptr = 0x40001c2c; +__locale_ctype_ptr_l = 0x40001c24; +__locale_mb_cur_max = 0x40001c0c; +__packed = 0x3ffffcec; +_PathLocale = 0x3ffffd80; diff --git a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-funcs.ld b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-funcs.ld index 22b41594b5..15dcfb5f34 100644 --- a/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-funcs.ld +++ b/components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.newlib-funcs.ld @@ -1,96 +1,93 @@ -/* These are the newlib functions present in ESP32S2beta ROM. - See also esp32s2beta.rom.newlib-data.ld for the list of .data/.bss symbols - used by these functions, and esp32s2beta.rom.newlib-stdio.ld for stdio related - functions. - - Unlike other ROM functions which are exported using PROVIDE, which declares - weak symbols, newlib related functions are exported using assignment, - which declares strong symbols. This is done so that ROM functions are always - used instead of the ones provided by libc.a. - */ - -abs = 0x4000073c; -__ascii_mbtowc = 0x40007de0; -__ascii_wctomb = 0x40001cac; -__assert = 0x4001565c; -__assert_func = 0x40015634; -atoi = 0x40000adc; -_atoi_r = 0x40000aec; -atol = 0x40000b04; -_atol_r = 0x40000b14; -bzero = 0x40007ca4; -_cvt = 0x4000c6d8; -div = 0x40000744; -isalnum = 0x40007cb4; -isalpha = 0x40007cc4; -isascii = 0x40015d18; -isblank = 0x40007cd4; -iscntrl = 0x40007cf4; -isdigit = 0x40007d0c; -isgraph = 0x40007d44; -islower = 0x40007d24; -isprint = 0x40007d5c; -ispunct = 0x40007d70; -isspace = 0x40007d88; -isupper = 0x40007da0; -itoa = 0x40000acc; -__itoa = 0x40000a90; -labs = 0x4000076c; -ldiv = 0x40000774; -longjmp = 0x400006c8; -_mbtowc_r = 0x40007dbc; -memccpy = 0x40015d2c; -memchr = 0x40015d50; -memcmp = 0x40015d6c; -memcpy = 0x40015dd4; -memmove = 0x40015edc; -memrchr = 0x40015f18; -memset = 0x40015f68; -pthread_setcancelstate = 0x400151d4; -qsort = 0x40000818; -rand = 0x40007e54; -rand_r = 0x40007ed0; -setjmp = 0x40000664; -srand = 0x40007e00; -strcasecmp = 0x40007f14; -strcasestr = 0x40007f58; -strcat = 0x40015fbc; -strchr = 0x40015fdc; -strcmp = 0x40007fc0; -strcoll = 0x400080c4; -strcpy = 0x400080d8; -strcspn = 0x40015ff8; -strdup = 0x40008160; -_strdup_r = 0x40008174; -strlcat = 0x40008194; -strlcpy = 0x40016024; -strlen = 0x400081e4; -strlwr = 0x40008244; -strncasecmp = 0x40008270; -strncat = 0x40016060; -strncmp = 0x40016090; -strncpy = 0x400082fc; -strndup = 0x400083c4; -_strndup_r = 0x400083d8; -strnlen = 0x400160c8; -strrchr = 0x4000841c; -strsep = 0x40008448; -strspn = 0x400160e8; -strstr = 0x40016114; -__strtok_r = 0x40016144; -strtok_r = 0x400161a8; -strtol = 0x40000c70; -strtol_l = 0x40000c58; -_strtol_r = 0x40000c34; -strtoul = 0x40000dcc; -strtoul_l = 0x40000db4; -_strtoul_r = 0x40000d90; -strupr = 0x40008460; -toascii = 0x400161bc; -tolower = 0x40008534; -toupper = 0x40008550; -utoa = 0x40000654; -__utoa = 0x400005f0; -wcrtomb = 0x400016d0; -_wcrtomb_r = 0x4000167c; -_wctomb_r = 0x40001c88; +abs = 0x40000618; +__ascii_mbtowc = 0x40007a04; +__ascii_wctomb = 0x400018d0; +__assert = 0x4001a430; +__assert_func = 0x4001a408; +/* +atoi = ; +_atoi_r = ; +atol = ; +_atol_r = ; +*/ +bzero = 0x400078c8; +_cvt = 0x4000f9b8; +div = 0x40000620; +isalnum = 0x400078d8; +isalpha = 0x400078e8; +isascii = 0x4001aaec; +isblank = 0x400078f8; +iscntrl = 0x40007918; +isdigit = 0x40007930; +isgraph = 0x40007968; +islower = 0x40007948; +isprint = 0x40007980; +ispunct = 0x40007994; +isspace = 0x400079ac; +isupper = 0x400079c4; +/* +itoa = ; +__itoa = ; +*/ +labs = 0x40000648; +ldiv = 0x40000650; +longjmp = 0x400005a4; +_mbtowc_r = 0x400079e0; +memccpy = 0x4001ab00; +memchr = 0x4001ab24; +memcmp = 0x4001ab40; +memcpy = 0x4001aba8; +memmove = 0x4001acb0; +memrchr = 0x4001acec; +memset = 0x4001ad3c; +pthread_setcancelstate = 0x40019fa8; +qsort = 0x400006f4; +rand = 0x40007a78; +rand_r = 0x40007af4; +setjmp = 0x40000540; +srand = 0x40007a24; +strcasecmp = 0x40007b38; +strcasestr = 0x40007b7c; +strcat = 0x4001ad90; +strchr = 0x4001adb0; +strcmp = 0x40007be4; +strcoll = 0x40007ce8; +strcpy = 0x40007cfc; +strcspn = 0x4001adcc; +strdup = 0x40007d84; +_strdup_r = 0x40007d98; +strlcat = 0x40007db8; +strlcpy = 0x4001adf8; +strlen = 0x40007e08; +strlwr = 0x40007e68; +strncasecmp = 0x40007e94; +strncat = 0x4001ae34; +strncmp = 0x4001ae64; +strncpy = 0x40007f20; +strndup = 0x40007fe8; +_strndup_r = 0x40007ffc; +strnlen = 0x4001ae9c; +strrchr = 0x40008040; +strsep = 0x4000806c; +strspn = 0x4001aebc; +strstr = 0x4001aee8; +__strtok_r = 0x4001af18; +strtok_r = 0x4001af7c; +/* +strtol = ; +strtol_l = ; +_strtol_r = ; +strtoul = ; +strtoul_l = ; +_strtoul_r = ; +*/ +strupr = 0x40008084; +toascii = 0x4001af90; +tolower = 0x40008158; +toupper = 0x40008174; +/* +utoa = ; +__utoa = ; +*/ +wcrtomb = 0x400012f4; +_wcrtomb_r = 0x400012a0; +_wctomb_r = 0x400018ac; diff --git a/components/esp_rom/esp_rom.c b/components/esp_rom/esp_rom.c deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/esp_rom/include/esp32s2beta/rom/cache.h b/components/esp_rom/include/esp32s2beta/rom/cache.h index 666053b36c..76ede22baf 100644 --- a/components/esp_rom/include/esp32s2beta/rom/cache.h +++ b/components/esp_rom/include/esp32s2beta/rom/cache.h @@ -15,7 +15,6 @@ #ifndef _ROM_CACHE_H_ #define _ROM_CACHE_H_ -#include "esp_bit_defs.h" #ifdef __cplusplus extern "C" { @@ -32,18 +31,23 @@ extern "C" { #define MIN_CACHE_SIZE 8192 #define MAX_CACHE_SIZE 16384 #define MIN_CACHE_WAYS 4 -#define MAX_CACHE_WAYS 8 +#define MAX_CACHE_WAYS 4 #define MIN_CACHE_LINE_SIZE 16 -#define MAX_CACHE_LINE_SIZE 64 //normally should be (MAX_CACHE_SIZE / MIN_CACHE_WAYS / MIN_CACHE_LINE_SIZE), however, the items not all in one tag memory block. -#define MAX_TAG_BLOCK_ITEMS (MAX_CACHE_SIZE / MAX_CACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_TAG_BLOCK_ITEMS (MAX_CACHE_SIZE / 8 / MIN_CACHE_LINE_SIZE) #define TAG_SIZE 4 #define MAX_TAG_BLOCK_SIZE (MAX_TAG_BLOCK_ITEMS * TAG_SIZE) +#define INVALID_PHY_PAGE 0xffff #define ESP_CACHE_TEMP_ADDR DROM0_ADDRESS_LOW #define CACHE_MAX_OPERATION_SIZE BUS_ADDR_SIZE +typedef enum { + CACHE_DCACHE = 0, + CACHE_ICACHE = 1, +} cache_t; + typedef enum { CACHE_MEMORY_INVALID = 0, CACHE_MEMORY_ICACHE_LOW = BIT(0), @@ -52,27 +56,22 @@ typedef enum { CACHE_MEMORY_DCACHE_HIGH = BIT(3), } cache_layout_t; +#define CACHE_SIZE_8KB CACHE_SIZE_HALF +#define CACHE_SIZE_16KB CACHE_SIZE_FULL typedef enum { - CACHE_SIZE_8KB = 0, - CACHE_SIZE_16KB = 1, + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ } cache_size_t; typedef enum { - CACHE_4WAYS_ASSOC = 0, - CACHE_8WAYS_ASSOC = 1, + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ } cache_ways_t; typedef enum { - CACHE_LINE_SIZE_16B = 0, - CACHE_LINE_SIZE_32B = 1, - CACHE_LINE_SIZE_64B = 2, + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ } cache_line_size_t; -typedef enum { - CACHE_AUTOLOAD_NORMAL_MODE = 0, /*!< normal mode will autoload anytime if enabled */ - CACHE_AUTOLOAD_REGION_MODE = 1, /*!< region mode only autoload if access the memory in regions */ -} cache_autoload_mode_t; - typedef enum { CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ @@ -87,10 +86,10 @@ typedef enum { } cache_autoload_trigger_t; struct cache_mode { - uint32_t cache_size; - uint16_t cache_line_size; - uint8_t cache_ways; - uint8_t icache; + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */ }; struct tag_item { @@ -105,11 +104,10 @@ struct tag_item { }; struct autoload_config { - uint8_t mode; /*!< autoload mode */ uint8_t order; /*!< autoload step is positive or negative */ - uint8_t step; /*!< autoload step */ uint8_t trigger; /*!< autoload trigger */ - uint32_t autoload_size; /*!< autoload size */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ uint32_t addr0; /*!< autoload region0 start address */ uint32_t size0; /*!< autoload region0 size */ uint32_t addr1; /*!< autoload region1 start address */ @@ -118,6 +116,7 @@ struct autoload_config { struct tag_group_info { struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ @@ -129,9 +128,10 @@ struct lock_config { uint16_t group; /*!< manual lock group, 0 or 1*/ }; -#define MMU_SET_ADDR_ALIGNED_ERROR 1 -#define MMU_SET_PASE_SIZE_ERROR 3 -#define MMU_SET_VADDR_OUT_RANGE 5 +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 /** * @brief Initialise cache mmu, mark all entries as invalid. @@ -164,9 +164,9 @@ void Cache_MMU_Init(void); * * @return uint32_t: error status * 0 : mmu set success - * 1 : vaddr or paddr is not aligned + * 2 : vaddr or paddr is not aligned * 3 : psize error - * 5 : vaddr is out of range + * 4 : vaddr is out of range */ int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); @@ -191,32 +191,12 @@ int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32 * * @return uint32_t: error status * 0 : mmu set success - * 1 : vaddr or paddr is not aligned + * 2 : vaddr or paddr is not aligned * 3 : psize error - * 5 : vaddr is out of range + * 4 : vaddr is out of range */ int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); -/** - * @brief Copy DRom0 ICache MMU to DCache MMU. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void MMU_Drom0_I2D_Copy(void); - -/** - * @brief Unmap DRom0 ICache MMU. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void MMU_Drom_ICache_Unmap(void); - /** * @brief Count the pages in the bus room address which map to Flash. * Please do not call this function in your SDK application. @@ -252,11 +232,11 @@ uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus, uint32_t bus_start_addr, uint3 * * @param cache_layout_t sram0_layout : the usage of first 8KB internal memory block, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW and CACHE_MEMORY_DCACHE_HIGH * - * @param cache_layout_t sram1_layout : the usage of second 8KB internal memory block + * @param cache_layout_t sram1_layout : the usage of second 8KB internal memory block * - * @param cache_layout_t sram2_layout : the usage of third 8KB internal memory block + * @param cache_layout_t sram2_layout : the usage of third 8KB internal memory block * - * @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block + * @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block * * return none */ @@ -266,7 +246,7 @@ void Cache_Allocate_SRAM(cache_layout_t sram0_layout, cache_layout_t sram1_layou * @brief Get cache mode of ICache or DCache. * Please do not call this function in your SDK application. * - * @param struct cache_mode * mode : the pointer of cache mode struct + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field * * return none */ @@ -276,13 +256,11 @@ void Cache_Get_Mode(struct cache_mode * mode); * @brief set ICache modes: cache size, associate ways and cache line size. * Please do not call this function in your SDK application. * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL * - * @param cache_ways_t ways : the associate ways of cache, cane be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * @param cache_ways_t ways : the associate ways of cache, can only be CACHE_4WAYS_ASSOC * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B * * return none */ @@ -292,13 +270,11 @@ void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_lin * @brief set DCache modes: cache size, associate ways and cache line size. * Please do not call this function in your SDK application. * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL * - * @param cache_ways_t ways : the associate ways of cache, cane be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * @param cache_ways_t ways : the associate ways of cache, can only be CACHE_4WAYS_ASSOC * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B * * return none */ @@ -327,92 +303,100 @@ uint32_t Cache_Address_Through_DCache(uint32_t addr); /** * @brief Invalidate the cache items for ICache. * Operation will be done CACHE_LINE_SIZE aligned. - * If the addr is not in our addr room, we will Flush all Cache. + * If the region is not in ICache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr: start address to invalidate * - * @param uint32_t size: size to invalidate, should <= 4MB + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) * * @return None */ -void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t size); +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); /** * @brief Invalidate the cache items for DCache. * Operation will be done CACHE_LINE_SIZE aligned. - * If the addr is not in our addr room, we will Flush all Cache. + * If the region is not in DCache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr: start address to invalidate * - * @param uint32_t size: size to invalidate, should <= 4MB + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) * * @return None */ -void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t size); +void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t items); /** * @brief Clean the dirty bit of cache Items of DCache. * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr: start address to Clean * - * @param uint32_t size: size to Clean, should <= 4MB + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) * * @return None */ -void Cache_Clean_Items(uint32_t addr, uint32_t size); +void Cache_Clean_Items(uint32_t addr, uint32_t items); /** * @brief Write back the cache items of DCache. * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr: start address to write back * - * @param uint32_t size: size to write back, should <= 4MB + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) * * @return None */ -void Cache_WriteBack_Items(uint32_t addr, uint32_t size); +void Cache_WriteBack_Items(uint32_t addr, uint32_t items); /** * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr : invalidated region start address. * * @param uint32_t size : invalidated region size. * - * @return None + * @return 0 for success + * 1 for invalid argument */ -void Cache_Invalidate_Addr(uint32_t addr, uint32_t size); +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); /** * @brief Clean the dirty bit of Cache items in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr : cleaned region start address. * * @param uint32_t size : cleaned region size. * - * @return None + * @return 0 for success + * 1 for invalid argument */ -void Cache_Clean_Addr(uint32_t addr, uint32_t size); +int Cache_Clean_Addr(uint32_t addr, uint32_t size); /** * @brief Writeback the Cache items(also clean the dirty bit) in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. * Please do not call this function in your SDK application. * * @param uint32_t addr : writeback region start address. * * @param uint32_t size : writeback region size. * - * @return None + * @return 0 for success + * 1 for invalid argument */ -void Cache_WriteBack_Addr(uint32_t addr, uint32_t size); +int Cache_WriteBack_Addr(uint32_t addr, uint32_t size); /** @@ -466,7 +450,7 @@ void Cache_WriteBack_All(void); void Cache_Mask_All(void); /** - * @brief UnMask DRom0 bus through ICache or DCache. + * @brief UnMask DRom0 bus through ICache. * Please do not call this function in your SDK application. * * @param None @@ -644,17 +628,18 @@ void Cache_Enable_DCache_Autoload(void); void Cache_Disable_DCache_Autoload(void); /** - * @brief Config a group of lock parameters of ICache. + * @brief Config a group of prelock parameters of ICache. * Please do not call this function in your SDK application. * * @param struct lock_config * config : a group of lock parameters. * * @return None */ -void Cache_Enable_ICache_Lock(const struct lock_config *config); + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); /** - * @brief Disable a group of lock parameters for ICache. + * @brief Disable a group of prelock parameters for ICache. * However, the locked data will not be released. * Please do not call this function in your SDK application. * @@ -662,32 +647,48 @@ void Cache_Enable_ICache_Lock(const struct lock_config *config); * * @return None */ -void Cache_Disable_ICache_Lock(uint16_t group); +void Cache_Disable_ICache_PreLock(uint16_t group); /** - * @brief Unlock the cache items in tag memory for ICache. + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. * Please do not call this function in your SDK application. * - * @param uint32_t addr : start address of unlock region. + * @param uint32_t addr: start address to lock * - * @param uint32_t size : size of unlock region. + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(4MB) * * @return None */ -void Cache_Unlock_ICache(uint32_t addr, uint32_t size); +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); /** - * @brief Config a group of lock parameters of DCache. + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(4MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Config a group of prelock parameters of DCache. * Please do not call this function in your SDK application. * * @param struct lock_config * config : a group of lock parameters. * * @return None */ -void Cache_Enable_DCache_Lock(const struct lock_config *config); +void Cache_Enable_DCache_PreLock(const struct lock_config *config); /** - * @brief Disable a group of lock parameters for DCache. + * @brief Disable a group of prelock parameters for DCache. * However, the locked data will not be released. * Please do not call this function in your SDK application. * @@ -695,19 +696,61 @@ void Cache_Enable_DCache_Lock(const struct lock_config *config); * * @return None */ -void Cache_Disable_DCache_Lock(uint16_t group); +void Cache_Disable_DCache_PreLock(uint16_t group); /** - * @brief Unlock the cache items in tag memory for DCache. + * @brief Lock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(4MB) + * + * @return None + */ +void Cache_Lock_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(4MB) + * + * @return None + */ +void Cache_Unlock_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. * Please do not call this function in your SDK application. * * @param uint32_t addr : start address of unlock region. * * @param uint32_t size : size of unlock region. * - * @return None + * @return 0 for success + * 1 for invalid argument */ -void Cache_Unlock_DCache(uint32_t addr, uint32_t size); +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); /** * @brief Disable ICache access for the cpu. @@ -729,7 +772,7 @@ uint32_t Cache_Disable_ICache(void); void Cache_Enable_ICache(uint32_t autoload); /** - * @brief Disable DCache access for the cpu. + * @brief Disable DCache access for the cpu. * This operation will make all DCache tag memory invalid, CPU can't access DCache, DCache will keep idle * Please do not call this function in your SDK application. * @@ -748,7 +791,7 @@ uint32_t Cache_Disable_DCache(void); void Cache_Enable_DCache(uint32_t autoload); /** - * @brief Suspend ICache access for the cpu. + * @brief Suspend ICache access for the cpu. * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). * Please do not call this function in your SDK application. @@ -791,48 +834,12 @@ uint32_t Cache_Suspend_DCache(void); */ void Cache_Resume_DCache(uint32_t autoload); -/** - * @brief Make Drom0 bus access from ICache. - * - * @param None - * - * @return None - */ -void Cache_Drom0_Source_ICache(void); - -/** - * @brief Make Drom0 bus access from DCache. - * - * @param None - * - * @return None - */ -void Cache_Drom0_Source_DCache(void); - -/** - * @brief Return if Drom0 bus access from ICache. - * - * @param None - * - * @return uint32_t: 0 for no, other for yes - */ -uint32_t Cache_Drom0_Using_ICache(void); - -/** - * @brief Return if Drom0 bus access from DCache. - * - * @param None - * - * @return uint32_t: 0 for no, other for yes - */ -uint32_t Cache_Drom0_Using_DCache(void); - /** * @brief Get ICache cache line size * * @param None * - * @return uint32_t: 16, 32, 64 Byte + * @return uint32_t: 16, 32 Byte */ uint32_t Cache_Get_ICache_Line_Size(void); @@ -841,12 +848,12 @@ uint32_t Cache_Get_ICache_Line_Size(void); * * @param None * - * @return uint32_t: 16, 32, 64 Byte + * @return uint32_t: 16, 32 Byte */ uint32_t Cache_Get_DCache_Line_Size(void); /** - * @brief Set default mode from boot. + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. * * @param None * @@ -854,6 +861,15 @@ uint32_t Cache_Get_DCache_Line_Size(void); */ void Cache_Set_Default_Mode(void); +/** + * @brief Set default mode from boot, 8KB DCache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +void Cache_Enable_Defalut_DCache_Mode(void); + /** * @brief Travel tag memory to run a call back function. * ICache and DCache are suspend when doing this. diff --git a/components/esp_rom/include/esp32s2beta/rom/digital_signature.h b/components/esp_rom/include/esp32s2beta/rom/digital_signature.h new file mode 100644 index 0000000000..1f8a943d49 --- /dev/null +++ b/components/esp_rom/include/esp32s2beta/rom/digital_signature.h @@ -0,0 +1,148 @@ +/* + ROM functions for hardware Digital Signature peripheral verification +*/ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ETS_DS_IV_LEN 16 + +/* Length of parameter 'C' stored in flash */ +#define ETS_DS_C_LEN (12672 / 8) + +/* Encrypted ETS data. Recommended to store in flash in this format. + */ +typedef struct { + /* RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * Max value 127 (for RSA 4096). + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + */ + unsigned rsa_length; + + /* IV value used to encrypt 'c' */ + uint8_t iv[ETS_DS_IV_LEN]; + + /* Encrypted Digital Signature parameters. Result of AES-CBC encryption + of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ETS_DS_C_LEN]; +} ets_ds_data_t; + +typedef enum { + ETS_DS_OK, + ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ + ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ + ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ + ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ +} ets_ds_result_t; + +void ets_ds_enable(void); + +void ets_ds_disable(void); + + +/* + * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral + * + * - @param message Pointer to message (or padded digest) containing the message to sign. Should be + * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data + * in flash. + * + * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling + * this function, and is responsible for calling ets_ds_finish_sign() and then + * ets_hmac_invalidate_downstream() afterwards. + * + * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, + * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. + */ +ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); + + +/* + * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() + * + * A result of false indicates that a call to ets_ds_finish_sign() will not block. + * + * Only valid if ets_ds_enable() has been called. + */ +bool ets_ds_is_busy(void); + + +/* @brief Finish signing a message using the Digital Signature peripheral + * + * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until + * peripheral is no longer busy. + * + * - @param signature Pointer to buffer to contain the signature. Should be + * (data->rsa_length + 1)*4 bytes long. + * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() + * + * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, + * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the + * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a + * digest is produced anyhow.) + */ +ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); + + +/* Plaintext parameters used by Digital Signature. + + Not used for signing with DS peripheral, but can be encrypted + in-device by calling ets_ds_encrypt_params() +*/ +typedef struct { + uint32_t Y[4096/32]; + uint32_t M[4096/32]; + uint32_t Rb[4096/32]; + uint32_t M_prime; + uint32_t length; +} ets_ds_p_data_t; + +typedef enum { + ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ + ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ +} ets_ds_key_t; + +/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. + * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) + * + * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. + */ +ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); + + +#ifdef __cplusplus +} +#endif + diff --git a/components/esp_rom/include/esp32s2beta/rom/efuse.h b/components/esp_rom/include/esp32s2beta/rom/efuse.h index 4697bc305a..ae887278bd 100644 --- a/components/esp_rom/include/esp32s2beta/rom/efuse.h +++ b/components/esp_rom/include/esp32s2beta/rom/efuse.h @@ -50,7 +50,7 @@ typedef enum { typedef enum { ETS_EFUSE_BLOCK0 = 0, - ETS_EFUSE_MAC_SPI_8M_0 = 1, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, ETS_EFUSE_BLOCK_SYS_DATA = 2, ETS_EFUSE_BLOCK_USR_DATA = 3, ETS_EFUSE_BLOCK_KEY0 = 4, @@ -63,6 +63,15 @@ typedef enum { ETS_EFUSE_BLOCK_MAX, } ets_efuse_block_t; +/** + * @brief set timing accroding the apb clock, so no read error or write error happens. + * + * @param clock: apb clock in HZ, only accept 20M, 40M, 80M. + * + * @return : 0 if success, others if clock not accepted + */ +int ets_efuse_set_timing(uint32_t clock); + /** * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. */ @@ -73,18 +82,18 @@ void ets_efuse_start(void); * * @param null * - * @return null + * @return : 0 is success, others if apb clock is not accepted */ -void ets_efuse_read(void); +int ets_efuse_read(void); /** * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. * * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. * - * @return null + * @return : 0 is success, others if apb clock is not accepted */ -void ets_efuse_program(ets_efuse_block_t block); +int ets_efuse_program(ets_efuse_block_t block); /** * @brief Set all Efuse program registers to zero. @@ -97,7 +106,7 @@ void ets_efuse_clear_program_registers(void); * @brief Program a block of key data to an efuse block * * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). - * @param purpose Purpose to set for this key. + * @param purpose Purpose to set for this key. Purpose must be already unset. * @param data Pointer to data to write. * @param data_len Length of data to write. * @@ -167,25 +176,6 @@ unsigned ets_efuse_count_unused_key_blocks(void); */ void ets_efuse_rs_calculate(const void *data, void *rs_values); -/** - * @brief Read 8M Analog Clock value(12 bits) in efuse, the analog clock will not change with temperature. - * It can be used to test the external xtal frequency, do not touch this efuse field. - * - * @param null - * - * @return uint32_t: 1 for 10KHZ, range is 0 to 4095. - */ -uint32_t ets_efuse_get_8M_clock(void); - -/** - * @brief Read xtal frequency value(6 bits) in efuse. - * - * @param null - * - * @return uint32_t: 1 for 1MHz, range is 0 to 63, 0 means the xtal frequency not record in efuse. - */ -uint32_t ets_efuse_get_xtal_freq(void); - /** * @brief Read spi flash pads configuration from Efuse * @@ -207,6 +197,16 @@ uint32_t ets_efuse_get_spiconfig(void); */ uint32_t ets_efuse_get_wp_pad(void); +/** + * @brief Read opi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: + * DQS, D4, D5, D6, D7 accordingly. + */ +uint32_t ets_efuse_get_opiconfig(void); + /** * @brief Read if download mode disabled from Efuse * @@ -246,7 +246,10 @@ uint32_t ets_efuse_get_uart_print_control(void); uint32_t ets_efuse_get_uart_print_channel(void); /** - * @brief Read if usb dowload mode disabled from Efuse + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) * * @return * - true for efuse disable usb download mode. @@ -282,14 +285,49 @@ bool ets_efuse_usb_module_disabled(void); bool ets_efuse_security_download_modes_enabled(void); /** - * @brief Return true if secure boot enable in EFuse + * @brief Return true if secure boot is enabled in EFuse */ bool ets_efuse_secure_boot_enabled(void); -/** - * @brief return the time in us ROM boot need wait flash to power on from Efuse - * - * @return +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, PSRAM, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates an external phy needs to be used for USB + */ +bool ets_efuse_usb_use_ext_phy(void); + +/** + * @brief Return true if EFuse indicates USB device persistence is disabled + */ +bool ets_efuse_usb_force_nopersist(void); + +/** + * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU + */ +bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); + +/** + * @brief Return true if EFuse indicates an opi flash is attached. + */ +bool ets_efuse_flash_opi_mode(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return * - uint32_t the time in us. */ uint32_t ets_efuse_get_flash_delay_us(void); diff --git a/components/esp_rom/include/esp32s2beta/rom/ets_sys.h b/components/esp_rom/include/esp32s2beta/rom/ets_sys.h index 653ca2826c..1d4763dbf9 100644 --- a/components/esp_rom/include/esp32s2beta/rom/ets_sys.h +++ b/components/esp_rom/include/esp32s2beta/rom/ets_sys.h @@ -12,7 +12,8 @@ // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _ROM_ETS_SYS_H_ +#define _ROM_ETS_SYS_H_ #include #include @@ -188,6 +189,23 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); +/** + * @brief Set the uart channel of ets_printf(uart_tx_one_char). + * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. + * + * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2. + * + * @return None + */ +void ets_set_printf_channel(uint8_t uart_no); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + /** * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. * Can not print float point data format, or longlong data format @@ -359,6 +377,18 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * + * @note This function only sets the tick rate for the current CPU. It is located in ROM, + * so the deep sleep stub can use it even if IRAM is not initialized yet. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. @@ -369,15 +399,6 @@ void ets_update_cpu_frequency(uint32_t ticks_per_us); */ uint32_t ets_get_cpu_frequency(void); -/** - * @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module. - * - * @param None - * - * @return uint32_t : xtal_freq/analog_8M*256. - */ -uint32_t ets_get_xtal_scale(void); - /** * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. * @@ -391,6 +412,32 @@ uint32_t ets_get_xtal_scale(void); */ uint32_t ets_get_xtal_freq(void); +/** + * @brief Get the apb divisor. The xtal frequency gets divided + * by this value to generate the APB clock. + * When any types of reset happens, the default value is 2. + * + * @param None + * + * @return uint32_t : 1 or 2. + */ +uint32_t ets_get_xtal_div(void); + + +/** + * @brief Modifies the apb divisor. The xtal frequency gets divided by this to + * generate the APB clock. + * + * @note The xtal frequency divisor is 2 by default as the glitch detector + * doesn't properly stop glitches when it is 1. Please do not set the + * divisor to 1 before the PLL is active without being aware that you + * may be introducing a security risk. + * + * @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq. + */ +void ets_set_xtal_div(int div); + + /** * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. * @@ -607,3 +654,5 @@ typedef enum { #ifdef __cplusplus } #endif + +#endif /* _ROM_ETS_SYS_H_ */ diff --git a/components/esp_rom/include/esp32s2beta/rom/gpio.h b/components/esp_rom/include/esp32s2beta/rom/gpio.h index 0842208b16..eaf46da2e9 100644 --- a/components/esp_rom/include/esp32s2beta/rom/gpio.h +++ b/components/esp_rom/include/esp32s2beta/rom/gpio.h @@ -242,18 +242,18 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_ * * @return None */ -void gpio_pad_select_gpio(uint8_t gpio_num); +void gpio_pad_select_gpio(uint32_t gpio_num); /** * @brief Set pad driver capability. * * @param uint32_t gpio_num : gpio number, 0~0x2f * - * @param uint8_t drv : 0-3 + * @param uint32_t drv : 0-3 * * @return None */ -void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv); +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); /** * @brief Pull up the pad from gpio number. @@ -262,7 +262,7 @@ void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv); * * @return None */ -void gpio_pad_pullup(uint8_t gpio_num); +void gpio_pad_pullup(uint32_t gpio_num); /** * @brief Pull down the pad from gpio number. @@ -271,7 +271,7 @@ void gpio_pad_pullup(uint8_t gpio_num); * * @return None */ -void gpio_pad_pulldown(uint8_t gpio_num); +void gpio_pad_pulldown(uint32_t gpio_num); /** * @brief Unhold the pad from gpio number. @@ -280,7 +280,7 @@ void gpio_pad_pulldown(uint8_t gpio_num); * * @return None */ -void gpio_pad_unhold(uint8_t gpio_num); +void gpio_pad_unhold(uint32_t gpio_num); /** * @brief Hold the pad from gpio number. @@ -289,7 +289,25 @@ void gpio_pad_unhold(uint8_t gpio_num); * * @return None */ -void gpio_pad_hold(uint8_t gpio_num); +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @brief disable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_input_disable(uint32_t gpio_num); /** * @} diff --git a/components/esp_rom/include/esp32s2beta/rom/lldesc.h b/components/esp_rom/include/esp32s2beta/rom/lldesc.h index ae5b4160ba..a11be3767f 100644 --- a/components/esp_rom/include/esp32s2beta/rom/lldesc.h +++ b/components/esp_rom/include/esp32s2beta/rom/lldesc.h @@ -71,7 +71,7 @@ typedef struct lldesc_s { sosf : 1, /* start of sub-frame */ eof : 1, /* end of frame */ owner : 1; /* hw or sw */ - volatile uint8_t *buf; /* point to buffer data */ + volatile const uint8_t *buf; /* point to buffer data */ union{ volatile uint32_t empty; STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */ diff --git a/components/esp_rom/include/esp32s2beta/rom/opi_flash.h b/components/esp_rom/include/esp32s2beta/rom/opi_flash.h new file mode 100644 index 0000000000..ee2490bed4 --- /dev/null +++ b/components/esp_rom/include/esp32s2beta/rom/opi_flash.h @@ -0,0 +1,291 @@ +/* + * copyright (c) Espressif System 2019 + * + */ + +#ifndef _ROM_OPI_FLASH_H_ +#define _ROM_OPI_FLASH_H_ +#include +#include +#include +#include "spi_flash.h" + +typedef struct { + uint16_t cmd; /*!< Command value */ + uint16_t cmdBitLen; /*!< Command byte length*/ + uint32_t *addr; /*!< Point to address value*/ + uint32_t addrBitLen; /*!< Address byte length*/ + uint32_t *txData; /*!< Point to send data buffer*/ + uint32_t txDataBitLen; /*!< Send data byte length.*/ + uint32_t *rxData; /*!< Point to recevie data buffer*/ + uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/ + uint32_t dummyBitLen; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +// Definition of MX25UM25645G Octa Flash +// SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +// FLASH commands +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +// Definitions for GigaDevice GD25LX256E Flash +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +// spi user mode command config + +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission + */ +void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ +void esp_rom_opiflash_pin_config(void); + +// set SPI read/write mode +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ +void esp_rom_opiflash_mode_reset(int spi_num); + +#if 0 +// MX25UM25645G opi flash interface +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase flash operation + */ +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash ID(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash id + */ +uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash status register(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash status value + */ +uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief wait opi flash status register to be idle + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of configure register + * @return value of config register2 + */ +uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr); + +/** + * @brief to write the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of config register + * @param val the value to write + */ +void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val); + +/** + * @brief to erase flash sector(for MX25UM25645G) + * @param spi_num spi port + * @param address the sector address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase flash block(for MX25UM25645G) + * @param spi_num spi port + * @param address the block address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase a flash area define by start address and length(for MX25UM25645G) + * @param spi_num spi port + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @param mode flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read data from opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len); + +/** + * @brief to write data to opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len); + +/** + * @brief to set opi flash operation mode(for MX25UM25645G) + * @param spi_num spi port + * @param cur_mode current operation mode + * @param target the target operation mode to be set + */ +void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode); +#endif + +#endif diff --git a/components/esp_rom/include/esp32s2beta/rom/rsa_pss.h b/components/esp_rom/include/esp32s2beta/rom/rsa_pss.h index cd6218f7f8..6a70c578c3 100644 --- a/components/esp_rom/include/esp32s2beta/rom/rsa_pss.h +++ b/components/esp_rom/include/esp32s2beta/rom/rsa_pss.h @@ -16,6 +16,7 @@ #define _ROM_RSA_PSS_H_ #include +#include "rsa_pss.h" #define ETS_SIG_LEN 384 /* Bytes */ #define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ diff --git a/components/esp_rom/include/esp32s2beta/rom/rtc.h b/components/esp_rom/include/esp32s2beta/rom/rtc.h index c46c9c1f56..593e885457 100644 --- a/components/esp_rom/include/esp32s2beta/rom/rtc.h +++ b/components/esp_rom/include/esp32s2beta/rom/rtc.h @@ -82,8 +82,7 @@ typedef enum { NO_MEAN = 0, POWERON_RESET = 1, /**<1, Vbat power on reset*/ RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/ - DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/ - SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/ + DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/ TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/ TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/ RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/ @@ -93,8 +92,9 @@ typedef enum { RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ - TG1WDT_CPU_RESET = 17, /**<11, Time Group1 reset CPU*/ - SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/ + TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/ + SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/ + GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/ } RESET_REASON; typedef enum { diff --git a/components/esp_rom/include/esp32s2beta/rom/spi_flash.h b/components/esp_rom/include/esp32s2beta/rom/spi_flash.h index a94772b6ea..5d2a261fd8 100644 --- a/components/esp_rom/include/esp32s2beta/rom/spi_flash.h +++ b/components/esp_rom/include/esp32s2beta/rom/spi_flash.h @@ -19,7 +19,6 @@ #include #include "esp_attr.h" - #include "soc/spi_mem_reg.h" #ifdef __cplusplus @@ -83,18 +82,18 @@ extern "C" { #define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) #define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) -#define SPI0_R_QIO_DUMMY_CYCLELEN 3 -#define SPI0_R_QIO_ADDR_BITSLEN 31 +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 #define SPI0_R_DIO_DUMMY_CYCLELEN 3 #define SPI0_R_FAST_ADDR_BITSLEN 23 #define SPI0_R_SIO_ADDR_BITSLEN 23 -#define SPI1_R_QIO_DUMMY_CYCLELEN 3 -#define SPI1_R_QIO_ADDR_BITSLEN 31 +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 #define SPI1_R_FAST_DUMMY_CYCLELEN 7 #define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 31 +#define SPI1_R_DIO_ADDR_BITSLEN 23 #define SPI1_R_FAST_ADDR_BITSLEN 23 #define SPI1_R_SIO_ADDR_BITSLEN 23 @@ -125,7 +124,12 @@ typedef enum { ESP_ROM_SPIFLASH_DIO_MODE, ESP_ROM_SPIFLASH_DOUT_MODE, ESP_ROM_SPIFLASH_FASTRD_MODE, - ESP_ROM_SPIFLASH_SLOWRD_MODE + ESP_ROM_SPIFLASH_SLOWRD_MODE, + ESP_ROM_SPIFASH_OPI_STR_MODE, + ESP_ROM_SPIFASH_OPI_DTR_MODE, + ESP_ROM_SPIFASH_OOUT_MODE, + ESP_ROM_SPIFASH_OIO_STR_MODE, + ESP_ROM_SPIFASH_OIO_DTR_MODE, } esp_rom_spiflash_read_mode_t; typedef enum { @@ -359,7 +363,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. */ -esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); /** diff --git a/components/esp_rom/include/esp32s2beta/rom/uart.h b/components/esp_rom/include/esp32s2beta/rom/uart.h index d69354d3f0..0c23c976b5 100644 --- a/components/esp_rom/include/esp32s2beta/rom/uart.h +++ b/components/esp_rom/include/esp32s2beta/rom/uart.h @@ -33,7 +33,7 @@ extern "C" { * @{ */ -#define RX_BUFF_SIZE 0x100 +#define RX_BUFF_SIZE 0x400 #define TX_BUFF_SIZE 100 //uart int enalbe register ctrl bits @@ -156,7 +156,6 @@ typedef struct { UartStopBitsNum stop_bits; UartFlowCtrl flow_ctrl; uint8_t buff_uart_no; //indicate which uart use tx/rx buffer - uint8_t tx_uart_no; RcvMsgBuff rcv_buff; // TrxMsgBuff trx_buff; RcvMsgState rcv_state; @@ -167,11 +166,11 @@ typedef struct { * @brief Init uart device struct value and reset uart0/uart1 rx. * Please do not call this function in SDK. * - * @param None + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL * * @return None */ -void uartAttach(void); +void uartAttach(void *rxBuffer); /** * @brief Init uart0 or uart1 for UART download booting mode. @@ -197,6 +196,21 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Re-calculate UART baudrate divisor for a given (changed) + * clock speed. + * This function will not reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void uart_div_reinit(uint8_t uart_no, uint32_t clock); + + /** * @brief Init uart0 or uart1 for UART download booting mode. * Please do not call this function in SDK. @@ -401,6 +415,33 @@ STATUS SendMsg(uint8_t *pData, uint16_t DataLen); */ STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); +/** + * @brief Check if this UART is in download connection. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return ETS_NO_BOOT = 0 for no. + * SEL_UART_BOOT = BIT(1) for yes. + */ +uint8_t UartConnCheck(uint8_t uart_no); + +/** + * @brief Initialize the USB ACM UART + * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. + * + * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code + * @param cdc_acm_work_mem_len Length of work mem + */ +void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); + + +/** + * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. + */ +void uart_usb_enable_reset_on_rts(void); + + extern UartDevice UartDev; /** diff --git a/components/espcoredump/src/core_dump_common.c b/components/espcoredump/src/core_dump_common.c index 39c6150e41..1b6d7bac72 100644 --- a/components/espcoredump/src/core_dump_common.c +++ b/components/espcoredump/src/core_dump_common.c @@ -21,7 +21,7 @@ const static DRAM_ATTR char TAG[] __attribute__((unused)) = "esp_core_dump_commo #if CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN -static inline uint32_t esp_core_dump_get_tcb_len() +static inline uint32_t esp_core_dump_get_tcb_len(void) { if (COREDUMP_TCB_SIZE % sizeof(uint32_t)) { return ((COREDUMP_TCB_SIZE / sizeof(uint32_t) + 1) * sizeof(uint32_t)); diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index f04d34bcab..51fe3c19f1 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit f04d34bcab29ace798d2d3800ba87020cccbbfdd +Subproject commit 51fe3c19f1b999869d9b071665c9555f24df924c diff --git a/components/mbedtls/port/esp32s2beta/aes.c b/components/mbedtls/port/esp32s2beta/aes.c index 6aeec03196..ab28518354 100644 --- a/components/mbedtls/port/esp32s2beta/aes.c +++ b/components/mbedtls/port/esp32s2beta/aes.c @@ -25,20 +25,57 @@ * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ +#include #include +#include #include "mbedtls/aes.h" #include "esp32s2beta/aes.h" +#include "esp32s2beta/gcm.h" +#include "soc/soc.h" +#include "soc/cpu.h" #include "soc/dport_reg.h" #include "soc/hwcrypto_reg.h" -#include +#include "soc/crypto_dma_reg.h" +#include "esp32s2beta/crypto_dma.h" +#include "esp32s2beta/rom/lldesc.h" +#include "esp32s2beta/rom/cache.h" +#include "soc/periph_defs.h" +#include "esp_intr_alloc.h" -#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" -#include "soc/cpu.h" -#include #define AES_BLOCK_BYTES 16 +#define LE_TO_BE(x) (((x) >> 24) & 0x000000ff) | \ + (((x) << 24) & 0xff000000) | \ + (((x) >> 8) & 0x0000ff00) | \ + (((x) << 8) & 0x00ff0000) + +static inline uint32_t WPA_GET_BE32(const uint8_t *a) +{ + return ((uint32_t) a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]; +} + +static inline void WPA_PUT_BE32(uint8_t *a, uint32_t val) +{ + a[0] = (val >> 24) & 0xff; + a[1] = (val >> 16) & 0xff; + a[2] = (val >> 8) & 0xff; + a[3] = val & 0xff; +} + + +/* Enable this if want to use AES interrupt */ +//#define CONFIG_MBEDTLS_AES_USE_INTERRUPT + +portMUX_TYPE crypto_dma_spinlock = portMUX_INITIALIZER_UNLOCKED; + +#if defined(CONFIG_MBEDTLS_AES_USE_INTERRUPT) +static SemaphoreHandle_t op_complete_sem; +#endif /* AES uses a spinlock mux not a lock as the underlying block operation only takes a small number of cycles, much less than using @@ -47,7 +84,28 @@ For CBC, CFB, etc. this may mean that interrupts are disabled for a longer period of time for bigger data lengths. */ -static portMUX_TYPE aes_spinlock = portMUX_INITIALIZER_UNLOCKED; +portMUX_TYPE aes_spinlock = portMUX_INITIALIZER_UNLOCKED; + +/* The function will pad 0 if the length is not multiple of + * 16 bytes for the incoming data buffer + */ +static uint8_t *textpad_zero(const unsigned char *buf, unsigned char *len) +{ + uint8_t offset; + uint8_t *data = NULL; + + offset = *len % AES_BLOCK_BYTES; + + if (offset) { + data = (uint8_t *)calloc(1, (*len + (AES_BLOCK_BYTES - offset))); + if (data) { + memcpy(data, buf, *len); + *len += (AES_BLOCK_BYTES - offset); + } + } + + return data; +} static inline bool valid_key_length(const esp_aes_context *ctx) { @@ -59,31 +117,44 @@ void esp_aes_acquire_hardware( void ) /* newlib locks lazy initialize on ESP-IDF */ portENTER_CRITICAL(&aes_spinlock); + /* Need to lock DMA since it is shared with SHA block */ + portENTER_CRITICAL(&crypto_dma_spinlock); + /* Enable AES hardware */ - REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES); + REG_SET_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_AES_CLK_EN | DPORT_CRYPTO_DMA_CLK_EN); /* Clear reset on digital signature unit, otherwise AES unit is held in reset also. */ - REG_CLR_BIT(DPORT_PERI_RST_EN_REG, - DPORT_PERI_EN_AES - | DPORT_PERI_EN_DIGITAL_SIGNATURE); + REG_CLR_BIT(DPORT_PERIP_RST_EN1_REG, + DPORT_CRYPTO_AES_RST | DPORT_CRYPTO_DMA_RST | DPORT_CRYPTO_DS_RST); } +/* Function to disable AES and Crypto DMA clocks and release locks */ void esp_aes_release_hardware( void ) { + /* Disable DMA mode */ + REG_WRITE(AES_DMA_ENABLE_REG, 0); /* Disable AES hardware */ - REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_AES); + REG_SET_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_AES_RST | DPORT_CRYPTO_DMA_RST); /* Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively. */ - REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_AES); + REG_CLR_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_AES_CLK_EN | DPORT_CRYPTO_DMA_CLK_EN); + + portEXIT_CRITICAL(&crypto_dma_spinlock); portEXIT_CRITICAL(&aes_spinlock); } +/* Function to init AES context to zero */ void esp_aes_init( esp_aes_context *ctx ) { + if ( ctx == NULL ) { + return; + } + bzero( ctx, sizeof( esp_aes_context ) ); } +/* Function to clear AES context */ void esp_aes_free( esp_aes_context *ctx ) { if ( ctx == NULL ) { @@ -111,14 +182,16 @@ int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, /* * Helper function to copy key from esp_aes_context buffer - * to hardware key registers. + * to hardware key registers. Also, set the AES block mode + * (ECb, CBC, CFB, OFB, GCM, CTR) and crypt mode (ENCRYPT/DECRYPT) + * Enable the DMA mode of operation * * Call only while holding esp_aes_acquire_hardware(). */ -static inline void esp_aes_setkey_hardware( esp_aes_context *ctx, int mode) +static inline void esp_aes_setkey_hardware( esp_aes_context *ctx, int crypt_mode, uint8_t block_mode) { const uint32_t MODE_DECRYPT_BIT = 4; - unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; + unsigned mode_reg_base = (crypt_mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT; ctx->key_in_hardware = 0; @@ -129,6 +202,20 @@ static inline void esp_aes_setkey_hardware( esp_aes_context *ctx, int mode) REG_WRITE(AES_MODE_REG, mode_reg_base + ((ctx->key_bytes / 8) - 2)); + /* Set the algorithm mode CBC, CFB ... */ + REG_WRITE(AES_BLOCK_MODE_REG, block_mode); + + /* Set the ENDIAN reg */ + REG_WRITE(AES_ENDIAN_REG, 0x3F); + + /* Enable DMA mode */ + REG_WRITE(AES_DMA_ENABLE_REG, 1); + + /* Presently hard-coding the INC function to 32 bit */ + if (block_mode == AES_BLOCK_MODE_CTR) { + REG_WRITE(AES_INC_SEL_REG, 0); + } + /* Fault injection check: all words of key data should have been written to hardware */ if (ctx->key_in_hardware < 16 || ctx->key_in_hardware != ctx->key_bytes) { @@ -136,12 +223,134 @@ static inline void esp_aes_setkey_hardware( esp_aes_context *ctx, int mode) } } -/* Run a single 16 byte block of AES, using the hardware engine. - * - * Call only while holding esp_aes_acquire_hardware(). +/* + * Function to write IV to hardware iv registers */ -static inline int esp_aes_block(esp_aes_context *ctx, const void *input, void *output) +static inline void esp_aes_set_iv(uint8_t *iv, uint8_t len) { + memcpy((uint8_t *)AES_IV_BASE, iv, len); +} + +/* + * Function to read IV from hardware iv registers + */ +static inline void esp_aes_get_iv(uint8_t *iv, uint8_t len) +{ + memcpy(iv, (uint8_t *)AES_IV_BASE, len); +} + +/* Function to set block number & trigger bit for AES GCM operation +*/ +static inline void esp_aes_gcm_set_block_num_and_trigger(uint16_t len) +{ + /* Write the number of blocks */ + REG_WRITE(AES_BLOCK_NUM_REG, (len / AES_BLOCK_BYTES)); + + REG_WRITE(AES_TRIGGER_REG, 1); + while (REG_READ(AES_STATE_REG) != AES_STATE_IDLE) { + } +} + +/* For AES-GCM mode once H has been calculated + * continue the AES operation & wait for DMA + * to finish if input data length is non-zero + * */ +static inline void esp_aes_gcm_continue(size_t len) +{ + volatile uint32_t dma_done = 0; + + REG_WRITE(AES_CONTINUE_REG, 1); + while (REG_READ(AES_STATE_REG) != AES_STATE_DONE) { + } + + if (len == 0) { + REG_WRITE(AES_DMA_EXIT_REG, 1); + return; + } + + /* Wait for AES-GCM DMA operation to complete */ + while (1) { + dma_done = REG_READ(CRYPTO_DMA_INT_RAW_REG); + if ((dma_done & INT_RAW_IN_SUC_EOF) == INT_RAW_IN_SUC_EOF) { + break; + } + } + + REG_WRITE(AES_DMA_EXIT_REG, 1); +} + +#if defined (CONFIG_MBEDTLS_AES_USE_INTERRUPT) +static IRAM_ATTR void esp_aes_dma_isr(void *arg) +{ + BaseType_t higher_woken; + REG_WRITE(AES_INT_CLR_REG, 1); + xSemaphoreGiveFromISR(op_complete_sem, &higher_woken); + if (higher_woken) { + portYIELD_FROM_ISR(); + } +} +#endif + +/* Wait for AES hardware block operation to complete */ +static int esp_aes_dma_complete(void) +{ +#if defined (CONFIG_MBEDTLS_AES_USE_INTERRUPT) + if (!xSemaphoreTake(op_complete_sem, 2000 / portTICK_PERIOD_MS)) { + ESP_LOGE("AES", "Timed out waiting for completion of AES Interrupt"); + abort(); + } +#endif + /* Checking this if interrupt is used also, to avoid + issues with AES fault injection + */ + while (REG_READ(AES_STATE_REG) != AES_STATE_DONE) { + } + + return 0; +} + +/* Perform AES-DMA operation and wait until the DMA operation is over + * + * input = Input data buffer, length len + * output = Output data buffer, length len + * len = Length of data in bytes, may not be multiple of AES block size + * stream_out = Pointer to 16 byte buffer to hold final stream block, if + * len is not a multiple of AES block size (16) + * + * The DMA processing works in following way: + * + * - If len >= AES_BLOCK_BYTES, there are DMA input and output + * descriptors which point to input & output (in_block_desc, out_block_desc) directly, + * to process block_bytes bytes. + * + * - If len % AES_BLOCK_BYTES != 0 then unaligned bytes are copied to stream_in block which is + * padded with zeroes. DMA descriptors (stream_in_desc, stream_out_desc) process this block and output to + * stream_out buffer argument. Otherwise, stream_out argument is ignored (may be NULL). + * + * - If both above conditions are true, DMA has two linked list input buffers and two linked list output buffers, + * and processes first the blocks and then the partial stream block. + * + * After the DMA operation, if we only processed full bytes then the IV memory block will contain the next IV + * for the configured AES mode. + * + * If a partial "stream block" was processed then IV memory block will contain a garbage IV value, because of + * the partial stream block. The IV can be recovered from the stream_out block (depending on algorithm some + * post-processing of the 'output' bytes also in stream_out may be needed, to translate them back to correct IV bytes). + * + */ +static int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsigned char *output, uint16_t len, uint8_t *stream_out) +{ + volatile lldesc_t block_in_desc, block_out_desc, stream_in_desc, stream_out_desc; + volatile lldesc_t *in_desc_head, *out_desc_head; + volatile uint32_t dma_done = 0; + uint8_t stream_in[16]; + unsigned stream_bytes = len % AES_BLOCK_BYTES; // bytes which aren't in a full block + unsigned block_bytes = len - stream_bytes; // bytes which are in a full block + unsigned blocks = (block_bytes / AES_BLOCK_BYTES) + ((stream_bytes > 0) ? 1 : 0); + + assert(len > 0); // caller shouldn't ever have len set to zero + assert(stream_bytes == 0 || stream_out != NULL); // stream_out can be NULL if we're processing full block(s) + /* If no key is written to hardware yet, either the user hasn't called mbedtls_aes_setkey_enc/mbedtls_aes_setkey_dec - meaning we also don't know which mode to use - or a fault skipped the @@ -152,22 +361,136 @@ static inline int esp_aes_block(esp_aes_context *ctx, const void *input, void *o return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; } - memcpy((void *)AES_TEXT_IN_BASE, input, AES_BLOCK_BYTES); + if (block_bytes > 0) { + /* If the block length is less than 16 we use internal RAM so no + * need to flush Cache + */ +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if ((unsigned int)input >= SOC_EXTRAM_DATA_LOW && (unsigned int)input <= SOC_EXTRAM_DATA_HIGH) { + assert((((unsigned int)(input) & 0xF) == 0)); + Cache_WriteBack_All(); + } + if ((unsigned int)output >= SOC_EXTRAM_DATA_LOW && (unsigned int)output <= SOC_EXTRAM_DATA_HIGH) { + assert((((unsigned int)(output) & 0xF) == 0)); + } +#endif + block_in_desc = (lldesc_t) { + .length = block_bytes, + .size = block_bytes, + .buf = (void *)input, + .owner = 1, + .empty = (stream_bytes > 0) ? (uint32_t)&stream_in_desc : 0, + .eof = (stream_bytes == 0), + }; + block_out_desc = (lldesc_t) { + .length = block_bytes, + .size = block_bytes, + .buf = output, + .owner = 1, + .empty = (stream_bytes > 0) ? (uint32_t)&stream_out_desc : 0, + .eof = (stream_bytes == 0), + }; + + in_desc_head = &block_in_desc; + out_desc_head = &block_out_desc; + } + + if (stream_bytes > 0) { + // can't read past end of 'input', so make a zero padded input buffer in RAM + memcpy(stream_in, input + block_bytes, stream_bytes); + bzero(stream_in + stream_bytes, AES_BLOCK_BYTES - stream_bytes); + + stream_in_desc = (lldesc_t) { + .length = AES_BLOCK_BYTES, + .size = AES_BLOCK_BYTES, + .buf = stream_in, + .owner = 1, + .eof = 1, + }; + + stream_out_desc = (lldesc_t) { + .length = AES_BLOCK_BYTES, + .size = AES_BLOCK_BYTES, + .buf = stream_out, + .owner = 1, + .eof = 1, + }; + } + + // block buffers are sent to DMA first, unless there aren't any + in_desc_head = (block_bytes > 0) ? &block_in_desc : &stream_in_desc; + out_desc_head = (block_bytes > 0) ? &block_out_desc : &stream_out_desc; + + /* Enable the DMA clock - currently only for FPGA test */ +#if CONFIG_IDF_ENV_FPGA + SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_GEN_CLK_EN); +#endif + + /* Reset DMA */ + SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_IN_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + CLEAR_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_IN_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + + /* Set DMA for AES Use */ + REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 0); + + /* Set descriptors */ + CLEAR_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_ADDR); + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, ((uint32_t)(in_desc_head))&OUT_LINK_REG_OUTLINK_ADDR); + CLEAR_PERI_REG_MASK(CRYPTO_DMA_IN_LINK_REG, IN_LINK_REG_INLINK_ADDR); + SET_PERI_REG_MASK(CRYPTO_DMA_IN_LINK_REG, ((uint32_t)(out_desc_head))&IN_LINK_REG_INLINK_ADDR); + + /* Start transfer */ + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_START); + SET_PERI_REG_MASK(CRYPTO_DMA_IN_LINK_REG, IN_LINK_REG_INLINK_START); + + /* Write the number of blocks */ + REG_WRITE(AES_BLOCK_NUM_REG, blocks); + +#if defined (CONFIG_MBEDTLS_AES_USE_INTERRUPT) + REG_WRITE(AES_INT_CLR_REG, 1); + if (op_complete_sem == NULL) { + op_complete_sem = xSemaphoreCreateBinary(); + esp_intr_alloc(ETS_AES_INTR_SOURCE, 0, esp_aes_dma_isr, 0, 0); + } + REG_WRITE(AES_INT_ENA_REG, 1); +#endif + + /* Start AES operation */ REG_WRITE(AES_TRIGGER_REG, 1); - while (REG_READ(AES_STATE_REG) != 0) { } - memcpy(output, (void *)AES_TEXT_OUT_BASE, AES_BLOCK_BYTES); + esp_aes_dma_complete(); + /* Wait for DMA operation to complete */ + while (1) { + dma_done = REG_READ(CRYPTO_DMA_INT_RAW_REG); + if ( (dma_done & INT_RAW_IN_SUC_EOF) == INT_RAW_IN_SUC_EOF) { + break; + } + } + + REG_WRITE(AES_DMA_EXIT_REG, 1); + +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if (block_bytes > 0) { + if ((unsigned int)input >= SOC_EXTRAM_DATA_LOW && (unsigned int)input <= SOC_EXTRAM_DATA_HIGH) { + Cache_Invalidate_DCache_All(); + } + } +#endif + + if (stream_bytes > 0) { + memcpy(output + block_bytes, stream_out, stream_bytes); + } return 0; } /* - * AES-ECB block encryption + * AES-ECB single block encryption */ int esp_internal_aes_encrypt( esp_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) + const unsigned char input[16], + unsigned char output[16] ) { int r; @@ -176,26 +499,26 @@ int esp_internal_aes_encrypt( esp_aes_context *ctx, } esp_aes_acquire_hardware(); - esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); - r = esp_aes_block(ctx, input, output); + esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT, AES_BLOCK_MODE_ECB); + r = esp_aes_process_dma(ctx, input, output, AES_BLOCK_BYTES, NULL); esp_aes_release_hardware(); + return r; } void esp_aes_encrypt( esp_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) + const unsigned char input[16], + unsigned char output[16] ) { esp_internal_aes_encrypt(ctx, input, output); } /* - * AES-ECB block decryption + * AES-ECB single block decryption */ - int esp_internal_aes_decrypt( esp_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16] ) + const unsigned char input[16], + unsigned char output[16] ) { int r; @@ -204,9 +527,10 @@ int esp_internal_aes_decrypt( esp_aes_context *ctx, } esp_aes_acquire_hardware(); - esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT); - r = esp_aes_block(ctx, input, output); + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT, AES_BLOCK_MODE_ECB); + r = esp_aes_process_dma(ctx, input, output, AES_BLOCK_BYTES, NULL); esp_aes_release_hardware(); + return r; } @@ -234,14 +558,13 @@ int esp_aes_crypt_ecb( esp_aes_context *ctx, esp_aes_acquire_hardware(); ctx->key_in_hardware = 0; - esp_aes_setkey_hardware(ctx, mode); - r = esp_aes_block(ctx, input, output); + esp_aes_setkey_hardware(ctx, mode, AES_BLOCK_MODE_ECB); + r = esp_aes_process_dma(ctx, input, output, AES_BLOCK_BYTES, NULL); esp_aes_release_hardware(); return r; } - /* * AES-CBC buffer encryption/decryption */ @@ -252,14 +575,14 @@ int esp_aes_crypt_cbc( esp_aes_context *ctx, const unsigned char *input, unsigned char *output ) { - int i; - uint32_t *output_words = (uint32_t *)output; - const uint32_t *input_words = (const uint32_t *)input; - uint32_t *iv_words = (uint32_t *)iv; - unsigned char temp[16]; - - if ( length % 16 ) { - return ( ERR_ESP_AES_INVALID_INPUT_LENGTH ); + /* For CBC input length should be multiple of + * AES BLOCK BYTES + * */ + if ( length % AES_BLOCK_BYTES ) { + return ERR_ESP_AES_INVALID_INPUT_LENGTH; + } + if ( length == 0 ) { + return 0; } if (!valid_key_length(ctx)) { return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; @@ -267,93 +590,10 @@ int esp_aes_crypt_cbc( esp_aes_context *ctx, esp_aes_acquire_hardware(); ctx->key_in_hardware = 0; - esp_aes_setkey_hardware(ctx, mode); - - if ( mode == ESP_AES_DECRYPT ) { - while ( length > 0 ) { - memcpy(temp, input_words, 16); - esp_aes_block(ctx, input_words, output_words); - - for ( i = 0; i < 4; i++ ) { - output_words[i] = output_words[i] ^ iv_words[i]; - } - - memcpy( iv_words, temp, 16 ); - - input_words += 4; - output_words += 4; - length -= 16; - } - } else { // ESP_AES_ENCRYPT - while ( length > 0 ) { - - for ( i = 0; i < 4; i++ ) { - output_words[i] = input_words[i] ^ iv_words[i]; - } - - esp_aes_block(ctx, output_words, output_words); - memcpy( iv_words, output_words, 16 ); - - input_words += 4; - output_words += 4; - length -= 16; - } - } - - esp_aes_release_hardware(); - - return 0; -} - -/* - * AES-CFB128 buffer encryption/decryption - */ -int esp_aes_crypt_cfb128( esp_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) -{ - int c; - size_t n = *iv_off; - - if (!valid_key_length(ctx)) { - return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; - } - - esp_aes_acquire_hardware(); - ctx->key_in_hardware = 0; - - esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); - - if ( mode == ESP_AES_DECRYPT ) { - while ( length-- ) { - if ( n == 0 ) { - esp_aes_block(ctx, iv, iv ); - } - - c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); - iv[n] = (unsigned char) c; - - n = ( n + 1 ) & 0x0F; - } - } else { - while ( length-- ) { - if ( n == 0 ) { - esp_aes_block(ctx, iv, iv ); - } - - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); - - n = ( n + 1 ) & 0x0F; - } - } - - *iv_off = n; - + esp_aes_setkey_hardware(ctx, mode, AES_BLOCK_MODE_CBC); + esp_aes_set_iv(iv, AES_BLOCK_BYTES); + esp_aes_process_dma(ctx, input, output, length, NULL); + esp_aes_get_iv(iv, AES_BLOCK_BYTES); esp_aes_release_hardware(); return 0; @@ -371,6 +611,65 @@ int esp_aes_crypt_cfb8( esp_aes_context *ctx, { unsigned char c; unsigned char ov[17]; + size_t block_bytes = length - (length % AES_BLOCK_BYTES); + + /* The DMA engine will only output correct IV if it runs + full blocks of input in CFB8 mode + */ + if (block_bytes > 0) { + esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, mode, AES_BLOCK_MODE_CFB8); + esp_aes_set_iv(iv, AES_BLOCK_BYTES); + esp_aes_process_dma(ctx, input, output, block_bytes, NULL); + esp_aes_get_iv(iv, AES_BLOCK_BYTES); + esp_aes_release_hardware(); + + length -= block_bytes; + input += block_bytes; + output += block_bytes; + } + + // Process remaining bytes block-at-a-time in ECB mode + if (length > 0) { + esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, MBEDTLS_AES_ENCRYPT, AES_BLOCK_MODE_ECB); + + while ( length-- ) { + memcpy( ov, iv, 16 ); + esp_aes_process_dma(ctx, iv, iv, AES_BLOCK_BYTES, NULL); + + if ( mode == MBEDTLS_AES_DECRYPT ) { + ov[16] = *input; + } + + c = *output++ = ( iv[0] ^ *input++ ); + + if ( mode == MBEDTLS_AES_ENCRYPT ) { + ov[16] = c; + } + memcpy( iv, ov + 1, 16 ); + } + esp_aes_release_hardware(); + } + + return 0; +} + +/* + * AES-CFB128 buffer encryption/decryption + */ +int esp_aes_crypt_cfb128( esp_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) + +{ + uint8_t c; + size_t stream_bytes = 0; + size_t n = *iv_off; if (!valid_key_length(ctx)) { return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; @@ -379,26 +678,48 @@ int esp_aes_crypt_cfb8( esp_aes_context *ctx, esp_aes_acquire_hardware(); ctx->key_in_hardware = 0; - esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); - - while ( length-- ) { - memcpy( ov, iv, 16 ); - esp_aes_block(ctx, iv, iv); - - if ( mode == ESP_AES_DECRYPT ) { - ov[16] = *input; + /* Lets process the *iv_off bytes first + * which are pending from the previous call to this API + */ + while (n > 0 && length > 0) { + if (mode == MBEDTLS_AES_ENCRYPT) { + iv[n] = *output++ = (unsigned char)(*input++ ^ iv[n]); + } else { + c = *input++; + *output++ = (c ^ iv[n]); + iv[n] = c; } - - c = *output++ = (unsigned char)( iv[0] ^ *input++ ); - - if ( mode == ESP_AES_ENCRYPT ) { - ov[16] = c; - } - - memcpy( iv, ov + 1, 16 ); + n = (n + 1) % AES_BLOCK_BYTES; + length--; } - esp_aes_release_hardware(); + + if (length > 0) { + stream_bytes = length % AES_BLOCK_BYTES; + + esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, mode, AES_BLOCK_MODE_CFB128); + esp_aes_set_iv(iv, AES_BLOCK_BYTES); + + esp_aes_process_dma(ctx, input, output, length, iv); + + if (stream_bytes == 0) { + // if we didn't need the partial 'stream block' then the new IV is in the IV register + esp_aes_get_iv(iv, AES_BLOCK_BYTES); + } else { + // if we did process a final partial block the new IV is already processed via DMA (and has some bytes of output in it), + // In decrypt mode any partial bytes are output plaintext (iv ^ c) and need to be swapped back to ciphertext (as the next + // block uses ciphertext as its IV input) + // + // Note: It may be more efficient to not process the partial block via DMA in this case. + if (mode == MBEDTLS_AES_DECRYPT) { + memcpy(iv, input + length - stream_bytes, stream_bytes); + } + } + esp_aes_release_hardware(); + } + + *iv_off = n + stream_bytes; return 0; } @@ -414,36 +735,415 @@ int esp_aes_crypt_ctr( esp_aes_context *ctx, const unsigned char *input, unsigned char *output ) { - int c, i; size_t n = *nc_off; - if (!valid_key_length(ctx)) { + while (n > 0 && length > 0) { + *output++ = (unsigned char)(*input++ ^ stream_block[n]); + n = (n + 1) & 0xF; + length--; + } + + if (length > 0) { + esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT, AES_BLOCK_MODE_CTR); + esp_aes_set_iv(nonce_counter, AES_BLOCK_BYTES); + esp_aes_process_dma(ctx, input, output, length, stream_block); + esp_aes_get_iv(nonce_counter, AES_BLOCK_BYTES); + esp_aes_release_hardware(); + } + + *nc_off = n + (length % AES_BLOCK_BYTES); + + return 0; +} + +/* XOR two 32 bit words */ +static void xor_block(uint8_t *dst, const uint8_t *src) +{ + uint32_t *d = (uint32_t *) dst; + uint32_t *s = (uint32_t *) src; + + *d++ ^= *s++; + *d++ ^= *s++; + *d++ ^= *s++; + *d++ ^= *s++; +} + +static void right_shift(uint8_t *v) +{ + uint32_t val; + + val = WPA_GET_BE32(v + 12); + val >>= 1; + + if (v[11] & 0x01) { + val |= 0x80000000; + } + WPA_PUT_BE32(v + 12, val); + val = WPA_GET_BE32(v + 8); + val >>= 1; + + if (v[7] & 0x01) { + val |= 0x80000000; + } + WPA_PUT_BE32(v + 8, val); + val = WPA_GET_BE32(v + 4); + val >>= 1; + + if (v[3] & 0x01) { + val |= 0x80000000; + } + WPA_PUT_BE32(v + 4, val); + val = WPA_GET_BE32(v); + val >>= 1; + WPA_PUT_BE32(v, val); +} + +/* AES-GCM multiplication z = y * h */ +static int gcm_mult(uint8_t *y, uint8_t *h, uint8_t *z) +{ + uint8_t v0[AES_BLOCK_BYTES]; + int i, j; + + if (!y || !h || !z) { + return -1; + } + + memset(z, 0, AES_BLOCK_BYTES); + memcpy(v0, y, AES_BLOCK_BYTES); + + for (i = 0; i < AES_BLOCK_BYTES; i++) { + for (j = 0; j < 8; j++) { + if (y[i] & BIT(7 - j)) { + xor_block(z, v0); + } + if (v0[15] & 0x01) { + right_shift(v0); + v0[0] ^= 0xE1; + } else { + right_shift(v0); + } + } + } + + return 0; +} + +/* Update the key value in gcm context */ +int esp_aes_gcm_setkey( esp_aes_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ) +{ + if (keybits != 128 && keybits != 192 && keybits != 256) { return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; } - esp_aes_acquire_hardware(); - ctx->key_in_hardware = 0; + ctx->aes_ctx.key_bytes = keybits / 8; + memcpy(ctx->aes_ctx.key, key, ctx->aes_ctx.key_bytes); - esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); + return ( 0 ); +} - while ( length-- ) { - if ( n == 0 ) { - esp_aes_block(ctx, nonce_counter, stream_block); +/* AES-GCM GHASH calculation for IV != 12 bytes */ +static void esp_aes_gcm_ghash(uint8_t *h0, uint8_t *iv, uint8_t iv_len, uint8_t *j0, uint16_t s) +{ + uint8_t *hash_buf; + uint8_t y0[AES_BLOCK_BYTES], old_y0[AES_BLOCK_BYTES]; + uint16_t len, rem = 0; - for ( i = 16; i > 0; i-- ) - if ( ++nonce_counter[i - 1] != 0 ) { - break; - } + memset(old_y0, 0, AES_BLOCK_BYTES); + + /* We need to concatenate IV, s + 8 byte zeros & 8 byte IV length + * J0 = GHASH( IV || 0 ^(s+64) || len(IV)^64 ) + */ + len = ( iv_len + (s + 8) + 8 ); + hash_buf = calloc( 1, len ); + if (hash_buf) { + memcpy(hash_buf, iv, iv_len); + + // ToDo: iv_len is 1 byte in size, how to copy 8 bytes to other memory? +#if 0 + memcpy((hash_buf + iv_len + s + 8), &iv_len, 8); +#endif + + /* GHASH(x) calculation + * Let X1, X2, ... , Xm-1, Xm denote the unique sequence of blocks + * such that X = X1 || X2 || ... || Xm-1 || Xm. + * Let Y0 be the “zero block,” 0 ^ 128. + * Fori=1,...,m, let Yi =(Yi-1 xor Xi) • H. + * Return Ym + */ + while (len) { + rem = ( len > AES_BLOCK_BYTES ) ? AES_BLOCK_BYTES : len; + /* Yi-1 xor hash_buf */ + for (uint8_t j = 0; j < rem; j++) { + y0[j] = old_y0[j] ^ hash_buf[j]; + } + + /* gcm multiplication : y0 x h0 */ + gcm_mult(y0, h0, j0); + memcpy(old_y0, y0, rem); + hash_buf += rem; + len -= rem; } - c = *input++; - *output++ = (unsigned char)( c ^ stream_block[n] ); - n = ( n + 1 ) & 0x0F; + memcpy(j0, y0, rem); + free(hash_buf); + } +} + +/* AES-GCM J0 calculation + */ +static void inline esp_aes_gcm_process_J0(uint8_t *data, uint8_t iv_len) +{ + uint8_t j_buf[AES_BLOCK_BYTES]; + uint8_t iv[32]; + uint16_t s; + + esp_aes_get_iv(iv, iv_len); + + /* If IV is 96 bits J0 = ( IV || 0^31 || 1 ) */ + if (iv_len == 12) { + memset(j_buf, 0, AES_BLOCK_BYTES); + memcpy(j_buf, iv, iv_len); + j_buf[AES_BLOCK_BYTES - 1] |= 1; + } else { + /* If IV is != 96 bits then + * J0 = GHASH( IV || 0 ^(s+64) || len(IV)^64 ) where + * s = ( 128 * floor of ( len(IV) / 128 ) - len(IV) ) + * floor of (x) denotes to be the least integer no less than x + * for example: floor of (1.5) = 2 since 2 is the least integer + * which is no less than 1.5 + */ + s = ((iv_len / AES_BLOCK_BYTES) + + ((iv_len % AES_BLOCK_BYTES) == 0) ? 0 : 1); + s = (s * AES_BLOCK_BYTES) - iv_len; + esp_aes_gcm_ghash(data, iv, iv_len, j_buf, s); } - *nc_off = n; + /* Write J0 to hardware registers */ + memcpy((uint8_t *)AES_J_BASE, j_buf, AES_BLOCK_BYTES); +} - esp_aes_release_hardware(); +/* Configure & start crypto DMA for AES GCM operation + */ +static void esp_aes_gcm_dma(unsigned char *aad, esp_aes_gcm_context *ctx, + unsigned char *input, size_t ilen, + unsigned char *len_buf, unsigned char *output) +{ + volatile lldesc_t dma_descr[4]; + int i = 0; + + bzero( (void *)dma_descr, sizeof( dma_descr ) ); + +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if ((unsigned int)input >= SOC_EXTRAM_DATA_LOW && (unsigned int)input <= SOC_EXTRAM_DATA_HIGH) { + assert((((unsigned int)(input) & 0xF) == 0)); + Cache_WriteBack_All(); + } + if ((unsigned int)output >= SOC_EXTRAM_DATA_LOW && (unsigned int)output <= SOC_EXTRAM_DATA_HIGH) { + assert((((unsigned int)(output) & 0xF) == 0)); + } +#endif + + dma_descr[0].length = ctx->aad_len; + dma_descr[0].size = ctx->aad_len; + dma_descr[0].buf = aad; + dma_descr[0].owner = 1; + dma_descr[0].eof = 0; + dma_descr[0].empty = (uint32_t)&dma_descr[1]; + + dma_descr[1].length = ilen; + dma_descr[1].size = ilen; + dma_descr[1].buf = input; + dma_descr[1].owner = 1; + dma_descr[1].eof = 0; + dma_descr[1].empty = (uint32_t)&dma_descr[2]; + + dma_descr[2].length = AES_BLOCK_BYTES; + dma_descr[2].size = AES_BLOCK_BYTES; + dma_descr[2].buf = len_buf; + dma_descr[2].owner = 1; + dma_descr[2].eof = 1; + dma_descr[2].empty = 0; + + dma_descr[3].length = ctx->aad_len + ilen + AES_BLOCK_BYTES; + dma_descr[3].size = ctx->aad_len + ilen + AES_BLOCK_BYTES; + dma_descr[3].buf = output; + dma_descr[3].owner = 1; + dma_descr[3].eof = 1; + dma_descr[3].empty = 0; + + /* If no additional authentication data */ + if (ctx->aad_len == 0) { + i = 1; + } + /* If no input data */ + if (ilen == 0) { + i = 2; + } + + /* Enable the DMA clock - currently only for FPGA test */ +#if CONFIG_IDF_ENV_FPGA + SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_GEN_CLK_EN); +#endif + + /* Reset DMA */ + SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_IN_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + CLEAR_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_IN_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + + /* Set DMA for AES Use */ + REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 0); + + /* Set descriptors */ + CLEAR_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_ADDR); + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, ((uint32_t)(&dma_descr[i]))&OUT_LINK_REG_OUTLINK_ADDR); + CLEAR_PERI_REG_MASK(CRYPTO_DMA_IN_LINK_REG, IN_LINK_REG_INLINK_ADDR); + SET_PERI_REG_MASK(CRYPTO_DMA_IN_LINK_REG, ((uint32_t)(&dma_descr[3]))&IN_LINK_REG_INLINK_ADDR); + + /* Start transfer */ + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_START); + SET_PERI_REG_MASK(CRYPTO_DMA_IN_LINK_REG, IN_LINK_REG_INLINK_START); + + /* Trigger AES: Let hardware perform GCTR operation */ + esp_aes_gcm_set_block_num_and_trigger(ilen); + + /* While hardware is busy meanwhile software will calculate GHASH + * Read H from hardware register + */ + memcpy(ctx->H, (uint8_t *)AES_H_BASE, AES_BLOCK_BYTES); + + esp_aes_gcm_process_J0(ctx->H, ctx->iv_len); + + /* After following call the ciphertext is available in output buffer */ + esp_aes_gcm_continue(ilen); + +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if ((unsigned int)input >= SOC_EXTRAM_DATA_LOW && (unsigned int)input <= SOC_EXTRAM_DATA_HIGH) { + Cache_Invalidate_DCache_All(); + } +#endif +} + +/* Function to init AES GCM context to zero */ +void esp_aes_gcm_init( esp_aes_gcm_context *ctx) +{ + if (ctx == NULL) { + return; + } + + bzero(ctx, sizeof(esp_aes_gcm_context)); +} + +/* Function to clear AES-GCM context */ +void esp_aes_gcm_free( esp_aes_gcm_context *ctx) +{ + if (ctx == NULL) { + return; + } + + bzero(ctx, sizeof(esp_aes_gcm_context)); +} + +/* Setup AES-GCM */ +int esp_aes_gcm_starts( esp_aes_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *aad, + size_t aad_len ) +{ + uint8_t temp[AES_BLOCK_BYTES] = {0}; + + memcpy(temp, iv, iv_len); + + esp_aes_acquire_hardware(); + esp_aes_setkey_hardware( &ctx->aes_ctx, mode, AES_BLOCK_MODE_GCM); + /* AES-GCM HW does not use IV but we program anyways so that + * we can retrieve later for J0 calculation */ + esp_aes_set_iv(temp, iv_len); + ctx->iv_len = iv_len; + ctx->aad = aad; + ctx->aad_len = aad_len; + + return ( 0 ); +} + +/* Perform AES-GCM operation */ +int esp_aes_gcm_update( esp_aes_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ) +{ + const uint8_t *dbuf = input; + uint8_t *abuf = (uint8_t *)ctx->aad; + uint64_t ori_aad_len = ctx->aad_len, ori_p_len = length; + uint32_t temp[4] = {0}; + bool abuf_alloc = false, dbuf_alloc = false; + + if ( output > input && (size_t) ( output - input ) < length ) { + return ( MBEDTLS_ERR_GCM_BAD_INPUT ); + } + + /* Check length of AAD & pad if required */ + if (ctx->aad_len % AES_BLOCK_BYTES) { + ori_aad_len = ctx->aad_len; + abuf = textpad_zero(ctx->aad, (uint8_t *)&ctx->aad_len); + if (!abuf) { + return -1; + } else { + abuf_alloc = true; + } + } + + /* Check length of input & pad if required */ + if ( length % AES_BLOCK_BYTES ) { + ori_p_len = length; + REG_WRITE(AES_BIT_VALID_NUM_REG, (length % AES_BLOCK_BYTES) * 8); + dbuf = textpad_zero(input, (uint8_t *)&length); + if (!dbuf) { + if (abuf_alloc) { + free(abuf); + return -1; + } + } else { + dbuf_alloc = true; + } + } + + /* Update number of AAD blocks in hardware register */ + REG_WRITE(AES_AAD_BLOCK_NUM_REG, (ctx->aad_len / AES_BLOCK_BYTES)); + + /* Input buffer is: length[textpad(input)] + length[textpad(aad)] + * + [length]64 + [aad_len]64 + */ + ori_aad_len *= 8; + ori_p_len *= 8; + + temp[0] = (uint32_t)LE_TO_BE(ori_aad_len >> 32); + temp[1] = (uint32_t)LE_TO_BE(ori_aad_len); + temp[2] = (uint32_t)LE_TO_BE(ori_p_len >> 32); + temp[3] = (uint32_t)LE_TO_BE(ori_p_len); + + esp_aes_gcm_dma(abuf, ctx, (uint8_t *)dbuf, length, (uint8_t *)temp, output); + + if (abuf_alloc) { + free((void *)abuf); + } + if (dbuf_alloc) { + free((void *)dbuf); + } + + return 0; +} + +/* Function to read the tag value */ +int esp_aes_gcm_finish( esp_aes_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ) +{ + memcpy(tag, (uint8_t *)AES_T_BASE, tag_len); return 0; } @@ -458,43 +1158,38 @@ int esp_aes_crypt_ofb( esp_aes_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret = 0; - size_t n; + size_t n = *iv_off; + size_t stream_bytes = 0; - if ( ctx == NULL || iv_off == NULL || iv == NULL || - input == NULL || output == NULL ) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + while (n > 0 && length > 0) { + *output++ = (unsigned char)(*input++ ^ iv[n]); + n = (n + 1) & 0xF; + length--; } - n = *iv_off; + if (length > 0) { + stream_bytes = (length % AES_BLOCK_BYTES); - if( n > 15 ) { - return( MBEDTLS_ERR_AES_BAD_INPUT_DATA ); - } - - if (!valid_key_length(ctx)) { - return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; - } - - esp_aes_acquire_hardware(); - ctx->key_in_hardware = 0; - - esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); - - while( length-- ) { - if( n == 0 ) { - esp_aes_block(ctx, iv, iv); + esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT, AES_BLOCK_MODE_OFB); + esp_aes_set_iv(iv, AES_BLOCK_BYTES); + esp_aes_process_dma(ctx, input, output, length, iv); + if (stream_bytes == 0) { + // new IV is in the IV block + esp_aes_get_iv(iv, AES_BLOCK_BYTES); + } else { + // IV is in the iv buffer (stream_out param), however 'stream_bytes' + // of it are already XORed with input bytes so need to un-XOR them + for (int i = 0; i < stream_bytes; i++) { + iv[i] ^= input[length - stream_bytes + i]; + } } - *output++ = *input++ ^ iv[n]; - - n = ( n + 1 ) & 0x0F; + esp_aes_release_hardware(); } - *iv_off = n; + *iv_off = n + stream_bytes; - esp_aes_release_hardware(); - - return( ret ); + return 0; } @@ -739,4 +1434,69 @@ int esp_aes_crypt_xts( esp_aes_xts_context *ctx, } return( 0 ); -} \ No newline at end of file +} +int esp_aes_gcm_crypt_and_tag( esp_aes_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ) +{ + int ret; + + if ( ( ret = esp_aes_gcm_starts( ctx, mode, iv, iv_len, add, add_len ) ) != 0 ) { + return ( ret ); + } + + if ( ( ret = esp_aes_gcm_update( ctx, length, input, output ) ) != 0 ) { + return ( ret ); + } + + if ( ( ret = esp_aes_gcm_finish( ctx, tag, tag_len ) ) != 0 ) { + return ( ret ); + } + + return ( 0 ); +} + +int esp_aes_gcm_auth_decrypt( esp_aes_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + unsigned char check_tag[16]; + size_t i; + int diff; + + if ( ( ret = esp_aes_gcm_crypt_and_tag( ctx, ESP_AES_DECRYPT, length, + iv, iv_len, add, add_len, + input, output, tag_len, check_tag ) ) != 0 ) { + return ( ret ); + } + + /* Check tag in "constant-time" */ + for ( diff = 0, i = 0; i < tag_len; i++ ) { + diff |= tag[i] ^ check_tag[i]; + } + + if ( diff != 0 ) { + bzero( output, length ); + return ( MBEDTLS_ERR_GCM_AUTH_FAILED ); + } + + return ( 0 ); +} + + diff --git a/components/mbedtls/port/esp32s2beta/esp_bignum.c b/components/mbedtls/port/esp32s2beta/esp_bignum.c index cfaa938843..da1f902899 100644 --- a/components/mbedtls/port/esp32s2beta/esp_bignum.c +++ b/components/mbedtls/port/esp32s2beta/esp_bignum.c @@ -56,15 +56,14 @@ void esp_mpi_acquire_hardware( void ) /* newlib locks lazy initialize on ESP-IDF */ _lock_acquire(&mpi_lock); - DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_CLK_EN_RSA); - /* also clear reset on digital signature & secure boot, otherwise RSA is held in reset */ - DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_RST_EN_RSA - | DPORT_RST_EN_DIGITAL_SIGNATURE - | DPORT_RST_EN_SECURE_BOOT); + DPORT_REG_SET_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_RSA_CLK_EN); + /* also clear reset on digital signature, otherwise RSA is held in reset */ + DPORT_REG_CLR_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_RSA_RST + | DPORT_CRYPTO_DS_RST); DPORT_REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_MEM_PD); - while(DPORT_REG_READ(RSA_QUERY_CLEAN_REG) != 1) { + while (DPORT_REG_READ(RSA_QUERY_CLEAN_REG) != 1) { } // Note: from enabling RSA clock to here takes about 1.3us } @@ -74,8 +73,8 @@ void esp_mpi_release_hardware( void ) DPORT_REG_SET_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); /* don't reset digital signature unit, as this resets AES also */ - DPORT_REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA); - DPORT_REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); + DPORT_REG_SET_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_RSA_RST); + DPORT_REG_CLR_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_RSA_CLK_EN); _lock_release(&mpi_lock); } @@ -141,12 +140,12 @@ static inline int mem_block_to_mpi(mbedtls_mpi *x, uint32_t mem_base, int num_wo esp_dport_access_read_buffer(x->p, mem_base, num_words); /* Zero any remaining limbs in the bignum, if the buffer is bigger than num_words */ - for(size_t i = num_words; i < x->n; i++) { + for (size_t i = num_words; i < x->n; i++) { x->p[i] = 0; } asm volatile ("memw"); - cleanup: +cleanup: return ret; } @@ -200,7 +199,7 @@ static int calculate_rinv(mbedtls_mpi *Rinv, const mbedtls_mpi *M, int num_words MBEDTLS_MPI_CHK(mbedtls_mpi_set_bit(&RR, num_bits * 2, 1)); MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(Rinv, &RR, M)); - cleanup: +cleanup: mbedtls_mpi_free(&RR); return ret; } @@ -213,6 +212,7 @@ static inline void start_op(uint32_t op_reg) { /* Clear interrupt status */ DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1); + DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1); /* Note: above REG_WRITE includes a memw, so we know any writes to the memory blocks are also complete. */ @@ -283,7 +283,7 @@ int esp_mpi_mul_mpi_mod(mbedtls_mpi *Z, const mbedtls_mpi *X, const mbedtls_mpi esp_mpi_release_hardware(); - cleanup: +cleanup: mbedtls_mpi_free(&Rinv); return ret; } @@ -298,7 +298,7 @@ int esp_mpi_mul_mpi_mod(mbedtls_mpi *Z, const mbedtls_mpi *X, const mbedtls_mpi * (See RSA Accelerator section in Technical Reference for more about Mprime, Rinv) * */ -int mbedtls_mpi_exp_mod( mbedtls_mpi* Z, const mbedtls_mpi* X, const mbedtls_mpi* Y, const mbedtls_mpi* M, mbedtls_mpi* _Rinv ) +int mbedtls_mpi_exp_mod( mbedtls_mpi *Z, const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M, mbedtls_mpi *_Rinv ) { int ret = 0; size_t y_bits = mbedtls_mpi_bitlen(Y); @@ -379,7 +379,7 @@ int mbedtls_mpi_exp_mod( mbedtls_mpi* Z, const mbedtls_mpi* X, const mbedtls_mpi Z->s = 1; } - cleanup: +cleanup: if (_Rinv == NULL) { mbedtls_mpi_free(&Rinv_new); } @@ -509,13 +509,13 @@ static int mpi_mult_mpi_failover_mod_mult(mbedtls_mpi *Z, const mbedtls_mpi *X, esp_mpi_acquire_hardware(); /* M = 2^num_words - 1, so block is entirely FF */ - for(int i = 0; i < num_words; i++) { + for (int i = 0; i < num_words; i++) { DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); } /* Mprime = 1 */ DPORT_REG_WRITE(RSA_M_DASH_REG, 1); - DPORT_REG_WRITE(RSA_LENGTH_REG, num_words -1); + DPORT_REG_WRITE(RSA_LENGTH_REG, num_words - 1); /* Load X & Y */ mpi_to_mem_block(RSA_MEM_X_BLOCK_BASE, X, num_words); @@ -523,7 +523,7 @@ static int mpi_mult_mpi_failover_mod_mult(mbedtls_mpi *Z, const mbedtls_mpi *X, /* Rinv = 1 */ DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 1); - for(int i = 1; i < num_words; i++) { + for (int i = 1; i < num_words; i++) { DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0); } @@ -586,7 +586,7 @@ static int mpi_mult_mpi_overlong(mbedtls_mpi *Z, const mbedtls_mpi *X, const mbe /* Z += Ztemp */ MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi(Z, Z, &Ztemp) ); - cleanup: +cleanup: mbedtls_mpi_free(&Ztemp); return ret; diff --git a/components/mbedtls/port/esp32s2beta/sha.c b/components/mbedtls/port/esp32s2beta/sha.c index d083d78167..9939a626f4 100644 --- a/components/mbedtls/port/esp32s2beta/sha.c +++ b/components/mbedtls/port/esp32s2beta/sha.c @@ -29,29 +29,47 @@ #include #include #include - +#include "soc/soc.h" +#include "esp32s2beta/crypto_dma.h" #include "esp32s2beta/sha.h" +#include "soc/crypto_dma_reg.h" #include "esp32s2beta/rom/ets_sys.h" #include "soc/dport_reg.h" #include "soc/hwcrypto_reg.h" +#include "esp32s2beta/rom/lldesc.h" +#include "esp32s2beta/rom/cache.h" +#include "esp_intr_alloc.h" +#include "esp_log.h" +#include "soc/periph_defs.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" /* Single lock for SHA engine */ static _lock_t s_sha_lock; -/* This API was designed for ESP32, which has seperate - engines for SHA1,256,512. ESP32C has a single engine. -*/ +/* Enable if want to use SHA interrupt */ +//#define CONFIG_MBEDTLS_SHA_USE_INTERRUPT + +#if defined(CONFIG_MBEDTLS_SHA_USE_INTERRUPT) +static SemaphoreHandle_t op_complete_sem; +#endif /* Return block size (in bytes) for a given SHA type */ -inline static size_t block_length(esp_sha_type type) { - switch(type) { +inline static size_t block_length(esp_sha_type type) +{ + switch (type) { case SHA1: case SHA2_224: case SHA2_256: return 64; case SHA2_384: case SHA2_512: + case SHA2_512224: + case SHA2_512256: + case SHA2_512T: return 128; default: return 0; @@ -59,50 +77,33 @@ inline static size_t block_length(esp_sha_type type) { } /* Return state size (in bytes) for a given SHA type */ -inline static size_t state_length(esp_sha_type type) { - switch(type) { +inline static size_t state_length(esp_sha_type type) +{ + switch (type) { case SHA1: - return 160/8; + return 160 / 8; case SHA2_224: case SHA2_256: - return 256/8; + return 256 / 8; case SHA2_384: case SHA2_512: - return 512/8; + case SHA2_512224: + case SHA2_512256: + case SHA2_512T: + return 512 / 8; default: return 0; } } -/* Copy words in memory (to/from a memory block), byte swapping as we go. */ -static void memcpy_endianswap(void *to, const void *from, size_t num_bytes) -{ - uint32_t *to_words = (uint32_t *)to; - const uint32_t *from_words = (const uint32_t *)from; - assert(num_bytes % 4 == 0); - for (int i = 0; i < num_bytes / 4; i++) { - to_words[i] = __builtin_bswap32(from_words[i]); - } - asm volatile ("memw"); -} - -static void memcpy_swapwords(void *to, const void *from, size_t num_bytes) -{ - uint32_t *to_words = (uint32_t *)to; - const uint32_t *from_words = (const uint32_t *)from; - assert(num_bytes % 8 == 0); - for (int i = 0; i < num_bytes / 4; i += 2) { - to_words[i] = from_words[i+1]; - to_words[i+1] = from_words[i]; - } - asm volatile ("memw"); -} - +/* This API was designed for ESP32, which has seperate + engines for SHA1,256,512. ESP32C has a single engine. +*/ static void esp_sha_lock_engine_inner(void); bool esp_sha_try_lock_engine(esp_sha_type sha_type) { - if(_lock_try_acquire(&s_sha_lock) != 0) { + if (_lock_try_acquire(&s_sha_lock) != 0) { /* SHA engine is already in use */ return false; } else { @@ -117,55 +118,156 @@ void esp_sha_lock_engine(esp_sha_type sha_type) esp_sha_lock_engine_inner(); } +/* Enable SHA block and then lock it */ static void esp_sha_lock_engine_inner(void) { - ets_sha_enable(); + /* Need to lock DMA since it is shared with AES block */ + portENTER_CRITICAL(&crypto_dma_spinlock); + + REG_SET_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_SHA_CLK_EN | DPORT_CRYPTO_DMA_CLK_EN); + REG_CLR_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_SHA_RST | DPORT_CRYPTO_HMAC_RST | + DPORT_CRYPTO_DMA_RST | DPORT_CRYPTO_DS_RST); + + /* DMA for SHA */ + REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 1); } +/* Disable SHA block and then unlock it */ void esp_sha_unlock_engine(esp_sha_type sha_type) { - ets_sha_disable(); + REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, 0); + + REG_SET_BIT(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_SHA_RST | DPORT_CRYPTO_DMA_RST | + DPORT_CRYPTO_DS_RST); + REG_CLR_BIT(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_SHA_CLK_EN | DPORT_CRYPTO_DMA_CLK_EN); + + portEXIT_CRITICAL(&crypto_dma_spinlock); + _lock_release(&s_sha_lock); } +#if defined (CONFIG_MBEDTLS_SHA_USE_INTERRUPT) +static IRAM_ATTR void esp_sha_dma_isr(void *arg) +{ + BaseType_t higher_woken; + REG_WRITE(SHA_CLEAR_IRQ_REG, 1); + xSemaphoreGiveFromISR(op_complete_sem, &higher_woken); + if (higher_woken) { + portYIELD_FROM_ISR(); + } +} +#endif + +/* Check if SHA operation completed */ +static int esp_sha_dma_complete(void) +{ +#if defined (CONFIG_MBEDTLS_SHA_USE_INTERRUPT) + if (!xSemaphoreTake(op_complete_sem, 2000 / portTICK_PERIOD_MS)) { + ESP_LOGE("SHA", "Timed out waiting for completion of SHA Interrupt"); + return -1; + } +#else + esp_sha_wait_idle(); +#endif + return 0; +} + +/* Wait until SHA is busy */ void esp_sha_wait_idle(void) { - while(DPORT_REG_READ(SHA_BUSY_REG) != 0) { } + while (DPORT_REG_READ(SHA_BUSY_REG) != 0) { } } +/* Read the SHA digest from hardware */ void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state) { - /* engine should be locked */ esp_sha_wait_idle(); - if (sha_type != SHA2_512 && sha_type != SHA2_384) { - /* = SOC_EXTRAM_DATA_LOW && (unsigned int)data_block <= SOC_EXTRAM_DATA_HIGH) { + Cache_WriteBack_All(); + } +#endif + + /* Reset DMA */ + SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + CLEAR_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + + /* Set descriptors */ + CLEAR_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_ADDR); + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, ((uint32_t)(&dma_descr))&OUT_LINK_REG_OUTLINK_ADDR); + /* Start transfer */ + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_START); + +#if defined (CONFIG_MBEDTLS_SHA_USE_INTERRUPT) + REG_WRITE(SHA_CLEAR_IRQ_REG, 1); + if (op_complete_sem == NULL) { + op_complete_sem = xSemaphoreCreateBinary(); + esp_intr_alloc(ETS_SHA_INTR_SOURCE, 0, esp_sha_dma_isr, 0, 0); + } + REG_WRITE(SHA_INT_ENA_REG, 1); +#endif + + if (is_first_block) { + REG_WRITE(SHA_DMA_START_REG, 1); + } else { + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); + } + + ret = esp_sha_dma_complete(); + +#if (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC) + if ((unsigned int)data_block >= SOC_EXTRAM_DATA_LOW && (unsigned int)data_block <= SOC_EXTRAM_DATA_HIGH) { + Cache_Invalidate_DCache_All(); + } +#endif + + return ret; } void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output) diff --git a/components/mbedtls/port/include/esp32s2beta/crypto_dma.h b/components/mbedtls/port/include/esp32s2beta/crypto_dma.h new file mode 100644 index 0000000000..b3eead844d --- /dev/null +++ b/components/mbedtls/port/include/esp32s2beta/crypto_dma.h @@ -0,0 +1,40 @@ +/** + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_CRYPTO_DMA_H +#define ESP_CRYPTO_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Since crypto DMA is shared between DMA-AES and SHA blocks + * Needs to be taken by respective blocks before using Crypto DMA + */ +extern portMUX_TYPE crypto_dma_spinlock; + +#ifdef __cplusplus +} +#endif + +#endif /* crypto_dma.h */ diff --git a/components/mbedtls/port/include/esp32s2beta/gcm.h b/components/mbedtls/port/include/esp32s2beta/gcm.h new file mode 100644 index 0000000000..44568c24df --- /dev/null +++ b/components/mbedtls/port/include/esp32s2beta/gcm.h @@ -0,0 +1,224 @@ +/** + * \brief AES block cipher, ESP32C hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_GCM_H +#define ESP_GCM_H + +#include "aes.h" +#include "mbedtls/cipher.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 /**< Authenticated decryption failed. */ +#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 /**< Bad input parameters to function.*/ + +/** + * \brief The GCM context structure. + */ +typedef struct { + uint8_t H[16]; /*!< H */ + size_t iv_len; /*!< The length of IV. */ + uint64_t aad_len; /*!< The total length of the additional data. */ + const unsigned char *aad; /*!< The additional data. */ + esp_aes_context aes_ctx; +} +esp_aes_gcm_context; + +/** + * \brief This function initializes the specified GCM context + * + * \param ctx The GCM context to initialize. + */ +void esp_aes_gcm_init( esp_aes_gcm_context *ctx); + +/** + * \brief This function associates a GCM context with a + * key. + * + * \param ctx The GCM context to initialize. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. + * \param keybits The key size in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int esp_aes_gcm_setkey( esp_aes_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function starts a GCM encryption or decryption + * operation. + * + * \param ctx The GCM context. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data, or NULL + * if \p add_len is 0. + * \param add_len The length of the additional data. If 0, + * \p add is NULL. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_starts( esp_aes_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *aad, + size_t aad_len ); + +/** + * \brief This function feeds an input buffer into an ongoing GCM + * encryption or decryption operation. + * + * ` The function expects input to be a multiple of 16 + * Bytes. Only the last call before calling + * mbedtls_gcm_finish() can be less than 16 Bytes. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_update( esp_aes_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function finishes the GCM operation and generates + * the authentication tag. + * + * It wraps up the GCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \param ctx The GCM context. + * \param tag The buffer for holding the tag. + * \param tag_len The length of the tag to generate. Must be at least four. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_finish( esp_aes_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ); + +/** + * \brief This function clears a GCM context + * + * \param ctx The GCM context to clear. + */ +void esp_aes_gcm_free( esp_aes_gcm_context *ctx); + +/** + * \brief This function performs GCM encryption or decryption of a buffer. + * + * \note For encryption, the output buffer can be the same as the + * input buffer. For decryption, the output buffer cannot be + * the same as input buffer. If the buffers overlap, the output + * buffer must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context to use for encryption or decryption. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * \param tag_len The length of the tag to generate. + * \param tag The buffer for holding the tag. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_crypt_and_tag( esp_aes_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ); + + +/** + * \brief This function performs a GCM authenticated decryption of a + * buffer. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple + * of 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param tag The buffer holding the tag. + * \param tag_len The length of the tag. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return 0 if successful and authenticated. + * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. + */ +int esp_aes_gcm_auth_decrypt( esp_aes_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ); + +#ifdef __cplusplus +} +#endif + +#endif /* gcm.h */ diff --git a/components/mbedtls/port/include/esp32s2beta/sha.h b/components/mbedtls/port/include/esp32s2beta/sha.h index b1b4bead2a..c063ff9215 100644 --- a/components/mbedtls/port/include/esp32s2beta/sha.h +++ b/components/mbedtls/port/include/esp32s2beta/sha.h @@ -11,6 +11,7 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #ifndef _ESP_SHA_H_ #define _ESP_SHA_H_ @@ -101,6 +102,31 @@ void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, uns */ void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block); +/* @brief Begin to execute SHA block operation using DMA + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA + * algorithm. + * + * @note Call esp_sha_try_lock_engine() before calling this + * function. Do not call esp_sha_lock_memory_block() beforehand, this + * is done inside the function. + * + * @param sha_type SHA algorithm to use. + * + * @param data_block Pointer to block of data. Block size is + * determined by algorithm (SHA1/SHA2_256 = 64 bytes, + * SHA2_384/SHA2_512 = 128 bytes) + * + * @param ilen length of input data should be multiple of block length. + * + * @param is_first_block If this parameter is true, the SHA state will + * be initialised (with the initial state of the given SHA algorithm) + * before the block is calculated. If false, the existing state of the + * SHA engine will be used. + * + */ +int esp_sha_dma(esp_sha_type sha_type, const void *data_block, uint32_t ilen, bool is_first_block); + /** @brief Read out the current state of the SHA digest loaded in the engine. * * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. diff --git a/components/soc/esp32s2beta/include/hal/adc_ll.h b/components/soc/esp32s2beta/include/hal/adc_ll.h index 0dd4ce40d2..c15b52d791 100644 --- a/components/soc/esp32s2beta/include/hal/adc_ll.h +++ b/components/soc/esp32s2beta/include/hal/adc_ll.h @@ -2,6 +2,7 @@ #include "soc/adc_periph.h" #include "hal/adc_types.h" +#include "soc/apb_ctrl_struct.h" #include typedef enum { @@ -78,11 +79,11 @@ typedef enum { static inline void adc_ll_dig_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait) { // Internal FSM reset wait time - SYSCON.saradc_fsm_wait.rstb_wait = rst_wait; + APB_CTRL.saradc_fsm_wait.rstb_wait = rst_wait; // Internal FSM start wait time - SYSCON.saradc_fsm_wait.xpd_wait = start_wait; + APB_CTRL.saradc_fsm_wait.xpd_wait = start_wait; // Internal FSM standby wait time - SYSCON.saradc_fsm_wait.standby_wait = standby_wait; + APB_CTRL.saradc_fsm_wait.standby_wait = standby_wait; } /** @@ -94,7 +95,7 @@ static inline void adc_ll_dig_set_fsm_time(uint32_t rst_wait, uint32_t start_wai */ static inline void adc_ll_dig_set_sample_cycle(uint32_t sample_cycle) { - SYSCON.saradc_fsm.sample_cycle = sample_cycle; + APB_CTRL.saradc_fsm.sample_cycle = sample_cycle; } /** @@ -104,7 +105,7 @@ static inline void adc_ll_dig_set_sample_cycle(uint32_t sample_cycle) */ static inline void adc_ll_dig_set_output_format(adc_ll_dig_output_format_t format) { - SYSCON.saradc_ctrl.data_sar_sel = format; + APB_CTRL.saradc_ctrl.data_sar_sel = format; } /** @@ -115,7 +116,7 @@ static inline void adc_ll_dig_set_output_format(adc_ll_dig_output_format_t forma */ static inline void adc_ll_dig_set_convert_limit_num(uint32_t meas_num) { - SYSCON.saradc_ctrl2.max_meas_num = meas_num; + APB_CTRL.saradc_ctrl2.max_meas_num = meas_num; } /** @@ -124,7 +125,7 @@ static inline void adc_ll_dig_set_convert_limit_num(uint32_t meas_num) */ static inline void adc_ll_dig_convert_limit_enable(void) { - SYSCON.saradc_ctrl2.meas_num_limit = 1; + APB_CTRL.saradc_ctrl2.meas_num_limit = 1; } /** @@ -133,7 +134,7 @@ static inline void adc_ll_dig_convert_limit_enable(void) */ static inline void adc_ll_dig_convert_limit_disable(void) { - SYSCON.saradc_ctrl2.meas_num_limit = 0; + APB_CTRL.saradc_ctrl2.meas_num_limit = 0; } /** @@ -146,15 +147,15 @@ static inline void adc_ll_dig_convert_limit_disable(void) static inline void adc_ll_dig_set_convert_mode(adc_ll_convert_mode_t mode) { if (mode == ADC_CONV_SINGLE_UNIT_1) { - SYSCON.saradc_ctrl.work_mode = 0; - SYSCON.saradc_ctrl.sar_sel = 0; + APB_CTRL.saradc_ctrl.work_mode = 0; + APB_CTRL.saradc_ctrl.sar_sel = 0; } else if (mode == ADC_CONV_SINGLE_UNIT_2) { - SYSCON.saradc_ctrl.work_mode = 0; - SYSCON.saradc_ctrl.sar_sel = 1; + APB_CTRL.saradc_ctrl.work_mode = 0; + APB_CTRL.saradc_ctrl.sar_sel = 1; } else if (mode == ADC_CONV_BOTH_UNIT) { - SYSCON.saradc_ctrl.work_mode = 1; + APB_CTRL.saradc_ctrl.work_mode = 1; } else if (mode == ADC_CONV_ALTER_UNIT) { - SYSCON.saradc_ctrl.work_mode = 2; + APB_CTRL.saradc_ctrl.work_mode = 2; } } @@ -166,7 +167,7 @@ static inline void adc_ll_dig_set_convert_mode(adc_ll_convert_mode_t mode) static inline void adc_ll_dig_set_data_source(adc_i2s_source_t src) { /* 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix */ - SYSCON.saradc_ctrl.data_to_i2s = src; + APB_CTRL.saradc_ctrl.data_to_i2s = src; } /** @@ -181,9 +182,9 @@ static inline void adc_ll_dig_set_data_source(adc_i2s_source_t src) static inline void adc_ll_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t patt_len) { if (adc_n == ADC_NUM_1) { - SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1; + APB_CTRL.saradc_ctrl.sar1_patt_len = patt_len - 1; } else { // adc_n == ADC_NUM_2 - SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1; + APB_CTRL.saradc_ctrl.sar2_patt_len = patt_len - 1; } } @@ -202,15 +203,15 @@ static inline void adc_ll_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern uint32_t tab; uint8_t *arg; if (adc_n == ADC_NUM_1) { - tab = SYSCON.saradc_sar1_patt_tab[pattern_index / 4]; + tab = *(uint32_t *)(&APB_CTRL.saradc_sar1_patt_tab1 + pattern_index / 4); arg = (uint8_t *)&tab; arg[pattern_index % 4] = pattern.val; - SYSCON.saradc_sar1_patt_tab[pattern_index / 4] = tab; + *(uint32_t *)(&APB_CTRL.saradc_sar1_patt_tab1 + pattern_index / 4) = tab; } else { // adc_n == ADC_NUM_2 - tab = SYSCON.saradc_sar2_patt_tab[pattern_index / 4]; + tab = *(uint32_t *)(&APB_CTRL.saradc_sar2_patt_tab1 + pattern_index / 4); arg = (uint8_t *)&tab; arg[pattern_index % 4] = pattern.val; - SYSCON.saradc_sar2_patt_tab[pattern_index / 4] = tab; + *(uint32_t *)(&APB_CTRL.saradc_sar2_patt_tab1 + pattern_index / 4) = tab; } } @@ -385,7 +386,7 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void) static inline void adc_ll_set_clk_div(uint32_t div) { /* ADC clock devided from APB clk, e.g. 80 / 2 = 40Mhz, */ - SYSCON.saradc_ctrl.sar_clk_div = div; + APB_CTRL.saradc_ctrl.sar_clk_div = div; } /** diff --git a/components/soc/esp32s2beta/include/hal/gpspi_flash_ll.h b/components/soc/esp32s2beta/include/hal/gpspi_flash_ll.h index b08564856e..27ed122e5e 100644 --- a/components/soc/esp32s2beta/include/hal/gpspi_flash_ll.h +++ b/components/soc/esp32s2beta/include/hal/gpspi_flash_ll.h @@ -33,8 +33,7 @@ #define gpspi_flash_ll_get_hw(host_id) (((host_id)==SPI2_HOST ? &GPSPI2 \ : ((host_id)==SPI3_HOST ? &GPSPI3 \ - : ((host_id)==SPI4_HOST ? &GPSPI4 \ - : ({abort();(spi_dev_t*)0;}))))) + : ({abort();(spi_dev_t*)0;})))) typedef typeof(GPSPI2.clock) gpspi_flash_ll_clock_reg_t; @@ -196,7 +195,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); - ctrl.val |= SPI_FAST_RD_MODE_M; + // ctrl.val |= SPI_FAST_RD_MODE_M; switch (read_mode) { case SPI_FLASH_FASTRD: //the default option @@ -219,9 +218,9 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod ctrl.fread_dual = 1; user.fwrite_dual = 1; break; - case SPI_FLASH_SLOWRD: - ctrl.fast_rd_mode = 0; - break; + // case SPI_FLASH_SLOWRD: + // ctrl.fast_rd_mode = 0; + // break; default: abort(); } diff --git a/components/soc/esp32s2beta/include/hal/spi_ll.h b/components/soc/esp32s2beta/include/hal/spi_ll.h index 3f70b228ef..814a865a60 100644 --- a/components/soc/esp32s2beta/include/hal/spi_ll.h +++ b/components/soc/esp32s2beta/include/hal/spi_ll.h @@ -22,12 +22,12 @@ #pragma once -#include "hal/hal_defs.h" -#include "soc/spi_periph.h" -#include "esp32/rom/lldesc.h" -#include -#include #include //for abs() +#include +#include "hal/hal_defs.h" +#include "esp_types.h" +#include "soc/spi_periph.h" +#include "esp32s2beta/rom/lldesc.h" /// Registers to reset during initialization. Don't use in app. #define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST) @@ -36,7 +36,7 @@ /// Swap the bit order to its correct place to send #define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len)) -#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : ((ID)==2? &GPSPI3: &GPSPI4))) +#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3)) /** * The data structure holding calculated clock configuration. Since the @@ -140,7 +140,7 @@ static inline void spi_ll_reset_dma(spi_dev_t *hw) hw->dma_conf.indscr_burst_en = 1; hw->dma_conf.outdscr_burst_en = 1; hw->dma_in_link.dma_rx_ena = 0; - assert(hw->dma_in_link.dma_rx_ena==0); + assert(hw->dma_in_link.dma_rx_ena == 0); } /** @@ -249,7 +249,7 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) */ static inline void spi_ll_disable_int(spi_dev_t *hw) { - hw->slave.int_trans_done_en = 0; + hw->slave.trans_inten = 0; } /** @@ -280,7 +280,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw) */ static inline void spi_ll_enable_int(spi_dev_t *hw) { - hw->slave.int_trans_done_en = 1; + hw->slave.trans_inten = 1; } /** @@ -291,17 +291,16 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) */ static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type) { - switch (int_type) - { + switch (int_type) { case SPI_LL_INT_TYPE_SEG: hw->dma_int_ena.in_suc_eof = 1; hw->dma_int_ena.out_total_eof = 1; - hw->slave.int_trans_done_en = 0; + hw->slave.trans_inten = 0; break; default: hw->dma_int_ena.in_suc_eof = 0; hw->dma_int_ena.out_total_eof = 0; - hw->slave.int_trans_done_en = 1; + hw->slave.trans_inten = 1; } } @@ -687,7 +686,7 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) */ static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en) { - hw->dma_conf.slv_rx_seg_trans_en = en; + hw->dma_conf.dma_seg_trans_en = en; } /*------------------------------------------------------------------------------ diff --git a/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h b/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h index ef86de5ad2..3f0075c72f 100644 --- a/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h +++ b/components/soc/esp32s2beta/include/hal/touch_sensor_ll.h @@ -945,11 +945,11 @@ static inline void touch_ll_proximity_get_meas_times(uint32_t *times) static inline void touch_ll_proximity_read_meas_cnt(touch_pad_t touch_num, uint32_t *cnt) { if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad0_cnt; + *cnt = SENS.sar_touch_status16.touch_approach_pad0_cnt; } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt; + *cnt = SENS.sar_touch_status16.touch_approach_pad1_cnt; } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) { - *cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt; + *cnt = SENS.sar_touch_status16.touch_approach_pad2_cnt; } } @@ -1040,7 +1040,7 @@ static inline void touch_ll_sleep_disable_approach(void) */ static inline void touch_ll_sleep_read_baseline(uint32_t *baseline) { - *baseline = REG_GET_FIELD(SENS_SAR_TOUCH_SLP_STATUS_REG, SENS_TOUCH_SLP_BASELINE); + *baseline = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_BASELINE); } /** @@ -1050,7 +1050,7 @@ static inline void touch_ll_sleep_read_baseline(uint32_t *baseline) */ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce) { - *debounce = REG_GET_FIELD(SENS_SAR_TOUCH_SLP_STATUS_REG, SENS_TOUCH_SLP_DEBOUNCE); + *debounce = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS15_REG, SENS_TOUCH_SLP_DEBOUNCE); } /** @@ -1059,7 +1059,7 @@ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce) */ static inline void touch_ll_sleep_read_proximity_cnt(uint32_t *approach_cnt) { - *approach_cnt = REG_GET_FIELD(SENS_SAR_TOUCH_APPR_STATUS_REG, SENS_TOUCH_SLP_APPROACH_CNT); + *approach_cnt = REG_GET_FIELD(SENS_SAR_TOUCH_STATUS16_REG, SENS_TOUCH_SLP_APPROACH_CNT); } /** diff --git a/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h b/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h index eefcf3b022..68b26c2e2a 100644 --- a/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h +++ b/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h @@ -49,7 +49,7 @@ extern "C" { #define APB_CTRL_CLK_320M_EN_M (BIT(10)) #define APB_CTRL_CLK_320M_EN_V 0x1 #define APB_CTRL_CLK_320M_EN_S 10 -/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ /*description: */ #define APB_CTRL_PRE_DIV_CNT 0x000003FF #define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) @@ -76,297 +76,7 @@ extern "C" { #define APB_CTRL_XTAL_TICK_NUM_V 0xFF #define APB_CTRL_XTAL_TICK_NUM_S 0 -#define APB_CTRL_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x008) -/* APB_CTRL_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ -/*description: force option to xpd sar blocks*/ -#define APB_CTRL_SARADC_XPD_SAR_FORCE 0x00000003 -#define APB_CTRL_SARADC_XPD_SAR_FORCE_M ((APB_CTRL_SARADC_XPD_SAR_FORCE_V)<<(APB_CTRL_SARADC_XPD_SAR_FORCE_S)) -#define APB_CTRL_SARADC_XPD_SAR_FORCE_V 0x3 -#define APB_CTRL_SARADC_XPD_SAR_FORCE_S 27 -/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data - is from GPIO matrix*/ -#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) -#define APB_CTRL_SARADC_DATA_TO_I2S_M (BIT(26)) -#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x1 -#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 -/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data - in this case the resolution should not be larger than 11 bits.*/ -#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) -#define APB_CTRL_SARADC_DATA_SAR_SEL_M (BIT(25)) -#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x1 -#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 -/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ -#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) -#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) -#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x1 -#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 -/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ -#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) -#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) -#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x1 -#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 -/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000F -#define APB_CTRL_SARADC_SAR2_PATT_LEN_M ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S)) -#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0xF -#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 -/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000F -#define APB_CTRL_SARADC_SAR1_PATT_LEN_M ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S)) -#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0xF -#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 -/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ -/*description: SAR clock divider*/ -#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000FF -#define APB_CTRL_SARADC_SAR_CLK_DIV_M ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S)) -#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0xFF -#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 -/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) -#define APB_CTRL_SARADC_SAR_CLK_GATED_M (BIT(6)) -#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x1 -#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 -/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ -#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) -#define APB_CTRL_SARADC_SAR_SEL_M (BIT(5)) -#define APB_CTRL_SARADC_SAR_SEL_V 0x1 -#define APB_CTRL_SARADC_SAR_SEL_S 5 -/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ -/*description: 0: single mode 1: double mode 2: alternate mode*/ -#define APB_CTRL_SARADC_WORK_MODE 0x00000003 -#define APB_CTRL_SARADC_WORK_MODE_M ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S)) -#define APB_CTRL_SARADC_WORK_MODE_V 0x3 -#define APB_CTRL_SARADC_WORK_MODE_S 3 -/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define APB_CTRL_SARADC_START (BIT(1)) -#define APB_CTRL_SARADC_START_M (BIT(1)) -#define APB_CTRL_SARADC_START_V 0x1 -#define APB_CTRL_SARADC_START_S 1 -/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define APB_CTRL_SARADC_START_FORCE (BIT(0)) -#define APB_CTRL_SARADC_START_FORCE_M (BIT(0)) -#define APB_CTRL_SARADC_START_FORCE_V 0x1 -#define APB_CTRL_SARADC_START_FORCE_S 0 - -#define APB_CTRL_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x00C) -/* APB_CTRL_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: to enable saradc timer trigger*/ -#define APB_CTRL_SARADC_TIMER_EN (BIT(20)) -#define APB_CTRL_SARADC_TIMER_EN_M (BIT(20)) -#define APB_CTRL_SARADC_TIMER_EN_V 0x1 -#define APB_CTRL_SARADC_TIMER_EN_S 20 -/* APB_CTRL_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */ -/*description: to set saradc timer target*/ -#define APB_CTRL_SARADC_TIMER_TARGET 0x000000FF -#define APB_CTRL_SARADC_TIMER_TARGET_M ((APB_CTRL_SARADC_TIMER_TARGET_V)<<(APB_CTRL_SARADC_TIMER_TARGET_S)) -#define APB_CTRL_SARADC_TIMER_TARGET_V 0xFF -#define APB_CTRL_SARADC_TIMER_TARGET_S 12 -/* APB_CTRL_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: 1: select saradc timer 0: i2s_ws trigger*/ -#define APB_CTRL_SARADC_TIMER_SEL (BIT(11)) -#define APB_CTRL_SARADC_TIMER_SEL_M (BIT(11)) -#define APB_CTRL_SARADC_TIMER_SEL_V 0x1 -#define APB_CTRL_SARADC_TIMER_SEL_S 11 -/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ -#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) -#define APB_CTRL_SARADC_SAR2_INV_M (BIT(10)) -#define APB_CTRL_SARADC_SAR2_INV_V 0x1 -#define APB_CTRL_SARADC_SAR2_INV_S 10 -/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ -#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) -#define APB_CTRL_SARADC_SAR1_INV_M (BIT(9)) -#define APB_CTRL_SARADC_SAR1_INV_V 0x1 -#define APB_CTRL_SARADC_SAR1_INV_S 9 -/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ -/*description: max conversion number*/ -#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000FF -#define APB_CTRL_SARADC_MAX_MEAS_NUM_M ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S)) -#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0xFF -#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 -/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) -#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x1 -#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 - -#define APB_CTRL_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x010) -/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ -/*description: sample cycles*/ -#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000FF -#define APB_CTRL_SARADC_SAMPLE_CYCLE_M ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S)) -#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0xFF -#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 -/* APB_CTRL_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */ -/*description: sample number*/ -#define APB_CTRL_SARADC_SAMPLE_NUM 0x000000FF -#define APB_CTRL_SARADC_SAMPLE_NUM_M ((APB_CTRL_SARADC_SAMPLE_NUM_V)<<(APB_CTRL_SARADC_SAMPLE_NUM_S)) -#define APB_CTRL_SARADC_SAMPLE_NUM_V 0xFF -#define APB_CTRL_SARADC_SAMPLE_NUM_S 16 - -#define APB_CTRL_SARADC_FSM_WAIT_REG (DR_REG_APB_CTRL_BASE + 0x014) -/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ -/*description: */ -#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000FF -#define APB_CTRL_SARADC_STANDBY_WAIT_M ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S)) -#define APB_CTRL_SARADC_STANDBY_WAIT_V 0xFF -#define APB_CTRL_SARADC_STANDBY_WAIT_S 16 -/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ -/*description: */ -#define APB_CTRL_SARADC_RSTB_WAIT 0x000000FF -#define APB_CTRL_SARADC_RSTB_WAIT_M ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S)) -#define APB_CTRL_SARADC_RSTB_WAIT_V 0xFF -#define APB_CTRL_SARADC_RSTB_WAIT_S 8 -/* APB_CTRL_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ -/*description: */ -#define APB_CTRL_SARADC_XPD_WAIT 0x000000FF -#define APB_CTRL_SARADC_XPD_WAIT_M ((APB_CTRL_SARADC_XPD_WAIT_V)<<(APB_CTRL_SARADC_XPD_WAIT_S)) -#define APB_CTRL_SARADC_XPD_WAIT_V 0xFF -#define APB_CTRL_SARADC_XPD_WAIT_S 0 - -#define APB_CTRL_SARADC_SAR1_STATUS_REG (DR_REG_APB_CTRL_BASE + 0x018) -/* APB_CTRL_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define APB_CTRL_SARADC_SAR1_STATUS 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_STATUS_M ((APB_CTRL_SARADC_SAR1_STATUS_V)<<(APB_CTRL_SARADC_SAR1_STATUS_S)) -#define APB_CTRL_SARADC_SAR1_STATUS_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_STATUS_S 0 - -#define APB_CTRL_SARADC_SAR2_STATUS_REG (DR_REG_APB_CTRL_BASE + 0x01C) -/* APB_CTRL_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define APB_CTRL_SARADC_SAR2_STATUS 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_STATUS_M ((APB_CTRL_SARADC_SAR2_STATUS_V)<<(APB_CTRL_SARADC_SAR2_STATUS_S)) -#define APB_CTRL_SARADC_SAR2_STATUS_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_STATUS_S 0 - -#define APB_CTRL_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x020) -/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S)) -#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 - -#define APB_CTRL_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x024) -/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S)) -#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 - -#define APB_CTRL_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x028) -/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S)) -#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 - -#define APB_CTRL_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x02C) -/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S)) -#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 - -#define APB_CTRL_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x030) -/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S)) -#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 - -#define APB_CTRL_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x034) -/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S)) -#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 - -#define APB_CTRL_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x038) -/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S)) -#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 - -#define APB_CTRL_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x03C) -/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ -#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S)) -#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF -#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 - -#define APB_CTRL_ADC_ARB_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x040) -/* APB_CTRL_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: adc2 arbiter uses fixed priority*/ -#define APB_CTRL_ADC_ARB_FIX_PRIORITY (BIT(12)) -#define APB_CTRL_ADC_ARB_FIX_PRIORITY_M (BIT(12)) -#define APB_CTRL_ADC_ARB_FIX_PRIORITY_V 0x1 -#define APB_CTRL_ADC_ARB_FIX_PRIORITY_S 12 -/* APB_CTRL_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ -/*description: Set adc2 arbiter wifi priority*/ -#define APB_CTRL_ADC_ARB_WIFI_PRIORITY 0x00000003 -#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_M ((APB_CTRL_ADC_ARB_WIFI_PRIORITY_V)<<(APB_CTRL_ADC_ARB_WIFI_PRIORITY_S)) -#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_V 0x3 -#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_S 10 -/* APB_CTRL_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ -/*description: Set adc2 arbiter rtc priority*/ -#define APB_CTRL_ADC_ARB_RTC_PRIORITY 0x00000003 -#define APB_CTRL_ADC_ARB_RTC_PRIORITY_M ((APB_CTRL_ADC_ARB_RTC_PRIORITY_V)<<(APB_CTRL_ADC_ARB_RTC_PRIORITY_S)) -#define APB_CTRL_ADC_ARB_RTC_PRIORITY_V 0x3 -#define APB_CTRL_ADC_ARB_RTC_PRIORITY_S 8 -/* APB_CTRL_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Set adc2 arbiter apb priority*/ -#define APB_CTRL_ADC_ARB_APB_PRIORITY 0x00000003 -#define APB_CTRL_ADC_ARB_APB_PRIORITY_M ((APB_CTRL_ADC_ARB_APB_PRIORITY_V)<<(APB_CTRL_ADC_ARB_APB_PRIORITY_S)) -#define APB_CTRL_ADC_ARB_APB_PRIORITY_V 0x3 -#define APB_CTRL_ADC_ARB_APB_PRIORITY_S 6 -/* APB_CTRL_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: adc2 arbiter force grant*/ -#define APB_CTRL_ADC_ARB_GRANT_FORCE (BIT(5)) -#define APB_CTRL_ADC_ARB_GRANT_FORCE_M (BIT(5)) -#define APB_CTRL_ADC_ARB_GRANT_FORCE_V 0x1 -#define APB_CTRL_ADC_ARB_GRANT_FORCE_S 5 -/* APB_CTRL_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable wifi controller*/ -#define APB_CTRL_ADC_ARB_WIFI_FORCE (BIT(4)) -#define APB_CTRL_ADC_ARB_WIFI_FORCE_M (BIT(4)) -#define APB_CTRL_ADC_ARB_WIFI_FORCE_V 0x1 -#define APB_CTRL_ADC_ARB_WIFI_FORCE_S 4 -/* APB_CTRL_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable rtc controller*/ -#define APB_CTRL_ADC_ARB_RTC_FORCE (BIT(3)) -#define APB_CTRL_ADC_ARB_RTC_FORCE_M (BIT(3)) -#define APB_CTRL_ADC_ARB_RTC_FORCE_V 0x1 -#define APB_CTRL_ADC_ARB_RTC_FORCE_S 3 -/* APB_CTRL_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable apb controller*/ -#define APB_CTRL_ADC_ARB_APB_FORCE (BIT(2)) -#define APB_CTRL_ADC_ARB_APB_FORCE_M (BIT(2)) -#define APB_CTRL_ADC_ARB_APB_FORCE_V 0x1 -#define APB_CTRL_ADC_ARB_APB_FORCE_S 2 - -#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x044) +#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008) /* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ /*description: */ #define APB_CTRL_CLK_XTAL_OEN (BIT(10)) @@ -434,25 +144,7 @@ extern "C" { #define APB_CTRL_CLK20_OEN_V 0x1 #define APB_CTRL_CLK20_OEN_S 0 -#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x048) -/* APB_CTRL_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI_PRIOR (BIT(13)) -#define APB_CTRL_SPI_PRIOR_M (BIT(13)) -#define APB_CTRL_SPI_PRIOR_V 0x1 -#define APB_CTRL_SPI_PRIOR_S 13 -/* APB_CTRL_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI1_HOLD (BIT(9)) -#define APB_CTRL_SPI1_HOLD_M (BIT(9)) -#define APB_CTRL_SPI1_HOLD_V 0x1 -#define APB_CTRL_SPI1_HOLD_S 9 -/* APB_CTRL_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI0_HOLD (BIT(8)) -#define APB_CTRL_SPI0_HOLD_M (BIT(8)) -#define APB_CTRL_SPI0_HOLD_V 0x1 -#define APB_CTRL_SPI0_HOLD_S 8 +#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x00C) /* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ #define APB_CTRL_PERI_IO_SWAP 0x000000FF @@ -460,7 +152,7 @@ extern "C" { #define APB_CTRL_PERI_IO_SWAP_V 0xFF #define APB_CTRL_PERI_IO_SWAP_S 0 -#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x04C) +#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x010) /* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) @@ -468,7 +160,7 @@ extern "C" { #define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 #define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 -#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x050) +#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x014) /* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_FLASH_ACE0_ATTR 0x00000007 @@ -476,7 +168,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE0_ATTR_V 0x7 #define APB_CTRL_FLASH_ACE0_ATTR_S 0 -#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x054) +#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x018) /* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_FLASH_ACE1_ATTR 0x00000007 @@ -484,7 +176,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE1_ATTR_V 0x7 #define APB_CTRL_FLASH_ACE1_ATTR_S 0 -#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058) +#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x01C) /* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_FLASH_ACE2_ATTR 0x00000007 @@ -492,7 +184,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE2_ATTR_V 0x7 #define APB_CTRL_FLASH_ACE2_ATTR_S 0 -#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C) +#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x020) /* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_FLASH_ACE3_ATTR 0x00000007 @@ -500,7 +192,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE3_ATTR_V 0x7 #define APB_CTRL_FLASH_ACE3_ATTR_S 0 -#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x060) +#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x024) /* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF @@ -508,7 +200,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x064) +#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x028) /* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF @@ -516,7 +208,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068) +#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x02C) /* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF @@ -524,7 +216,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C) +#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x030) /* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF @@ -532,7 +224,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 -#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x070) +#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x034) /* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF @@ -540,7 +232,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF #define APB_CTRL_FLASH_ACE0_SIZE_S 0 -#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x074) +#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x038) /* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF @@ -548,7 +240,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF #define APB_CTRL_FLASH_ACE1_SIZE_S 0 -#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078) +#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x03C) /* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF @@ -556,7 +248,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF #define APB_CTRL_FLASH_ACE2_SIZE_S 0 -#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C) +#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x040) /* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF @@ -564,7 +256,7 @@ extern "C" { #define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF #define APB_CTRL_FLASH_ACE3_SIZE_S 0 -#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x080) +#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x044) /* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_SRAM_ACE0_ATTR 0x00000007 @@ -572,7 +264,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE0_ATTR_V 0x7 #define APB_CTRL_SRAM_ACE0_ATTR_S 0 -#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x084) +#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x048) /* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_SRAM_ACE1_ATTR 0x00000007 @@ -580,7 +272,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE1_ATTR_V 0x7 #define APB_CTRL_SRAM_ACE1_ATTR_S 0 -#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x088) +#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x04C) /* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_SRAM_ACE2_ATTR 0x00000007 @@ -588,7 +280,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE2_ATTR_V 0x7 #define APB_CTRL_SRAM_ACE2_ATTR_S 0 -#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x08C) +#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x050) /* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define APB_CTRL_SRAM_ACE3_ATTR 0x00000007 @@ -596,7 +288,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE3_ATTR_V 0x7 #define APB_CTRL_SRAM_ACE3_ATTR_S 0 -#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x090) +#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x054) /* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF @@ -604,7 +296,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_SRAM_ACE0_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x094) +#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x058) /* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF @@ -612,7 +304,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_SRAM_ACE1_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x098) +#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x05C) /* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF @@ -620,7 +312,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_SRAM_ACE2_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x09C) +#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x060) /* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF @@ -628,7 +320,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF #define APB_CTRL_SRAM_ACE3_ADDR_S_S 0 -#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A0) +#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x064) /* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF @@ -636,7 +328,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF #define APB_CTRL_SRAM_ACE0_SIZE_S 0 -#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A4) +#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x068) /* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF @@ -644,7 +336,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF #define APB_CTRL_SRAM_ACE1_SIZE_S 0 -#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0A8) +#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x06C) /* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF @@ -652,7 +344,7 @@ extern "C" { #define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF #define APB_CTRL_SRAM_ACE2_SIZE_S 0 -#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x0AC) +#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x070) /* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF @@ -660,63 +352,35 @@ extern "C" { #define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF #define APB_CTRL_SRAM_ACE3_SIZE_S 0 -#define APB_CTRL_SPI0_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0B0) -/* APB_CTRL_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ +#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x074) +/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ /*description: */ -#define APB_CTRL_SPI0_REJECT_CDE 0x0000001F -#define APB_CTRL_SPI0_REJECT_CDE_M ((APB_CTRL_SPI0_REJECT_CDE_V)<<(APB_CTRL_SPI0_REJECT_CDE_S)) -#define APB_CTRL_SPI0_REJECT_CDE_V 0x1F -#define APB_CTRL_SPI0_REJECT_CDE_S 2 -/* APB_CTRL_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F +#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S)) +#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F +#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 +/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define APB_CTRL_SPI0_REJECT_CLR (BIT(1)) -#define APB_CTRL_SPI0_REJECT_CLR_M (BIT(1)) -#define APB_CTRL_SPI0_REJECT_CLR_V 0x1 -#define APB_CTRL_SPI0_REJECT_CLR_S 1 -/* APB_CTRL_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ +#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 +/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define APB_CTRL_SPI0_REJECT_INT (BIT(0)) -#define APB_CTRL_SPI0_REJECT_INT_M (BIT(0)) -#define APB_CTRL_SPI0_REJECT_INT_V 0x1 -#define APB_CTRL_SPI0_REJECT_INT_S 0 +#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 -#define APB_CTRL_SPI0_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B4) -/* APB_CTRL_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x078) +/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define APB_CTRL_SPI0_REJECT_ADDR 0xFFFFFFFF -#define APB_CTRL_SPI0_REJECT_ADDR_M ((APB_CTRL_SPI0_REJECT_ADDR_V)<<(APB_CTRL_SPI0_REJECT_ADDR_S)) -#define APB_CTRL_SPI0_REJECT_ADDR_V 0xFFFFFFFF -#define APB_CTRL_SPI0_REJECT_ADDR_S 0 +#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S)) +#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 -#define APB_CTRL_SPI1_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0B8) -/* APB_CTRL_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ -/*description: */ -#define APB_CTRL_SPI1_REJECT_CDE 0x0000001F -#define APB_CTRL_SPI1_REJECT_CDE_M ((APB_CTRL_SPI1_REJECT_CDE_V)<<(APB_CTRL_SPI1_REJECT_CDE_S)) -#define APB_CTRL_SPI1_REJECT_CDE_V 0x1F -#define APB_CTRL_SPI1_REJECT_CDE_S 2 -/* APB_CTRL_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI1_REJECT_CLR (BIT(1)) -#define APB_CTRL_SPI1_REJECT_CLR_M (BIT(1)) -#define APB_CTRL_SPI1_REJECT_CLR_V 0x1 -#define APB_CTRL_SPI1_REJECT_CLR_S 1 -/* APB_CTRL_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define APB_CTRL_SPI1_REJECT_INT (BIT(0)) -#define APB_CTRL_SPI1_REJECT_INT_M (BIT(0)) -#define APB_CTRL_SPI1_REJECT_INT_V 0x1 -#define APB_CTRL_SPI1_REJECT_INT_S 0 - -#define APB_CTRL_SPI1_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC) -/* APB_CTRL_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define APB_CTRL_SPI1_REJECT_ADDR 0xFFFFFFFF -#define APB_CTRL_SPI1_REJECT_ADDR_M ((APB_CTRL_SPI1_REJECT_ADDR_V)<<(APB_CTRL_SPI1_REJECT_ADDR_S)) -#define APB_CTRL_SPI1_REJECT_ADDR_V 0xFFFFFFFF -#define APB_CTRL_SPI1_REJECT_ADDR_S 0 - -#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0C0) +#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x07C) /* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ /*description: */ #define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) @@ -724,7 +388,7 @@ extern "C" { #define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 #define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 -#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x0C4) +#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x080) /* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ #define APB_CTRL_REDCY_ANDOR (BIT(31)) @@ -738,7 +402,7 @@ extern "C" { #define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF #define APB_CTRL_REDCY_SIG0_S 0 -#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x0C8) +#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x084) /* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ #define APB_CTRL_REDCY_NANDOR (BIT(31)) @@ -752,7 +416,7 @@ extern "C" { #define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF #define APB_CTRL_REDCY_SIG1_S 0 -#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x0CC) +#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x088) /* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF @@ -760,7 +424,7 @@ extern "C" { #define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF #define APB_CTRL_WIFI_BB_CFG_S 0 -#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x0D0) +#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x08C) /* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF @@ -768,7 +432,7 @@ extern "C" { #define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF #define APB_CTRL_WIFI_BB_CFG_2_S 0 -#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x0D4) +#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x090) /* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ /*description: */ #define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF @@ -776,7 +440,7 @@ extern "C" { #define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF #define APB_CTRL_WIFI_CLK_EN_S 0 -#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x0D8) +#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x094) /* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define APB_CTRL_WIFI_RST 0xFFFFFFFF @@ -784,7 +448,7 @@ extern "C" { #define APB_CTRL_WIFI_RST_V 0xFFFFFFFF #define APB_CTRL_WIFI_RST_S 0 -#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x0DC) +#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x098) /* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) @@ -823,7 +487,7 @@ extern "C" { #define APB_CTRL_AGC_MEM_FORCE_PU_S 0 #define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) -/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */ +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h1906210 ; */ /*description: */ #define APB_CTRL_DATE 0xFFFFFFFF #define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h b/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h index 9447912e91..58525fb161 100644 --- a/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h +++ b/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h @@ -91,8 +91,14 @@ typedef volatile struct { } saradc_fsm_wait; uint32_t saradc_sar1_status; /**/ uint32_t saradc_sar2_status; /**/ - uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 15 for pattern table 1 (each item one byte)*/ - uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 15 for pattern table 2 (each item one byte)*/ + uint32_t saradc_sar1_patt_tab1; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + uint32_t saradc_sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + uint32_t saradc_sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + uint32_t saradc_sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + uint32_t saradc_sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + uint32_t saradc_sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + uint32_t saradc_sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + uint32_t saradc_sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ union { struct { uint32_t reserved0: 2; diff --git a/components/soc/esp32s2beta/include/soc/apb_saradc_reg.h b/components/soc/esp32s2beta/include/soc/apb_saradc_reg.h new file mode 100644 index 0000000000..56f9c8c6f7 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/apb_saradc_reg.h @@ -0,0 +1,618 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_SARADC_REG_H_ +#define _SOC_APB_SARADC_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) +/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ +/*description: wait arbit signal stable after sar_done*/ +#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 +#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) +#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 +#define APB_SARADC_WAIT_ARB_CYCLE_S 30 +/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: force option to xpd sar blocks*/ +#define APB_SARADC_XPD_SAR_FORCE 0x00000003 +#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) +#define APB_SARADC_XPD_SAR_FORCE_V 0x3 +#define APB_SARADC_XPD_SAR_FORCE_S 27 +/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define APB_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_SARADC_DATA_TO_I2S_V 0x1 +#define APB_SARADC_DATA_TO_I2S_S 26 +/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define APB_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_SARADC_DATA_SAR_SEL_S 25 +/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S)) +#define APB_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_SARADC_SAR2_PATT_LEN_S 19 +/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S)) +#define APB_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_SARADC_SAR1_PATT_LEN_S 15 +/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) +#define APB_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_SARADC_SAR_CLK_DIV_S 7 +/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_SARADC_SAR_CLK_GATED_S 6 +/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define APB_SARADC_SAR_SEL (BIT(5)) +#define APB_SARADC_SAR_SEL_M (BIT(5)) +#define APB_SARADC_SAR_SEL_V 0x1 +#define APB_SARADC_SAR_SEL_S 5 +/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define APB_SARADC_WORK_MODE 0x00000003 +#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S)) +#define APB_SARADC_WORK_MODE_V 0x3 +#define APB_SARADC_WORK_MODE_S 3 +/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_START (BIT(1)) +#define APB_SARADC_START_M (BIT(1)) +#define APB_SARADC_START_V 0x1 +#define APB_SARADC_START_S 1 +/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_START_FORCE_M (BIT(0)) +#define APB_SARADC_START_FORCE_V 0x1 +#define APB_SARADC_START_FORCE_S 0 + +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) +/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: to enable saradc timer trigger*/ +#define APB_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_TIMER_EN_M (BIT(24)) +#define APB_SARADC_TIMER_EN_V 0x1 +#define APB_SARADC_TIMER_EN_S 24 +/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ +/*description: to set saradc timer target*/ +#define APB_SARADC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) +#define APB_SARADC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_TIMER_TARGET_S 12 +/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: 1: select saradc timer 0: i2s_ws trigger*/ +#define APB_SARADC_TIMER_SEL (BIT(11)) +#define APB_SARADC_TIMER_SEL_M (BIT(11)) +#define APB_SARADC_TIMER_SEL_V 0x1 +#define APB_SARADC_TIMER_SEL_S 11 +/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SAR2_INV_M (BIT(10)) +#define APB_SARADC_SAR2_INV_V 0x1 +#define APB_SARADC_SAR2_INV_S 10 +/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SAR1_INV_M (BIT(9)) +#define APB_SARADC_SAR1_INV_V 0x1 +#define APB_SARADC_SAR1_INV_S 9 +/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) +#define APB_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_SARADC_MAX_MEAS_NUM_S 1 +/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_SARADC_FSM_REG (DR_REG_APB_SARADC_BASE + 0x008) +/* APB_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ +/*description: sample cycles*/ +#define APB_SARADC_SAMPLE_CYCLE 0x000000FF +#define APB_SARADC_SAMPLE_CYCLE_M ((APB_SARADC_SAMPLE_CYCLE_V)<<(APB_SARADC_SAMPLE_CYCLE_S)) +#define APB_SARADC_SAMPLE_CYCLE_V 0xFF +#define APB_SARADC_SAMPLE_CYCLE_S 24 +/* APB_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */ +/*description: sample number*/ +#define APB_SARADC_SAMPLE_NUM 0x000000FF +#define APB_SARADC_SAMPLE_NUM_M ((APB_SARADC_SAMPLE_NUM_V)<<(APB_SARADC_SAMPLE_NUM_S)) +#define APB_SARADC_SAMPLE_NUM_V 0xFF +#define APB_SARADC_SAMPLE_NUM_S 16 + +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) +/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ +/*description: */ +#define APB_SARADC_STANDBY_WAIT 0x000000FF +#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) +#define APB_SARADC_STANDBY_WAIT_V 0xFF +#define APB_SARADC_STANDBY_WAIT_S 16 +/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ +/*description: */ +#define APB_SARADC_RSTB_WAIT 0x000000FF +#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) +#define APB_SARADC_RSTB_WAIT_V 0xFF +#define APB_SARADC_RSTB_WAIT_S 8 +/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_SARADC_XPD_WAIT 0x000000FF +#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) +#define APB_SARADC_XPD_WAIT_V 0xFF +#define APB_SARADC_XPD_WAIT_S 0 + +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) +/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) +#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_S 0 + +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) +/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) +#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_S 0 + +#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) +/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S)) +#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB1_S 0 + +#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) +/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S)) +#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB2_S 0 + +#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020) +/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S)) +#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB3_S 0 + +#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024) +/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S)) +#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF +#define APB_SARADC_SAR1_PATT_TAB4_S 0 + +#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028) +/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S)) +#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB1_S 0 + +#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C) +/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S)) +#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB2_S 0 + +#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030) +/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S)) +#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB3_S 0 + +#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034) +/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S)) +#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF +#define APB_SARADC_SAR2_PATT_TAB4_S 0 + +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) +/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: adc2 arbiter uses fixed priority*/ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 +/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ +/*description: Set adc2 arbiter wifi priority*/ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ +/*description: Set adc2 arbiter rtc priority*/ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Set adc2 arbiterapb priority*/ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: adc2 arbiter force grant*/ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enable wifi controller*/ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enable rtc controller*/ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enableapb controller*/ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 + +#define APB_SARADC_FILTER_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C) +/* APB_SARADC_ADC1_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable apb_adc1_filter*/ +#define APB_SARADC_ADC1_FILTER_EN (BIT(31)) +#define APB_SARADC_ADC1_FILTER_EN_M (BIT(31)) +#define APB_SARADC_ADC1_FILTER_EN_V 0x1 +#define APB_SARADC_ADC1_FILTER_EN_S 31 +/* APB_SARADC_ADC2_FILTER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable apb_adc2_filter*/ +#define APB_SARADC_ADC2_FILTER_EN (BIT(30)) +#define APB_SARADC_ADC2_FILTER_EN_M (BIT(30)) +#define APB_SARADC_ADC2_FILTER_EN_V 0x1 +#define APB_SARADC_ADC2_FILTER_EN_S 30 +/* APB_SARADC_ADC1_FILTER_FACTOR : R/W ;bitpos:[29:23] ;default: 7'd64 ; */ +/*description: apb_adc1_filter_factor*/ +#define APB_SARADC_ADC1_FILTER_FACTOR 0x0000007F +#define APB_SARADC_ADC1_FILTER_FACTOR_M ((APB_SARADC_ADC1_FILTER_FACTOR_V)<<(APB_SARADC_ADC1_FILTER_FACTOR_S)) +#define APB_SARADC_ADC1_FILTER_FACTOR_V 0x7F +#define APB_SARADC_ADC1_FILTER_FACTOR_S 23 +/* APB_SARADC_ADC2_FILTER_FACTOR : R/W ;bitpos:[22:16] ;default: 7'd64 ; */ +/*description: apb_adc2_filter_factor*/ +#define APB_SARADC_ADC2_FILTER_FACTOR 0x0000007F +#define APB_SARADC_ADC2_FILTER_FACTOR_M ((APB_SARADC_ADC2_FILTER_FACTOR_V)<<(APB_SARADC_ADC2_FILTER_FACTOR_S)) +#define APB_SARADC_ADC2_FILTER_FACTOR_V 0x7F +#define APB_SARADC_ADC2_FILTER_FACTOR_S 16 +/* APB_SARADC_ADC1_FILTER_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: reset_adc1_filter*/ +#define APB_SARADC_ADC1_FILTER_RESET (BIT(1)) +#define APB_SARADC_ADC1_FILTER_RESET_M (BIT(1)) +#define APB_SARADC_ADC1_FILTER_RESET_V 0x1 +#define APB_SARADC_ADC1_FILTER_RESET_S 1 +/* APB_SARADC_ADC2_FILTER_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: reset_adc2_filter*/ +#define APB_SARADC_ADC2_FILTER_RESET (BIT(0)) +#define APB_SARADC_ADC2_FILTER_RESET_M (BIT(0)) +#define APB_SARADC_ADC2_FILTER_RESET_V 0x1 +#define APB_SARADC_ADC2_FILTER_RESET_S 0 + +#define APB_SARADC_FILTER_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040) +/* APB_SARADC_ADC1_FILTER_DATA : RO ;bitpos:[31:16] ;default: 16'd0 ; */ +/*description: */ +#define APB_SARADC_ADC1_FILTER_DATA 0x0000FFFF +#define APB_SARADC_ADC1_FILTER_DATA_M ((APB_SARADC_ADC1_FILTER_DATA_V)<<(APB_SARADC_ADC1_FILTER_DATA_S)) +#define APB_SARADC_ADC1_FILTER_DATA_V 0xFFFF +#define APB_SARADC_ADC1_FILTER_DATA_S 16 +/* APB_SARADC_ADC2_FILTER_DATA : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define APB_SARADC_ADC2_FILTER_DATA 0x0000FFFF +#define APB_SARADC_ADC2_FILTER_DATA_M ((APB_SARADC_ADC2_FILTER_DATA_V)<<(APB_SARADC_ADC2_FILTER_DATA_S)) +#define APB_SARADC_ADC2_FILTER_DATA_V 0xFFFF +#define APB_SARADC_ADC2_FILTER_DATA_S 0 + +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044) +/* APB_SARADC_ADC1_THRES_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES_EN (BIT(31)) +#define APB_SARADC_ADC1_THRES_EN_M (BIT(31)) +#define APB_SARADC_ADC1_THRES_EN_V 0x1 +#define APB_SARADC_ADC1_THRES_EN_S 31 +/* APB_SARADC_ADC2_THRES_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES_EN (BIT(30)) +#define APB_SARADC_ADC2_THRES_EN_M (BIT(30)) +#define APB_SARADC_ADC2_THRES_EN_V 0x1 +#define APB_SARADC_ADC2_THRES_EN_S 30 +/* APB_SARADC_ADC1_THRES : R/W ;bitpos:[29:17] ;default: 13'd0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES 0x00001FFF +#define APB_SARADC_ADC1_THRES_M ((APB_SARADC_ADC1_THRES_V)<<(APB_SARADC_ADC1_THRES_S)) +#define APB_SARADC_ADC1_THRES_V 0x1FFF +#define APB_SARADC_ADC1_THRES_S 17 +/* APB_SARADC_ADC2_THRES : R/W ;bitpos:[16:4] ;default: 13'd0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES 0x00001FFF +#define APB_SARADC_ADC2_THRES_M ((APB_SARADC_ADC2_THRES_V)<<(APB_SARADC_ADC2_THRES_S)) +#define APB_SARADC_ADC2_THRES_V 0x1FFF +#define APB_SARADC_ADC2_THRES_S 4 +/* APB_SARADC_ADC1_THRES_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES_MODE (BIT(3)) +#define APB_SARADC_ADC1_THRES_MODE_M (BIT(3)) +#define APB_SARADC_ADC1_THRES_MODE_V 0x1 +#define APB_SARADC_ADC1_THRES_MODE_S 3 +/* APB_SARADC_ADC2_THRES_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES_MODE (BIT(2)) +#define APB_SARADC_ADC2_THRES_MODE_M (BIT(2)) +#define APB_SARADC_ADC2_THRES_MODE_V 0x1 +#define APB_SARADC_ADC2_THRES_MODE_S 2 +/* APB_SARADC_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_CLK_EN (BIT(0)) +#define APB_SARADC_CLK_EN_M (BIT(0)) +#define APB_SARADC_CLK_EN_V 0x1 +#define APB_SARADC_CLK_EN_S 0 + +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x048) +/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 +/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 +/* APB_SARADC_ADC1_THRES_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES_INT_ENA (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_ENA_M (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_ENA_V 0x1 +#define APB_SARADC_ADC1_THRES_INT_ENA_S 29 +/* APB_SARADC_ADC2_THRES_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES_INT_ENA (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_ENA_M (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_ENA_V 0x1 +#define APB_SARADC_ADC2_THRES_INT_ENA_S 28 + +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x04C) +/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 +/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 +/* APB_SARADC_ADC1_THRES_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES_INT_RAW (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_RAW_M (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_RAW_V 0x1 +#define APB_SARADC_ADC1_THRES_INT_RAW_S 29 +/* APB_SARADC_ADC2_THRES_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES_INT_RAW (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_RAW_M (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_RAW_V 0x1 +#define APB_SARADC_ADC2_THRES_INT_RAW_S 28 + +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x050) +/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ST_S 31 +/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ST_S 30 +/* APB_SARADC_ADC1_THRES_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES_INT_ST (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_ST_M (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_ST_V 0x1 +#define APB_SARADC_ADC1_THRES_INT_ST_S 29 +/* APB_SARADC_ADC2_THRES_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES_INT_ST (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_ST_M (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_ST_V 0x1 +#define APB_SARADC_ADC2_THRES_INT_ST_S 28 + +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x054) +/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 +/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 +/* APB_SARADC_ADC1_THRES_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_THRES_INT_CLR (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_CLR_M (BIT(29)) +#define APB_SARADC_ADC1_THRES_INT_CLR_V 0x1 +#define APB_SARADC_ADC1_THRES_INT_CLR_S 29 +/* APB_SARADC_ADC2_THRES_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_THRES_INT_CLR (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_CLR_M (BIT(28)) +#define APB_SARADC_ADC2_THRES_INT_CLR_V 0x1 +#define APB_SARADC_ADC2_THRES_INT_CLR_S 28 + +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x058) +/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: enable apb_adc use spi_dma*/ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_V 0x1 +#define APB_SARADC_APB_ADC_TRANS_S 31 +/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: reset_apb_adc_state*/ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ +/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF +#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 + +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x05c) +/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ +/*description: Set this bit to enable clk_apll*/ +#define APB_SARADC_CLK_SEL 0x00000003 +#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) +#define APB_SARADC_CLK_SEL_V 0x3 +#define APB_SARADC_CLK_SEL_S 21 +/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ +/*description: Fractional clock divider denominator value*/ +#define APB_SARADC_CLKM_DIV_A 0x0000003F +#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) +#define APB_SARADC_CLKM_DIV_A_V 0x3F +#define APB_SARADC_CLKM_DIV_A_S 14 +/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ +/*description: Fractional clock divider numerator value*/ +#define APB_SARADC_CLKM_DIV_B 0x0000003F +#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) +#define APB_SARADC_CLKM_DIV_B_V 0x3F +#define APB_SARADC_CLKM_DIV_B_S 8 +/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ +/*description: Integral I2S clock divider value*/ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FF +#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) +#define APB_SARADC_CLKM_DIV_NUM_V 0xFF +#define APB_SARADC_CLKM_DIV_NUM_S 0 + +#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x060) +/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_APB_DAC_RST (BIT(16)) +#define APB_SARADC_APB_DAC_RST_M (BIT(16)) +#define APB_SARADC_APB_DAC_RST_V 0x1 +#define APB_SARADC_APB_DAC_RST_S 16 +/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_DAC_RESET_FIFO (BIT(15)) +#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15)) +#define APB_SARADC_DAC_RESET_FIFO_V 0x1 +#define APB_SARADC_DAC_RESET_FIFO_S 15 +/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable dma_dac*/ +#define APB_SARADC_APB_DAC_TRANS (BIT(14)) +#define APB_SARADC_APB_DAC_TRANS_M (BIT(14)) +#define APB_SARADC_APB_DAC_TRANS_V 0x1 +#define APB_SARADC_APB_DAC_TRANS_S 14 +/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: enable dac alter mode*/ +#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13)) +#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13)) +#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1 +#define APB_SARADC_APB_DAC_ALTER_MODE_S 13 +/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable read dac data*/ +#define APB_SARADC_DAC_TIMER_EN (BIT(12)) +#define APB_SARADC_DAC_TIMER_EN_M (BIT(12)) +#define APB_SARADC_DAC_TIMER_EN_V 0x1 +#define APB_SARADC_DAC_TIMER_EN_S 12 +/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */ +/*description: dac_timer target*/ +#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V)<<(APB_SARADC_DAC_TIMER_TARGET_S)) +#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_DAC_TIMER_TARGET_S 0 + +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC) +/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h01907162 ; */ +/*description: */ +#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF +#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S)) +#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_SARADC_APB_CTRL_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + + +#endif /*_SOC_APB_SARADC_REG_H_ */ + + diff --git a/components/soc/esp32s2beta/include/soc/apb_saradc_struct.h b/components/soc/esp32s2beta/include/soc/apb_saradc_struct.h new file mode 100644 index 0000000000..2724e36e62 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/apb_saradc_struct.h @@ -0,0 +1,439 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_APB_SARADC_STRUCT_H_ +#define _SOC_APB_SARADC_STRUCT_H_ +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t start_force: 1; + uint32_t start: 1; + uint32_t reserved2: 1; + uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + uint32_t sar_clk_gated: 1; + uint32_t sar_clk_div: 8; /*SAR clock divider*/ + uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ + uint32_t reserved29: 1; + uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t meas_num_limit: 1; + uint32_t max_meas_num: 8; /*max conversion number*/ + uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/ + uint32_t timer_target: 12; /*to set saradc timer target*/ + uint32_t timer_en: 1; /*to enable saradc timer trigger*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t reserved0: 16; + uint32_t sample_num: 8; /*sample number*/ + uint32_t sample_cycle: 8; /*sample cycles*/ + }; + uint32_t val; + } fsm; + union { + struct { + uint32_t xpd_wait: 8; + uint32_t rstb_wait: 8; + uint32_t standby_wait: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } fsm_wait; + uint32_t sar1_status; /**/ + uint32_t sar2_status; /**/ + uint32_t sar1_patt_tab[4]; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + uint32_t sar2_patt_tab[4]; + // uint32_t sar1_patt_tab2; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + // uint32_t sar1_patt_tab3; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + // uint32_t sar1_patt_tab4; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + // uint32_t sar2_patt_tab1; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + // uint32_t sar2_patt_tab2; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + // uint32_t sar2_patt_tab3; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + // uint32_t sar2_patt_tab4; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ + union { + struct { + uint32_t reserved0: 2; + uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ + uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ + uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ + uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ + uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ + uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ + uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ + uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } apb_adc_arb_ctrl; + union { + struct { + uint32_t adc2_filter_reset: 1; /*reset_adc2_filter*/ + uint32_t adc1_filter_reset: 1; /*reset_adc1_filter*/ + uint32_t reserved2: 14; + uint32_t adc2_filter_factor: 7; /*apb_adc2_filter_factor*/ + uint32_t adc1_filter_factor: 7; /*apb_adc1_filter_factor*/ + uint32_t adc2_filter_en: 1; /*enable apb_adc2_filter*/ + uint32_t adc1_filter_en: 1; /*enable apb_adc1_filter*/ + }; + uint32_t val; + } filter_ctrl; + union { + struct { + uint32_t adc2_filter_data:16; + uint32_t adc1_filter_data:16; + }; + uint32_t val; + } filter_status; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 1; + uint32_t adc2_thres_mode: 1; + uint32_t adc1_thres_mode: 1; + uint32_t adc2_thres: 13; + uint32_t adc1_thres: 13; + uint32_t adc2_thres_en: 1; + uint32_t adc1_thres_en: 1; + }; + uint32_t val; + } thres_ctrl; + union { + struct { + uint32_t reserved0: 28; + uint32_t adc2_thres: 1; + uint32_t adc1_thres: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t reserved0: 28; + uint32_t adc2_thres: 1; + uint32_t adc1_thres: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t reserved0: 28; + uint32_t adc2_thres: 1; + uint32_t adc1_thres: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t reserved0: 28; + uint32_t adc2_thres: 1; + uint32_t adc1_thres: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ + uint32_t reserved16: 14; + uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ + uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ + uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ + uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ + uint32_t reserved20: 1; + uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } apb_adc_clkm_conf; + union { + struct { + uint32_t dac_timer_target: 12; /*dac_timer target*/ + uint32_t dac_timer_en: 1; /*enable read dac data*/ + uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/ + uint32_t apb_dac_trans: 1; /*enable dma_dac*/ + uint32_t dac_reset_fifo: 1; + uint32_t apb_dac_rst: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } apb_dac_ctrl; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t apb_ctrl_date; /**/ +} apb_saradc_dev_t; +extern apb_saradc_dev_t APB_SARADC; +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_APB_SARADC_STRUCT_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/assist_debug_reg.h b/components/soc/esp32s2beta/include/soc/assist_debug_reg.h index bb34e315de..42fadbb8bd 100644 --- a/components/soc/esp32s2beta/include/soc/assist_debug_reg.h +++ b/components/soc/esp32s2beta/include/soc/assist_debug_reg.h @@ -4,32 +4,53 @@ #define ASSIST_DEBUG_INTERRUPT_RAW ((ASSIST_DEBUG_BASE) +0x04) #define ASSIST_DEBUG_INTERRUPT_RLS ((ASSIST_DEBUG_BASE) +0x08) #define ASSIST_DEBUG_INTERRUPT_CLR ((ASSIST_DEBUG_BASE) +0x0C) -#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_RD BIT(0) -#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_WR BIT(1) -#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_RD BIT(2) -#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_WR BIT(3) -#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MIN BIT(4) -#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MAX BIT(5) + +#define ASSIST_DEBUG_SP_SPILL_MAX BIT(19) +#define ASSIST_DEBUG_SP_SPILL_MIN BIT(18) +#define ASSIST_DEBUG_AREA_2_1_AHB_WR BIT(17) +#define ASSIST_DEBUG_AREA_2_1_AHB_RD BIT(16) +#define ASSIST_DEBUG_AREA_2_0_AHB_WR BIT(15) +#define ASSIST_DEBUG_AREA_2_0_AHB_RD BIT(14) +#define ASSIST_DEBUG_AREA_1_1_DROM0_RD BIT(13) +#define ASSIST_DEBUG_AREA_1_0_DROM0_RD BIT(12) +#define ASSIST_DEBUG_AREA_0_1_DPORT0_WR BIT(11) +#define ASSIST_DEBUG_AREA_0_1_DPORT0_RD BIT(10) +#define ASSIST_DEBUG_AREA_0_1_DRAM1_WR BIT(9) +#define ASSIST_DEBUG_AREA_0_1_DRAM1_RD BIT(8) +#define ASSIST_DEBUG_AREA_0_1_DRAM0_WR BIT(7) +#define ASSIST_DEBUG_AREA_0_1_DRAM0_RD BIT(6) +#define ASSIST_DEBUG_AREA_0_0_DPORT0_WR BIT(5) +#define ASSIST_DEBUG_AREA_0_0_DPORT0_RD BIT(4) +#define ASSIST_DEBUG_AREA_0_0_DRAM1_WR BIT(3) +#define ASSIST_DEBUG_AREA_0_0_DRAM1_RD BIT(2) +#define ASSIST_DEBUG_AREA_0_0_DRAM0_WR BIT(1) +#define ASSIST_DEBUG_AREA_0_0_DRAM0_RD BIT(0) -#define ASSIST_DEBUG_AREA_0_MIN ((ASSIST_DEBUG_BASE) +0x10) -#define ASSIST_DEBUG_AREA_0_MAX ((ASSIST_DEBUG_BASE) +0x14) -#define ASSIST_DEBUG_AREA_0_PC ((ASSIST_DEBUG_BASE) +0x18) -#define ASSIST_DEBUG_AREA_0_SP ((ASSIST_DEBUG_BASE) +0x1C) +#define ASSIST_DEBUG_AREA_0_0_MIN ((ASSIST_DEBUG_BASE) +0x10) +#define ASSIST_DEBUG_AREA_0_0_MAX ((ASSIST_DEBUG_BASE) +0x14) +#define ASSIST_DEBUG_AREA_0_1_MIN ((ASSIST_DEBUG_BASE) +0x18) +#define ASSIST_DEBUG_AREA_0_1_MAX ((ASSIST_DEBUG_BASE) +0x1C) +#define ASSIST_DEBUG_AREA_1_0_MIN ((ASSIST_DEBUG_BASE) +0x20) +#define ASSIST_DEBUG_AREA_1_0_MAX ((ASSIST_DEBUG_BASE) +0x24) +#define ASSIST_DEBUG_AREA_1_1_MIN ((ASSIST_DEBUG_BASE) +0x28) +#define ASSIST_DEBUG_AREA_1_1_MAX ((ASSIST_DEBUG_BASE) +0x2C) +#define ASSIST_DEBUG_AREA_2_0_MIN ((ASSIST_DEBUG_BASE) +0x30) +#define ASSIST_DEBUG_AREA_2_0_MAX ((ASSIST_DEBUG_BASE) +0x34) +#define ASSIST_DEBUG_AREA_2_1_MIN ((ASSIST_DEBUG_BASE) +0x38) +#define ASSIST_DEBUG_AREA_2_1_MAX ((ASSIST_DEBUG_BASE) +0x3C) +#define ASSIST_DEBUG_AREA_PC ((ASSIST_DEBUG_BASE) +0x40) +#define ASSIST_DEBUG_AREA_SP ((ASSIST_DEBUG_BASE) +0x44) -#define ASSIST_DEBUG_AREA_1_MIN ((ASSIST_DEBUG_BASE) +0x20) -#define ASSIST_DEBUG_AREA_1_MAX ((ASSIST_DEBUG_BASE) +0x24) -#define ASSIST_DEBUG_AREA_1_PC ((ASSIST_DEBUG_BASE) +0x28) -#define ASSIST_DEBUG_AREA_1_SP ((ASSIST_DEBUG_BASE) +0x2C) -#define ASSIST_DEBUG_PRO_SP_UNSTABLE ((ASSIST_DEBUG_BASE) +0x30) -#define ASSIST_DEBUG_PRO_SP_MIN ((ASSIST_DEBUG_BASE) +0x34) -#define ASSIST_DEBUG_PRO_SP_MAX ((ASSIST_DEBUG_BASE) +0x38) -#define ASSIST_DEBUG_PRO_SP_PC ((ASSIST_DEBUG_BASE) +0x3C) +#define ASSIST_DEBUG_PRO_SP_UNSTABLE ((ASSIST_DEBUG_BASE) +0x48) +#define ASSIST_DEBUG_PRO_SP_MIN ((ASSIST_DEBUG_BASE) +0x4C) +#define ASSIST_DEBUG_PRO_SP_MAX ((ASSIST_DEBUG_BASE) +0x50) +#define ASSIST_DEBUG_PRO_SP_PC ((ASSIST_DEBUG_BASE) +0x54) -#define ASSIST_DEBUG_PRO_PDEBUGENABLE ((ASSIST_DEBUG_BASE) +0x40) -#define ASSIST_DEBUG_PRO_RCD_RECORDING ((ASSIST_DEBUG_BASE) +0x44) -#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST ((ASSIST_DEBUG_BASE) +0x48) +#define ASSIST_DEBUG_PRO_PDEBUGENABLE ((ASSIST_DEBUG_BASE) +0x58) +#define ASSIST_DEBUG_PRO_RCD_RECORDING ((ASSIST_DEBUG_BASE) +0x5C) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST ((ASSIST_DEBUG_BASE) +0x60) /* register layout: * SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given * by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing @@ -57,7 +78,7 @@ #define DPORT_RECORD_PDEBUGINST_CINTL_S 24 #define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V) -#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS ((ASSIST_DEBUG_BASE) +0x4C) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS ((ASSIST_DEBUG_BASE) +0x64) /* register layout: * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0 * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0 @@ -106,10 +127,12 @@ #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */ -#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA ((ASSIST_DEBUG_BASE) +0x50) -#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC ((ASSIST_DEBUG_BASE) +0x54) -#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT ((ASSIST_DEBUG_BASE) +0x58) -#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR ((ASSIST_DEBUG_BASE) +0x5C) -#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA ((ASSIST_DEBUG_BASE) +0x60) -#define ASSIST_DEBUG_PRO_RCD_SP ((ASSIST_DEBUG_BASE) +0x64) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA ((ASSIST_DEBUG_BASE) +0x68) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC ((ASSIST_DEBUG_BASE) +0x6C) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT ((ASSIST_DEBUG_BASE) +0x70) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR ((ASSIST_DEBUG_BASE) +0x74) +#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA ((ASSIST_DEBUG_BASE) +0x78) +#define ASSIST_DEBUG_PRO_RCD_SP ((ASSIST_DEBUG_BASE) +0x7C) +#define ASSIST_DEBUG_CLOCK_GATE ((ASSIST_DEBUG_BASE) +0x80) +#define ASSIST_DEBUG_REG_DATE ((ASSIST_DEBUG_BASE) +0xFFC) diff --git a/components/soc/esp32s2beta/include/soc/boot_mode.h b/components/soc/esp32s2beta/include/soc/boot_mode.h index 46d7205d4f..bba7f4c182 100644 --- a/components/soc/esp32s2beta/include/soc/boot_mode.h +++ b/components/soc/esp32s2beta/include/soc/boot_mode.h @@ -18,75 +18,84 @@ #include "soc.h" /*SPI Boot*/ -#define IS_1XXX(v) (((v)&0x08)==0x08) +#define IS_1XXX(v) (((v)&0x08)==0x08) -/*Download Boot, USB/SDIO/UART0/UART1*/ -#define IS_00XX(v) (((v)&0x0c)==0x00) +/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) /*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ -#define IS_0000(v) (((v)&0x0f)==0x00) +#define IS_0000(v) (((v)&0x0f)==0x00) /*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ -#define IS_0001(v) (((v)&0x0f)==0x01) +#define IS_0001(v) (((v)&0x0f)==0x01) /*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ -#define IS_0010(v) (((v)&0x0f)==0x02) +#define IS_0010(v) (((v)&0x0f)==0x02) /*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ -#define IS_0011(v) (((v)&0x0f)==0x03) - -/*ATE/ANALOG Mode*/ -#define IS_0101(v) (((v)&0x0f)==0x05) - -/*Diagnostic Mode+UART0 download Mode*/ -#define IS_0111(v) (((v)&0x0f)==0x07) +#define IS_0011(v) (((v)&0x0f)==0x03) /*legacy SPI Boot*/ -#define IS_0100(v) (((v)&0x0f)==0x04) +#define IS_0100(v) (((v)&0x0f)==0x04) -/*SDIO_Slave download Mode V1.1*/ -#define IS_0110(v) (((v)&0x0f)==0x06) +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) -#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) /*do not include download mode*/ -#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) /*all spi boot including spi/legacy*/ -#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) /*all faster spi boot including spi*/ -#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD /*all sdio V2 of failing edge input, failing edge output*/ -#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) /*all sdio V2 of failing edge input, raising edge output*/ -#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) /*all sdio V2 of raising edge input, failing edge output*/ -#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) /*all sdio V2 of raising edge input, raising edge output*/ -#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) /*all sdio V1 of raising edge input, failing edge output*/ -#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) -/*do not include download mode*/ -#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif /*joint download boot*/ -#define ETS_IS_USB_SDIO_UART_BOOT() IS_00XX(BOOT_MODE_GET()) +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) /*ATE mode*/ -#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) /*used by ETS_IS_SDIO_UART_BOOT*/ -#define SEL_NO_BOOT 0 -#define SEL_SDIO_BOOT BIT0 -#define SEL_UART_BOOT BIT1 +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 #endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/cache_memory.h b/components/soc/esp32s2beta/include/soc/cache_memory.h new file mode 100644 index 0000000000..c82401697c --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/cache_memory.h @@ -0,0 +1,139 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _CACHE_MEMORY_H_ +#define _CACHE_MEMORY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/*IRAM0 is connected with Cache IBUS0*/ +#define IRAM0_ADDRESS_LOW 0x40000000 +#define IRAM0_ADDRESS_HIGH 0x40400000 +#define IRAM0_CACHE_ADDRESS_LOW 0x40080000 +#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000 + +/*IRAM1 is connected with Cache IBUS1*/ +#define IRAM1_ADDRESS_LOW 0x40400000 +#define IRAM1_ADDRESS_HIGH 0x40800000 + +/*DROM0 is connected with Cache IBUS2*/ +#define DROM0_ADDRESS_LOW 0x3f000000 +#define DROM0_ADDRESS_HIGH 0x3f400000 + +/*DRAM0 is connected with Cache DBUS0*/ +#define DRAM0_ADDRESS_LOW 0x3fc00000 +#define DRAM0_ADDRESS_HIGH 0x40000000 +#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000 +#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000 + +/*DRAM1 is connected with Cache DBUS1*/ +#define DRAM1_ADDRESS_LOW 0x3f800000 +#define DRAM1_ADDRESS_HIGH 0x3fc00000 + +/*DPORT is connected with Cache DBUS2*/ +#define DPORT_ADDRESS_LOW 0x3f400000 +#define DPORT_ADDRESS_HIGH 0x3f800000 +#define DPORT_CACHE_ADDRESS_LOW 0x3f500000 +#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000 + +#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) +#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) +#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr) +#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr) +#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) +#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) +#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr) +#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr) +#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr) + +#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) +#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1) +#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0) +#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0) +#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) +#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1) +#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT) + +#define PRO_CACHE_IBUS0 0 +#define PRO_CACHE_IBUS0_MMU_START 0 +#define PRO_CACHE_IBUS0_MMU_END 0x100 + +#define PRO_CACHE_IBUS1 1 +#define PRO_CACHE_IBUS1_MMU_START 0x100 +#define PRO_CACHE_IBUS1_MMU_END 0x200 + +#define PRO_CACHE_IBUS2 2 +#define PRO_CACHE_IBUS2_MMU_START 0x200 +#define PRO_CACHE_IBUS2_MMU_END 0x300 + +#define PRO_CACHE_DBUS0 3 +#define PRO_CACHE_DBUS0_MMU_START 0x300 +#define PRO_CACHE_DBUS0_MMU_END 0x400 + +#define PRO_CACHE_DBUS1 4 +#define PRO_CACHE_DBUS1_MMU_START 0x400 +#define PRO_CACHE_DBUS1_MMU_END 0x500 + +#define PRO_CACHE_DBUS2 5 +#define PRO_CACHE_DBUS2_MMU_START 0x500 +#define PRO_CACHE_DBUS2_MMU_END 0x600 + +// #define MMU_SIZE 0x600 +#define ICACHE_MMU_SIZE 0x300 +#define DCACHE_MMU_SIZE 0x300 + +#define MMU_BUS_START(i) ((i) * 0x100) +#define MMU_BUS_SIZE 0x100 + +#define MMU_INVALID BIT(14) +#define MMU_ACCESS_FLASH BIT(15) +#define MMU_ACCESS_SPIRAM BIT(16) + +#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) +#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) + +#define MMU_TABLE_INVALID_VAL 0x4000 +#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL +#define MMU_ADDRESS_MASK 0x3fff +#define MMU_PAGE_SIZE 0x10000 + +#define BUS_ADDR_SIZE 0x400000 +#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) +#define BUS_NUM_MASK 0x3 + +#define CACHE_MEMORY_BANK_SIZE 8192 +#define CACHE_MEMORY_BANK_NUM 4 +#define CACHE_MEMORY_BANK_NUM_MASK 0x3 +#define CACHE_MEMORY_LAYOUT_SHIFT 4 +#define CACHE_MEMORY_LAYOUT_SHIFT0 0 +#define CACHE_MEMORY_LAYOUT_SHIFT1 4 +#define CACHE_MEMORY_LAYOUT_SHIFT2 8 +#define CACHE_MEMORY_LAYOUT_SHIFT3 12 +#define CACHE_MEMORY_LAYOUT_MASK 0xf +#define CACHE_MEMORY_BANK0_ADDR 0x3FFB0000 +#define CACHE_MEMORY_BANK1_ADDR 0x3FFB2000 +#define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000 +#define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000 + +#ifdef __cplusplus +} +#endif + +#endif /*_CACHE_MEMORY_H_ */ + + diff --git a/components/soc/esp32s2beta/include/soc/crypto_dma_reg.h b/components/soc/esp32s2beta/include/soc/crypto_dma_reg.h new file mode 100644 index 0000000000..58433ebb50 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/crypto_dma_reg.h @@ -0,0 +1,187 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_CRYPTO_DMA_REG_H_ +#define _SOC_CRYPTO_DMA_REG_H_ + + +#ifdef __cplusplus +extern "C" { +#endif +#include "soc.h" + +/* CRYPTO_DMA_CONF0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */ +/* CONF0_REG_GEN_CLK_EN : RW ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_GEN_CLK_EN (BIT(13)) +#define CONF0_REG_GEN_CLK_EN_M (BIT(13)) +#define CONF0_REG_GEN_CLK_EN_V 0x1 +#define CONF0_REG_GEN_CLK_EN_S 13 +/* CONF0_REG_MEM_TRANS_EN: RW ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_MEM_TRANS_EN (BIT(12)) +#define CONF0_REG_MEM_TRANS_EN_M (BIT(12)) +#define CONF0_REG_MEM_TRANS_EN_V 0x1 +#define CONF0_REG_MEM_TRANS_EN_S 12 +/* CONF0_REG_OUT_DATA_BURST_EN: RW ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUT_DATA_BURST_EN (BIT(11)) +#define CONF0_REG_OUT_DATA_BURST_EN_M (BIT(11)) +#define CONF0_REG_OUT_DATA_BURST_EN_V 0x1 +#define CONF0_REG_OUT_DATA_BURST_EN_S 11 +/* CONF0_REG_INDSCR_BURST_EN: RW ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_INDSCR_BURST_EN (BIT(10)) +#define CONF0_REG_INDSCR_BURST_EN_M (BIT(10)) +#define CONF0_REG_INDSCR_BURST_EN_V 0x1 +#define CONF0_REG_INDSCR_BURST_EN_S 10 +/* CONF0_REG_OUTDSCR_BURST_EN: RW ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUTDSCR_BURST_EN (BIT(9)) +#define CONF0_REG_OUTDSCR_BURST_EN_M (BIT(9)) +#define CONF0_REG_OUTDSCR_BURST_EN_V 0x1 +#define CONF0_REG_OUTDSCR_BURST_EN_S 9 +/* CONF0_REG_OUT_EOF_MODE: RW ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUT_EOF_MODE (BIT(8)) +#define CONF0_REG_OUT_EOF_MODE_M (BIT(8)) +#define CONF0_REG_OUT_EOF_MODE_V 0x1 +#define CONF0_REG_OUT_EOF_MODE_S 8 +/* CONF0_REG_OUT_NO_RESTART_CLR: RW ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUT_NO_RESTART_CLR (BIT(7)) +#define CONF0_REG_OUT_NO_RESTART_CLR_M (BIT(7)) +#define CONF0_REG_OUT_NO_RESTART_CLR_V 0x1 +#define CONF0_REG_OUT_NO_RESTART_CLR_S 7 +/* CONF0_REG_OUT_AUTO_WRBACK: RW ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUT_AUTO_WRBACK (BIT(6)) +#define CONF0_REG_OUT_AUTO_WRBACK_M (BIT(6)) +#define CONF0_REG_OUT_AUTO_WRBACK_V 0x1 +#define CONF0_REG_OUT_AUTO_WRBACK_S 6 +/* CONF0_REG_OUT_LOOP_TEST: RW ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUT_LOOP_TEST (BIT(5)) +#define CONF0_REG_OUT_LOOP_TEST_M (BIT(5)) +#define CONF0_REG_OUT_LOOP_TEST_V 0x1 +#define CONF0_REG_OUT_LOOP_TEST_S 5 +/* CONF0_REG_IN_LOOP_TEST: RW ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_IN_LOOP_TEST (BIT(4)) +#define CONF0_REG_IN_LOOP_TEST_M (BIT(4)) +#define CONF0_REG_IN_LOOP_TEST_V 0x1 +#define CONF0_REG_IN_LOOP_TEST_S 4 +/* CONF0_REG_AHBM_RST: RW ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_AHBM_RST (BIT(3)) +#define CONF0_REG_AHBM_RST_M (BIT(3)) +#define CONF0_REG_AHBM_RST_V 0x1 +#define CONF0_REG_AHBM_RST_S 3 +/* CONF0_REG_AHBM_FIFO_RST: RW ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_AHBM_FIFO_RST (BIT(2)) +#define CONF0_REG_AHBM_FIFO_RST_M (BIT(2)) +#define CONF0_REG_AHBM_FIFO_RST_V 0x1 +#define CONF0_REG_AHBM_FIFO_RST_S 2 +/* CONF0_REG_OUT_RST: RW ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_OUT_RST (BIT(1)) +#define CONF0_REG_OUT_RST_M (BIT(1)) +#define CONF0_REG_OUT_RST_V 0x1 +#define CONF0_REG_OUT_RST_S 1 +/* CONF0_REG_IN_RST: RW ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CONF0_REG_IN_RST (BIT(0)) +#define CONF0_REG_IN_RST_M (BIT(0)) +#define CONF0_REG_IN_RST_V 0x1 +#define CONF0_REG_IN_RST_S 0 +/* CRYPTO_DMA_INT_RAW : RO ;bitpos:[31:10] ;default: 22'h0 ; */ +/* INT_RAW_OUT_TOTAL_EOF : RW ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define INT_RAW_OUT_TOTAL_EOF ( BIT(8)) +#define INT_RAW_OUT_TOTAL_EOF_M (BIT(8)) +#define INT_RAW_OUT_TOTAL_EOF_V 0x1 +#define INT_RAW_OUT_TOTAL_EOF_S 8 +/* INT_RAW_IN_SUC_EOF : RW ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define INT_RAW_IN_SUC_EOF ( BIT(1)) +#define INT_RAW_IN_SUC_EOF_M (BIT(1)) +#define INT_RAW_IN_SUC_EOF_V 0x1 +#define INT_RAW_IN_SUC_EOF_S 1 +/* CRYPTO_DMA_OUT_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/* OUT_LINK_REG_OUTLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define OUT_LINK_REG_OUTLINK_RESTART ( BIT(30)) +#define OUT_LINK_REG_OUTLINK_RESTART_M (BIT(30)) +#define OUT_LINK_REG_OUTLINK_RESTART_V 0x1 +#define OUT_LINK_REG_OUTLINK_RESTART_S 30 +/* OUT_LINK_REG_OUTLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define OUT_LINK_REG_OUTLINK_START ( BIT(29)) +#define OUT_LINK_REG_OUTLINK_START_M (BIT(29)) +#define OUT_LINK_REG_OUTLINK_START_V 0x1 +#define OUT_LINK_REG_OUTLINK_START_S 29 +/* OUT_LINK_REG_OUTLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define OUT_LINK_REG_OUTLINK_STOP ( BIT(28)) +#define OUT_LINK_REG_OUTLINK_STOP_M (BIT(28)) +#define OUT_LINK_REG_OUTLINK_STOP_V 0x1 +#define OUT_LINK_REG_OUTLINK_STOP_S 28 +/* OUT_LINK_REG_OUTLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define OUT_LINK_REG_OUTLINK_ADDR 0x000FFFFF +#define OUT_LINK_REG_OUTLINK_ADDR_M (OUT_LINK_REG_OUTLINK_ADDR_V<= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) - -#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) -#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) -#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr) -#define ADDRESS_IN_AHB_IBUS1(vaddr) ADDRESS_IN_BUS(AHB_IBUS1, vaddr) -#define ADDRESS_IN_IROM0(vaddr) ADDRESS_IN_BUS(IROM0, vaddr) -#define ADDRESS_IN_AHB_IBUS2(vaddr) ADDRESS_IN_BUS(AHB_IBUS2, vaddr) -#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr) -#define ADDRESS_IN_AHB_IBUS3(vaddr) ADDRESS_IN_BUS(AHB_IBUS3, vaddr) -#define ADDRESS_IN_AHB_DBUS3(vaddr) ADDRESS_IN_BUS(AHB_DBUS3, vaddr) -#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) -#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) -#define ADDRESS_IN_AHB_DBUS0(vaddr) ADDRESS_IN_BUS(AHB_DBUS0, vaddr) -#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr) -#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr) -#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr) -#define ADDRESS_IN_AHB_DBUS2(vaddr) ADDRESS_IN_BUS(AHB_DBUS2, vaddr) - -#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) -#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1) -#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0) -#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0) -#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) -#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1) -#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT) - -#define BUS_AHB_IBUS1_CACHE_SIZE BUS_SIZE(AHB_IBUS1) -#define BUS_AHB_IBUS2_CACHE_SIZE BUS_SIZE(AHB_IBUS2) -#define BUS_AHB_IBUS3_CACHE_SIZE BUS_SIZE(AHB_IBUS3) -#define BUS_AHB_DBUS0_CACHE_SIZE BUS_SIZE(AHB_DBUS0) -#define BUS_AHB_DBUS2_CACHE_SIZE BUS_SIZE(AHB_DBUS2) -#define BUS_AHB_DBUS3_CACHE_SIZE BUS_SIZE(AHB_DBUS3) - - - -#define PRO_CACHE_IBUS0 0 -#define PRO_CACHE_IBUS0_MMU_START 0 -#define PRO_CACHE_IBUS0_MMU_END 0x100 - -#define PRO_CACHE_IBUS1 1 -#define PRO_CACHE_IBUS1_MMU_START 0x100 -#define PRO_CACHE_IBUS1_MMU_END 0x200 - -#define PRO_CACHE_IBUS2 2 -#define PRO_CACHE_IBUS2_MMU_START 0x200 -#define PRO_CACHE_IBUS2_MMU_END 0x300 - -#define PRO_CACHE_IBUS3 3 -#define PRO_CACHE_IBUS3_MMU_START 0x300 -#define PRO_CACHE_IBUS3_MMU_END 0x400 - -#define PRO_CACHE_DBUS0 4 -#define PRO_CACHE_DBUS0_MMU_START 0x400 -#define PRO_CACHE_DBUS0_MMU_END 0x500 - -#define PRO_CACHE_DBUS1 5 -#define PRO_CACHE_DBUS1_MMU_START 0x500 -#define PRO_CACHE_DBUS1_MMU_END 0x600 - -#define PRO_CACHE_DBUS2 6 -#define PRO_CACHE_DBUS2_MMU_START 0x600 -#define PRO_CACHE_DBUS2_MMU_END 0x700 - -#define PRO_CACHE_DBUS3 7 -#define PRO_CACHE_DBUS3_MMU_START 0x700 -#define PRO_CACHE_DBUS3_MMU_END 0x800 - -#define DPORT_MMU_SIZE 0x800 -#define DPORT_ICACHE_MMU_SIZE 0x400 -#define DPORT_DCACHE_MMU_SIZE 0x400 - -#define DPORT_MMU_BUS_START(i) ((i) * 0x100) -#define DPORT_MMU_BUS_SIZE 0x100 - -#define DPORT_MMU_INVALID BIT(14) -#define DPORT_MMU_ACCESS_FLASH BIT(15) -#define DPORT_MMU_ACCESS_SPIRAM BIT(16) - -/* Flash MMU table for PRO CPU */ -#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) - -#define DPORT_FLASH_MMU_TABLE_SIZE (DPORT_ICACHE_MMU_SIZE/sizeof(uint32_t)) - -#define DPORT_MMU_TABLE_INVALID_VAL 0x4000 -#define DPORT_FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL -#define DPORT_MMU_ADDRESS_MASK 0x3fff - -#define BUS_ADDR_SIZE 0x400000 -#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) -#define BUS_NUM_MASK 0x3 - -#define CACHE_MEMORY_BLOCK_SIZE 8192 -#define CACHE_MEMORY_BLOCK_NUM 4 -#define CACHE_MEMORY_BLOCK_NUM_MASK 0x3 -#define CACHE_MEMORY_LAYOUT_SHIFT 4 -#define CACHE_MEMORY_LAYOUT_SHIFT0 0 -#define CACHE_MEMORY_LAYOUT_SHIFT1 4 -#define CACHE_MEMORY_LAYOUT_SHIFT2 8 -#define CACHE_MEMORY_LAYOUT_SHIFT3 12 -#define CACHE_MEMORY_LAYOUT_MASK 0xf -#define CACHE_MEMORY_BLOCK0_ADDR 0x40020000 -#define CACHE_MEMORY_BLOCK1_ADDR 0x40022000 -#define CACHE_MEMORY_BLOCK2_ADDR 0x40024000 -#define CACHE_MEMORY_BLOCK3_ADDR 0x40026000 - #define DPORT_DATE_REG SYSTEM_DATE_REG #ifndef __ASSEMBLER__ diff --git a/components/soc/esp32s2beta/include/soc/efuse_reg.h b/components/soc/esp32s2beta/include/soc/efuse_reg.h index b208fa9658..766f714aea 100644 --- a/components/soc/esp32s2beta/include/soc/efuse_reg.h +++ b/components/soc/esp32s2beta/include/soc/efuse_reg.h @@ -20,898 +20,961 @@ extern "C" { #endif #include "soc.h" #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x000) -/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ +/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Set this bit to disable eFuse programming.*/ #define EFUSE_WR_DIS 0xFFFFFFFF #define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) #define EFUSE_WR_DIS_V 0xFFFFFFFF #define EFUSE_WR_DIS_S 0 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x004) -/* EFUSE_SDIO_DREFH : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFH 0x00000003 -#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) -#define EFUSE_SDIO_DREFH_V 0x3 -#define EFUSE_SDIO_DREFH_S 30 -/* EFUSE_SDIO_MODECURLIM : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_MODECURLIM (BIT(29)) -#define EFUSE_SDIO_MODECURLIM_M (BIT(29)) -#define EFUSE_SDIO_MODECURLIM_V 0x1 -#define EFUSE_SDIO_MODECURLIM_S 29 -/* EFUSE_USB_DRES : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_USB_DRES 0x00000003 -#define EFUSE_USB_DRES_M ((EFUSE_USB_DRES_V)<<(EFUSE_USB_DRES_S)) -#define EFUSE_USB_DRES_V 0x3 -#define EFUSE_USB_DRES_S 27 -/* EFUSE_USB_FORCE_B : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_USB_FORCE_B (BIT(26)) -#define EFUSE_USB_FORCE_B_M (BIT(26)) -#define EFUSE_USB_FORCE_B_V 0x1 -#define EFUSE_USB_FORCE_B_S 26 -/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_VDD_SPI_DREFH : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: SPI regulator high voltage reference.*/ +#define EFUSE_VDD_SPI_DREFH 0x00000003 +#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) +#define EFUSE_VDD_SPI_DREFH_V 0x3 +#define EFUSE_VDD_SPI_DREFH_S 30 +/* EFUSE_VDD_SPI_MODECURLIM : R/W ;bitpos:[29] ;default: 1'h0 ; */ +/*description: SPI regulator switches current limit mode.*/ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 +#define EFUSE_VDD_SPI_MODECURLIM_S 29 +/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[28:27] ;default: 2'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED0 0x00000003 +#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) +#define EFUSE_RPT4_RESERVED0_V 0x3 +#define EFUSE_RPT4_RESERVED0_S 27 +/* EFUSE_USB_FORCE_NOPERSIST : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Force nopersist to 1.*/ +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x1 +#define EFUSE_USB_FORCE_NOPERSIST_S 26 +/* EFUSE_USB_EXT_PHY_ENABLE : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: Set this bit to enable external PHY.*/ #define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) #define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(25)) #define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 #define EFUSE_USB_EXT_PHY_ENABLE_S 25 -/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Set this bit to exchange D+ and D- pins.*/ #define EFUSE_USB_EXCHG_PINS (BIT(24)) #define EFUSE_USB_EXCHG_PINS_M (BIT(24)) #define EFUSE_USB_EXCHG_PINS_V 0x1 #define EFUSE_USB_EXCHG_PINS_S 24 -/* EFUSE_USB_DREFL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_USB_DREFL : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ +/*description: Controls single-end input threshold vrefl 0.8 V to 1.04 V with + step of 80 mV stored in eFuse.*/ #define EFUSE_USB_DREFL 0x00000003 #define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) #define EFUSE_USB_DREFL_V 0x3 #define EFUSE_USB_DREFL_S 22 -/* EFUSE_USB_DREFH : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_USB_DREFH : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: Controls single-end input threshold vrefh 1.76 V to 2 V with + step of 80 mV stored in eFuse.*/ #define EFUSE_USB_DREFH 0x00000003 #define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) #define EFUSE_USB_DREFH_V 0x3 #define EFUSE_USB_DREFH_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: Set this bit to disable flash encrypt function (except in SPI/HSPI/Legacy_SPI + boot mode).*/ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(19)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 -/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ #define EFUSE_HARD_DIS_JTAG (BIT(18)) #define EFUSE_HARD_DIS_JTAG_M (BIT(18)) #define EFUSE_HARD_DIS_JTAG_V 0x1 #define EFUSE_HARD_DIS_JTAG_S 18 -/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Set this bit to disable JTAG in the soft way. JTAG can be enabled + in HMAC module.*/ #define EFUSE_SOFT_DIS_JTAG (BIT(17)) #define EFUSE_SOFT_DIS_JTAG_M (BIT(17)) #define EFUSE_SOFT_DIS_JTAG_V 0x1 #define EFUSE_SOFT_DIS_JTAG_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_EFUSE_ATE_WR : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit to disable programming eFuse through ATE mode.*/ #define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) #define EFUSE_DIS_EFUSE_ATE_WR_M (BIT(16)) #define EFUSE_DIS_EFUSE_ATE_WR_V 0x1 #define EFUSE_DIS_EFUSE_ATE_WR_S 16 -/* EFUSE_DIS_SDIO_ACCESS : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DIS_SDIO_ACCESS (BIT(15)) -#define EFUSE_DIS_SDIO_ACCESS_M (BIT(15)) -#define EFUSE_DIS_SDIO_ACCESS_V 0x1 -#define EFUSE_DIS_SDIO_ACCESS_S 15 -/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_BOOT_REMAP : R/W ;bitpos:[15] ;default: 1'h0 ; */ +/*description: Set this bit to disable boot remap from RAM to ROM.*/ +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_V 0x1 +#define EFUSE_DIS_BOOT_REMAP_S 15 +/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'h0 ; */ +/*description: Set this bit to disable CAN function.*/ #define EFUSE_DIS_CAN (BIT(14)) #define EFUSE_DIS_CAN_M (BIT(14)) #define EFUSE_DIS_CAN_V 0x1 #define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: Set this bit to disable USB function.*/ #define EFUSE_DIS_USB (BIT(13)) #define EFUSE_DIS_USB_M (BIT(13)) #define EFUSE_DIS_USB_V 0x1 #define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_BT : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DIS_BT (BIT(12)) -#define EFUSE_DIS_BT_M (BIT(12)) -#define EFUSE_DIS_BT_V 0x1 -#define EFUSE_DIS_BT_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to disable the function that forces chip into download mode.*/ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: Set this bit to disable Dcache in download mode ( boot_mode[3:0] + is 0 1 2 3 6 7).*/ #define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 #define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: Set this bit to disable Icache in download mode (boot_mode[3:0] + is 0 1 2 3 6 7).*/ #define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 #define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to disable Dcache.*/ #define EFUSE_DIS_DCACHE (BIT(9)) #define EFUSE_DIS_DCACHE_M (BIT(9)) #define EFUSE_DIS_DCACHE_V 0x1 #define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: Set this bit to disable Icache.*/ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: Set this bit to disable boot from RTC RAM.*/ #define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 #define EFUSE_DIS_RTC_RAM_BOOT_S 7 /* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: */ +/*description: Set this bit to disable reading from BlOCK4-10.*/ #define EFUSE_RD_DIS 0x0000007F #define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) #define EFUSE_RD_DIS_V 0x7F #define EFUSE_RD_DIS_S 0 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x008) -/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: Purpose of Key1. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_1 0x0000000F #define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) #define EFUSE_KEY_PURPOSE_1_V 0xF #define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: Purpose of Key0. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_0 0x0000000F #define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) #define EFUSE_KEY_PURPOSE_0_V 0xF #define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: Set this bit to enable revoking third secure boot key.*/ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: Set this bit to enable revoking second secure boot key.*/ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to enable revoking first secure boot key.*/ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'b0 ; */ -/*description: */ +/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable*/ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 #define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) -#define EFUSE_WDT_DELAY_SEL_V 0x3 -#define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_SDIO_DCAP : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DCAP 0x00000003 -#define EFUSE_SDIO_DCAP_M ((EFUSE_SDIO_DCAP_V)<<(EFUSE_SDIO_DCAP_S)) -#define EFUSE_SDIO_DCAP_V 0x3 -#define EFUSE_SDIO_DCAP_S 14 -/* EFUSE_SDIO_INIT : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_INIT 0x00000003 -#define EFUSE_SDIO_INIT_M ((EFUSE_SDIO_INIT_V)<<(EFUSE_SDIO_INIT_S)) -#define EFUSE_SDIO_INIT_V 0x3 -#define EFUSE_SDIO_INIT_S 12 -/* EFUSE_SDIO_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DCURLIM 0x00000007 -#define EFUSE_SDIO_DCURLIM_M ((EFUSE_SDIO_DCURLIM_V)<<(EFUSE_SDIO_DCURLIM_S)) -#define EFUSE_SDIO_DCURLIM_V 0x7 -#define EFUSE_SDIO_DCURLIM_S 9 -/* EFUSE_SDIO_ENCURLIM : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_ENCURLIM (BIT(8)) -#define EFUSE_SDIO_ENCURLIM_M (BIT(8)) -#define EFUSE_SDIO_ENCURLIM_V 0x1 -#define EFUSE_SDIO_ENCURLIM_S 8 -/* EFUSE_SDIO_EN_INIT : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_EN_INIT (BIT(7)) -#define EFUSE_SDIO_EN_INIT_M (BIT(7)) -#define EFUSE_SDIO_EN_INIT_V 0x1 -#define EFUSE_SDIO_EN_INIT_S 7 -/* EFUSE_SDIO_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_FORCE (BIT(6)) -#define EFUSE_SDIO_FORCE_M (BIT(6)) -#define EFUSE_SDIO_FORCE_V 0x1 -#define EFUSE_SDIO_FORCE_S 6 -/* EFUSE_SDIO_TIEH : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_TIEH (BIT(5)) -#define EFUSE_SDIO_TIEH_M (BIT(5)) -#define EFUSE_SDIO_TIEH_V 0x1 -#define EFUSE_SDIO_TIEH_S 5 -/* EFUSE_SDIO_XPD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_XPD (BIT(4)) -#define EFUSE_SDIO_XPD_M (BIT(4)) -#define EFUSE_SDIO_XPD_V 0x1 -#define EFUSE_SDIO_XPD_S 4 -/* EFUSE_SDIO_DREFL : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFL 0x00000003 -#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) -#define EFUSE_SDIO_DREFL_V 0x3 -#define EFUSE_SDIO_DREFL_S 2 -/* EFUSE_SDIO_DREFM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFM 0x00000003 -#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) -#define EFUSE_SDIO_DREFM_V 0x3 -#define EFUSE_SDIO_DREFM_S 0 +/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: Selects RTC watchdog timeout threshold.*/ +#define EFUSE_WAT_DELAY_SEL 0x00000003 +#define EFUSE_WAT_DELAY_SEL_M ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S)) +#define EFUSE_WAT_DELAY_SEL_V 0x3 +#define EFUSE_WAT_DELAY_SEL_S 16 +/* EFUSE_VDD_SPI_DCAP : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: Prevents SPI regulator from overshoot.*/ +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) +#define EFUSE_VDD_SPI_DCAP_V 0x3 +#define EFUSE_VDD_SPI_DCAP_S 14 +/* EFUSE_VDD_SPI_INIT : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: Adds resistor from LDO output to ground. 0: no resistance*/ +#define EFUSE_VDD_SPI_INIT 0x00000003 +#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) +#define EFUSE_VDD_SPI_INIT_V 0x3 +#define EFUSE_VDD_SPI_INIT_S 12 +/* EFUSE_VDD_SPI_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: Tunes the current limit threshold of SPI regulator when tieh=0 + about 800 mA/(8+d).*/ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) +#define EFUSE_VDD_SPI_DCURLIM_V 0x7 +#define EFUSE_VDD_SPI_DCURLIM_S 9 +/* EFUSE_VDD_SPI_ENCURLIM : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: Set SPI regulator to 1 to enable output current limit.*/ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 +#define EFUSE_VDD_SPI_ENCURLIM_S 8 +/* EFUSE_VDD_SPI_EN_INIT : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: Set SPI regulator to 0 to configure init[1:0]=0.*/ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_V 0x1 +#define EFUSE_VDD_SPI_EN_INIT_S 7 +/* EFUSE_VDD_SPI_FORCE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_V 0x1 +#define EFUSE_VDD_SPI_FORCE_S 6 +/* EFUSE_VDD_SPI_TIEH : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: SPI regulator output is short connected to VDD3P3_RTC_IO.*/ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_V 0x1 +#define EFUSE_VDD_SPI_TIEH_S 5 +/* EFUSE_VDD_SPI_XPD : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: SPI regulator power up signal.*/ +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (BIT(4)) +#define EFUSE_VDD_SPI_XPD_V 0x1 +#define EFUSE_VDD_SPI_XPD_S 4 +/* EFUSE_VDD_SPI_DREFL : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: SPI regulator low voltage reference.*/ +#define EFUSE_VDD_SPI_DREFL 0x00000003 +#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) +#define EFUSE_VDD_SPI_DREFL_V 0x3 +#define EFUSE_VDD_SPI_DREFL_S 2 +/* EFUSE_VDD_SPI_DREFM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI regulator medium voltage reference.*/ +#define EFUSE_VDD_SPI_DREFM 0x00000003 +#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) +#define EFUSE_VDD_SPI_DREFM_V 0x3 +#define EFUSE_VDD_SPI_DREFM_S 0 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0x00c) -/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: Configures flash waiting time after power-up in unit of ms. + When the value is 15 the waiting time is 30 ms.*/ #define EFUSE_FLASH_TPUW 0x0000000F #define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) #define EFUSE_FLASH_TPUW_V 0xF #define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_XTAL_FREQ : R/W ;bitpos:[27:22] ;default: 6'b0 ; */ -/*description: */ -#define EFUSE_XTAL_FREQ 0x0000003F -#define EFUSE_XTAL_FREQ_M ((EFUSE_XTAL_FREQ_V)<<(EFUSE_XTAL_FREQ_S)) -#define EFUSE_XTAL_FREQ_V 0x3F -#define EFUSE_XTAL_FREQ_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED1 0x0000003F +#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) +#define EFUSE_RPT4_RESERVED1_V 0x3F +#define EFUSE_RPT4_RESERVED1_S 22 +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: Set this bit to enable revoking aggressive secure boot.*/ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: Set this bit to enable secure boot.*/ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (BIT(20)) #define EFUSE_SECURE_BOOT_EN_V 0x1 #define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: Purpose of Key6. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_6 0x0000000F #define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) #define EFUSE_KEY_PURPOSE_6_V 0xF #define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: Purpose of Key5. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_5 0x0000000F #define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) #define EFUSE_KEY_PURPOSE_5_V 0xF #define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: Purpose of Key4. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_4 0x0000000F #define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) #define EFUSE_KEY_PURPOSE_4_V 0xF #define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: Purpose of Key3. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_3 0x0000000F #define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) #define EFUSE_KEY_PURPOSE_3_V 0xF #define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: Purpose of Key2. Refer to Table KEY_PURPOSE Values.*/ #define EFUSE_KEY_PURPOSE_2 0x0000000F #define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) #define EFUSE_KEY_PURPOSE_2_V 0xF #define EFUSE_KEY_PURPOSE_2_S 0 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010) -/* EFUSE_RESERVE : R/W ;bitpos:[31:8] ;default: 24'h0 ; */ -/*description: */ -#define EFUSE_RESERVE 0x00FFFFFF -#define EFUSE_RESERVE_M ((EFUSE_RESERVE_V)<<(EFUSE_RESERVE_S)) -#define EFUSE_RESERVE_V 0xFFFFFF -#define EFUSE_RESERVE_S 8 -/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[31:27] ;default: 5'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED2 0x0000001F +#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) +#define EFUSE_RPT4_RESERVED2_V 0x1F +#define EFUSE_RPT4_RESERVED2_S 27 +/* EFUSE_SECURE_VERSION : R/W ;bitpos:[26:11] ;default: 16'h0 ; */ +/*description: IDF secure version.*/ +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) +#define EFUSE_SECURE_VERSION_V 0xFFFF +#define EFUSE_SECURE_VERSION_S 11 +/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/ +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_V 0x1 +#define EFUSE_FORCE_SEND_RESUME_S 10 +/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The type of the interfaced flash. 0: four data lines 1: eight data lines.*/ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (BIT(9)) +#define EFUSE_FLASH_TYPE_V 0x1 +#define EFUSE_FLASH_TYPE_S 9 +/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU*/ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_V 0x1 +#define EFUSE_PIN_POWER_SELECTION_S 8 +/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The type of UART print control.00: Forces to print.01: Controlled + by GPIO46 print at low level.10: Controlled by GPIO46 print at high level.11: Forces to disable print.*/ #define EFUSE_UART_PRINT_CONTROL 0x00000003 #define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) #define EFUSE_UART_PRINT_CONTROL_V 0x3 #define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: Set this bit to enable security download mode.*/ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: Set this bit to disable download through USB.*/ #define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 #define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_DIS_TINY_BASIC : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DIS_TINY_BASIC (BIT(3)) -#define EFUSE_DIS_TINY_BASIC_M (BIT(3)) -#define EFUSE_DIS_TINY_BASIC_V 0x1 -#define EFUSE_DIS_TINY_BASIC_S 3 -/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_RPT4_RESERVED3 : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: Set this bit to disable tiny basic console in ROM.*/ +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (BIT(3)) +#define EFUSE_RPT4_RESERVED3_V 0x1 +#define EFUSE_RPT4_RESERVED3_S 3 +/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Selectes UART print channel. 0: UART0*/ #define EFUSE_UART_PRINT_CHANNEL (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_V 0x1 #define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/ #define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 #define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 #define EFUSE_DIS_DOWNLOAD_MODE_S 0 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x014) -/* EFUSE_RS_DATA_23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define EFUSE_RS_DATA_23 0x000000FF -#define EFUSE_RS_DATA_23_M ((EFUSE_RS_DATA_23_V)<<(EFUSE_RS_DATA_23_S)) -#define EFUSE_RS_DATA_23_V 0xFF -#define EFUSE_RS_DATA_23_S 24 -/* EFUSE_CHIP_VERSION : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VERSION 0x00FFFFFF -#define EFUSE_CHIP_VERSION_M ((EFUSE_CHIP_VERSION_V)<<(EFUSE_CHIP_VERSION_S)) -#define EFUSE_CHIP_VERSION_V 0xFFFFFF -#define EFUSE_CHIP_VERSION_S 0 +/* EFUSE_RPT1_RESERVED0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT1_RESERVED0 0x000000FF +#define EFUSE_RPT1_RESERVED0_M ((EFUSE_RPT1_RESERVED0_V)<<(EFUSE_RPT1_RESERVED0_S)) +#define EFUSE_RPT1_RESERVED0_V 0xFF +#define EFUSE_RPT1_RESERVED0_S 24 +/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved (used for four backups method).*/ +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) +#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x018) -/* EFUSE_RS_DATA_24_27 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_RS_DATA_24_27 0xFFFFFFFF -#define EFUSE_RS_DATA_24_27_M ((EFUSE_RS_DATA_24_27_V)<<(EFUSE_RS_DATA_24_27_S)) -#define EFUSE_RS_DATA_24_27_V 0xFFFFFFFF -#define EFUSE_RS_DATA_24_27_S 0 +/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the sixth 32-bit data to be programmed.*/ +#define EFUSE_PGM_DATA_6 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_M ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S)) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_S 0 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x01c) -/* EFUSE_RS_DATA_28_31 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_RS_DATA_28_31 0xFFFFFFFF -#define EFUSE_RS_DATA_28_31_M ((EFUSE_RS_DATA_28_31_V)<<(EFUSE_RS_DATA_28_31_S)) -#define EFUSE_RS_DATA_28_31_V 0xFFFFFFFF -#define EFUSE_RS_DATA_28_31_S 0 +/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The value of pgm data 7.*/ +#define EFUSE_PGM_DATA_7 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_M ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S)) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_S 0 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x020) -/* EFUSE_RS_DATA_32_35 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_RS_DATA_32_35 0xFFFFFFFF -#define EFUSE_RS_DATA_32_35_M ((EFUSE_RS_DATA_32_35_V)<<(EFUSE_RS_DATA_32_35_S)) -#define EFUSE_RS_DATA_32_35_V 0xFFFFFFFF -#define EFUSE_RS_DATA_32_35_S 0 +/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the 0th 32-bit RS code to be programmed.*/ +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_M ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S)) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_S 0 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x024) -/* EFUSE_RS_DATA_36_39 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_RS_DATA_36_39 0xFFFFFFFF -#define EFUSE_RS_DATA_36_39_M ((EFUSE_RS_DATA_36_39_V)<<(EFUSE_RS_DATA_36_39_S)) -#define EFUSE_RS_DATA_36_39_V 0xFFFFFFFF -#define EFUSE_RS_DATA_36_39_S 0 +/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the first 32-bit RS code to be programmed.*/ +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_M ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S)) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_S 0 #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x028) -/* EFUSE_RS_DATA_40_43 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_RS_DATA_40_43 0xFFFFFFFF -#define EFUSE_RS_DATA_40_43_M ((EFUSE_RS_DATA_40_43_V)<<(EFUSE_RS_DATA_40_43_S)) -#define EFUSE_RS_DATA_40_43_V 0xFFFFFFFF -#define EFUSE_RS_DATA_40_43_S 0 +/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The content of the second 32-bit RS code to be programmed.*/ +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_M ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S)) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_S 0 #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x02c) -/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ +/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The value of WR_DIS.*/ #define EFUSE_WR_DIS 0xFFFFFFFF #define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) #define EFUSE_WR_DIS_V 0xFFFFFFFF #define EFUSE_WR_DIS_S 0 #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x030) -/* EFUSE_SDIO_DREFH : RO ;bitpos:[31:30] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFH 0x00000003 -#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) -#define EFUSE_SDIO_DREFH_V 0x3 -#define EFUSE_SDIO_DREFH_S 30 -/* EFUSE_SDIO_MODECURLIM : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_MODECURLIM (BIT(29)) -#define EFUSE_SDIO_MODECURLIM_M (BIT(29)) -#define EFUSE_SDIO_MODECURLIM_V 0x1 -#define EFUSE_SDIO_MODECURLIM_S 29 -/* EFUSE_USB_DRES : RO ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_USB_DRES 0x00000003 -#define EFUSE_USB_DRES_M ((EFUSE_USB_DRES_V)<<(EFUSE_USB_DRES_S)) -#define EFUSE_USB_DRES_V 0x3 -#define EFUSE_USB_DRES_S 27 -/* EFUSE_USB_FORCE_B : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_USB_FORCE_B (BIT(26)) -#define EFUSE_USB_FORCE_B_M (BIT(26)) -#define EFUSE_USB_FORCE_B_V 0x1 -#define EFUSE_USB_FORCE_B_S 26 -/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_VDD_SPI_DREFH : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: The value of VDD_SPI_DREFH.*/ +#define EFUSE_VDD_SPI_DREFH 0x00000003 +#define EFUSE_VDD_SPI_DREFH_M ((EFUSE_VDD_SPI_DREFH_V)<<(EFUSE_VDD_SPI_DREFH_S)) +#define EFUSE_VDD_SPI_DREFH_V 0x3 +#define EFUSE_VDD_SPI_DREFH_S 30 +/* EFUSE_VDD_SPI_MODECURLIM : RO ;bitpos:[29] ;default: 1'h0 ; */ +/*description: The value of VDD_SPI_MODECURLIM.*/ +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x1 +#define EFUSE_VDD_SPI_MODECURLIM_S 29 +/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[28:27] ;default: 2'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED0 0x00000003 +#define EFUSE_RPT4_RESERVED0_M ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S)) +#define EFUSE_RPT4_RESERVED0_V 0x3 +#define EFUSE_RPT4_RESERVED0_S 27 +/* EFUSE_USB_FORCE_NOPERSIST : RO ;bitpos:[26] ;default: 1'h0 ; */ +/*description: The value of usb_force_nopersist*/ +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x1 +#define EFUSE_USB_FORCE_NOPERSIST_S 26 +/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: The value of EXT_PHY_ENABLE.*/ #define EFUSE_USB_EXT_PHY_ENABLE (BIT(25)) #define EFUSE_USB_EXT_PHY_ENABLE_M (BIT(25)) #define EFUSE_USB_EXT_PHY_ENABLE_V 0x1 #define EFUSE_USB_EXT_PHY_ENABLE_S 25 -/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[24] ;default: 1'h0 ; */ +/*description: Reserved.*/ #define EFUSE_USB_EXCHG_PINS (BIT(24)) #define EFUSE_USB_EXCHG_PINS_M (BIT(24)) #define EFUSE_USB_EXCHG_PINS_V 0x1 #define EFUSE_USB_EXCHG_PINS_S 24 -/* EFUSE_USB_DREFL : RO ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_USB_DREFL : RO ;bitpos:[23:22] ;default: 2'h0 ; */ +/*description: The value of USB_DREFL.*/ #define EFUSE_USB_DREFL 0x00000003 #define EFUSE_USB_DREFL_M ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S)) #define EFUSE_USB_DREFL_V 0x3 #define EFUSE_USB_DREFL_S 22 -/* EFUSE_USB_DREFH : RO ;bitpos:[21:20] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_USB_DREFH : RO ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: The value of USB_DREFH.*/ #define EFUSE_USB_DREFH 0x00000003 #define EFUSE_USB_DREFH_M ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S)) #define EFUSE_USB_DREFH_V 0x3 #define EFUSE_USB_DREFH_S 20 -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[19] ;default: 1'h0 ; */ +/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(19)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 -/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[18] ;default: 1'h0 ; */ +/*description: The value of HARD_DIS_JTAG.*/ #define EFUSE_HARD_DIS_JTAG (BIT(18)) #define EFUSE_HARD_DIS_JTAG_M (BIT(18)) #define EFUSE_HARD_DIS_JTAG_V 0x1 #define EFUSE_HARD_DIS_JTAG_S 18 -/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[17] ;default: 1'h0 ; */ +/*description: The value of SOFT_DIS_JTAG.*/ #define EFUSE_SOFT_DIS_JTAG (BIT(17)) #define EFUSE_SOFT_DIS_JTAG_M (BIT(17)) #define EFUSE_SOFT_DIS_JTAG_V 0x1 #define EFUSE_SOFT_DIS_JTAG_S 17 -/* EFUSE_DIS_EFUSE_ATE_WR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_EFUSE_ATE_WR : RO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: The value of DIS_EFUSE_ATE_WR.*/ #define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) #define EFUSE_DIS_EFUSE_ATE_WR_M (BIT(16)) #define EFUSE_DIS_EFUSE_ATE_WR_V 0x1 #define EFUSE_DIS_EFUSE_ATE_WR_S 16 -/* EFUSE_DIS_SDIO_ACCESS : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DIS_SDIO_ACCESS (BIT(15)) -#define EFUSE_DIS_SDIO_ACCESS_M (BIT(15)) -#define EFUSE_DIS_SDIO_ACCESS_V 0x1 -#define EFUSE_DIS_SDIO_ACCESS_S 15 -/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_BOOT_REMAP : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: The value of DIS_BOOT_REMAP.*/ +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_V 0x1 +#define EFUSE_DIS_BOOT_REMAP_S 15 +/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'h0 ; */ +/*description: The value of DIS_CAN.*/ #define EFUSE_DIS_CAN (BIT(14)) #define EFUSE_DIS_CAN_M (BIT(14)) #define EFUSE_DIS_CAN_V 0x1 #define EFUSE_DIS_CAN_S 14 -/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'h0 ; */ +/*description: The value of DIS_USB.*/ #define EFUSE_DIS_USB (BIT(13)) #define EFUSE_DIS_USB_M (BIT(13)) #define EFUSE_DIS_USB_V 0x1 #define EFUSE_DIS_USB_S 13 -/* EFUSE_DIS_BT : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DIS_BT (BIT(12)) -#define EFUSE_DIS_BT_M (BIT(12)) -#define EFUSE_DIS_BT_V 0x1 -#define EFUSE_DIS_BT_S 12 -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'h0 ; */ +/*description: The value of DIS_FORCE_DOWNLOAD.*/ +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x1 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 +/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: The value of DIS_DOWNLOAD_DCACHE.*/ #define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_M (BIT(11)) #define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x1 #define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: The value of DIS_DOWNLOAD_ICACHE.*/ #define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_M (BIT(10)) #define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x1 #define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 -/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The value of DIS_DCACHE.*/ #define EFUSE_DIS_DCACHE (BIT(9)) #define EFUSE_DIS_DCACHE_M (BIT(9)) #define EFUSE_DIS_DCACHE_V 0x1 #define EFUSE_DIS_DCACHE_S 9 -/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The value of DIS_ICACHE.*/ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (BIT(8)) #define EFUSE_DIS_ICACHE_V 0x1 #define EFUSE_DIS_ICACHE_S 8 -/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The value of DIS_RTC_RAM_BOOT.*/ #define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7)) #define EFUSE_DIS_RTC_RAM_BOOT_V 0x1 #define EFUSE_DIS_RTC_RAM_BOOT_S 7 /* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: */ +/*description: The value of RD_DIS.*/ #define EFUSE_RD_DIS 0x0000007F #define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) #define EFUSE_RD_DIS_V 0x7F #define EFUSE_RD_DIS_S 0 #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x034) -/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_1.*/ #define EFUSE_KEY_PURPOSE_1 0x0000000F #define EFUSE_KEY_PURPOSE_1_M ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S)) #define EFUSE_KEY_PURPOSE_1_V 0xF #define EFUSE_KEY_PURPOSE_1_S 28 -/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_0.*/ #define EFUSE_KEY_PURPOSE_0 0x0000000F #define EFUSE_KEY_PURPOSE_0_M ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S)) #define EFUSE_KEY_PURPOSE_0_V 0xF #define EFUSE_KEY_PURPOSE_0_S 24 -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'h0 ; */ +/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'h0 ; */ +/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x1 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'b0 ; */ -/*description: */ +/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: The value of SPI_BOOT_CRYPT_CNT.*/ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 #define EFUSE_SPI_BOOT_CRYPT_CNT_M ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S)) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x7 #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 -/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The value of WDT_DELAY_SEL.*/ #define EFUSE_WDT_DELAY_SEL 0x00000003 #define EFUSE_WDT_DELAY_SEL_M ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S)) #define EFUSE_WDT_DELAY_SEL_V 0x3 #define EFUSE_WDT_DELAY_SEL_S 16 -/* EFUSE_EUFSE_SDIO_DCAP : RO ;bitpos:[15:14] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_EUFSE_SDIO_DCAP 0x00000003 -#define EFUSE_EUFSE_SDIO_DCAP_M ((EFUSE_EUFSE_SDIO_DCAP_V)<<(EFUSE_EUFSE_SDIO_DCAP_S)) -#define EFUSE_EUFSE_SDIO_DCAP_V 0x3 -#define EFUSE_EUFSE_SDIO_DCAP_S 14 -/* EFUSE_SDIO_INIT : RO ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_INIT 0x00000003 -#define EFUSE_SDIO_INIT_M ((EFUSE_SDIO_INIT_V)<<(EFUSE_SDIO_INIT_S)) -#define EFUSE_SDIO_INIT_V 0x3 -#define EFUSE_SDIO_INIT_S 12 -/* EFUSE_SDIO_DCURLIM : RO ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DCURLIM 0x00000007 -#define EFUSE_SDIO_DCURLIM_M ((EFUSE_SDIO_DCURLIM_V)<<(EFUSE_SDIO_DCURLIM_S)) -#define EFUSE_SDIO_DCURLIM_V 0x7 -#define EFUSE_SDIO_DCURLIM_S 9 -/* EFUSE_SDIO_ENCURLIM : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_ENCURLIM (BIT(8)) -#define EFUSE_SDIO_ENCURLIM_M (BIT(8)) -#define EFUSE_SDIO_ENCURLIM_V 0x1 -#define EFUSE_SDIO_ENCURLIM_S 8 -/* EFUSE_SDIO_EN_INIT : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_EN_INIT (BIT(7)) -#define EFUSE_SDIO_EN_INIT_M (BIT(7)) -#define EFUSE_SDIO_EN_INIT_V 0x1 -#define EFUSE_SDIO_EN_INIT_S 7 -/* EFUSE_SDIO_FORCE : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_FORCE (BIT(6)) -#define EFUSE_SDIO_FORCE_M (BIT(6)) -#define EFUSE_SDIO_FORCE_V 0x1 -#define EFUSE_SDIO_FORCE_S 6 -/* EFUSE_SDIO_TIEH : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_TIEH (BIT(5)) -#define EFUSE_SDIO_TIEH_M (BIT(5)) -#define EFUSE_SDIO_TIEH_V 0x1 -#define EFUSE_SDIO_TIEH_S 5 -/* EFUSE_SDIO_XPD : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_SDIO_XPD (BIT(4)) -#define EFUSE_SDIO_XPD_M (BIT(4)) -#define EFUSE_SDIO_XPD_V 0x1 -#define EFUSE_SDIO_XPD_S 4 -/* EFUSE_SDIO_DREFL : RO ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFL 0x00000003 -#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) -#define EFUSE_SDIO_DREFL_V 0x3 -#define EFUSE_SDIO_DREFL_S 2 -/* EFUSE_SDIO_DREFM : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_SDIO_DREFM 0x00000003 -#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) -#define EFUSE_SDIO_DREFM_V 0x3 -#define EFUSE_SDIO_DREFM_S 0 +/* EFUSE_VDD_SPI_DCAP : RO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: The value of REG_VDD_SPI_DCAP.*/ +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M ((EFUSE_VDD_SPI_DCAP_V)<<(EFUSE_VDD_SPI_DCAP_S)) +#define EFUSE_VDD_SPI_DCAP_V 0x3 +#define EFUSE_VDD_SPI_DCAP_S 14 +/* EFUSE_VDD_SPI_INIT : RO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: The value of VDD_SPI_INIT.*/ +#define EFUSE_VDD_SPI_INIT 0x00000003 +#define EFUSE_VDD_SPI_INIT_M ((EFUSE_VDD_SPI_INIT_V)<<(EFUSE_VDD_SPI_INIT_S)) +#define EFUSE_VDD_SPI_INIT_V 0x3 +#define EFUSE_VDD_SPI_INIT_S 12 +/* EFUSE_VDD_SPI_DCURLIM : RO ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: The value of VDD_SPI_DCURLIM.*/ +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_M ((EFUSE_VDD_SPI_DCURLIM_V)<<(EFUSE_VDD_SPI_DCURLIM_S)) +#define EFUSE_VDD_SPI_DCURLIM_V 0x7 +#define EFUSE_VDD_SPI_DCURLIM_S 9 +/* EFUSE_VDD_SPI_ENCURLIM : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The value of VDD_SPI_ENCURLIM.*/ +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x1 +#define EFUSE_VDD_SPI_ENCURLIM_S 8 +/* EFUSE_VDD_SPI_EN_INIT : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The value of VDD_SPI_EN_INIT.*/ +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_V 0x1 +#define EFUSE_VDD_SPI_EN_INIT_S 7 +/* EFUSE_VDD_SPI_FORCE : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The value of VDD_SPI_FORCE.*/ +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_V 0x1 +#define EFUSE_VDD_SPI_FORCE_S 6 +/* EFUSE_VDD_SPI_TIEH : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The value of VDD_SPI_TIEH.*/ +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_V 0x1 +#define EFUSE_VDD_SPI_TIEH_S 5 +/* EFUSE_VDD_SPI_XPD : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The value of VDD_SPI_XPD.*/ +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (BIT(4)) +#define EFUSE_VDD_SPI_XPD_V 0x1 +#define EFUSE_VDD_SPI_XPD_S 4 +/* EFUSE_VDD_SPI_DREFL : RO ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: The value of VDD_SPI_DREFL.*/ +#define EFUSE_VDD_SPI_DREFL 0x00000003 +#define EFUSE_VDD_SPI_DREFL_M ((EFUSE_VDD_SPI_DREFL_V)<<(EFUSE_VDD_SPI_DREFL_S)) +#define EFUSE_VDD_SPI_DREFL_V 0x3 +#define EFUSE_VDD_SPI_DREFL_S 2 +/* EFUSE_VDD_SPI_DREFM : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The value of VDD_SPI_DREFM.*/ +#define EFUSE_VDD_SPI_DREFM 0x00000003 +#define EFUSE_VDD_SPI_DREFM_M ((EFUSE_VDD_SPI_DREFM_V)<<(EFUSE_VDD_SPI_DREFM_S)) +#define EFUSE_VDD_SPI_DREFM_V 0x3 +#define EFUSE_VDD_SPI_DREFM_S 0 #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x038) -/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: The value of FLASH_TPUW.*/ #define EFUSE_FLASH_TPUW 0x0000000F #define EFUSE_FLASH_TPUW_M ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S)) #define EFUSE_FLASH_TPUW_V 0xF #define EFUSE_FLASH_TPUW_S 28 -/* EFUSE_XTAL_FREQ : RO ;bitpos:[27:22] ;default: 6'b0 ; */ -/*description: */ -#define EFUSE_XTAL_FREQ 0x0000003F -#define EFUSE_XTAL_FREQ_M ((EFUSE_XTAL_FREQ_V)<<(EFUSE_XTAL_FREQ_S)) -#define EFUSE_XTAL_FREQ_V 0x3F -#define EFUSE_XTAL_FREQ_S 22 -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[27:22] ;default: 6'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED1 0x0000003F +#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S)) +#define EFUSE_RPT4_RESERVED1_V 0x3F +#define EFUSE_RPT4_RESERVED1_S 22 +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'h0 ; */ +/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x1 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'h0 ; */ +/*description: The value of SECURE_BOOT_EN.*/ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (BIT(20)) #define EFUSE_SECURE_BOOT_EN_V 0x1 #define EFUSE_SECURE_BOOT_EN_S 20 -/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_6.*/ #define EFUSE_KEY_PURPOSE_6 0x0000000F #define EFUSE_KEY_PURPOSE_6_M ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S)) #define EFUSE_KEY_PURPOSE_6_V 0xF #define EFUSE_KEY_PURPOSE_6_S 16 -/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_5.*/ #define EFUSE_KEY_PURPOSE_5 0x0000000F #define EFUSE_KEY_PURPOSE_5_M ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S)) #define EFUSE_KEY_PURPOSE_5_V 0xF #define EFUSE_KEY_PURPOSE_5_S 12 -/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_4.*/ #define EFUSE_KEY_PURPOSE_4 0x0000000F #define EFUSE_KEY_PURPOSE_4_M ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S)) #define EFUSE_KEY_PURPOSE_4_V 0xF #define EFUSE_KEY_PURPOSE_4_S 8 -/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_3.*/ #define EFUSE_KEY_PURPOSE_3 0x0000000F #define EFUSE_KEY_PURPOSE_3_M ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S)) #define EFUSE_KEY_PURPOSE_3_V 0xF #define EFUSE_KEY_PURPOSE_3_S 4 -/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ +/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: The value of KEY_PURPOSE_2.*/ #define EFUSE_KEY_PURPOSE_2 0x0000000F #define EFUSE_KEY_PURPOSE_2_M ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S)) #define EFUSE_KEY_PURPOSE_2_V 0xF #define EFUSE_KEY_PURPOSE_2_S 0 #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03c) -/* EFUSE_RESERVE : RO ;bitpos:[31:8] ;default: 24'h0 ; */ -/*description: */ -#define EFUSE_RESERVE 0x00FFFFFF -#define EFUSE_RESERVE_M ((EFUSE_RESERVE_V)<<(EFUSE_RESERVE_S)) -#define EFUSE_RESERVE_V 0xFFFFFF -#define EFUSE_RESERVE_S 8 -/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ +/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[31:27] ;default: 5'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED2 0x0000001F +#define EFUSE_RPT4_RESERVED2_M ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S)) +#define EFUSE_RPT4_RESERVED2_V 0x1F +#define EFUSE_RPT4_RESERVED2_S 27 +/* EFUSE_SECURE_VERSION : RO ;bitpos:[26:11] ;default: 16'h0 ; */ +/*description: The value of SECURE_VERSION.*/ +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S)) +#define EFUSE_SECURE_VERSION_V 0xFFFF +#define EFUSE_SECURE_VERSION_S 11 +/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: The value of FORCE_SEND_RESUME.*/ +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_V 0x1 +#define EFUSE_FORCE_SEND_RESUME_S 10 +/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The value of FLASH_TYPE.*/ +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (BIT(9)) +#define EFUSE_FLASH_TYPE_V 0x1 +#define EFUSE_FLASH_TYPE_S 9 +/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The value of PIN_POWER_SELECTION.*/ +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_V 0x1 +#define EFUSE_PIN_POWER_SELECTION_S 8 +/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The value of UART_PRINT_CONTROL.*/ #define EFUSE_UART_PRINT_CONTROL 0x00000003 #define EFUSE_UART_PRINT_CONTROL_M ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S)) #define EFUSE_UART_PRINT_CONTROL_V 0x3 #define EFUSE_UART_PRINT_CONTROL_S 6 -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x1 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The value of DIS_USB_DOWNLOAD_MODE.*/ #define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) #define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x1 #define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_DIS_TINY_BASIC : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_DIS_TINY_BASIC (BIT(3)) -#define EFUSE_DIS_TINY_BASIC_M (BIT(3)) -#define EFUSE_DIS_TINY_BASIC_V 0x1 -#define EFUSE_DIS_TINY_BASIC_S 3 -/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The value of RPT4_RESERVED4.*/ +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (BIT(3)) +#define EFUSE_RPT4_RESERVED3_V 0x1 +#define EFUSE_RPT4_RESERVED3_S 3 +/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The value of UART_PRINT_CHANNEL.*/ #define EFUSE_UART_PRINT_CHANNEL (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_M (BIT(2)) #define EFUSE_UART_PRINT_CHANNEL_V 0x1 #define EFUSE_UART_PRINT_CHANNEL_S 2 -/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The value of DIS_LEGACY_SPI_BOOT.*/ #define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_M (BIT(1)) #define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x1 #define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 -/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The value of DIS_DOWNLOAD_MODE.*/ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x1 #define EFUSE_DIS_DOWNLOAD_MODE_S 0 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x040) -/* EFUSE_CHIP_VERSION : RO ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VERSION 0x00FFFFFF -#define EFUSE_CHIP_VERSION_M ((EFUSE_CHIP_VERSION_V)<<(EFUSE_CHIP_VERSION_S)) -#define EFUSE_CHIP_VERSION_V 0xFFFFFF -#define EFUSE_CHIP_VERSION_S 0 +/* EFUSE_RPT1_RESERVED0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT1_RESERVED0 0x000000FF +#define EFUSE_RPT1_RESERVED0_M ((EFUSE_RPT1_RESERVED0_V)<<(EFUSE_RPT1_RESERVED0_S)) +#define EFUSE_RPT1_RESERVED0_V 0xFF +#define EFUSE_RPT1_RESERVED0_S 24 +/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved ( four backup method ).*/ +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S)) +#define EFUSE_RPT4_RESERVED4_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 -#define EFUSE_RD_MAC_SPI_8M_0_REG (DR_REG_EFUSE_BASE + 0x044) +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x044) /* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the low 32 bits of MAC address.*/ #define EFUSE_MAC_0 0xFFFFFFFF #define EFUSE_MAC_0_M ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S)) #define EFUSE_MAC_0_V 0xFFFFFFFF #define EFUSE_MAC_0_S 0 -#define EFUSE_RD_MAC_SPI_8M_1_REG (DR_REG_EFUSE_BASE + 0x048) +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x048) /* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: */ +/*description: Stores the zeroth part of SPI_PAD_CONF.*/ #define EFUSE_SPI_PAD_CONF_0 0x0000FFFF #define EFUSE_SPI_PAD_CONF_0_M ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S)) #define EFUSE_SPI_PAD_CONF_0_V 0xFFFF #define EFUSE_SPI_PAD_CONF_0_S 16 /* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ +/*description: Stores the high 16 bits of MAC address.*/ #define EFUSE_MAC_1 0x0000FFFF #define EFUSE_MAC_1_M ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S)) #define EFUSE_MAC_1_V 0xFFFF #define EFUSE_MAC_1_S 0 -#define EFUSE_RD_MAC_SPI_8M_2_REG (DR_REG_EFUSE_BASE + 0x04c) -/* EFUSE_CLK8M_FREQ : RO ;bitpos:[31:20] ;default: 12'h0 ; */ -/*description: */ -#define EFUSE_CLK8M_FREQ 0x00000FFF -#define EFUSE_CLK8M_FREQ_M ((EFUSE_CLK8M_FREQ_V)<<(EFUSE_CLK8M_FREQ_S)) -#define EFUSE_CLK8M_FREQ_V 0xFFF -#define EFUSE_CLK8M_FREQ_S 20 -/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define EFUSE_SPI_PAD_CONF_1 0x000FFFFF +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x04c) +/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first part of SPI_PAD_CONF.*/ +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_M ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S)) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFF +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF #define EFUSE_SPI_PAD_CONF_1_S 0 -#define EFUSE_RD_MAC_SPI_8M_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA_PART0_0 0xFFFFFFFF +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) +/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ +/*description: Stores the fist 14 bits of the zeroth part of system data.*/ +#define EFUSE_SYS_DATA_PART0_0 0x00003FFF #define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_0_S 0 +#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF +#define EFUSE_SYS_DATA_PART0_0_S 18 +/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ +/*description: Stores the second part of SPI_PAD_CONF.*/ +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S)) +#define EFUSE_SPI_PAD_CONF_2_V 0x3FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 -#define EFUSE_RD_MAC_SPI_8M_4_REG (DR_REG_EFUSE_BASE + 0x054) +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x054) /* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fist 32 bits of the zeroth part of system data.*/ #define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_1_M ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S)) #define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_1_S 0 -#define EFUSE_RD_MAC_SPI_8M_5_REG (DR_REG_EFUSE_BASE + 0x058) +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x058) /* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of the zeroth part of system data.*/ #define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_2_M ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S)) #define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF #define EFUSE_SYS_DATA_PART0_2_S 0 -#define EFUSE_RD_SYS_DATA0_REG (DR_REG_EFUSE_BASE + 0x05c) -/* EFUSE_SYS_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA0 0xFFFFFFFF -#define EFUSE_SYS_DATA0_M ((EFUSE_SYS_DATA0_V)<<(EFUSE_SYS_DATA0_S)) -#define EFUSE_SYS_DATA0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA0_S 0 +#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x05c) +/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the zeroth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_M ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S)) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_S 0 -#define EFUSE_RD_SYS_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) -/* EFUSE_SYS_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA1 0xFFFFFFFF -#define EFUSE_SYS_DATA1_M ((EFUSE_SYS_DATA1_V)<<(EFUSE_SYS_DATA1_S)) -#define EFUSE_SYS_DATA1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA1_S 0 +#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x060) +/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the first 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_M ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S)) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_S 0 -#define EFUSE_RD_SYS_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) -/* EFUSE_SYS_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA2 0xFFFFFFFF -#define EFUSE_SYS_DATA2_M ((EFUSE_SYS_DATA2_V)<<(EFUSE_SYS_DATA2_S)) -#define EFUSE_SYS_DATA2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA2_S 0 +#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x064) +/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the second 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_M ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S)) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_S 0 -#define EFUSE_RD_SYS_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) -/* EFUSE_SYS_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA3 0xFFFFFFFF -#define EFUSE_SYS_DATA3_M ((EFUSE_SYS_DATA3_V)<<(EFUSE_SYS_DATA3_S)) -#define EFUSE_SYS_DATA3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA3_S 0 +#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x068) +/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the third 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_M ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S)) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_S 0 -#define EFUSE_RD_SYS_DATA4_REG (DR_REG_EFUSE_BASE + 0x06c) -/* EFUSE_SYS_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA4 0xFFFFFFFF -#define EFUSE_SYS_DATA4_M ((EFUSE_SYS_DATA4_V)<<(EFUSE_SYS_DATA4_S)) -#define EFUSE_SYS_DATA4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA4_S 0 +#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x06c) +/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fourth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_M ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S)) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_S 0 -#define EFUSE_RD_SYS_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) -/* EFUSE_SYS_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA5 0xFFFFFFFF -#define EFUSE_SYS_DATA5_M ((EFUSE_SYS_DATA5_V)<<(EFUSE_SYS_DATA5_S)) -#define EFUSE_SYS_DATA5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA5_S 0 +#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x070) +/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the fifth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_M ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S)) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_S 0 -#define EFUSE_RD_SYS_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) -/* EFUSE_SYS_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA6 0xFFFFFFFF -#define EFUSE_SYS_DATA6_M ((EFUSE_SYS_DATA6_V)<<(EFUSE_SYS_DATA6_S)) -#define EFUSE_SYS_DATA6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA6_S 0 +#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x074) +/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the sixth 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_M ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S)) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_S 0 -#define EFUSE_RD_SYS_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) -/* EFUSE_SYS_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_SYS_DATA7 0xFFFFFFFF -#define EFUSE_SYS_DATA7_M ((EFUSE_SYS_DATA7_V)<<(EFUSE_SYS_DATA7_S)) -#define EFUSE_SYS_DATA7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA7_S 0 +#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x078) +/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the seventh 32 bits of the first part of system data.*/ +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_M ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S)) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_S 0 #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x07c) /* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA0 0xFFFFFFFF #define EFUSE_USR_DATA0_M ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S)) #define EFUSE_USR_DATA0_V 0xFFFFFFFF @@ -919,7 +982,7 @@ extern "C" { #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x080) /* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA1 0xFFFFFFFF #define EFUSE_USR_DATA1_M ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S)) #define EFUSE_USR_DATA1_V 0xFFFFFFFF @@ -927,7 +990,7 @@ extern "C" { #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x084) /* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA2 0xFFFFFFFF #define EFUSE_USR_DATA2_M ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S)) #define EFUSE_USR_DATA2_V 0xFFFFFFFF @@ -935,7 +998,7 @@ extern "C" { #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x088) /* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA3 0xFFFFFFFF #define EFUSE_USR_DATA3_M ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S)) #define EFUSE_USR_DATA3_V 0xFFFFFFFF @@ -943,7 +1006,7 @@ extern "C" { #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x08c) /* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA4 0xFFFFFFFF #define EFUSE_USR_DATA4_M ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S)) #define EFUSE_USR_DATA4_V 0xFFFFFFFF @@ -951,7 +1014,7 @@ extern "C" { #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x090) /* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA5 0xFFFFFFFF #define EFUSE_USR_DATA5_M ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S)) #define EFUSE_USR_DATA5_V 0xFFFFFFFF @@ -959,7 +1022,7 @@ extern "C" { #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x094) /* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA6 0xFFFFFFFF #define EFUSE_USR_DATA6_M ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S)) #define EFUSE_USR_DATA6_V 0xFFFFFFFF @@ -967,7 +1030,7 @@ extern "C" { #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x098) /* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of BLOCK3 (user).*/ #define EFUSE_USR_DATA7 0xFFFFFFFF #define EFUSE_USR_DATA7_M ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S)) #define EFUSE_USR_DATA7_V 0xFFFFFFFF @@ -975,7 +1038,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x09c) /* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA0 0xFFFFFFFF #define EFUSE_KEY0_DATA0_M ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S)) #define EFUSE_KEY0_DATA0_V 0xFFFFFFFF @@ -983,7 +1046,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0x0a0) /* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA1 0xFFFFFFFF #define EFUSE_KEY0_DATA1_M ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S)) #define EFUSE_KEY0_DATA1_V 0xFFFFFFFF @@ -991,7 +1054,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0x0a4) /* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA2 0xFFFFFFFF #define EFUSE_KEY0_DATA2_M ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S)) #define EFUSE_KEY0_DATA2_V 0xFFFFFFFF @@ -999,7 +1062,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0x0a8) /* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA3 0xFFFFFFFF #define EFUSE_KEY0_DATA3_M ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S)) #define EFUSE_KEY0_DATA3_V 0xFFFFFFFF @@ -1007,7 +1070,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0x0ac) /* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA4 0xFFFFFFFF #define EFUSE_KEY0_DATA4_M ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S)) #define EFUSE_KEY0_DATA4_V 0xFFFFFFFF @@ -1015,7 +1078,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0x0b0) /* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA5 0xFFFFFFFF #define EFUSE_KEY0_DATA5_M ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S)) #define EFUSE_KEY0_DATA5_V 0xFFFFFFFF @@ -1023,7 +1086,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0x0b4) /* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA6 0xFFFFFFFF #define EFUSE_KEY0_DATA6_M ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S)) #define EFUSE_KEY0_DATA6_V 0xFFFFFFFF @@ -1031,7 +1094,7 @@ extern "C" { #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0x0b8) /* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of KEY0.*/ #define EFUSE_KEY0_DATA7 0xFFFFFFFF #define EFUSE_KEY0_DATA7_M ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S)) #define EFUSE_KEY0_DATA7_V 0xFFFFFFFF @@ -1039,7 +1102,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0x0bc) /* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA0 0xFFFFFFFF #define EFUSE_KEY1_DATA0_M ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S)) #define EFUSE_KEY1_DATA0_V 0xFFFFFFFF @@ -1047,7 +1110,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0x0c0) /* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA1 0xFFFFFFFF #define EFUSE_KEY1_DATA1_M ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S)) #define EFUSE_KEY1_DATA1_V 0xFFFFFFFF @@ -1055,7 +1118,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0x0c4) /* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA2 0xFFFFFFFF #define EFUSE_KEY1_DATA2_M ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S)) #define EFUSE_KEY1_DATA2_V 0xFFFFFFFF @@ -1063,7 +1126,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0x0c8) /* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA3 0xFFFFFFFF #define EFUSE_KEY1_DATA3_M ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S)) #define EFUSE_KEY1_DATA3_V 0xFFFFFFFF @@ -1071,7 +1134,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0x0cc) /* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA4 0xFFFFFFFF #define EFUSE_KEY1_DATA4_M ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S)) #define EFUSE_KEY1_DATA4_V 0xFFFFFFFF @@ -1079,7 +1142,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0x0d0) /* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA5 0xFFFFFFFF #define EFUSE_KEY1_DATA5_M ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S)) #define EFUSE_KEY1_DATA5_V 0xFFFFFFFF @@ -1087,7 +1150,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0x0d4) /* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA6 0xFFFFFFFF #define EFUSE_KEY1_DATA6_M ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S)) #define EFUSE_KEY1_DATA6_V 0xFFFFFFFF @@ -1095,7 +1158,7 @@ extern "C" { #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0x0d8) /* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of KEY1.*/ #define EFUSE_KEY1_DATA7 0xFFFFFFFF #define EFUSE_KEY1_DATA7_M ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S)) #define EFUSE_KEY1_DATA7_V 0xFFFFFFFF @@ -1103,7 +1166,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0x0dc) /* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA0 0xFFFFFFFF #define EFUSE_KEY2_DATA0_M ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S)) #define EFUSE_KEY2_DATA0_V 0xFFFFFFFF @@ -1111,7 +1174,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0x0e0) /* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA1 0xFFFFFFFF #define EFUSE_KEY2_DATA1_M ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S)) #define EFUSE_KEY2_DATA1_V 0xFFFFFFFF @@ -1119,7 +1182,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0x0e4) /* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA2 0xFFFFFFFF #define EFUSE_KEY2_DATA2_M ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S)) #define EFUSE_KEY2_DATA2_V 0xFFFFFFFF @@ -1127,7 +1190,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0x0e8) /* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA3 0xFFFFFFFF #define EFUSE_KEY2_DATA3_M ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S)) #define EFUSE_KEY2_DATA3_V 0xFFFFFFFF @@ -1135,7 +1198,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0x0ec) /* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA4 0xFFFFFFFF #define EFUSE_KEY2_DATA4_M ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S)) #define EFUSE_KEY2_DATA4_V 0xFFFFFFFF @@ -1143,7 +1206,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0x0f0) /* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA5 0xFFFFFFFF #define EFUSE_KEY2_DATA5_M ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S)) #define EFUSE_KEY2_DATA5_V 0xFFFFFFFF @@ -1151,7 +1214,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x0f4) /* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA6 0xFFFFFFFF #define EFUSE_KEY2_DATA6_M ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S)) #define EFUSE_KEY2_DATA6_V 0xFFFFFFFF @@ -1159,7 +1222,7 @@ extern "C" { #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x0f8) /* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of KEY2.*/ #define EFUSE_KEY2_DATA7 0xFFFFFFFF #define EFUSE_KEY2_DATA7_M ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S)) #define EFUSE_KEY2_DATA7_V 0xFFFFFFFF @@ -1167,7 +1230,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x0fc) /* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA0 0xFFFFFFFF #define EFUSE_KEY3_DATA0_M ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S)) #define EFUSE_KEY3_DATA0_V 0xFFFFFFFF @@ -1175,7 +1238,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA1 0xFFFFFFFF #define EFUSE_KEY3_DATA1_M ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S)) #define EFUSE_KEY3_DATA1_V 0xFFFFFFFF @@ -1183,7 +1246,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA2 0xFFFFFFFF #define EFUSE_KEY3_DATA2_M ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S)) #define EFUSE_KEY3_DATA2_V 0xFFFFFFFF @@ -1191,7 +1254,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA3 0xFFFFFFFF #define EFUSE_KEY3_DATA3_M ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S)) #define EFUSE_KEY3_DATA3_V 0xFFFFFFFF @@ -1199,7 +1262,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) /* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA4 0xFFFFFFFF #define EFUSE_KEY3_DATA4_M ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S)) #define EFUSE_KEY3_DATA4_V 0xFFFFFFFF @@ -1207,7 +1270,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA5 0xFFFFFFFF #define EFUSE_KEY3_DATA5_M ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S)) #define EFUSE_KEY3_DATA5_V 0xFFFFFFFF @@ -1215,7 +1278,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA6 0xFFFFFFFF #define EFUSE_KEY3_DATA6_M ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S)) #define EFUSE_KEY3_DATA6_V 0xFFFFFFFF @@ -1223,7 +1286,7 @@ extern "C" { #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of KEY3.*/ #define EFUSE_KEY3_DATA7 0xFFFFFFFF #define EFUSE_KEY3_DATA7_M ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S)) #define EFUSE_KEY3_DATA7_V 0xFFFFFFFF @@ -1231,7 +1294,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) /* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA0 0xFFFFFFFF #define EFUSE_KEY4_DATA0_M ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S)) #define EFUSE_KEY4_DATA0_V 0xFFFFFFFF @@ -1239,7 +1302,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA1 0xFFFFFFFF #define EFUSE_KEY4_DATA1_M ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S)) #define EFUSE_KEY4_DATA1_V 0xFFFFFFFF @@ -1247,7 +1310,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA2 0xFFFFFFFF #define EFUSE_KEY4_DATA2_M ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S)) #define EFUSE_KEY4_DATA2_V 0xFFFFFFFF @@ -1255,7 +1318,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA3 0xFFFFFFFF #define EFUSE_KEY4_DATA3_M ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S)) #define EFUSE_KEY4_DATA3_V 0xFFFFFFFF @@ -1263,7 +1326,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) /* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA4 0xFFFFFFFF #define EFUSE_KEY4_DATA4_M ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S)) #define EFUSE_KEY4_DATA4_V 0xFFFFFFFF @@ -1271,7 +1334,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA5 0xFFFFFFFF #define EFUSE_KEY4_DATA5_M ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S)) #define EFUSE_KEY4_DATA5_V 0xFFFFFFFF @@ -1279,7 +1342,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA6 0xFFFFFFFF #define EFUSE_KEY4_DATA6_M ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S)) #define EFUSE_KEY4_DATA6_V 0xFFFFFFFF @@ -1287,7 +1350,7 @@ extern "C" { #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of KEY4.*/ #define EFUSE_KEY4_DATA7 0xFFFFFFFF #define EFUSE_KEY4_DATA7_M ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S)) #define EFUSE_KEY4_DATA7_V 0xFFFFFFFF @@ -1295,7 +1358,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) /* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the zeroth 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA0 0xFFFFFFFF #define EFUSE_KEY5_DATA0_M ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S)) #define EFUSE_KEY5_DATA0_V 0xFFFFFFFF @@ -1303,7 +1366,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the first 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA1 0xFFFFFFFF #define EFUSE_KEY5_DATA1_M ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S)) #define EFUSE_KEY5_DATA1_V 0xFFFFFFFF @@ -1311,7 +1374,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the second 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA2 0xFFFFFFFF #define EFUSE_KEY5_DATA2_M ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S)) #define EFUSE_KEY5_DATA2_V 0xFFFFFFFF @@ -1319,7 +1382,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the third 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA3 0xFFFFFFFF #define EFUSE_KEY5_DATA3_M ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S)) #define EFUSE_KEY5_DATA3_V 0xFFFFFFFF @@ -1327,7 +1390,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) /* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fourth 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA4 0xFFFFFFFF #define EFUSE_KEY5_DATA4_M ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S)) #define EFUSE_KEY5_DATA4_V 0xFFFFFFFF @@ -1335,7 +1398,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the fifth 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA5 0xFFFFFFFF #define EFUSE_KEY5_DATA5_M ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S)) #define EFUSE_KEY5_DATA5_V 0xFFFFFFFF @@ -1343,7 +1406,7 @@ extern "C" { #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the sixth 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA6 0xFFFFFFFF #define EFUSE_KEY5_DATA6_M ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S)) #define EFUSE_KEY5_DATA6_V 0xFFFFFFFF @@ -1351,765 +1414,840 @@ extern "C" { #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ +/*description: Stores the seventh 32 bits of KEY5.*/ #define EFUSE_KEY5_DATA7 0xFFFFFFFF #define EFUSE_KEY5_DATA7_M ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S)) #define EFUSE_KEY5_DATA7_V 0xFFFFFFFF #define EFUSE_KEY5_DATA7_S 0 -#define EFUSE_RD_KEY6_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/* EFUSE_KEY6_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA0 0xFFFFFFFF -#define EFUSE_KEY6_DATA0_M ((EFUSE_KEY6_DATA0_V)<<(EFUSE_KEY6_DATA0_S)) -#define EFUSE_KEY6_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA0_S 0 +#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) +/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_M ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S)) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_S 0 -#define EFUSE_RD_KEY6_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/* EFUSE_KEY6_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA1 0xFFFFFFFF -#define EFUSE_KEY6_DATA1_M ((EFUSE_KEY6_DATA1_V)<<(EFUSE_KEY6_DATA1_S)) -#define EFUSE_KEY6_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA1_S 0 +#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) +/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_M ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S)) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_S 0 -#define EFUSE_RD_KEY6_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/* EFUSE_KEY6_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA2 0xFFFFFFFF -#define EFUSE_KEY6_DATA2_M ((EFUSE_KEY6_DATA2_V)<<(EFUSE_KEY6_DATA2_S)) -#define EFUSE_KEY6_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA2_S 0 +#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) +/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_M ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S)) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_S 0 -#define EFUSE_RD_KEY6_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/* EFUSE_KEY6_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA3 0xFFFFFFFF -#define EFUSE_KEY6_DATA3_M ((EFUSE_KEY6_DATA3_V)<<(EFUSE_KEY6_DATA3_S)) -#define EFUSE_KEY6_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA3_S 0 +#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) +/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_M ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S)) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_S 0 -#define EFUSE_RD_KEY6_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) -/* EFUSE_KEY6_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA4 0xFFFFFFFF -#define EFUSE_KEY6_DATA4_M ((EFUSE_KEY6_DATA4_V)<<(EFUSE_KEY6_DATA4_S)) -#define EFUSE_KEY6_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA4_S 0 +#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) +/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_M ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S)) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_S 0 -#define EFUSE_RD_KEY6_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) -/* EFUSE_KEY6_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA5 0xFFFFFFFF -#define EFUSE_KEY6_DATA5_M ((EFUSE_KEY6_DATA5_V)<<(EFUSE_KEY6_DATA5_S)) -#define EFUSE_KEY6_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA5_S 0 +#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) +/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_M ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S)) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_S 0 -#define EFUSE_RD_KEY6_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/* EFUSE_KEY6_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA6 0xFFFFFFFF -#define EFUSE_KEY6_DATA6_M ((EFUSE_KEY6_DATA6_V)<<(EFUSE_KEY6_DATA6_S)) -#define EFUSE_KEY6_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA6_S 0 +#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) +/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_M ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S)) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_S 0 -#define EFUSE_RD_KEY6_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/* EFUSE_KEY6_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define EFUSE_KEY6_DATA7 0xFFFFFFFF -#define EFUSE_KEY6_DATA7_M ((EFUSE_KEY6_DATA7_V)<<(EFUSE_KEY6_DATA7_S)) -#define EFUSE_KEY6_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY6_DATA7_S 0 +#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) +/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: Stores the $nth 32 bits of the 2nd part of system data.*/ +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_M ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S)) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_S 0 #define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) -/* EFUSE_RD_SDIO_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFH_ERR 0x00000003 -#define EFUSE_RD_SDIO_DREFH_ERR_M ((EFUSE_RD_SDIO_DREFH_ERR_V)<<(EFUSE_RD_SDIO_DREFH_ERR_S)) -#define EFUSE_RD_SDIO_DREFH_ERR_V 0x3 -#define EFUSE_RD_SDIO_DREFH_ERR_S 30 -/* EFUSE_RD_SDIO_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_MODECURLIM_ERR (BIT(29)) -#define EFUSE_RD_SDIO_MODECURLIM_ERR_M (BIT(29)) -#define EFUSE_RD_SDIO_MODECURLIM_ERR_V 0x1 -#define EFUSE_RD_SDIO_MODECURLIM_ERR_S 29 -/* EFUSE_RD_USB_DRES_ERR : RO ;bitpos:[28:25] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_USB_DRES_ERR 0x0000000F -#define EFUSE_RD_USB_DRES_ERR_M ((EFUSE_RD_USB_DRES_ERR_V)<<(EFUSE_RD_USB_DRES_ERR_S)) -#define EFUSE_RD_USB_DRES_ERR_V 0xF -#define EFUSE_RD_USB_DRES_ERR_S 25 -/* EFUSE_RD_USB_EXCHG_PINS_ERR : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_USB_EXCHG_PINS_ERR (BIT(24)) -#define EFUSE_RD_USB_EXCHG_PINS_ERR_M (BIT(24)) -#define EFUSE_RD_USB_EXCHG_PINS_ERR_V 0x1 -#define EFUSE_RD_USB_EXCHG_PINS_ERR_S 24 -/* EFUSE_RD_USB_DREFL_ERR : RO ;bitpos:[23:22] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_USB_DREFL_ERR 0x00000003 -#define EFUSE_RD_USB_DREFL_ERR_M ((EFUSE_RD_USB_DREFL_ERR_V)<<(EFUSE_RD_USB_DREFL_ERR_S)) -#define EFUSE_RD_USB_DREFL_ERR_V 0x3 -#define EFUSE_RD_USB_DREFL_ERR_S 22 -/* EFUSE_RD_USB_DREFH_ERR : RO ;bitpos:[21:20] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_USB_DREFH_ERR 0x00000003 -#define EFUSE_RD_USB_DREFH_ERR_M ((EFUSE_RD_USB_DREFH_ERR_V)<<(EFUSE_RD_USB_DREFH_ERR_S)) -#define EFUSE_RD_USB_DREFH_ERR_V 0x3 -#define EFUSE_RD_USB_DREFH_ERR_S 20 -/* EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) -#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(19)) -#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 -#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 -/* EFUSE_RD_HARD_DIS_JTAG_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_HARD_DIS_JTAG_ERR (BIT(18)) -#define EFUSE_RD_HARD_DIS_JTAG_ERR_M (BIT(18)) -#define EFUSE_RD_HARD_DIS_JTAG_ERR_V 0x1 -#define EFUSE_RD_HARD_DIS_JTAG_ERR_S 18 -/* EFUSE_RD_SOFT_DIS_JTAG_ERR : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SOFT_DIS_JTAG_ERR (BIT(17)) -#define EFUSE_RD_SOFT_DIS_JTAG_ERR_M (BIT(17)) -#define EFUSE_RD_SOFT_DIS_JTAG_ERR_V 0x1 -#define EFUSE_RD_SOFT_DIS_JTAG_ERR_S 17 -/* EFUSE_RD_DIS_EFUSE_ATE_WR_ERR : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR (BIT(16)) -#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR_M (BIT(16)) -#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR_V 0x1 -#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR_S 16 -/* EFUSE_RD_DIS_SDIO_ACCESS_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_SDIO_ACCESS_ERR (BIT(15)) -#define EFUSE_RD_DIS_SDIO_ACCESS_ERR_M (BIT(15)) -#define EFUSE_RD_DIS_SDIO_ACCESS_ERR_V 0x1 -#define EFUSE_RD_DIS_SDIO_ACCESS_ERR_S 15 -/* EFUSE_RD_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_CAN_ERR (BIT(14)) -#define EFUSE_RD_DIS_CAN_ERR_M (BIT(14)) -#define EFUSE_RD_DIS_CAN_ERR_V 0x1 -#define EFUSE_RD_DIS_CAN_ERR_S 14 -/* EFUSE_RD_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_USB_ERR (BIT(13)) -#define EFUSE_RD_DIS_USB_ERR_M (BIT(13)) -#define EFUSE_RD_DIS_USB_ERR_V 0x1 -#define EFUSE_RD_DIS_USB_ERR_S 13 -/* EFUSE_RD_DIS_BT_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_BT_ERR (BIT(12)) -#define EFUSE_RD_DIS_BT_ERR_M (BIT(12)) -#define EFUSE_RD_DIS_BT_ERR_V 0x1 -#define EFUSE_RD_DIS_BT_ERR_S 12 -/* EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) -#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 -#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR_S 11 -/* EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) -#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 -#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR_S 10 -/* EFUSE_RD_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_RD_DIS_DCACHE_ERR_M (BIT(9)) -#define EFUSE_RD_DIS_DCACHE_ERR_V 0x1 -#define EFUSE_RD_DIS_DCACHE_ERR_S 9 -/* EFUSE_RD_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_RD_DIS_ICACHE_ERR_M (BIT(8)) -#define EFUSE_RD_DIS_ICACHE_ERR_V 0x1 -#define EFUSE_RD_DIS_ICACHE_ERR_S 8 -/* EFUSE_RD_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) -#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR_V 0x1 -#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR_S 7 -/* EFUSE_RD_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ -/*description: */ -#define EFUSE_RD_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_RD_DIS_ERR_M ((EFUSE_RD_RD_DIS_ERR_V)<<(EFUSE_RD_RD_DIS_ERR_S)) -#define EFUSE_RD_RD_DIS_ERR_V 0x7F -#define EFUSE_RD_RD_DIS_ERR_S 0 +/* EFUSE_VDD_SPI_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: If any bit in VDD_SPI_DREFH is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_M ((EFUSE_VDD_SPI_DREFH_ERR_V)<<(EFUSE_VDD_SPI_DREFH_ERR_S)) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x3 +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 +/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'h0 ; */ +/*description: If VDD_SPI_MODECURLIM is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x1 +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 +/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_M ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S)) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x3 +#define EFUSE_RPT4_RESERVED0_ERR_S 27 +/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO ;bitpos:[26] ;default: 1'h0 ; */ +/*description: Record error infomation of the burning result of usb_force_nopersist.*/ +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x1 +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 +/* EFUSE_EXT_PHY_ENABLE_ERR : RO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: If EXT_PHY_ENABLE is 1 then it indicates a programming error.*/ +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x1 +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 +/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[24] ;default: 1'h0 ; */ +/*description: If USB_EXCHG_PINS is 1 then it indicates a programming error.*/ +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x1 +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 +/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[23:22] ;default: 2'h0 ; */ +/*description: If any bit in USB_DREFL is 1 then it indicates a programming error.*/ +#define EFUSE_USB_DREFL_ERR 0x00000003 +#define EFUSE_USB_DREFL_ERR_M ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S)) +#define EFUSE_USB_DREFL_ERR_V 0x3 +#define EFUSE_USB_DREFL_ERR_S 22 +/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: If any bit in USB_DREFH is 1 then it indicates a programming error.*/ +#define EFUSE_USB_DREFH_ERR 0x00000003 +#define EFUSE_USB_DREFH_ERR_M ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S)) +#define EFUSE_USB_DREFH_ERR_V 0x3 +#define EFUSE_USB_DREFH_ERR_S 20 +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[19] ;default: 1'h0 ; */ +/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 +/* EFUSE_HARD_DIS_JTAG_ERR : RO ;bitpos:[18] ;default: 1'h0 ; */ +/*description: If HARD_DIS_JTAG is 1 then it indicates a programming error.*/ +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x1 +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 +/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[17] ;default: 1'h0 ; */ +/*description: If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/ +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x1 +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 +/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: If DIS_EFUSE_ATE_WR is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x1 +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 +/* EFUSE_DIS_BOOT_REMAP_ERR : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: If DIS_BOOT_REMAP is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x1 +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 +/* EFUSE_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'h0 ; */ +/*description: If DIS_CAN is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (BIT(14)) +#define EFUSE_DIS_CAN_ERR_V 0x1 +#define EFUSE_DIS_CAN_ERR_S 14 +/* EFUSE_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'h0 ; */ +/*description: If DIS_USB is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (BIT(13)) +#define EFUSE_DIS_USB_ERR_V 0x1 +#define EFUSE_DIS_USB_ERR_S 13 +/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'h0 ; */ +/*description: If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x1 +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 +/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: If DIS_DOWNLOAD_DCACHE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 +/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 +/* EFUSE_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'h0 ; */ +/*description: If DIS_DCACHE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_V 0x1 +#define EFUSE_DIS_DCACHE_ERR_S 9 +/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: If DIS_ICACHE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_V 0x1 +#define EFUSE_DIS_ICACHE_ERR_S 8 +/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1 +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 +/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/ +#define EFUSE_RD_DIS_ERR 0x0000007F +#define EFUSE_RD_DIS_ERR_M ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S)) +#define EFUSE_RD_DIS_ERR_V 0x7F +#define EFUSE_RD_DIS_ERR_S 0 #define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/* EFUSE_RD_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_1_ERR_M ((EFUSE_RD_KEY_PURPOSE_1_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_1_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_1_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_1_ERR_S 28 -/* EFUSE_RD_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_0_ERR_M ((EFUSE_RD_KEY_PURPOSE_0_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_0_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_0_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_0_ERR_S 24 -/* EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 -/* EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 -/* EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 -#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 -/* EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_S)) -#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 -#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_S 18 -/* EFUSE_RD_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_RD_WDT_DELAY_SEL_ERR_M ((EFUSE_RD_WDT_DELAY_SEL_ERR_V)<<(EFUSE_RD_WDT_DELAY_SEL_ERR_S)) -#define EFUSE_RD_WDT_DELAY_SEL_ERR_V 0x3 -#define EFUSE_RD_WDT_DELAY_SEL_ERR_S 16 -/* EFUSE_RD_SDIO_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DCAP_ERR 0x00000003 -#define EFUSE_RD_SDIO_DCAP_ERR_M ((EFUSE_RD_SDIO_DCAP_ERR_V)<<(EFUSE_RD_SDIO_DCAP_ERR_S)) -#define EFUSE_RD_SDIO_DCAP_ERR_V 0x3 -#define EFUSE_RD_SDIO_DCAP_ERR_S 14 -/* EFUSE_RD_SDIO_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_INIT_ERR 0x00000003 -#define EFUSE_RD_SDIO_INIT_ERR_M ((EFUSE_RD_SDIO_INIT_ERR_V)<<(EFUSE_RD_SDIO_INIT_ERR_S)) -#define EFUSE_RD_SDIO_INIT_ERR_V 0x3 -#define EFUSE_RD_SDIO_INIT_ERR_S 12 -/* EFUSE_RD_SDIO_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DCURLIM_ERR 0x00000007 -#define EFUSE_RD_SDIO_DCURLIM_ERR_M ((EFUSE_RD_SDIO_DCURLIM_ERR_V)<<(EFUSE_RD_SDIO_DCURLIM_ERR_S)) -#define EFUSE_RD_SDIO_DCURLIM_ERR_V 0x7 -#define EFUSE_RD_SDIO_DCURLIM_ERR_S 9 -/* EFUSE_RD_SDIO_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_ENCURLIM_ERR (BIT(8)) -#define EFUSE_RD_SDIO_ENCURLIM_ERR_M (BIT(8)) -#define EFUSE_RD_SDIO_ENCURLIM_ERR_V 0x1 -#define EFUSE_RD_SDIO_ENCURLIM_ERR_S 8 -/* EFUSE_RD_SDIO_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_EN_INIT_ERR (BIT(7)) -#define EFUSE_RD_SDIO_EN_INIT_ERR_M (BIT(7)) -#define EFUSE_RD_SDIO_EN_INIT_ERR_V 0x1 -#define EFUSE_RD_SDIO_EN_INIT_ERR_S 7 -/* EFUSE_RD_SDIO_FORCE_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_FORCE_ERR (BIT(6)) -#define EFUSE_RD_SDIO_FORCE_ERR_M (BIT(6)) -#define EFUSE_RD_SDIO_FORCE_ERR_V 0x1 -#define EFUSE_RD_SDIO_FORCE_ERR_S 6 -/* EFUSE_RD_SDIO_TIEH_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_TIEH_ERR (BIT(5)) -#define EFUSE_RD_SDIO_TIEH_ERR_M (BIT(5)) -#define EFUSE_RD_SDIO_TIEH_ERR_V 0x1 -#define EFUSE_RD_SDIO_TIEH_ERR_S 5 -/* EFUSE_RD_SDIO_XPD_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_XPD_ERR (BIT(4)) -#define EFUSE_RD_SDIO_XPD_ERR_M (BIT(4)) -#define EFUSE_RD_SDIO_XPD_ERR_V 0x1 -#define EFUSE_RD_SDIO_XPD_ERR_S 4 -/* EFUSE_RD_SDIO_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFL_ERR 0x00000003 -#define EFUSE_RD_SDIO_DREFL_ERR_M ((EFUSE_RD_SDIO_DREFL_ERR_V)<<(EFUSE_RD_SDIO_DREFL_ERR_S)) -#define EFUSE_RD_SDIO_DREFL_ERR_V 0x3 -#define EFUSE_RD_SDIO_DREFL_ERR_S 2 -/* EFUSE_RD_SDIO_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_SDIO_DREFM_ERR 0x00000003 -#define EFUSE_RD_SDIO_DREFM_ERR_M ((EFUSE_RD_SDIO_DREFM_ERR_V)<<(EFUSE_RD_SDIO_DREFM_ERR_S)) -#define EFUSE_RD_SDIO_DREFM_ERR_V 0x3 -#define EFUSE_RD_SDIO_DREFM_ERR_S 0 +/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_M ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S)) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 +/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_M ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S)) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 +/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 +/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'h0 ; */ +/*description: If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 +/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'h0 ; */ +/*description: If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 +/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/ +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x7 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 +/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/ +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_M ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S)) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x3 +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +/* EFUSE_VDD_SPI_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: If any bit in VDD_SPI_DCAP is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_M ((EFUSE_VDD_SPI_DCAP_ERR_V)<<(EFUSE_VDD_SPI_DCAP_ERR_S)) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x3 +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 +/* EFUSE_VDD_SPI_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: If any bit in VDD_SPI_INIT is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_M ((EFUSE_VDD_SPI_INIT_ERR_V)<<(EFUSE_VDD_SPI_INIT_ERR_S)) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x3 +#define EFUSE_VDD_SPI_INIT_ERR_S 12 +/* EFUSE_VDD_SPI_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: If any bit in VDD_SPI_DCURLIM is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_M ((EFUSE_VDD_SPI_DCURLIM_ERR_V)<<(EFUSE_VDD_SPI_DCURLIM_ERR_S)) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x7 +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 +/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: If VDD_SPI_ENCURLIM is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x1 +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 +/* EFUSE_VDD_SPI_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: If VDD_SPI_EN_INIT is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x1 +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 +/* EFUSE_VDD_SPI_FORCE_ERR : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: If VDD_SPI_FORCE is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x1 +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 +/* EFUSE_VDD_SPI_TIEH_ERR : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: If VDD_SPI_TIEH is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x1 +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 +/* EFUSE_VDD_SPI_XPD_ERR : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: If VDD_SPI_XPD is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x1 +#define EFUSE_VDD_SPI_XPD_ERR_S 4 +/* EFUSE_VDD_SPI_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: If any bit in VDD_SPI_DREFL is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_M ((EFUSE_VDD_SPI_DREFL_ERR_V)<<(EFUSE_VDD_SPI_DREFL_ERR_S)) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x3 +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 +/* EFUSE_VDD_SPI_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: If any bit in VDD_SPI_DREFM is 1 then it indicates a programming error.*/ +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_M ((EFUSE_VDD_SPI_DREFM_ERR_V)<<(EFUSE_VDD_SPI_DREFM_ERR_S)) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x3 +#define EFUSE_VDD_SPI_DREFM_ERR_S 0 #define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) -/* EFUSE_RD_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_RD_FLASH_TPUW_ERR_M ((EFUSE_RD_FLASH_TPUW_ERR_V)<<(EFUSE_RD_FLASH_TPUW_ERR_S)) -#define EFUSE_RD_FLASH_TPUW_ERR_V 0xF -#define EFUSE_RD_FLASH_TPUW_ERR_S 28 -/* EFUSE_RD_XTAL_FREQ_ERR : RO ;bitpos:[27:22] ;default: 6'b0 ; */ -/*description: */ -#define EFUSE_RD_XTAL_FREQ_ERR 0x0000003F -#define EFUSE_RD_XTAL_FREQ_ERR_M ((EFUSE_RD_XTAL_FREQ_ERR_V)<<(EFUSE_RD_XTAL_FREQ_ERR_S)) -#define EFUSE_RD_XTAL_FREQ_ERR_V 0x3F -#define EFUSE_RD_XTAL_FREQ_ERR_S 22 -/* EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) -#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 -#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/* EFUSE_RD_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_RD_SECURE_BOOT_EN_ERR_M (BIT(20)) -#define EFUSE_RD_SECURE_BOOT_EN_ERR_V 0x1 -#define EFUSE_RD_SECURE_BOOT_EN_ERR_S 20 -/* EFUSE_RD_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_6_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_6_ERR_M ((EFUSE_RD_KEY_PURPOSE_6_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_6_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_6_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_6_ERR_S 16 -/* EFUSE_RD_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_5_ERR_M ((EFUSE_RD_KEY_PURPOSE_5_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_5_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_5_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_5_ERR_S 12 -/* EFUSE_RD_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_4_ERR_M ((EFUSE_RD_KEY_PURPOSE_4_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_4_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_4_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_4_ERR_S 8 -/* EFUSE_RD_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_3_ERR_M ((EFUSE_RD_KEY_PURPOSE_3_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_3_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_3_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_3_ERR_S 4 -/* EFUSE_RD_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_RD_KEY_PURPOSE_2_ERR_M ((EFUSE_RD_KEY_PURPOSE_2_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_2_ERR_S)) -#define EFUSE_RD_KEY_PURPOSE_2_ERR_V 0xF -#define EFUSE_RD_KEY_PURPOSE_2_ERR_S 0 +/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_TPUW_ERR 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_M ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S)) +#define EFUSE_FLASH_TPUW_ERR_V 0xF +#define EFUSE_FLASH_TPUW_ERR_S 28 +/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S)) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x3F +#define EFUSE_RPT4_RESERVED1_ERR_S 22 +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'h0 ; */ +/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 +/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'h0 ; */ +/*description: If SECURE_BOOT_EN is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x1 +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 +/* EFUSE_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_6 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_M ((EFUSE_KEY_PURPOSE_6_ERR_V)<<(EFUSE_KEY_PURPOSE_6_ERR_S)) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 +/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_M ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S)) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 +/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_M ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S)) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 +/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_M ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S)) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 +/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/ +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_M ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S)) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0xF +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 #define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) -/* EFUSE_RD_RESERVE_ERR : RO ;bitpos:[31:8] ;default: 24'h0 ; */ -/*description: */ -#define EFUSE_RD_RESERVE_ERR 0x00FFFFFF -#define EFUSE_RD_RESERVE_ERR_M ((EFUSE_RD_RESERVE_ERR_V)<<(EFUSE_RD_RESERVE_ERR_S)) -#define EFUSE_RD_RESERVE_ERR_V 0xFFFFFF -#define EFUSE_RD_RESERVE_ERR_S 8 -/* EFUSE_RD_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: */ -#define EFUSE_RD_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_RD_UART_PRINT_CONTROL_M ((EFUSE_RD_UART_PRINT_CONTROL_V)<<(EFUSE_RD_UART_PRINT_CONTROL_S)) -#define EFUSE_RD_UART_PRINT_CONTROL_V 0x3 -#define EFUSE_RD_UART_PRINT_CONTROL_S 6 -/* EFUSE_RD_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD_M (BIT(5)) -#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD_V 0x1 -#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD_S 5 -/* EFUSE_RD_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE_M (BIT(4)) -#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE_V 0x1 -#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE_S 4 -/* EFUSE_RD_DIS_TINY_BASIC : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_TINY_BASIC (BIT(3)) -#define EFUSE_RD_DIS_TINY_BASIC_M (BIT(3)) -#define EFUSE_RD_DIS_TINY_BASIC_V 0x1 -#define EFUSE_RD_DIS_TINY_BASIC_S 3 -/* EFUSE_RD_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_RD_UART_PRINT_CHANNEL_M (BIT(2)) -#define EFUSE_RD_UART_PRINT_CHANNEL_V 0x1 -#define EFUSE_RD_UART_PRINT_CHANNEL_S 2 -/* EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) -#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR_M (BIT(1)) -#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR_V 0x1 -#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR_S 1 -/* EFUSE_RD_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) -#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR_V 0x1 -#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR_S 0 +/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[31:27] ;default: 5'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_M ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S)) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x1F +#define EFUSE_RPT4_RESERVED2_ERR_S 27 +/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[26:11] ;default: 16'h0 ; */ +/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/ +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_M ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S)) +#define EFUSE_SECURE_VERSION_ERR_V 0xFFFF +#define EFUSE_SECURE_VERSION_ERR_S 11 +/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[10] ;default: 1'h0 ; */ +/*description: If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/ +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x1 +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 +/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'h0 ; */ +/*description: If FLASH_TYPE is 1 then it indicates a programming error.*/ +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_V 0x1 +#define EFUSE_FLASH_TYPE_ERR_S 9 +/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/ +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x1 +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 +/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/ +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_M ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S)) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x3 +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 +/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/ +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x1 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 +/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 +/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: If RPT4_RESERVED3 is 1 then it indicates a programming error.*/ +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x1 +#define EFUSE_RPT4_RESERVED3_ERR_S 3 +/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/ +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x1 +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 +/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x1 +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 +/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/ +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) -/* EFUSE_RD_CHIP_VERSION_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VERSION_ERR 0x00FFFFFF -#define EFUSE_RD_CHIP_VERSION_ERR_M ((EFUSE_RD_CHIP_VERSION_ERR_V)<<(EFUSE_RD_CHIP_VERSION_ERR_S)) -#define EFUSE_RD_CHIP_VERSION_ERR_V 0xFFFFFF -#define EFUSE_RD_CHIP_VERSION_ERR_S 0 +/* EFUSE_RPT1_RESERVED0_ERR : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Reserved.*/ +#define EFUSE_RPT1_RESERVED0_ERR 0x000000FF +#define EFUSE_RPT1_RESERVED0_ERR_M ((EFUSE_RPT1_RESERVED0_ERR_V)<<(EFUSE_RPT1_RESERVED0_ERR_S)) +#define EFUSE_RPT1_RESERVED0_ERR_V 0xFF +#define EFUSE_RPT1_RESERVED0_ERR_S 24 +/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Reserved ( four backup method ).*/ +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_M ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S)) +#define EFUSE_RPT4_RESERVED4_ERR_V 0xFFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_S 0 -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x194) -/* EFUSE_RD_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY4_FAIL (BIT(31)) -#define EFUSE_RD_KEY4_FAIL_M (BIT(31)) -#define EFUSE_RD_KEY4_FAIL_V 0x1 -#define EFUSE_RD_KEY4_FAIL_S 31 -/* EFUSE_RD_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY4_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY4_ERR_NUM_M ((EFUSE_RD_KEY4_ERR_NUM_V)<<(EFUSE_RD_KEY4_ERR_NUM_S)) -#define EFUSE_RD_KEY4_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY4_ERR_NUM_S 28 -/* EFUSE_RD_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY3_FAIL (BIT(27)) -#define EFUSE_RD_KEY3_FAIL_M (BIT(27)) -#define EFUSE_RD_KEY3_FAIL_V 0x1 -#define EFUSE_RD_KEY3_FAIL_S 27 -/* EFUSE_RD_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY3_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY3_ERR_NUM_M ((EFUSE_RD_KEY3_ERR_NUM_V)<<(EFUSE_RD_KEY3_ERR_NUM_S)) -#define EFUSE_RD_KEY3_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY3_ERR_NUM_S 24 -/* EFUSE_RD_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY2_FAIL (BIT(23)) -#define EFUSE_RD_KEY2_FAIL_M (BIT(23)) -#define EFUSE_RD_KEY2_FAIL_V 0x1 -#define EFUSE_RD_KEY2_FAIL_S 23 -/* EFUSE_RD_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY2_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY2_ERR_NUM_M ((EFUSE_RD_KEY2_ERR_NUM_V)<<(EFUSE_RD_KEY2_ERR_NUM_S)) -#define EFUSE_RD_KEY2_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY2_ERR_NUM_S 20 -/* EFUSE_RD_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY1_FAIL (BIT(19)) -#define EFUSE_RD_KEY1_FAIL_M (BIT(19)) -#define EFUSE_RD_KEY1_FAIL_V 0x1 -#define EFUSE_RD_KEY1_FAIL_S 19 -/* EFUSE_RD_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY1_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY1_ERR_NUM_M ((EFUSE_RD_KEY1_ERR_NUM_V)<<(EFUSE_RD_KEY1_ERR_NUM_S)) -#define EFUSE_RD_KEY1_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY1_ERR_NUM_S 16 -/* EFUSE_RD_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY0_FAIL (BIT(15)) -#define EFUSE_RD_KEY0_FAIL_M (BIT(15)) -#define EFUSE_RD_KEY0_FAIL_V 0x1 -#define EFUSE_RD_KEY0_FAIL_S 15 -/* EFUSE_RD_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY0_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY0_ERR_NUM_M ((EFUSE_RD_KEY0_ERR_NUM_V)<<(EFUSE_RD_KEY0_ERR_NUM_S)) -#define EFUSE_RD_KEY0_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY0_ERR_NUM_S 12 -/* EFUSE_RD_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) -#define EFUSE_RD_USR_DATA_FAIL_M (BIT(11)) -#define EFUSE_RD_USR_DATA_FAIL_V 0x1 -#define EFUSE_RD_USR_DATA_FAIL_S 11 -/* EFUSE_RD_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_RD_USR_DATA_ERR_NUM_M ((EFUSE_RD_USR_DATA_ERR_NUM_V)<<(EFUSE_RD_USR_DATA_ERR_NUM_S)) -#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x7 -#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 -/* EFUSE_RD_SYS_ERR_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_SYS_ERR_FAIL (BIT(7)) -#define EFUSE_RD_SYS_ERR_FAIL_M (BIT(7)) -#define EFUSE_RD_SYS_ERR_FAIL_V 0x1 -#define EFUSE_RD_SYS_ERR_FAIL_S 7 -/* EFUSE_RD_SYS_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_SYS_ERR_NUM 0x00000007 -#define EFUSE_RD_SYS_ERR_NUM_M ((EFUSE_RD_SYS_ERR_NUM_V)<<(EFUSE_RD_SYS_ERR_NUM_S)) -#define EFUSE_RD_SYS_ERR_NUM_V 0x7 -#define EFUSE_RD_SYS_ERR_NUM_S 4 -/* EFUSE_RD_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_RD_MAC_SPI_8M_FAIL_M (BIT(3)) -#define EFUSE_RD_MAC_SPI_8M_FAIL_V 0x1 -#define EFUSE_RD_MAC_SPI_8M_FAIL_S 3 -/* EFUSE_RD_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_M ((EFUSE_RD_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_RD_MAC_SPI_8M_ERR_NUM_S)) -#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_V 0x7 -#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_S 0 +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable*/ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (BIT(31)) +#define EFUSE_KEY4_FAIL_V 0x1 +#define EFUSE_KEY4_FAIL_S 31 +/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY4_ERR_NUM 0x00000007 +#define EFUSE_KEY4_ERR_NUM_M ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S)) +#define EFUSE_KEY4_ERR_NUM_V 0x7 +#define EFUSE_KEY4_ERR_NUM_S 28 +/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable*/ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (BIT(27)) +#define EFUSE_KEY3_FAIL_V 0x1 +#define EFUSE_KEY3_FAIL_S 27 +/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY3_ERR_NUM 0x00000007 +#define EFUSE_KEY3_ERR_NUM_M ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S)) +#define EFUSE_KEY3_ERR_NUM_V 0x7 +#define EFUSE_KEY3_ERR_NUM_S 24 +/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable*/ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (BIT(23)) +#define EFUSE_KEY2_FAIL_V 0x1 +#define EFUSE_KEY2_FAIL_S 23 +/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY2_ERR_NUM 0x00000007 +#define EFUSE_KEY2_ERR_NUM_M ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S)) +#define EFUSE_KEY2_ERR_NUM_V 0x7 +#define EFUSE_KEY2_ERR_NUM_S 20 +/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable*/ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (BIT(19)) +#define EFUSE_KEY1_FAIL_V 0x1 +#define EFUSE_KEY1_FAIL_S 19 +/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY1_ERR_NUM 0x00000007 +#define EFUSE_KEY1_ERR_NUM_M ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S)) +#define EFUSE_KEY1_ERR_NUM_V 0x7 +#define EFUSE_KEY1_ERR_NUM_S 16 +/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable*/ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (BIT(15)) +#define EFUSE_KEY0_FAIL_V 0x1 +#define EFUSE_KEY0_FAIL_S 15 +/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY0_ERR_NUM 0x00000007 +#define EFUSE_KEY0_ERR_NUM_M ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S)) +#define EFUSE_KEY0_ERR_NUM_V 0x7 +#define EFUSE_KEY0_ERR_NUM_S 12 +/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the user data is reliable*/ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (BIT(11)) +#define EFUSE_USR_DATA_FAIL_V 0x1 +#define EFUSE_USR_DATA_FAIL_S 11 +/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_M ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S)) +#define EFUSE_USR_DATA_ERR_NUM_V 0x7 +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of system part1 is reliable*/ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_V 0x1 +#define EFUSE_SYS_PART1_FAIL_S 7 +/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_SYS_PART1_NUM 0x00000007 +#define EFUSE_SYS_PART1_NUM_M ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S)) +#define EFUSE_SYS_PART1_NUM_V 0x7 +#define EFUSE_SYS_PART1_NUM_S 4 +/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable*/ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x1 +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_M ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S)) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x7 +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x198) -/* EFUSE_RD_KEY6_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY6_FAIL (BIT(7)) -#define EFUSE_RD_KEY6_FAIL_M (BIT(7)) -#define EFUSE_RD_KEY6_FAIL_V 0x1 -#define EFUSE_RD_KEY6_FAIL_S 7 -/* EFUSE_RD_KEY6_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY6_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY6_ERR_NUM_M ((EFUSE_RD_KEY6_ERR_NUM_V)<<(EFUSE_RD_KEY6_ERR_NUM_S)) -#define EFUSE_RD_KEY6_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY6_ERR_NUM_S 4 -/* EFUSE_RD_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY5_FAIL (BIT(3)) -#define EFUSE_RD_KEY5_FAIL_M (BIT(3)) -#define EFUSE_RD_KEY5_FAIL_V 0x1 -#define EFUSE_RD_KEY5_FAIL_S 3 -/* EFUSE_RD_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_RD_KEY5_ERR_NUM 0x00000007 -#define EFUSE_RD_KEY5_ERR_NUM_M ((EFUSE_RD_KEY5_ERR_NUM_V)<<(EFUSE_RD_KEY5_ERR_NUM_S)) -#define EFUSE_RD_KEY5_ERR_NUM_V 0x7 -#define EFUSE_RD_KEY5_ERR_NUM_S 0 +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of system part2 is reliable*/ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_V 0x1 +#define EFUSE_SYS_PART2_FAIL_S 7 +/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_M ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S)) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x7 +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: 0: Means no failure and that the data of KEY5 is reliable*/ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (BIT(3)) +#define EFUSE_KEY5_FAIL_V 0x1 +#define EFUSE_KEY5_FAIL_S 3 +/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_KEY5_ERR_NUM 0x00000007 +#define EFUSE_KEY5_ERR_NUM_M ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S)) +#define EFUSE_KEY5_ERR_NUM_V 0x7 +#define EFUSE_KEY5_ERR_NUM_S 0 -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x19c) -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: Set this bit and force to enable clock signal of eFuse memory.*/ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (BIT(16)) #define EFUSE_CLK_EN_V 0x1 #define EFUSE_CLK_EN_S 16 -/* EFUSE_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_MEM_PD (BIT(0)) -#define EFUSE_MEM_PD_M (BIT(0)) -#define EFUSE_MEM_PD_V 0x1 -#define EFUSE_MEM_PD_S 0 +/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to force eFuse SRAM into working mode.*/ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (BIT(2)) +#define EFUSE_MEM_FORCE_PU_V 0x1 +#define EFUSE_MEM_FORCE_PU_S 2 +/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (BIT(0)) +#define EFUSE_MEM_FORCE_PD_V 0x1 +#define EFUSE_MEM_FORCE_PD_S 0 -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1a0) +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ +/*description: 0x5A5A: Operate programming command*/ #define EFUSE_OP_CODE 0x0000FFFF #define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) #define EFUSE_OP_CODE_V 0xFFFF #define EFUSE_OP_CODE_S 0 -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1a4) -/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[16:9] ;default: 8'h0 ; */ -/*description: */ +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ +/*description: Indicates the number of error bits during programming BLOCK0.*/ #define EFUSE_REPEAT_ERR_CNT 0x000000FF #define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S)) #define EFUSE_REPEAT_ERR_CNT_V 0xFF -#define EFUSE_REPEAT_ERR_CNT_S 9 -/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_OTP_VDDQ_IS_SW (BIT(8)) -#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(8)) +#define EFUSE_REPEAT_ERR_CNT_S 10 +/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'h0 ; */ +/*description: The value of OTP_VDDQ_IS_SW.*/ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) #define EFUSE_OTP_VDDQ_IS_SW_V 0x1 -#define EFUSE_OTP_VDDQ_IS_SW_S 8 -/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_OTP_PGENB_SW (BIT(7)) -#define EFUSE_OTP_PGENB_SW_M (BIT(7)) +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The value of OTP_PGENB_SW.*/ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (BIT(8)) #define EFUSE_OTP_PGENB_SW_V 0x1 -#define EFUSE_OTP_PGENB_SW_S 7 -/* EFUSE_OTP_CSB_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_OTP_CSB_SW (BIT(6)) -#define EFUSE_OTP_CSB_SW_M (BIT(6)) +#define EFUSE_OTP_PGENB_SW_S 8 +/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The value of OTP_CSB_SW.*/ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (BIT(7)) #define EFUSE_OTP_CSB_SW_V 0x1 -#define EFUSE_OTP_CSB_SW_S 6 -/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_OTP_STROBE_SW (BIT(5)) -#define EFUSE_OTP_STROBE_SW_M (BIT(5)) +#define EFUSE_OTP_CSB_SW_S 7 +/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The value of OTP_STROBE_SW.*/ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (BIT(6)) #define EFUSE_OTP_STROBE_SW_V 0x1 -#define EFUSE_OTP_STROBE_SW_S 5 -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(4)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(4)) +#define EFUSE_OTP_STROBE_SW_S 6 +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The value of OTP_VDDQ_C_SYNC2.*/ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) #define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 4 -/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_OTP_LOAD_SW (BIT(3)) -#define EFUSE_OTP_LOAD_SW_M (BIT(3)) +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The value of OTP_LOAD_SW.*/ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (BIT(4)) #define EFUSE_OTP_LOAD_SW_V 0x1 -#define EFUSE_OTP_LOAD_SW_S 3 -/* EFUSE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define EFUSE_STATE 0x00000007 +#define EFUSE_OTP_LOAD_SW_S 4 +/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: Indicates the state of the eFuse state machine.*/ +#define EFUSE_STATE 0x0000000F #define EFUSE_STATE_M ((EFUSE_STATE_V)<<(EFUSE_STATE_S)) -#define EFUSE_STATE_V 0x7 +#define EFUSE_STATE_V 0xF #define EFUSE_STATE_S 0 -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1a8) -/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'b0 ; */ -/*description: */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ +/*description: The serial number of the block to be programmed. Value 0-10 corresponds + to block number 0-10 respectively.*/ #define EFUSE_BLK_NUM 0x0000000F #define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S)) #define EFUSE_BLK_NUM_V 0xF #define EFUSE_BLK_NUM_S 2 -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to send programming command.*/ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (BIT(1)) #define EFUSE_PGM_CMD_V 0x1 #define EFUSE_PGM_CMD_S 1 -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to send read command.*/ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (BIT(0)) #define EFUSE_READ_CMD_V 0x1 #define EFUSE_READ_CMD_S 0 -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1ac) -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The raw bit signal for pgm_done interrupt.*/ #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_V 0x1 #define EFUSE_PGM_DONE_INT_RAW_S 1 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The raw bit signal for read_done interrupt.*/ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_V 0x1 #define EFUSE_READ_DONE_INT_RAW_S 0 -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1b0) -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The status signal for pgm_done interrupt.*/ #define EFUSE_PGM_DONE_INT_ST (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_V 0x1 #define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The status signal for read_done interrupt.*/ #define EFUSE_READ_DONE_INT_ST (BIT(0)) #define EFUSE_READ_DONE_INT_ST_M (BIT(0)) #define EFUSE_READ_DONE_INT_ST_V 0x1 #define EFUSE_READ_DONE_INT_ST_S 0 -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1b4) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The enable signal for pgm_done interrupt.*/ #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_V 0x1 #define EFUSE_PGM_DONE_INT_ENA_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The enable signal for read_done interrupt.*/ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_V 0x1 #define EFUSE_READ_DONE_INT_ENA_S 0 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1b8) -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The clear signal for pgm_done interrupt.*/ #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_V 0x1 #define EFUSE_PGM_DONE_INT_CLR_S 1 -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ +/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The clear signal for read_done interrupt.*/ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_V 0x1 #define EFUSE_READ_DONE_INT_CLR_S 0 -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1bc) -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: Reduces the power supply of the programming voltage.*/ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (BIT(17)) +#define EFUSE_OE_CLR_V 0x1 +#define EFUSE_OE_CLR_S 17 +/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ +/*description: Controls the rising period of the programming voltage.*/ +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S)) +#define EFUSE_DAC_NUM_V 0xFF +#define EFUSE_DAC_NUM_S 9 +/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: Don't care.*/ #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) #define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) #define EFUSE_DAC_CLK_PAD_SEL_V 0x1 #define EFUSE_DAC_CLK_PAD_SEL_S 8 -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ -/*description: */ +/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */ +/*description: Controls the division factor of the rising clock of the programming voltage.*/ #define EFUSE_DAC_CLK_DIV 0x000000FF #define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) #define EFUSE_DAC_CLK_DIV_V 0xFF #define EFUSE_DAC_CLK_DIV_S 0 -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1c0) +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) /* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ -/*description: */ +/*description: Configures the initial read time of eFuse.*/ #define EFUSE_READ_INIT_NUM 0x000000FF #define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S)) #define EFUSE_READ_INIT_NUM_V 0xFF #define EFUSE_READ_INIT_NUM_S 24 -/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ +/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ +/*description: Configures the setup time of read operation.*/ #define EFUSE_TSUR_A 0x000000FF #define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S)) #define EFUSE_TSUR_A_V 0xFF #define EFUSE_TSUR_A_S 16 -/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ +/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: Configures the length of pulse of read operation.*/ #define EFUSE_TRD 0x000000FF #define EFUSE_TRD_M ((EFUSE_TRD_V)<<(EFUSE_TRD_S)) #define EFUSE_TRD_V 0xFF #define EFUSE_TRD_S 8 /* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: */ +/*description: Configures the hold time of read operation.*/ #define EFUSE_THR_A 0x000000FF #define EFUSE_THR_A_M ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S)) #define EFUSE_THR_A_V 0xFF #define EFUSE_THR_A_S 0 -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1c4) -/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'h190 ; */ -/*description: */ +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) +/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */ +/*description: Configures the length of pulse during programming 1 to eFuse.*/ #define EFUSE_TPGM 0x0000FFFF #define EFUSE_TPGM_M ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S)) #define EFUSE_TPGM_V 0xFFFF #define EFUSE_TPGM_S 16 -/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: */ +/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: Configures the length of pulse during programming 0 to eFuse.*/ #define EFUSE_TPGM_INACTIVE 0x000000FF #define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S)) #define EFUSE_TPGM_INACTIVE_V 0xFF #define EFUSE_TPGM_INACTIVE_S 8 /* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: */ +/*description: Configures the hold time of programming operation.*/ #define EFUSE_THP_A 0x000000FF #define EFUSE_THP_A_M ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S)) #define EFUSE_THP_A_V 0xFF #define EFUSE_THP_A_S 0 -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1c8) -/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h7000 ; */ -/*description: */ +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) +/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ +/*description: Configures the power up time for VDDQ.*/ #define EFUSE_PWR_ON_NUM 0x0000FFFF #define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S)) #define EFUSE_PWR_ON_NUM_V 0xFFFF #define EFUSE_PWR_ON_NUM_S 8 /* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ -/*description: */ +/*description: Configures the setup time of programming operation.*/ #define EFUSE_TSUP_A 0x000000FF #define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S)) #define EFUSE_TSUP_A_V 0xFF #define EFUSE_TSUP_A_S 0 +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) +/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ +/*description: Configures the power outage time for VDDQ.*/ +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S)) +#define EFUSE_PWR_OFF_NUM_V 0xFFFF +#define EFUSE_PWR_OFF_NUM_S 0 + #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h18101600 ; */ -/*description: */ +/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h19081100 ; */ +/*description: Stores eFuse version.*/ #define EFUSE_DATE 0xFFFFFFFF #define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) #define EFUSE_DATE_V 0xFFFFFFFF @@ -2119,4 +2257,8 @@ extern "C" { } #endif + + #endif /*_SOC_EFUSE_REG_H_ */ + + diff --git a/components/soc/esp32s2beta/include/soc/efuse_struct.h b/components/soc/esp32s2beta/include/soc/efuse_struct.h index bde2b54f9d..a9679c267c 100644 --- a/components/soc/esp32s2beta/include/soc/efuse_struct.h +++ b/components/soc/esp32s2beta/include/soc/efuse_struct.h @@ -18,189 +18,388 @@ extern "C" { #endif typedef volatile struct { + uint32_t pgm_data0; /**/ union { struct { - uint32_t rd_efuse_wr_dis: 16; - uint32_t rd_efuse_rd_dis: 4; - uint32_t rd_flash_crypt_cnt: 8; - uint32_t reserved28: 4; + uint32_t rd_dis: 7; + uint32_t dis_rtc_ram_boot: 1; + uint32_t dis_icache: 1; + uint32_t dis_dcache: 1; + uint32_t dis_download_icache: 1; + uint32_t dis_download_dcache: 1; + uint32_t dis_force_download: 1; + uint32_t dis_usb: 1; + uint32_t dis_can: 1; + uint32_t dis_sdio_access: 1; + uint32_t dis_efuse_ate_wr: 1; + uint32_t soft_dis_jtag: 1; + uint32_t hard_dis_jtag: 1; + uint32_t dis_download_manual_encrypt: 1; + uint32_t usb_drefh: 2; + uint32_t usb_drefl: 2; + uint32_t usb_exchg_pins: 1; + uint32_t ext_phy_enable: 1; + uint32_t usb_force_b: 1; + uint32_t usb_dres: 2; + uint32_t sdio_modecurlim: 1; + uint32_t sdio_drefh: 2; }; uint32_t val; - } blk0_rdata0; - uint32_t blk0_rdata1; /**/ + } pgm_data1; union { struct { - uint32_t rd_wifi_mac_crc_high:24; - uint32_t reserved24: 8; + uint32_t sdio_drefm: 2; + uint32_t sdio_drefl: 2; + uint32_t sdio_xpd: 1; + uint32_t sdio_tieh: 1; + uint32_t sdio_force: 1; + uint32_t sdio_en_init: 1; + uint32_t sdio_encurlim: 1; + uint32_t sdio_dcurlim: 3; + uint32_t sdio_init: 2; + uint32_t sdio_dcap: 2; + uint32_t wdt_delay_sel: 2; + uint32_t spi_boot_crypt_cnt: 3; + uint32_t secure_boot_key_revoke0: 1; + uint32_t secure_boot_key_revoke1: 1; + uint32_t secure_boot_key_revoke2: 1; + uint32_t key_purpose_0: 4; + uint32_t key_purpose_1: 4; }; uint32_t val; - } blk0_rdata2; + } pgm_data2; union { struct { - uint32_t rd_soft_disable_jtag: 1; - uint32_t rd_chip_ver_dis_bt: 1; - uint32_t rd_chip_ver_32pad: 1; - uint32_t rd_chip_ver_dis_cache: 1; - uint32_t rd_chip_ver_reserve: 13; - uint32_t reserved17: 15; + uint32_t key_purpose_2: 4; + uint32_t key_purpose_3: 4; + uint32_t key_purpose_4: 4; + uint32_t key_purpose_5: 4; + uint32_t key_purpose_6: 4; + uint32_t secure_boot_en: 1; + uint32_t secure_boot_aggressive_revoke: 1; + uint32_t xtal_freq: 6; + uint32_t flash_tpuw: 4; }; uint32_t val; - } blk0_rdata3; + } pgm_data3; union { struct { - uint32_t rd_ck8m_freq: 8; - uint32_t rd_sdio_drefh: 2; - uint32_t rd_sdio_drefm: 2; - uint32_t rd_sdio_drefl: 2; - uint32_t rd_xpd_sdio: 1; - uint32_t rd_sdio_tieh: 1; - uint32_t rd_sdio_force: 1; - uint32_t reserved17: 15; + uint32_t dis_download_mode: 1; + uint32_t dis_legacy_spi_boot: 1; + uint32_t uart_print_channel: 1; + uint32_t dis_tiny_basic: 1; + uint32_t dis_usb_download_mode: 1; + uint32_t enable_security_download: 1; + uint32_t uart_print_control: 2; + uint32_t reserve: 24; }; uint32_t val; - } blk0_rdata4; + } pgm_data4; union { struct { - uint32_t rd_spi_pad_config: 20; - uint32_t rd_tsens_dos: 4; - uint32_t rd_reserve_use1: 4; - uint32_t rd_flash_crypt_config: 4; + uint32_t chip_version:24; + uint32_t rs_data_23: 8; }; uint32_t val; - } blk0_rdata5; + } pgm_data5; + uint32_t pgm_data6; /**/ + uint32_t pgm_data7; /**/ + uint32_t pgm_check_value0; /**/ + uint32_t pgm_check_value1; /**/ + uint32_t pgm_check_value2; /**/ + uint32_t rd_wr_dis; /**/ union { struct { - uint32_t rd_coding_scheme: 2; - uint32_t rd_dig_reserve: 1; - uint32_t rd_disable_sdio_host: 1; - uint32_t rd_abs_done_0: 1; - uint32_t rd_abs_done_1: 1; - uint32_t rd_hard_disable_jtag: 1; - uint32_t rd_disable_dl_encrypt: 1; - uint32_t rd_disable_dl_decrypt: 1; - uint32_t rd_disable_dl_cache: 1; - uint32_t rd_key_status: 1; - uint32_t reserved11: 21; + uint32_t rd_dis: 7; + uint32_t dis_rtc_ram_boot: 1; + uint32_t dis_icache: 1; + uint32_t dis_dcache: 1; + uint32_t dis_download_icache: 1; + uint32_t dis_download_dcache: 1; + uint32_t dis_force_download: 1; + uint32_t dis_usb: 1; + uint32_t dis_can: 1; + uint32_t dis_sdio_access: 1; + uint32_t dis_ate_wr: 1; + uint32_t soft_dis_jtag: 1; + uint32_t hard_dis_jtag: 1; + uint32_t dis_download_manual_encrypt: 1; + uint32_t usb_drefh: 2; + uint32_t usb_drefl: 2; + uint32_t usb_exchg_pins: 1; + uint32_t ext_phy_enable: 1; + uint32_t usb_force_b: 1; + uint32_t usb_dres: 2; + uint32_t sdio_modecurlim: 1; + uint32_t sdio_drefh: 2; }; uint32_t val; - } blk0_rdata6; + } rd_repeat_data0; union { struct { - uint32_t wr_dis: 16; - uint32_t rd_dis: 4; - uint32_t flash_crypt_cnt: 8; - uint32_t reserved28: 4; + uint32_t sdio_drefm: 2; + uint32_t sdio_drefl: 2; + uint32_t sdio_xpd: 1; + uint32_t sdio_tieh: 1; + uint32_t sdio_force: 1; + uint32_t sdio_en_init: 1; + uint32_t sdio_encurlim: 1; + uint32_t sdio_dcurlim: 3; + uint32_t sdio_init: 2; + uint32_t eufse_sdio_dcap: 2; + uint32_t wdt_delay_sel: 2; + uint32_t spi_boot_crypt_cnt: 3; + uint32_t secure_boot_key_revoke0: 1; + uint32_t secure_boot_key_revoke1: 1; + uint32_t secure_boot_key_revoke2: 1; + uint32_t key_purpose_0: 4; + uint32_t key_purpose_1: 4; }; uint32_t val; - } blk0_wdata0; - uint32_t blk0_wdata1; /**/ + } rd_repeat_data1; union { struct { - uint32_t wifi_mac_crc_high:24; - uint32_t reserved24: 8; + uint32_t key_purpose_2: 4; + uint32_t key_purpose_3: 4; + uint32_t key_purpose_4: 4; + uint32_t key_purpose_5: 4; + uint32_t key_purpose_6: 4; + uint32_t secure_boot_en: 1; + uint32_t secure_boot_aggressive_revoke: 1; + uint32_t xtal_freq: 6; + uint32_t flash_tpuw: 4; }; uint32_t val; - } blk0_wdata2; + } rd_repeat_data2; union { struct { - uint32_t soft_disable_jtag: 1; - uint32_t chip_ver_dis_bt: 1; - uint32_t chip_ver_32pad: 1; - uint32_t chip_ver_dis_cache: 1; - uint32_t chip_ver_reserve: 13; - uint32_t reserved17: 15; + uint32_t dis_download_mode: 1; + uint32_t dis_legacy_spi_boot: 1; + uint32_t uart_print_channel: 1; + uint32_t dis_tiny_basic: 1; + uint32_t dis_usb_download_mode: 1; + uint32_t enable_security_download: 1; + uint32_t uart_print_control: 2; + uint32_t reserve: 24; }; uint32_t val; - } blk0_wdata3; + } rd_repeat_data3; union { struct { - uint32_t ck8m_freq: 8; - uint32_t sdio_drefh: 2; - uint32_t sdio_drefm: 2; - uint32_t sdio_drefl: 2; - uint32_t xpd_sdio: 1; - uint32_t sdio_tieh: 1; - uint32_t sdio_force: 1; - uint32_t reserved17:15; + uint32_t chip_version:24; + uint32_t reserved24: 8; }; uint32_t val; - } blk0_wdata4; + } rd_repeat_data4; + uint32_t rd_mac_spi_8m_0; /**/ union { struct { - uint32_t spi_pad_config: 20; - uint32_t tsens_dos: 4; - uint32_t reserve_use1: 4; - uint32_t flash_crypt_config: 4; + uint32_t mac_1: 16; + uint32_t spi_pad_conf_0:16; }; uint32_t val; - } blk0_wdata5; + } rd_mac_spi_8m_1; union { struct { - uint32_t coding_scheme: 2; - uint32_t dig_reserve: 1; - uint32_t disable_sdio_host: 1; - uint32_t abs_done_0: 1; - uint32_t abs_done_1: 1; - uint32_t hard_disable_jtag: 1; - uint32_t disable_dl_encrypt: 1; - uint32_t disable_dl_decrypt: 1; - uint32_t disable_dl_cache: 1; - uint32_t key_status: 1; - uint32_t reserved11: 21; + uint32_t spi_pad_conf_1:20; + uint32_t clk8m_freq: 12; }; uint32_t val; - } blk0_wdata6; - uint32_t blk1_rdata0; /**/ - uint32_t blk1_rdata1; /**/ - uint32_t blk1_rdata2; /**/ - uint32_t blk1_rdata3; /**/ - uint32_t blk1_rdata4; /**/ - uint32_t blk1_rdata5; /**/ - uint32_t blk1_rdata6; /**/ - uint32_t blk1_rdata7; /**/ - uint32_t blk2_rdata0; /**/ - uint32_t blk2_rdata1; /**/ - uint32_t blk2_rdata2; /**/ - uint32_t blk2_rdata3; /**/ - uint32_t blk2_rdata4; /**/ - uint32_t blk2_rdata5; /**/ - uint32_t blk2_rdata6; /**/ - uint32_t blk2_rdata7; /**/ - uint32_t blk3_rdata0; /**/ - uint32_t blk3_rdata1; /**/ - uint32_t blk3_rdata2; /**/ - uint32_t blk3_rdata3; /**/ - uint32_t blk3_rdata4; /**/ - uint32_t blk3_rdata5; /**/ - uint32_t blk3_rdata6; /**/ - uint32_t blk3_rdata7; /**/ - uint32_t blk1_wdata0; /**/ - uint32_t blk1_wdata1; /**/ - uint32_t blk1_wdata2; /**/ - uint32_t blk1_wdata3; /**/ - uint32_t blk1_wdata4; /**/ - uint32_t blk1_wdata5; /**/ - uint32_t blk1_wdata6; /**/ - uint32_t blk1_wdata7; /**/ - uint32_t blk2_wdata0; /**/ - uint32_t blk2_wdata1; /**/ - uint32_t blk2_wdata2; /**/ - uint32_t blk2_wdata3; /**/ - uint32_t blk2_wdata4; /**/ - uint32_t blk2_wdata5; /**/ - uint32_t blk2_wdata6; /**/ - uint32_t blk2_wdata7; /**/ - uint32_t blk3_wdata0; /**/ - uint32_t blk3_wdata1; /**/ - uint32_t blk3_wdata2; /**/ - uint32_t blk3_wdata3; /**/ - uint32_t blk3_wdata4; /**/ - uint32_t blk3_wdata5; /**/ - uint32_t blk3_wdata6; /**/ - uint32_t blk3_wdata7; /**/ + } rd_mac_spi_8m_2; + uint32_t rd_mac_spi_8m_3; /**/ + uint32_t rd_mac_spi_8m_4; /**/ + uint32_t rd_mac_spi_8m_5; /**/ + uint32_t rd_sys_data0; /**/ + uint32_t rd_sys_data1; /**/ + uint32_t rd_sys_data2; /**/ + uint32_t rd_sys_data3; /**/ + uint32_t rd_sys_data4; /**/ + uint32_t rd_sys_data5; /**/ + uint32_t rd_sys_data6; /**/ + uint32_t rd_sys_data7; /**/ + uint32_t rd_usr_data0; /**/ + uint32_t rd_usr_data1; /**/ + uint32_t rd_usr_data2; /**/ + uint32_t rd_usr_data3; /**/ + uint32_t rd_usr_data4; /**/ + uint32_t rd_usr_data5; /**/ + uint32_t rd_usr_data6; /**/ + uint32_t rd_usr_data7; /**/ + uint32_t rd_key0_data0; /**/ + uint32_t rd_key0_data1; /**/ + uint32_t rd_key0_data2; /**/ + uint32_t rd_key0_data3; /**/ + uint32_t rd_key0_data4; /**/ + uint32_t rd_key0_data5; /**/ + uint32_t rd_key0_data6; /**/ + uint32_t rd_key0_data7; /**/ + uint32_t rd_key1_data0; /**/ + uint32_t rd_key1_data1; /**/ + uint32_t rd_key1_data2; /**/ + uint32_t rd_key1_data3; /**/ + uint32_t rd_key1_data4; /**/ + uint32_t rd_key1_data5; /**/ + uint32_t rd_key1_data6; /**/ + uint32_t rd_key1_data7; /**/ + uint32_t rd_key2_data0; /**/ + uint32_t rd_key2_data1; /**/ + uint32_t rd_key2_data2; /**/ + uint32_t rd_key2_data3; /**/ + uint32_t rd_key2_data4; /**/ + uint32_t rd_key2_data5; /**/ + uint32_t rd_key2_data6; /**/ + uint32_t rd_key2_data7; /**/ + uint32_t rd_key3_data0; /**/ + uint32_t rd_key3_data1; /**/ + uint32_t rd_key3_data2; /**/ + uint32_t rd_key3_data3; /**/ + uint32_t rd_key3_data4; /**/ + uint32_t rd_key3_data5; /**/ + uint32_t rd_key3_data6; /**/ + uint32_t rd_key3_data7; /**/ + uint32_t rd_key4_data0; /**/ + uint32_t rd_key4_data1; /**/ + uint32_t rd_key4_data2; /**/ + uint32_t rd_key4_data3; /**/ + uint32_t rd_key4_data4; /**/ + uint32_t rd_key4_data5; /**/ + uint32_t rd_key4_data6; /**/ + uint32_t rd_key4_data7; /**/ + uint32_t rd_key5_data0; /**/ + uint32_t rd_key5_data1; /**/ + uint32_t rd_key5_data2; /**/ + uint32_t rd_key5_data3; /**/ + uint32_t rd_key5_data4; /**/ + uint32_t rd_key5_data5; /**/ + uint32_t rd_key5_data6; /**/ + uint32_t rd_key5_data7; /**/ + uint32_t rd_key6_data0; /**/ + uint32_t rd_key6_data1; /**/ + uint32_t rd_key6_data2; /**/ + uint32_t rd_key6_data3; /**/ + uint32_t rd_key6_data4; /**/ + uint32_t rd_key6_data5; /**/ + uint32_t rd_key6_data6; /**/ + uint32_t rd_key6_data7; /**/ union { struct { - uint32_t reserved0: 16; + uint32_t rd_rd_dis_err: 7; + uint32_t rd_dis_rtc_ram_boot_err: 1; + uint32_t rd_dis_icache_err: 1; + uint32_t rd_dis_dcache_err: 1; + uint32_t rd_dis_download_icache_err: 1; + uint32_t rd_dis_download_dcache_err: 1; + uint32_t rd_dis_force_download: 1; + uint32_t rd_dis_usb_err: 1; + uint32_t rd_dis_can_err: 1; + uint32_t rd_dis_sdio_access_err: 1; + uint32_t rd_dis_efuse_ate_wr_err: 1; + uint32_t rd_soft_dis_jtag_err: 1; + uint32_t rd_hard_dis_jtag_err: 1; + uint32_t rd_dis_download_manual_encrypt_err: 1; + uint32_t rd_usb_drefh_err: 2; + uint32_t rd_usb_drefl_err: 2; + uint32_t rd_usb_exchg_pins_err: 1; + uint32_t rd_ext_phy_enable: 1; + uint32_t rd_usb_force: 1; + uint32_t rd_usb_dres_err: 2; + uint32_t rd_sdio_modecurlim_err: 1; + uint32_t rd_sdio_drefh_err: 2; + }; + uint32_t val; + } rd_repeat_err0; + union { + struct { + uint32_t rd_sdio_drefm_err: 2; + uint32_t rd_sdio_drefl_err: 2; + uint32_t rd_sdio_xpd_err: 1; + uint32_t rd_sdio_tieh_err: 1; + uint32_t rd_sdio_force_err: 1; + uint32_t rd_sdio_en_init_err: 1; + uint32_t rd_sdio_encurlim_err: 1; + uint32_t rd_sdio_dcurlim_err: 3; + uint32_t rd_sdio_init_err: 2; + uint32_t rd_sdio_dcap_err: 2; + uint32_t rd_wdt_delay_sel_err: 2; + uint32_t rd_spi_boot_crypt_cnt_err: 3; + uint32_t rd_secure_boot_key_revoke0_err: 1; + uint32_t rd_secure_boot_key_revoke1_err: 1; + uint32_t rd_secure_boot_key_revoke2_err: 1; + uint32_t rd_key_purpose_0_err: 4; + uint32_t rd_key_purpose_1_err: 4; + }; + uint32_t val; + } rd_repeat_err1; + union { + struct { + uint32_t rd_key_purpose_2_err: 4; + uint32_t rd_key_purpose_3_err: 4; + uint32_t rd_key_purpose_4_err: 4; + uint32_t rd_key_purpose_5_err: 4; + uint32_t rd_key_purpose_6_err: 4; + uint32_t rd_secure_boot_en_err: 1; + uint32_t rd_secure_boot_aggressive_revoke_err: 1; + uint32_t rd_xtal_freq_err: 6; + uint32_t rd_flash_tpuw_err: 4; + }; + uint32_t val; + } rd_repeat_err2; + union { + struct { + uint32_t rd_dis_download_mode_err: 1; + uint32_t rd_dis_legacy_spi_boot_err: 1; + uint32_t rd_uart_print_channel: 1; + uint32_t rd_dis_tiny_basic: 1; + uint32_t rd_dis_usb_download_mode: 1; + uint32_t rd_enable_security_download: 1; + uint32_t rd_uart_print_control: 2; + uint32_t rd_reserve_err: 24; + }; + uint32_t val; + } rd_repeat_err3; + uint32_t reserved_18c; + union { + struct { + uint32_t rd_chip_version_err:24; + uint32_t reserved24: 8; + }; + uint32_t val; + } rd_repeat_err4; + union { + struct { + uint32_t rd_mac_spi_8m_err_num: 3; + uint32_t rd_mac_spi_8m_fail: 1; + uint32_t rd_sys_err_num: 3; + uint32_t rd_sys_err_fail: 1; + uint32_t rd_usr_data_err_num: 3; + uint32_t rd_usr_data_fail: 1; + uint32_t rd_key0_err_num: 3; + uint32_t rd_key0_fail: 1; + uint32_t rd_key1_err_num: 3; + uint32_t rd_key1_fail: 1; + uint32_t rd_key2_err_num: 3; + uint32_t rd_key2_fail: 1; + uint32_t rd_key3_err_num: 3; + uint32_t rd_key3_fail: 1; + uint32_t rd_key4_err_num: 3; + uint32_t rd_key4_fail: 1; + }; + uint32_t val; + } rd_rs_err0; + union { + struct { + uint32_t rd_key5_err_num: 3; + uint32_t rd_key5_fail: 1; + uint32_t rd_key6_err_num: 3; + uint32_t rd_key6_fail: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } rd_rs_err1; + union { + struct { + uint32_t mem_pd: 1; + uint32_t reserved1: 15; uint32_t clk_en: 1; uint32_t reserved17:15; }; @@ -208,18 +407,31 @@ typedef volatile struct { } clk; union { struct { - uint32_t op_code: 16; - uint32_t force_no_wr_rd_dis: 1; - uint32_t reserved17: 15; + uint32_t op_code: 16; + uint32_t reserved16:16; }; uint32_t val; } conf; - uint32_t status; /**/ + union { + struct { + uint32_t state: 3; + uint32_t otp_load_sw: 1; + uint32_t otp_vddq_c_sync2: 1; + uint32_t otp_strobe_sw: 1; + uint32_t otp_csb_sw: 1; + uint32_t otp_pgenb_sw: 1; + uint32_t otp_vddq_is_sw: 1; + uint32_t repeat_err_cnt: 8; + uint32_t reserved17: 15; + }; + uint32_t val; + } status; union { struct { uint32_t read_cmd: 1; uint32_t pgm_cmd: 1; - uint32_t reserved2: 30; + uint32_t blk_num: 4; + uint32_t reserved6: 26; }; uint32_t val; } cmd; @@ -263,13 +475,6 @@ typedef volatile struct { }; uint32_t val; } dac_conf; - union { - struct { - uint32_t dec_warnings:12; - uint32_t reserved12: 20; - }; - uint32_t val; - } dec_status; union { struct { uint32_t thr_a: 8; @@ -295,96 +500,6 @@ typedef volatile struct { }; uint32_t val; } wr_tim_conf1; - union { - struct { - uint32_t rd_dis_err: 4; - uint32_t chip_ver_reserve_err:13; - uint32_t ck8m_freq_err: 8; - uint32_t sdio_drefh_err: 2; - uint32_t sdio_drefm_err: 2; - uint32_t sdio_drefl_err: 2; - uint32_t key_status_err: 1; - }; - uint32_t val; - } repeat_err0; - union { - struct { - uint32_t spi_pad_config_err: 20; - uint32_t flash_crypt_config_err: 4; - uint32_t tsens_dos_err: 4; - uint32_t reserve_use1_err: 4; - }; - uint32_t val; - } repeat_err1; - union { - struct { - uint32_t abs_done_0_err: 1; - uint32_t abs_done_1_err: 1; - uint32_t hard_disable_jtag_err: 1; - uint32_t disable_dl_encrypt_err: 1; - uint32_t disable_dl_decrypt_err: 1; - uint32_t disable_dl_cache_err: 1; - uint32_t disable_sdio_host_err: 1; - uint32_t dig_reserve_err: 1; - uint32_t soft_disable_jtag_err: 1; - uint32_t chip_ver_dis_bt_err: 1; - uint32_t chip_ver_32pad_err: 1; - uint32_t chip_ver_dis_cache_err: 1; - uint32_t xpd_sdio_err: 1; - uint32_t sdio_tieh_err: 1; - uint32_t sdio_force_err: 1; - uint32_t reserved15: 17; - }; - uint32_t val; - } repeat_err2; - uint32_t repeat_blk1_err0; /**/ - uint32_t repeat_blk1_err1; /**/ - uint32_t repeat_blk1_err2; /**/ - uint32_t repeat_blk1_err3; /**/ - uint32_t repeat_blk2_err0; /**/ - uint32_t repeat_blk2_err1; /**/ - uint32_t repeat_blk2_err2; /**/ - uint32_t repeat_blk2_err3; /**/ - uint32_t repeat_blk3_err0; /**/ - uint32_t repeat_blk3_err1; /**/ - uint32_t repeat_blk3_err2; /**/ - uint32_t repeat_blk3_err3; /**/ - union { - struct { - uint32_t rs_errornum_blk1: 4; - uint32_t rs_fail_blk1: 1; - uint32_t rs_errornum_blk2: 4; - uint32_t rs_fail_blk2: 1; - uint32_t rs_errornum_blk3: 4; - uint32_t rs_fail_blk3: 1; - uint32_t reserved15: 17; - }; - uint32_t val; - } rs_state; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; uint32_t reserved_1cc; uint32_t reserved_1d0; uint32_t reserved_1d4; @@ -397,7 +512,7 @@ typedef volatile struct { uint32_t reserved_1f0; uint32_t reserved_1f4; uint32_t reserved_1f8; - uint32_t date; /**/ + uint32_t date; /**/ } efuse_dev_t; extern efuse_dev_t EFUSE; #ifdef __cplusplus diff --git a/components/soc/esp32s2beta/include/soc/extmem_reg.h b/components/soc/esp32s2beta/include/soc/extmem_reg.h index 815cde7cc5..f36554ca4f 100644 --- a/components/soc/esp32s2beta/include/soc/extmem_reg.h +++ b/components/soc/esp32s2beta/include/soc/extmem_reg.h @@ -19,1430 +19,1654 @@ extern "C" { #endif #include "soc.h" -#define DPORT_PRO_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) -/* DPORT_PRO_DCACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_UNLOCK_DONE (BIT(23)) -#define DPORT_PRO_DCACHE_UNLOCK_DONE_M (BIT(23)) -#define DPORT_PRO_DCACHE_UNLOCK_DONE_V 0x1 -#define DPORT_PRO_DCACHE_UNLOCK_DONE_S 23 -/* DPORT_PRO_DCACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_UNLOCK_ENA (BIT(22)) -#define DPORT_PRO_DCACHE_UNLOCK_ENA_M (BIT(22)) -#define DPORT_PRO_DCACHE_UNLOCK_ENA_V 0x1 -#define DPORT_PRO_DCACHE_UNLOCK_ENA_S 22 -/* DPORT_PRO_DCACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_DONE (BIT(21)) -#define DPORT_PRO_DCACHE_PRELOAD_DONE_M (BIT(21)) -#define DPORT_PRO_DCACHE_PRELOAD_DONE_V 0x1 -#define DPORT_PRO_DCACHE_PRELOAD_DONE_S 21 -/* DPORT_PRO_DCACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_ENA (BIT(20)) -#define DPORT_PRO_DCACHE_PRELOAD_ENA_M (BIT(20)) -#define DPORT_PRO_DCACHE_PRELOAD_ENA_V 0x1 -#define DPORT_PRO_DCACHE_PRELOAD_ENA_S 20 -/* DPORT_PRO_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_DONE (BIT(19)) -#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_M (BIT(19)) -#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_V 0x1 -#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_S 19 -/* DPORT_PRO_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_ENA (BIT(18)) -#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_M (BIT(18)) -#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_V 0x1 -#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_S 18 -/* DPORT_PRO_DCACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_LOCK1_EN (BIT(15)) -#define DPORT_PRO_DCACHE_LOCK1_EN_M (BIT(15)) -#define DPORT_PRO_DCACHE_LOCK1_EN_V 0x1 -#define DPORT_PRO_DCACHE_LOCK1_EN_S 15 -/* DPORT_PRO_DCACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_LOCK0_EN (BIT(14)) -#define DPORT_PRO_DCACHE_LOCK0_EN_M (BIT(14)) -#define DPORT_PRO_DCACHE_LOCK0_EN_V 0x1 -#define DPORT_PRO_DCACHE_LOCK0_EN_S 14 -/* DPORT_PRO_DCACHE_CLEAN_DONE : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_CLEAN_DONE (BIT(13)) -#define DPORT_PRO_DCACHE_CLEAN_DONE_M (BIT(13)) -#define DPORT_PRO_DCACHE_CLEAN_DONE_V 0x1 -#define DPORT_PRO_DCACHE_CLEAN_DONE_S 13 -/* DPORT_PRO_DCACHE_CLEAN_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_CLEAN_ENA (BIT(12)) -#define DPORT_PRO_DCACHE_CLEAN_ENA_M (BIT(12)) -#define DPORT_PRO_DCACHE_CLEAN_ENA_V 0x1 -#define DPORT_PRO_DCACHE_CLEAN_ENA_S 12 -/* DPORT_PRO_DCACHE_FLUSH_DONE : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_FLUSH_DONE (BIT(11)) -#define DPORT_PRO_DCACHE_FLUSH_DONE_M (BIT(11)) -#define DPORT_PRO_DCACHE_FLUSH_DONE_V 0x1 -#define DPORT_PRO_DCACHE_FLUSH_DONE_S 11 -/* DPORT_PRO_DCACHE_FLUSH_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_FLUSH_ENA (BIT(10)) -#define DPORT_PRO_DCACHE_FLUSH_ENA_M (BIT(10)) -#define DPORT_PRO_DCACHE_FLUSH_ENA_V 0x1 -#define DPORT_PRO_DCACHE_FLUSH_ENA_S 10 -/* DPORT_PRO_DCACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_INVALIDATE_DONE (BIT(9)) -#define DPORT_PRO_DCACHE_INVALIDATE_DONE_M (BIT(9)) -#define DPORT_PRO_DCACHE_INVALIDATE_DONE_V 0x1 -#define DPORT_PRO_DCACHE_INVALIDATE_DONE_S 9 -/* DPORT_PRO_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_INVALIDATE_ENA (BIT(8)) -#define DPORT_PRO_DCACHE_INVALIDATE_ENA_M (BIT(8)) -#define DPORT_PRO_DCACHE_INVALIDATE_ENA_V 0x1 -#define DPORT_PRO_DCACHE_INVALIDATE_ENA_S 8 -/* DPORT_PRO_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE 0x00000003 -#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_M ((DPORT_PRO_DCACHE_BLOCKSIZE_MODE_V)<<(DPORT_PRO_DCACHE_BLOCKSIZE_MODE_S)) -#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_V 0x3 -#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_S 3 -/* DPORT_PRO_DCACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_SETSIZE_MODE (BIT(2)) -#define DPORT_PRO_DCACHE_SETSIZE_MODE_M (BIT(2)) -#define DPORT_PRO_DCACHE_SETSIZE_MODE_V 0x1 -#define DPORT_PRO_DCACHE_SETSIZE_MODE_S 2 -/* DPORT_PRO_DCACHE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MODE (BIT(1)) -#define DPORT_PRO_DCACHE_MODE_M (BIT(1)) -#define DPORT_PRO_DCACHE_MODE_V 0x1 -#define DPORT_PRO_DCACHE_MODE_S 1 -/* DPORT_PRO_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_ENABLE (BIT(0)) -#define DPORT_PRO_DCACHE_ENABLE_M (BIT(0)) -#define DPORT_PRO_DCACHE_ENABLE_V 0x1 -#define DPORT_PRO_DCACHE_ENABLE_S 0 - -#define DPORT_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) -/* DPORT_PRO_DCACHE_MASK_BUS3 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MASK_BUS3 (BIT(3)) -#define DPORT_PRO_DCACHE_MASK_BUS3_M (BIT(3)) -#define DPORT_PRO_DCACHE_MASK_BUS3_V 0x1 -#define DPORT_PRO_DCACHE_MASK_BUS3_S 3 -/* DPORT_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MASK_BUS2 (BIT(2)) -#define DPORT_PRO_DCACHE_MASK_BUS2_M (BIT(2)) -#define DPORT_PRO_DCACHE_MASK_BUS2_V 0x1 -#define DPORT_PRO_DCACHE_MASK_BUS2_S 2 -/* DPORT_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MASK_BUS1 (BIT(1)) -#define DPORT_PRO_DCACHE_MASK_BUS1_M (BIT(1)) -#define DPORT_PRO_DCACHE_MASK_BUS1_V 0x1 -#define DPORT_PRO_DCACHE_MASK_BUS1_S 1 -/* DPORT_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MASK_BUS0 (BIT(0)) -#define DPORT_PRO_DCACHE_MASK_BUS0_M (BIT(0)) -#define DPORT_PRO_DCACHE_MASK_BUS0_V 0x1 -#define DPORT_PRO_DCACHE_MASK_BUS0_S 0 -#define DPORT_PRO_DCACHE_MASK_DRAM0 DPORT_PRO_DCACHE_MASK_BUS0 -#define DPORT_PRO_DCACHE_MASK_DRAM1 DPORT_PRO_DCACHE_MASK_BUS1 -#define DPORT_PRO_DCACHE_MASK_DPORT DPORT_PRO_DCACHE_MASK_BUS2 -#define DPORT_PRO_DCACHE_MASK_DROM0 DPORT_PRO_DCACHE_MASK_BUS3 - -#define DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) -/* DPORT_PRO_DCACHE_TAG_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_TAG_MEM_PD (BIT(1)) -#define DPORT_PRO_DCACHE_TAG_MEM_PD_M (BIT(1)) -#define DPORT_PRO_DCACHE_TAG_MEM_PD_V 0x1 -#define DPORT_PRO_DCACHE_TAG_MEM_PD_S 1 -/* DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0)) -#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_V 0x1 -#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_S 0 - -#define DPORT_PRO_DCACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x00C) -/* DPORT_PRO_DCACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_LOCK0_ADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_LOCK0_ADDR_M ((DPORT_PRO_DCACHE_LOCK0_ADDR_V)<<(DPORT_PRO_DCACHE_LOCK0_ADDR_S)) -#define DPORT_PRO_DCACHE_LOCK0_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_LOCK0_ADDR_S 0 - -#define DPORT_PRO_DCACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x010) -/* DPORT_PRO_DCACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_LOCK0_SIZE 0x0000FFFF -#define DPORT_PRO_DCACHE_LOCK0_SIZE_M ((DPORT_PRO_DCACHE_LOCK0_SIZE_V)<<(DPORT_PRO_DCACHE_LOCK0_SIZE_S)) -#define DPORT_PRO_DCACHE_LOCK0_SIZE_V 0xFFFF -#define DPORT_PRO_DCACHE_LOCK0_SIZE_S 0 - -#define DPORT_PRO_DCACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) -/* DPORT_PRO_DCACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_LOCK1_ADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_LOCK1_ADDR_M ((DPORT_PRO_DCACHE_LOCK1_ADDR_V)<<(DPORT_PRO_DCACHE_LOCK1_ADDR_S)) -#define DPORT_PRO_DCACHE_LOCK1_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_LOCK1_ADDR_S 0 - -#define DPORT_PRO_DCACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) -/* DPORT_PRO_DCACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_LOCK1_SIZE 0x0000FFFF -#define DPORT_PRO_DCACHE_LOCK1_SIZE_M ((DPORT_PRO_DCACHE_LOCK1_SIZE_V)<<(DPORT_PRO_DCACHE_LOCK1_SIZE_S)) -#define DPORT_PRO_DCACHE_LOCK1_SIZE_V 0xFFFF -#define DPORT_PRO_DCACHE_LOCK1_SIZE_S 0 - -#define DPORT_PRO_DCACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x01C) -/* DPORT_PRO_DCACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MEMSYNC_ADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_M ((DPORT_PRO_DCACHE_MEMSYNC_ADDR_V)<<(DPORT_PRO_DCACHE_MEMSYNC_ADDR_S)) -#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_S 0 - -#define DPORT_PRO_DCACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x020) -/* DPORT_PRO_DCACHE_MEMSYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h400000 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_MEMSYNC_SIZE 0x007FFFFF -#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_M ((DPORT_PRO_DCACHE_MEMSYNC_SIZE_V)<<(DPORT_PRO_DCACHE_MEMSYNC_SIZE_S)) -#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_V 0x7FFFFF -#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_S 0 - -#define DPORT_PRO_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x024) -/* DPORT_PRO_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_ADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_PRELOAD_ADDR_M ((DPORT_PRO_DCACHE_PRELOAD_ADDR_V)<<(DPORT_PRO_DCACHE_PRELOAD_ADDR_S)) -#define DPORT_PRO_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_PRELOAD_ADDR_S 0 - -#define DPORT_PRO_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x028) -/* DPORT_PRO_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_ORDER (BIT(16)) -#define DPORT_PRO_DCACHE_PRELOAD_ORDER_M (BIT(16)) -#define DPORT_PRO_DCACHE_PRELOAD_ORDER_V 0x1 -#define DPORT_PRO_DCACHE_PRELOAD_ORDER_S 16 -/* DPORT_PRO_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h8000 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_SIZE 0x0000FFFF -#define DPORT_PRO_DCACHE_PRELOAD_SIZE_M ((DPORT_PRO_DCACHE_PRELOAD_SIZE_V)<<(DPORT_PRO_DCACHE_PRELOAD_SIZE_S)) -#define DPORT_PRO_DCACHE_PRELOAD_SIZE_V 0xFFFF -#define DPORT_PRO_DCACHE_PRELOAD_SIZE_S 0 - -#define DPORT_PRO_DCACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x02C) -/* DPORT_PRO_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[21:6] ;default: 16'h1 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE 0x0000FFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_M ((DPORT_PRO_DCACHE_AUTOLOAD_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SIZE_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_V 0xFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_S 6 -/* DPORT_PRO_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_RQST 0x00000003 -#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_M ((DPORT_PRO_DCACHE_AUTOLOAD_RQST_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_RQST_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_V 0x3 -#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_S 4 -/* DPORT_PRO_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER (BIT(3)) -#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_M (BIT(3)) -#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_V 0x1 -#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_S 3 -/* DPORT_PRO_DCACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_STEP 0x00000003 -#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_M ((DPORT_PRO_DCACHE_AUTOLOAD_STEP_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_STEP_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_V 0x3 -#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_S 1 -/* DPORT_PRO_DCACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_MODE (BIT(0)) -#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_M (BIT(0)) -#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_V 0x1 -#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_S 0 - -#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x030) -/* DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M ((DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 - -#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x034) -/* DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M ((DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 - -#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) -/* DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M ((DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 - -#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) -/* DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M ((DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S)) -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF -#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 - -#define DPORT_PRO_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) -/* DPORT_PRO_ICACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_UNLOCK_DONE (BIT(23)) -#define DPORT_PRO_ICACHE_UNLOCK_DONE_M (BIT(23)) -#define DPORT_PRO_ICACHE_UNLOCK_DONE_V 0x1 -#define DPORT_PRO_ICACHE_UNLOCK_DONE_S 23 -/* DPORT_PRO_ICACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_UNLOCK_ENA (BIT(22)) -#define DPORT_PRO_ICACHE_UNLOCK_ENA_M (BIT(22)) -#define DPORT_PRO_ICACHE_UNLOCK_ENA_V 0x1 -#define DPORT_PRO_ICACHE_UNLOCK_ENA_S 22 -/* DPORT_PRO_ICACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_DONE (BIT(21)) -#define DPORT_PRO_ICACHE_PRELOAD_DONE_M (BIT(21)) -#define DPORT_PRO_ICACHE_PRELOAD_DONE_V 0x1 -#define DPORT_PRO_ICACHE_PRELOAD_DONE_S 21 -/* DPORT_PRO_ICACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_ENA (BIT(20)) -#define DPORT_PRO_ICACHE_PRELOAD_ENA_M (BIT(20)) -#define DPORT_PRO_ICACHE_PRELOAD_ENA_V 0x1 -#define DPORT_PRO_ICACHE_PRELOAD_ENA_S 20 -/* DPORT_PRO_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_DONE (BIT(19)) -#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_M (BIT(19)) -#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_V 0x1 -#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_S 19 -/* DPORT_PRO_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_ENA (BIT(18)) -#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_M (BIT(18)) -#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_V 0x1 -#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_S 18 -/* DPORT_PRO_ICACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_LOCK1_EN (BIT(15)) -#define DPORT_PRO_ICACHE_LOCK1_EN_M (BIT(15)) -#define DPORT_PRO_ICACHE_LOCK1_EN_V 0x1 -#define DPORT_PRO_ICACHE_LOCK1_EN_S 15 -/* DPORT_PRO_ICACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_LOCK0_EN (BIT(14)) -#define DPORT_PRO_ICACHE_LOCK0_EN_M (BIT(14)) -#define DPORT_PRO_ICACHE_LOCK0_EN_V 0x1 -#define DPORT_PRO_ICACHE_LOCK0_EN_S 14 -/* DPORT_PRO_ICACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_INVALIDATE_DONE (BIT(9)) -#define DPORT_PRO_ICACHE_INVALIDATE_DONE_M (BIT(9)) -#define DPORT_PRO_ICACHE_INVALIDATE_DONE_V 0x1 -#define DPORT_PRO_ICACHE_INVALIDATE_DONE_S 9 -/* DPORT_PRO_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_INVALIDATE_ENA (BIT(8)) -#define DPORT_PRO_ICACHE_INVALIDATE_ENA_M (BIT(8)) -#define DPORT_PRO_ICACHE_INVALIDATE_ENA_V 0x1 -#define DPORT_PRO_ICACHE_INVALIDATE_ENA_S 8 -/* DPORT_PRO_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE 0x00000003 -#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_M ((DPORT_PRO_ICACHE_BLOCKSIZE_MODE_V)<<(DPORT_PRO_ICACHE_BLOCKSIZE_MODE_S)) -#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_V 0x3 -#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_S 3 -/* DPORT_PRO_ICACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_SETSIZE_MODE (BIT(2)) -#define DPORT_PRO_ICACHE_SETSIZE_MODE_M (BIT(2)) -#define DPORT_PRO_ICACHE_SETSIZE_MODE_V 0x1 -#define DPORT_PRO_ICACHE_SETSIZE_MODE_S 2 -/* DPORT_PRO_ICACHE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MODE (BIT(1)) -#define DPORT_PRO_ICACHE_MODE_M (BIT(1)) -#define DPORT_PRO_ICACHE_MODE_V 0x1 -#define DPORT_PRO_ICACHE_MODE_S 1 -/* DPORT_PRO_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_ENABLE (BIT(0)) -#define DPORT_PRO_ICACHE_ENABLE_M (BIT(0)) -#define DPORT_PRO_ICACHE_ENABLE_V 0x1 -#define DPORT_PRO_ICACHE_ENABLE_S 0 - -#define DPORT_PRO_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x044) -/* DPORT_PRO_ICACHE_MASK_BUS3 : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MASK_BUS3 (BIT(3)) -#define DPORT_PRO_ICACHE_MASK_BUS3_M (BIT(3)) -#define DPORT_PRO_ICACHE_MASK_BUS3_V 0x1 -#define DPORT_PRO_ICACHE_MASK_BUS3_S 3 -/* DPORT_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MASK_BUS2 (BIT(2)) -#define DPORT_PRO_ICACHE_MASK_BUS2_M (BIT(2)) -#define DPORT_PRO_ICACHE_MASK_BUS2_V 0x1 -#define DPORT_PRO_ICACHE_MASK_BUS2_S 2 -/* DPORT_PRO_ICACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MASK_BUS1 (BIT(1)) -#define DPORT_PRO_ICACHE_MASK_BUS1_M (BIT(1)) -#define DPORT_PRO_ICACHE_MASK_BUS1_V 0x1 -#define DPORT_PRO_ICACHE_MASK_BUS1_S 1 -/* DPORT_PRO_ICACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MASK_BUS0 (BIT(0)) -#define DPORT_PRO_ICACHE_MASK_BUS0_M (BIT(0)) -#define DPORT_PRO_ICACHE_MASK_BUS0_V 0x1 -#define DPORT_PRO_ICACHE_MASK_BUS0_S 0 -#define DPORT_PRO_ICACHE_MASK_IRAM0 DPORT_PRO_ICACHE_MASK_BUS0 -#define DPORT_PRO_ICACHE_MASK_IRAM1 DPORT_PRO_ICACHE_MASK_BUS1 -#define DPORT_PRO_ICACHE_MASK_IROM0 DPORT_PRO_ICACHE_MASK_BUS2 -#define DPORT_PRO_ICACHE_MASK_DROM0 DPORT_PRO_ICACHE_MASK_BUS3 - -#define DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x048) -/* DPORT_PRO_ICACHE_TAG_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_TAG_MEM_PD (BIT(1)) -#define DPORT_PRO_ICACHE_TAG_MEM_PD_M (BIT(1)) -#define DPORT_PRO_ICACHE_TAG_MEM_PD_V 0x1 -#define DPORT_PRO_ICACHE_TAG_MEM_PD_S 1 -/* DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) -#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_V 0x1 -#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_S 0 - -#define DPORT_PRO_ICACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x04C) -/* DPORT_PRO_ICACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_LOCK0_ADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_LOCK0_ADDR_M ((DPORT_PRO_ICACHE_LOCK0_ADDR_V)<<(DPORT_PRO_ICACHE_LOCK0_ADDR_S)) -#define DPORT_PRO_ICACHE_LOCK0_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_LOCK0_ADDR_S 0 - -#define DPORT_PRO_ICACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x050) -/* DPORT_PRO_ICACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_LOCK0_SIZE 0x0000FFFF -#define DPORT_PRO_ICACHE_LOCK0_SIZE_M ((DPORT_PRO_ICACHE_LOCK0_SIZE_V)<<(DPORT_PRO_ICACHE_LOCK0_SIZE_S)) -#define DPORT_PRO_ICACHE_LOCK0_SIZE_V 0xFFFF -#define DPORT_PRO_ICACHE_LOCK0_SIZE_S 0 - -#define DPORT_PRO_ICACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x054) -/* DPORT_PRO_ICACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_LOCK1_ADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_LOCK1_ADDR_M ((DPORT_PRO_ICACHE_LOCK1_ADDR_V)<<(DPORT_PRO_ICACHE_LOCK1_ADDR_S)) -#define DPORT_PRO_ICACHE_LOCK1_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_LOCK1_ADDR_S 0 - -#define DPORT_PRO_ICACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x058) -/* DPORT_PRO_ICACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_LOCK1_SIZE 0x0000FFFF -#define DPORT_PRO_ICACHE_LOCK1_SIZE_M ((DPORT_PRO_ICACHE_LOCK1_SIZE_V)<<(DPORT_PRO_ICACHE_LOCK1_SIZE_S)) -#define DPORT_PRO_ICACHE_LOCK1_SIZE_V 0xFFFF -#define DPORT_PRO_ICACHE_LOCK1_SIZE_S 0 - -#define DPORT_PRO_ICACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x05C) -/* DPORT_PRO_ICACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MEMSYNC_ADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_M ((DPORT_PRO_ICACHE_MEMSYNC_ADDR_V)<<(DPORT_PRO_ICACHE_MEMSYNC_ADDR_S)) -#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_S 0 - -#define DPORT_PRO_ICACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x060) -/* DPORT_PRO_ICACHE_MEMSYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h400000 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_MEMSYNC_SIZE 0x007FFFFF -#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_M ((DPORT_PRO_ICACHE_MEMSYNC_SIZE_V)<<(DPORT_PRO_ICACHE_MEMSYNC_SIZE_S)) -#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_V 0x7FFFFF -#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_S 0 - -#define DPORT_PRO_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x064) -/* DPORT_PRO_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_ADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_PRELOAD_ADDR_M ((DPORT_PRO_ICACHE_PRELOAD_ADDR_V)<<(DPORT_PRO_ICACHE_PRELOAD_ADDR_S)) -#define DPORT_PRO_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_PRELOAD_ADDR_S 0 - -#define DPORT_PRO_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x068) -/* DPORT_PRO_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_ORDER (BIT(16)) -#define DPORT_PRO_ICACHE_PRELOAD_ORDER_M (BIT(16)) -#define DPORT_PRO_ICACHE_PRELOAD_ORDER_V 0x1 -#define DPORT_PRO_ICACHE_PRELOAD_ORDER_S 16 -/* DPORT_PRO_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h8000 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_SIZE 0x0000FFFF -#define DPORT_PRO_ICACHE_PRELOAD_SIZE_M ((DPORT_PRO_ICACHE_PRELOAD_SIZE_V)<<(DPORT_PRO_ICACHE_PRELOAD_SIZE_S)) -#define DPORT_PRO_ICACHE_PRELOAD_SIZE_V 0xFFFF -#define DPORT_PRO_ICACHE_PRELOAD_SIZE_S 0 - -#define DPORT_PRO_ICACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x06C) -/* DPORT_PRO_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[21:6] ;default: 16'h1 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE 0x0000FFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_M ((DPORT_PRO_ICACHE_AUTOLOAD_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SIZE_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_V 0xFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_S 6 -/* DPORT_PRO_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_RQST 0x00000003 -#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_M ((DPORT_PRO_ICACHE_AUTOLOAD_RQST_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_RQST_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_V 0x3 -#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_S 4 -/* DPORT_PRO_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER (BIT(3)) -#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_M (BIT(3)) -#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_V 0x1 -#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_S 3 -/* DPORT_PRO_ICACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_STEP 0x00000003 -#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_M ((DPORT_PRO_ICACHE_AUTOLOAD_STEP_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_STEP_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_V 0x3 -#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_S 1 -/* DPORT_PRO_ICACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_MODE (BIT(0)) -#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_M (BIT(0)) -#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_V 0x1 -#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_S 0 - -#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x070) -/* DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M ((DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 - -#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x074) -/* DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M ((DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 - -#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x078) -/* DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M ((DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 - -#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x07C) -/* DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M ((DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S)) -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF -#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 - -#define DPORT_IC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x080) -/* DPORT_IC_PRELOAD_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_CNT 0xFFFFFFFF -#define DPORT_IC_PRELOAD_CNT_M ((DPORT_IC_PRELOAD_CNT_V)<<(DPORT_IC_PRELOAD_CNT_S)) -#define DPORT_IC_PRELOAD_CNT_V 0xFFFFFFFF -#define DPORT_IC_PRELOAD_CNT_S 0 - -#define DPORT_IC_PRELOAD_EVICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x084) -/* DPORT_IC_PRELOAD_EVICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_EVICT_CNT 0xFFFFFFFF -#define DPORT_IC_PRELOAD_EVICT_CNT_M ((DPORT_IC_PRELOAD_EVICT_CNT_V)<<(DPORT_IC_PRELOAD_EVICT_CNT_S)) -#define DPORT_IC_PRELOAD_EVICT_CNT_V 0xFFFFFFFF -#define DPORT_IC_PRELOAD_EVICT_CNT_S 0 - -#define DPORT_IC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x088) -/* DPORT_IC_PRELOAD_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_MISS_CNT 0xFFFFFFFF -#define DPORT_IC_PRELOAD_MISS_CNT_M ((DPORT_IC_PRELOAD_MISS_CNT_V)<<(DPORT_IC_PRELOAD_MISS_CNT_S)) -#define DPORT_IC_PRELOAD_MISS_CNT_V 0xFFFFFFFF -#define DPORT_IC_PRELOAD_MISS_CNT_S 0 - -#define DPORT_IBUS3_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x08C) -/* DPORT_IBUS3_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS3_ABANDON_CNT 0xFFFFFFFF -#define DPORT_IBUS3_ABANDON_CNT_M ((DPORT_IBUS3_ABANDON_CNT_V)<<(DPORT_IBUS3_ABANDON_CNT_S)) -#define DPORT_IBUS3_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_IBUS3_ABANDON_CNT_S 0 - -#define DPORT_IBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x090) -/* DPORT_IBUS2_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS2_ABANDON_CNT 0xFFFFFFFF -#define DPORT_IBUS2_ABANDON_CNT_M ((DPORT_IBUS2_ABANDON_CNT_V)<<(DPORT_IBUS2_ABANDON_CNT_S)) -#define DPORT_IBUS2_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_IBUS2_ABANDON_CNT_S 0 - -#define DPORT_IBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x094) -/* DPORT_IBUS1_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS1_ABANDON_CNT 0xFFFFFFFF -#define DPORT_IBUS1_ABANDON_CNT_M ((DPORT_IBUS1_ABANDON_CNT_V)<<(DPORT_IBUS1_ABANDON_CNT_S)) -#define DPORT_IBUS1_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_IBUS1_ABANDON_CNT_S 0 - -#define DPORT_IBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x098) -/* DPORT_IBUS0_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS0_ABANDON_CNT 0xFFFFFFFF -#define DPORT_IBUS0_ABANDON_CNT_M ((DPORT_IBUS0_ABANDON_CNT_V)<<(DPORT_IBUS0_ABANDON_CNT_S)) -#define DPORT_IBUS0_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_IBUS0_ABANDON_CNT_S 0 - -#define DPORT_IBUS3_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x09C) -/* DPORT_IBUS3_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS3_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_IBUS3_ACS_MISS_CNT_M ((DPORT_IBUS3_ACS_MISS_CNT_V)<<(DPORT_IBUS3_ACS_MISS_CNT_S)) -#define DPORT_IBUS3_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS3_ACS_MISS_CNT_S 0 - -#define DPORT_IBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A0) -/* DPORT_IBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS2_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_IBUS2_ACS_MISS_CNT_M ((DPORT_IBUS2_ACS_MISS_CNT_V)<<(DPORT_IBUS2_ACS_MISS_CNT_S)) -#define DPORT_IBUS2_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS2_ACS_MISS_CNT_S 0 - -#define DPORT_IBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A4) -/* DPORT_IBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS1_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_IBUS1_ACS_MISS_CNT_M ((DPORT_IBUS1_ACS_MISS_CNT_V)<<(DPORT_IBUS1_ACS_MISS_CNT_S)) -#define DPORT_IBUS1_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS1_ACS_MISS_CNT_S 0 - -#define DPORT_IBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A8) -/* DPORT_IBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS0_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_IBUS0_ACS_MISS_CNT_M ((DPORT_IBUS0_ACS_MISS_CNT_V)<<(DPORT_IBUS0_ACS_MISS_CNT_S)) -#define DPORT_IBUS0_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS0_ACS_MISS_CNT_S 0 - -#define DPORT_IBUS3_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0AC) -/* DPORT_IBUS3_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS3_ACS_CNT 0xFFFFFFFF -#define DPORT_IBUS3_ACS_CNT_M ((DPORT_IBUS3_ACS_CNT_V)<<(DPORT_IBUS3_ACS_CNT_S)) -#define DPORT_IBUS3_ACS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS3_ACS_CNT_S 0 - -#define DPORT_IBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B0) -/* DPORT_IBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS2_ACS_CNT 0xFFFFFFFF -#define DPORT_IBUS2_ACS_CNT_M ((DPORT_IBUS2_ACS_CNT_V)<<(DPORT_IBUS2_ACS_CNT_S)) -#define DPORT_IBUS2_ACS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS2_ACS_CNT_S 0 - -#define DPORT_IBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B4) -/* DPORT_IBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS1_ACS_CNT 0xFFFFFFFF -#define DPORT_IBUS1_ACS_CNT_M ((DPORT_IBUS1_ACS_CNT_V)<<(DPORT_IBUS1_ACS_CNT_S)) -#define DPORT_IBUS1_ACS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS1_ACS_CNT_S 0 - -#define DPORT_IBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B8) -/* DPORT_IBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_IBUS0_ACS_CNT 0xFFFFFFFF -#define DPORT_IBUS0_ACS_CNT_M ((DPORT_IBUS0_ACS_CNT_V)<<(DPORT_IBUS0_ACS_CNT_S)) -#define DPORT_IBUS0_ACS_CNT_V 0xFFFFFFFF -#define DPORT_IBUS0_ACS_CNT_S 0 - -#define DPORT_DC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x0BC) -/* DPORT_DC_PRELOAD_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_CNT 0xFFFFFFFF -#define DPORT_DC_PRELOAD_CNT_M ((DPORT_DC_PRELOAD_CNT_V)<<(DPORT_DC_PRELOAD_CNT_S)) -#define DPORT_DC_PRELOAD_CNT_V 0xFFFFFFFF -#define DPORT_DC_PRELOAD_CNT_S 0 - -#define DPORT_DC_PRELOAD_EVICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C0) -/* DPORT_DC_PRELOAD_EVICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_EVICT_CNT 0xFFFFFFFF -#define DPORT_DC_PRELOAD_EVICT_CNT_M ((DPORT_DC_PRELOAD_EVICT_CNT_V)<<(DPORT_DC_PRELOAD_EVICT_CNT_S)) -#define DPORT_DC_PRELOAD_EVICT_CNT_V 0xFFFFFFFF -#define DPORT_DC_PRELOAD_EVICT_CNT_S 0 - -#define DPORT_DC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C4) -/* DPORT_DC_PRELOAD_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_MISS_CNT 0xFFFFFFFF -#define DPORT_DC_PRELOAD_MISS_CNT_M ((DPORT_DC_PRELOAD_MISS_CNT_V)<<(DPORT_DC_PRELOAD_MISS_CNT_S)) -#define DPORT_DC_PRELOAD_MISS_CNT_V 0xFFFFFFFF -#define DPORT_DC_PRELOAD_MISS_CNT_S 0 - -#define DPORT_DBUS3_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C8) -/* DPORT_DBUS3_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS3_ABANDON_CNT 0xFFFFFFFF -#define DPORT_DBUS3_ABANDON_CNT_M ((DPORT_DBUS3_ABANDON_CNT_V)<<(DPORT_DBUS3_ABANDON_CNT_S)) -#define DPORT_DBUS3_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_DBUS3_ABANDON_CNT_S 0 - -#define DPORT_DBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0CC) -/* DPORT_DBUS2_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS2_ABANDON_CNT 0xFFFFFFFF -#define DPORT_DBUS2_ABANDON_CNT_M ((DPORT_DBUS2_ABANDON_CNT_V)<<(DPORT_DBUS2_ABANDON_CNT_S)) -#define DPORT_DBUS2_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_DBUS2_ABANDON_CNT_S 0 - -#define DPORT_DBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D0) -/* DPORT_DBUS1_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS1_ABANDON_CNT 0xFFFFFFFF -#define DPORT_DBUS1_ABANDON_CNT_M ((DPORT_DBUS1_ABANDON_CNT_V)<<(DPORT_DBUS1_ABANDON_CNT_S)) -#define DPORT_DBUS1_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_DBUS1_ABANDON_CNT_S 0 - -#define DPORT_DBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D4) -/* DPORT_DBUS0_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS0_ABANDON_CNT 0xFFFFFFFF -#define DPORT_DBUS0_ABANDON_CNT_M ((DPORT_DBUS0_ABANDON_CNT_V)<<(DPORT_DBUS0_ABANDON_CNT_S)) -#define DPORT_DBUS0_ABANDON_CNT_V 0xFFFFFFFF -#define DPORT_DBUS0_ABANDON_CNT_S 0 - -#define DPORT_DBUS3_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D8) -/* DPORT_DBUS3_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_WB_CNT 0xFFFFFFFF -#define DPORT_DBUS3_ACS_WB_CNT_M ((DPORT_DBUS3_ACS_WB_CNT_V)<<(DPORT_DBUS3_ACS_WB_CNT_S)) -#define DPORT_DBUS3_ACS_WB_CNT_V 0xFFFFFFFF -#define DPORT_DBUS3_ACS_WB_CNT_S 0 - -#define DPORT_DBUS2_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0DC) -/* DPORT_DBUS2_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_WB_CNT 0xFFFFFFFF -#define DPORT_DBUS2_ACS_WB_CNT_M ((DPORT_DBUS2_ACS_WB_CNT_V)<<(DPORT_DBUS2_ACS_WB_CNT_S)) -#define DPORT_DBUS2_ACS_WB_CNT_V 0xFFFFFFFF -#define DPORT_DBUS2_ACS_WB_CNT_S 0 - -#define DPORT_DBUS1_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0E0) -/* DPORT_DBUS1_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_WB_CNT 0xFFFFFFFF -#define DPORT_DBUS1_ACS_WB_CNT_M ((DPORT_DBUS1_ACS_WB_CNT_V)<<(DPORT_DBUS1_ACS_WB_CNT_S)) -#define DPORT_DBUS1_ACS_WB_CNT_V 0xFFFFFFFF -#define DPORT_DBUS1_ACS_WB_CNT_S 0 - -#define DPORT_DBUS0_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0E4) -/* DPORT_DBUS0_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_WB_CNT 0xFFFFFFFF -#define DPORT_DBUS0_ACS_WB_CNT_M ((DPORT_DBUS0_ACS_WB_CNT_V)<<(DPORT_DBUS0_ACS_WB_CNT_S)) -#define DPORT_DBUS0_ACS_WB_CNT_V 0xFFFFFFFF -#define DPORT_DBUS0_ACS_WB_CNT_S 0 - -#define DPORT_DBUS3_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0E8) -/* DPORT_DBUS3_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_DBUS3_ACS_MISS_CNT_M ((DPORT_DBUS3_ACS_MISS_CNT_V)<<(DPORT_DBUS3_ACS_MISS_CNT_S)) -#define DPORT_DBUS3_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS3_ACS_MISS_CNT_S 0 - -#define DPORT_DBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0EC) -/* DPORT_DBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_DBUS2_ACS_MISS_CNT_M ((DPORT_DBUS2_ACS_MISS_CNT_V)<<(DPORT_DBUS2_ACS_MISS_CNT_S)) -#define DPORT_DBUS2_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS2_ACS_MISS_CNT_S 0 - -#define DPORT_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0F0) -/* DPORT_DBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_DBUS1_ACS_MISS_CNT_M ((DPORT_DBUS1_ACS_MISS_CNT_V)<<(DPORT_DBUS1_ACS_MISS_CNT_S)) -#define DPORT_DBUS1_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS1_ACS_MISS_CNT_S 0 - -#define DPORT_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0F4) -/* DPORT_DBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_MISS_CNT 0xFFFFFFFF -#define DPORT_DBUS0_ACS_MISS_CNT_M ((DPORT_DBUS0_ACS_MISS_CNT_V)<<(DPORT_DBUS0_ACS_MISS_CNT_S)) -#define DPORT_DBUS0_ACS_MISS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS0_ACS_MISS_CNT_S 0 - -#define DPORT_DBUS3_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0F8) -/* DPORT_DBUS3_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_CNT 0xFFFFFFFF -#define DPORT_DBUS3_ACS_CNT_M ((DPORT_DBUS3_ACS_CNT_V)<<(DPORT_DBUS3_ACS_CNT_S)) -#define DPORT_DBUS3_ACS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS3_ACS_CNT_S 0 - -#define DPORT_DBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0FC) -/* DPORT_DBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_CNT 0xFFFFFFFF -#define DPORT_DBUS2_ACS_CNT_M ((DPORT_DBUS2_ACS_CNT_V)<<(DPORT_DBUS2_ACS_CNT_S)) -#define DPORT_DBUS2_ACS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS2_ACS_CNT_S 0 - -#define DPORT_DBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x100) -/* DPORT_DBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_CNT 0xFFFFFFFF -#define DPORT_DBUS1_ACS_CNT_M ((DPORT_DBUS1_ACS_CNT_V)<<(DPORT_DBUS1_ACS_CNT_S)) -#define DPORT_DBUS1_ACS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS1_ACS_CNT_S 0 - -#define DPORT_DBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x104) -/* DPORT_DBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_CNT 0xFFFFFFFF -#define DPORT_DBUS0_ACS_CNT_M ((DPORT_DBUS0_ACS_CNT_V)<<(DPORT_DBUS0_ACS_CNT_S)) -#define DPORT_DBUS0_ACS_CNT_V 0xFFFFFFFF -#define DPORT_DBUS0_ACS_CNT_S 0 - -#define DPORT_PRO_CACHE_IA_INT_EN_REG DPORT_CACHE_DBG_INT_ENA_REG -#define DPORT_PRO_CACHE_INT_CLR DPORT_CACHE_DBG_INT_CLR -#define DPORT_PRO_CACHE_DBG_EN DPORT_CACHE_DBG_EN -#define DPORT_CACHE_DBG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x108) -/* DPORT_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_MMU_ENTRY_FAULT_INT_ENA (BIT(13)) -#define DPORT_MMU_ENTRY_FAULT_INT_ENA_M (BIT(13)) -#define DPORT_MMU_ENTRY_FAULT_INT_ENA_V 0x1 -#define DPORT_MMU_ENTRY_FAULT_INT_ENA_S 13 -/* DPORT_DCACHE_REJECT_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DCACHE_REJECT_INT_ENA (BIT(12)) -#define DPORT_DCACHE_REJECT_INT_ENA_M (BIT(12)) -#define DPORT_DCACHE_REJECT_INT_ENA_V 0x1 -#define DPORT_DCACHE_REJECT_INT_ENA_S 12 -/* DPORT_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DCACHE_WRITE_FLASH_INT_ENA (BIT(11)) -#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(11)) -#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_V 0x1 -#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_S 11 -/* DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(10)) -#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_M (BIT(10)) -#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x1 -#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_S 10 -/* DPORT_DC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA (BIT(9)) -#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_M (BIT(9)) -#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_V 0x1 -#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_S 9 -/* DPORT_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS_CNT_OVF_INT_ENA (BIT(8)) -#define DPORT_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) -#define DPORT_DBUS_CNT_OVF_INT_ENA_V 0x1 -#define DPORT_DBUS_CNT_OVF_INT_ENA_S 8 -/* DPORT_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS_ACS_MSK_IC_INT_ENA (BIT(7)) -#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(7)) -#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_V 0x1 -#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_S 7 -/* DPORT_ICACHE_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_ICACHE_REJECT_INT_ENA (BIT(6)) -#define DPORT_ICACHE_REJECT_INT_ENA_M (BIT(6)) -#define DPORT_ICACHE_REJECT_INT_ENA_V 0x1 -#define DPORT_ICACHE_REJECT_INT_ENA_S 6 -/* DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(5)) -#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_M (BIT(5)) -#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x1 -#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_S 5 -/* DPORT_IC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA (BIT(4)) -#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_M (BIT(4)) -#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_V 0x1 -#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_S 4 -/* DPORT_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS_CNT_OVF_INT_ENA (BIT(3)) -#define DPORT_IBUS_CNT_OVF_INT_ENA_M (BIT(3)) -#define DPORT_IBUS_CNT_OVF_INT_ENA_V 0x1 -#define DPORT_IBUS_CNT_OVF_INT_ENA_S 3 -/* DPORT_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS_ACS_MSK_IC_INT_ENA (BIT(2)) -#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(2)) -#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 -#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_S 2 -/* DPORT_CACHE_DBG_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CACHE_DBG_INT_CLR (BIT(1)) -#define DPORT_CACHE_DBG_INT_CLR_M (BIT(1)) -#define DPORT_CACHE_DBG_INT_CLR_V 0x1 -#define DPORT_CACHE_DBG_INT_CLR_S 1 -/* DPORT_CACHE_DBG_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_CACHE_DBG_EN (BIT(0)) -#define DPORT_CACHE_DBG_EN_M (BIT(0)) -#define DPORT_CACHE_DBG_EN_V 0x1 -#define DPORT_CACHE_DBG_EN_S 0 - -#define DPORT_CACHE_DBG_STATUS0_REG (DR_REG_EXTMEM_BASE + 0x10C) -/* DPORT_ICACHE_REJECT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_ICACHE_REJECT_ST (BIT(21)) -#define DPORT_ICACHE_REJECT_ST_M (BIT(21)) -#define DPORT_ICACHE_REJECT_ST_V 0x1 -#define DPORT_ICACHE_REJECT_ST_S 21 -/* DPORT_IC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_SIZE_FAULT_ST (BIT(20)) -#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_M (BIT(20)) -#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_V 0x1 -#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_S 20 -/* DPORT_IC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_SYNC_SIZE_FAULT_ST (BIT(19)) -#define DPORT_IC_SYNC_SIZE_FAULT_ST_M (BIT(19)) -#define DPORT_IC_SYNC_SIZE_FAULT_ST_V 0x1 -#define DPORT_IC_SYNC_SIZE_FAULT_ST_S 19 -/* DPORT_IC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_CNT_OVF_ST (BIT(18)) -#define DPORT_IC_PRELOAD_CNT_OVF_ST_M (BIT(18)) -#define DPORT_IC_PRELOAD_CNT_OVF_ST_V 0x1 -#define DPORT_IC_PRELOAD_CNT_OVF_ST_S 18 -/* DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST (BIT(17)) -#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_M (BIT(17)) -#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_V 0x1 -#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_S 17 -/* DPORT_IC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST (BIT(16)) -#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_M (BIT(16)) -#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_S 16 -/* DPORT_IBUS3_ABANDON_CNT_OVF_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS3_ABANDON_CNT_OVF_ST (BIT(15)) -#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_M (BIT(15)) -#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_S 15 -/* DPORT_IBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS2_ABANDON_CNT_OVF_ST (BIT(14)) -#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_M (BIT(14)) -#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_S 14 -/* DPORT_IBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS1_ABANDON_CNT_OVF_ST (BIT(13)) -#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_M (BIT(13)) -#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_S 13 -/* DPORT_IBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS0_ABANDON_CNT_OVF_ST (BIT(12)) -#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_M (BIT(12)) -#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_S 12 -/* DPORT_IBUS3_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST (BIT(11)) -#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_M (BIT(11)) -#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_S 11 -/* DPORT_IBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST (BIT(10)) -#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_M (BIT(10)) -#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_S 10 -/* DPORT_IBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST (BIT(9)) -#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_M (BIT(9)) -#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_S 9 -/* DPORT_IBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST (BIT(8)) -#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_M (BIT(8)) -#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_S 8 -/* DPORT_IBUS3_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS3_ACS_CNT_OVF_ST (BIT(7)) -#define DPORT_IBUS3_ACS_CNT_OVF_ST_M (BIT(7)) -#define DPORT_IBUS3_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS3_ACS_CNT_OVF_ST_S 7 -/* DPORT_IBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS2_ACS_CNT_OVF_ST (BIT(6)) -#define DPORT_IBUS2_ACS_CNT_OVF_ST_M (BIT(6)) -#define DPORT_IBUS2_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS2_ACS_CNT_OVF_ST_S 6 -/* DPORT_IBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS1_ACS_CNT_OVF_ST (BIT(5)) -#define DPORT_IBUS1_ACS_CNT_OVF_ST_M (BIT(5)) -#define DPORT_IBUS1_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS1_ACS_CNT_OVF_ST_S 5 -/* DPORT_IBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS0_ACS_CNT_OVF_ST (BIT(4)) -#define DPORT_IBUS0_ACS_CNT_OVF_ST_M (BIT(4)) -#define DPORT_IBUS0_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_IBUS0_ACS_CNT_OVF_ST_S 4 -/* DPORT_IBUS3_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS3_ACS_MSK_ICACHE_ST (BIT(3)) -#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_M (BIT(3)) -#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_V 0x1 -#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_S 3 -/* DPORT_IBUS2_ACS_MSK_ICACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS2_ACS_MSK_ICACHE_ST (BIT(2)) -#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_M (BIT(2)) -#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_V 0x1 -#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_S 2 -/* DPORT_IBUS1_ACS_MSK_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS1_ACS_MSK_ICACHE_ST (BIT(1)) -#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_M (BIT(1)) -#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_V 0x1 -#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_S 1 -/* DPORT_IBUS0_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_IBUS0_ACS_MSK_ICACHE_ST (BIT(0)) -#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_M (BIT(0)) -#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_V 0x1 -#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_S 0 - -#define DPORT_CACHE_DBG_STATUS1_REG (DR_REG_EXTMEM_BASE + 0x110) -/* DPORT_MMU_ENTRY_FAULT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_MMU_ENTRY_FAULT_ST (BIT(27)) -#define DPORT_MMU_ENTRY_FAULT_ST_M (BIT(27)) -#define DPORT_MMU_ENTRY_FAULT_ST_V 0x1 -#define DPORT_MMU_ENTRY_FAULT_ST_S 27 -/* DPORT_DCACHE_REJECT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DCACHE_REJECT_ST (BIT(26)) -#define DPORT_DCACHE_REJECT_ST_M (BIT(26)) -#define DPORT_DCACHE_REJECT_ST_V 0x1 -#define DPORT_DCACHE_REJECT_ST_S 26 -/* DPORT_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DCACHE_WRITE_FLASH_ST (BIT(25)) -#define DPORT_DCACHE_WRITE_FLASH_ST_M (BIT(25)) -#define DPORT_DCACHE_WRITE_FLASH_ST_V 0x1 -#define DPORT_DCACHE_WRITE_FLASH_ST_S 25 -/* DPORT_DC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_SIZE_FAULT_ST (BIT(24)) -#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_M (BIT(24)) -#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_V 0x1 -#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_S 24 -/* DPORT_DC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_SYNC_SIZE_FAULT_ST (BIT(23)) -#define DPORT_DC_SYNC_SIZE_FAULT_ST_M (BIT(23)) -#define DPORT_DC_SYNC_SIZE_FAULT_ST_V 0x1 -#define DPORT_DC_SYNC_SIZE_FAULT_ST_S 23 -/* DPORT_DC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_CNT_OVF_ST (BIT(22)) -#define DPORT_DC_PRELOAD_CNT_OVF_ST_M (BIT(22)) -#define DPORT_DC_PRELOAD_CNT_OVF_ST_V 0x1 -#define DPORT_DC_PRELOAD_CNT_OVF_ST_S 22 -/* DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST (BIT(21)) -#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_M (BIT(21)) -#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_V 0x1 -#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_S 21 -/* DPORT_DC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST (BIT(20)) -#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_M (BIT(20)) -#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_S 20 -/* DPORT_DBUS3_ABANDON_CNT_OVF_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS3_ABANDON_CNT_OVF_ST (BIT(19)) -#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_M (BIT(19)) -#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_S 19 -/* DPORT_DBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS2_ABANDON_CNT_OVF_ST (BIT(18)) -#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_M (BIT(18)) -#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_S 18 -/* DPORT_DBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS1_ABANDON_CNT_OVF_ST (BIT(17)) -#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_M (BIT(17)) -#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_S 17 -/* DPORT_DBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS0_ABANDON_CNT_OVF_ST (BIT(16)) -#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_M (BIT(16)) -#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_S 16 -/* DPORT_DBUS3_ACS_WB_CNT_OVF_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST (BIT(15)) -#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_M (BIT(15)) -#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_S 15 -/* DPORT_DBUS2_ACS_WB_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST (BIT(14)) -#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_M (BIT(14)) -#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_S 14 -/* DPORT_DBUS1_ACS_WB_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST (BIT(13)) -#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_M (BIT(13)) -#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_S 13 -/* DPORT_DBUS0_ACS_WB_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST (BIT(12)) -#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_M (BIT(12)) -#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_S 12 -/* DPORT_DBUS3_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST (BIT(11)) -#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_M (BIT(11)) -#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_S 11 -/* DPORT_DBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST (BIT(10)) -#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_M (BIT(10)) -#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_S 10 -/* DPORT_DBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST (BIT(9)) -#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_M (BIT(9)) -#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_S 9 -/* DPORT_DBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST (BIT(8)) -#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_M (BIT(8)) -#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_S 8 -/* DPORT_DBUS3_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_CNT_OVF_ST (BIT(7)) -#define DPORT_DBUS3_ACS_CNT_OVF_ST_M (BIT(7)) -#define DPORT_DBUS3_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS3_ACS_CNT_OVF_ST_S 7 -/* DPORT_DBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_CNT_OVF_ST (BIT(6)) -#define DPORT_DBUS2_ACS_CNT_OVF_ST_M (BIT(6)) -#define DPORT_DBUS2_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS2_ACS_CNT_OVF_ST_S 6 -/* DPORT_DBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_CNT_OVF_ST (BIT(5)) -#define DPORT_DBUS1_ACS_CNT_OVF_ST_M (BIT(5)) -#define DPORT_DBUS1_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS1_ACS_CNT_OVF_ST_S 5 -/* DPORT_DBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_CNT_OVF_ST (BIT(4)) -#define DPORT_DBUS0_ACS_CNT_OVF_ST_M (BIT(4)) -#define DPORT_DBUS0_ACS_CNT_OVF_ST_V 0x1 -#define DPORT_DBUS0_ACS_CNT_OVF_ST_S 4 -/* DPORT_DBUS3_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS3_ACS_MSK_DCACHE_ST (BIT(3)) -#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_M (BIT(3)) -#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_V 0x1 -#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_S 3 -/* DPORT_DBUS2_ACS_MSK_DCACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS2_ACS_MSK_DCACHE_ST (BIT(2)) -#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_M (BIT(2)) -#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_V 0x1 -#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_S 2 -/* DPORT_DBUS1_ACS_MSK_DCACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS1_ACS_MSK_DCACHE_ST (BIT(1)) -#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_M (BIT(1)) -#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_V 0x1 -#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_S 1 -/* DPORT_DBUS0_ACS_MSK_DCACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_DBUS0_ACS_MSK_DCACHE_ST (BIT(0)) -#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_M (BIT(0)) -#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_V 0x1 -#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_S 0 - -#define DPORT_PRO_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x114) -/* DPORT_PRO_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_ACS_CNT_CLR (BIT(1)) -#define DPORT_PRO_ICACHE_ACS_CNT_CLR_M (BIT(1)) -#define DPORT_PRO_ICACHE_ACS_CNT_CLR_V 0x1 -#define DPORT_PRO_ICACHE_ACS_CNT_CLR_S 1 -/* DPORT_PRO_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_ACS_CNT_CLR (BIT(0)) -#define DPORT_PRO_DCACHE_ACS_CNT_CLR_M (BIT(0)) -#define DPORT_PRO_DCACHE_ACS_CNT_CLR_V 0x1 -#define DPORT_PRO_DCACHE_ACS_CNT_CLR_S 0 - -#define DPORT_PRO_DCACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) -/* DPORT_PRO_DCACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_CPU_ATTR 0x00000007 -#define DPORT_PRO_DCACHE_CPU_ATTR_M ((DPORT_PRO_DCACHE_CPU_ATTR_V)<<(DPORT_PRO_DCACHE_CPU_ATTR_S)) -#define DPORT_PRO_DCACHE_CPU_ATTR_V 0x7 -#define DPORT_PRO_DCACHE_CPU_ATTR_S 3 -/* DPORT_PRO_DCACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_TAG_ATTR 0x00000007 -#define DPORT_PRO_DCACHE_TAG_ATTR_M ((DPORT_PRO_DCACHE_TAG_ATTR_V)<<(DPORT_PRO_DCACHE_TAG_ATTR_S)) -#define DPORT_PRO_DCACHE_TAG_ATTR_V 0x7 -#define DPORT_PRO_DCACHE_TAG_ATTR_S 0 - -#define DPORT_PRO_DCACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11C) -/* DPORT_PRO_DCACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_CPU_VADDR 0xFFFFFFFF -#define DPORT_PRO_DCACHE_CPU_VADDR_M ((DPORT_PRO_DCACHE_CPU_VADDR_V)<<(DPORT_PRO_DCACHE_CPU_VADDR_S)) -#define DPORT_PRO_DCACHE_CPU_VADDR_V 0xFFFFFFFF -#define DPORT_PRO_DCACHE_CPU_VADDR_S 0 - -#define DPORT_PRO_ICACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x120) -/* DPORT_PRO_ICACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_CPU_ATTR 0x00000007 -#define DPORT_PRO_ICACHE_CPU_ATTR_M ((DPORT_PRO_ICACHE_CPU_ATTR_V)<<(DPORT_PRO_ICACHE_CPU_ATTR_S)) -#define DPORT_PRO_ICACHE_CPU_ATTR_V 0x7 -#define DPORT_PRO_ICACHE_CPU_ATTR_S 3 -/* DPORT_PRO_ICACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_TAG_ATTR 0x00000007 -#define DPORT_PRO_ICACHE_TAG_ATTR_M ((DPORT_PRO_ICACHE_TAG_ATTR_V)<<(DPORT_PRO_ICACHE_TAG_ATTR_S)) -#define DPORT_PRO_ICACHE_TAG_ATTR_V 0x7 -#define DPORT_PRO_ICACHE_TAG_ATTR_S 0 - -#define DPORT_PRO_ICACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) -/* DPORT_PRO_ICACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_CPU_VADDR 0xFFFFFFFF -#define DPORT_PRO_ICACHE_CPU_VADDR_M ((DPORT_PRO_ICACHE_CPU_VADDR_V)<<(DPORT_PRO_ICACHE_CPU_VADDR_S)) -#define DPORT_PRO_ICACHE_CPU_VADDR_V 0xFFFFFFFF -#define DPORT_PRO_ICACHE_CPU_VADDR_S 0 - -#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x128) -/* DPORT_PRO_CACHE_MMU_ERROR_CONTENT : RO ;bitpos:[16:0] ;default: 17'h0 ; */ -/*description: */ -#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT 0x0001FFFF -#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_M ((DPORT_PRO_CACHE_MMU_ERROR_CONTENT_V)<<(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_S)) -#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_V 0x1FFFF -#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_S 0 - -#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_REG (DR_REG_EXTMEM_BASE + 0x12C) -/* DPORT_PRO_CACHE_MMU_ERROR_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define DPORT_PRO_CACHE_MMU_ERROR_VADDR 0xFFFFFFFF -#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_M ((DPORT_PRO_CACHE_MMU_ERROR_VADDR_V)<<(DPORT_PRO_CACHE_MMU_ERROR_VADDR_S)) -#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_V 0xFFFFFFFF -#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_S 0 - -#define DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x130) -/* DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) -#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_M (BIT(1)) -#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_V 0x1 -#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_S 1 -/* DPORT_PRO_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND (BIT(0)) -#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) -#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_V 0x1 -#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_S 0 - -#define DPORT_PRO_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) -/* DPORT_PRO_CACHE_MMU_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_CACHE_MMU_MEM_PD (BIT(1)) -#define DPORT_PRO_CACHE_MMU_MEM_PD_M (BIT(1)) -#define DPORT_PRO_CACHE_MMU_MEM_PD_V 0x1 -#define DPORT_PRO_CACHE_MMU_MEM_PD_S 1 -/* DPORT_PRO_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON (BIT(0)) -#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) -#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_V 0x1 -#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_S 0 - -#define DPORT_PRO_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x138) -/* DPORT_PRO_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_STATE 0x00000FFF -#define DPORT_PRO_DCACHE_STATE_M ((DPORT_PRO_DCACHE_STATE_V)<<(DPORT_PRO_DCACHE_STATE_S)) -#define DPORT_PRO_DCACHE_STATE_V 0xFFF -#define DPORT_PRO_DCACHE_STATE_S 12 -/* DPORT_PRO_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_STATE 0x00000FFF -#define DPORT_PRO_ICACHE_STATE_M ((DPORT_PRO_ICACHE_STATE_V)<<(DPORT_PRO_ICACHE_STATE_S)) -#define DPORT_PRO_ICACHE_STATE_V 0xFFF -#define DPORT_PRO_ICACHE_STATE_S 0 - -#define DPORT_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x13C) -/* DPORT_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) -#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) -#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 -#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_S 1 -/* DPORT_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) -#define DPORT_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) -#define DPORT_RECORD_DISABLE_DB_ENCRYPT_V 0x1 -#define DPORT_RECORD_DISABLE_DB_ENCRYPT_S 0 - -#define DPORT_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x140) -/* DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT (BIT(2)) -#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M (BIT(2)) -#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V 0x1 -#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S 2 -/* DPORT_CLK_FORCE_ON_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT (BIT(1)) -#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_M (BIT(1)) -#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_V 0x1 -#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_S 1 -/* DPORT_CLK_FORCE_ON_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_CLK_FORCE_ON_DB_ENCRYPT (BIT(0)) -#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_M (BIT(0)) -#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_V 0x1 -#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_S 0 - -#define DPORT_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) -/* DPORT_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_ALLOC_WB_HOLD_ARBITER (BIT(0)) -#define DPORT_ALLOC_WB_HOLD_ARBITER_M (BIT(0)) -#define DPORT_ALLOC_WB_HOLD_ARBITER_V 0x1 -#define DPORT_ALLOC_WB_HOLD_ARBITER_S 0 - -#define DPORT_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x148) -/* DPORT_PRO_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR (BIT(5)) -#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_M (BIT(5)) -#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_V 0x1 -#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_S 5 -/* DPORT_PRO_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA (BIT(4)) -#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_M (BIT(4)) -#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_V 0x1 -#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_S 4 -/* DPORT_PRO_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_DCACHE_PRELOAD_INT_ST (BIT(3)) -#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_M (BIT(3)) -#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_V 0x1 -#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_S 3 -/* DPORT_PRO_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR (BIT(2)) -#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) -#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_V 0x1 -#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_S 2 -/* DPORT_PRO_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA (BIT(1)) -#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) -#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_V 0x1 -#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_S 1 -/* DPORT_PRO_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_PRO_ICACHE_PRELOAD_INT_ST (BIT(0)) -#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_M (BIT(0)) -#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_V 0x1 -#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_S 0 - -#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x14C) +#define EXTMEM_PRO_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) +/* EXTMEM_PRO_DCACHE_LOCK_DONE : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The bit is used to indicate lock operation is finished.*/ +#define EXTMEM_PRO_DCACHE_LOCK_DONE (BIT(25)) +#define EXTMEM_PRO_DCACHE_LOCK_DONE_M (BIT(25)) +#define EXTMEM_PRO_DCACHE_LOCK_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_LOCK_DONE_S 25 +/* EXTMEM_PRO_DCACHE_LOCK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared + by hardware after lock operation done.*/ +#define EXTMEM_PRO_DCACHE_LOCK_ENA (BIT(24)) +#define EXTMEM_PRO_DCACHE_LOCK_ENA_M (BIT(24)) +#define EXTMEM_PRO_DCACHE_LOCK_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_LOCK_ENA_S 24 +/* EXTMEM_PRO_DCACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The bit is used to indicate unlock operation is finished.*/ +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE (BIT(23)) +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_M (BIT(23)) +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_S 23 +/* EXTMEM_PRO_DCACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared + by hardware after unlock operation done.*/ +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA (BIT(22)) +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_M (BIT(22)) +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_S 22 +/* EXTMEM_PRO_DCACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The bit is used to indicate preload operation is finished.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE (BIT(21)) +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_M (BIT(21)) +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_S 21 +/* EXTMEM_PRO_DCACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The bit is used to enable preload operation. It will be cleared + by hardware after preload operation done.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA (BIT(20)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_M (BIT(20)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_S 20 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The bit is used to indicate conditional-preload operation is finished.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE (BIT(19)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_M (BIT(19)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_S 19 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The bit is used to enable and disable conditional-preload operation. + It is combined with pre_dcache_autoload_done. 1: enable 0: disable.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA (BIT(18)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_M (BIT(18)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S 18 +/* EXTMEM_PRO_DCACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The bit is used to enable pre-lock operation which is combined + with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG.*/ +#define EXTMEM_PRO_DCACHE_LOCK1_EN (BIT(15)) +#define EXTMEM_PRO_DCACHE_LOCK1_EN_M (BIT(15)) +#define EXTMEM_PRO_DCACHE_LOCK1_EN_V 0x1 +#define EXTMEM_PRO_DCACHE_LOCK1_EN_S 15 +/* EXTMEM_PRO_DCACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The bit is used to enable pre-lock operation which is combined + with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG.*/ +#define EXTMEM_PRO_DCACHE_LOCK0_EN (BIT(14)) +#define EXTMEM_PRO_DCACHE_LOCK0_EN_M (BIT(14)) +#define EXTMEM_PRO_DCACHE_LOCK0_EN_V 0x1 +#define EXTMEM_PRO_DCACHE_LOCK0_EN_S 14 +/* EXTMEM_PRO_DCACHE_CLEAN_DONE : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to indicate clean operation is finished.*/ +#define EXTMEM_PRO_DCACHE_CLEAN_DONE (BIT(13)) +#define EXTMEM_PRO_DCACHE_CLEAN_DONE_M (BIT(13)) +#define EXTMEM_PRO_DCACHE_CLEAN_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_CLEAN_DONE_S 13 +/* EXTMEM_PRO_DCACHE_CLEAN_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The bit is used to enable clean operation. It will be cleared + by hardware after clean operation done.*/ +#define EXTMEM_PRO_DCACHE_CLEAN_ENA (BIT(12)) +#define EXTMEM_PRO_DCACHE_CLEAN_ENA_M (BIT(12)) +#define EXTMEM_PRO_DCACHE_CLEAN_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_CLEAN_ENA_S 12 +/* EXTMEM_PRO_DCACHE_FLUSH_DONE : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to indicate flush operation is finished.*/ +#define EXTMEM_PRO_DCACHE_FLUSH_DONE (BIT(11)) +#define EXTMEM_PRO_DCACHE_FLUSH_DONE_M (BIT(11)) +#define EXTMEM_PRO_DCACHE_FLUSH_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_FLUSH_DONE_S 11 +/* EXTMEM_PRO_DCACHE_FLUSH_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to enable flush operation. It will be cleared + by hardware after flush operation done.*/ +#define EXTMEM_PRO_DCACHE_FLUSH_ENA (BIT(10)) +#define EXTMEM_PRO_DCACHE_FLUSH_ENA_M (BIT(10)) +#define EXTMEM_PRO_DCACHE_FLUSH_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_FLUSH_ENA_S 10 +/* EXTMEM_PRO_DCACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to indicate invalidate operation is finished.*/ +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE (BIT(9)) +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_M (BIT(9)) +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_V 0x1 +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_S 9 +/* EXTMEM_PRO_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared + by hardware after invalidate operation done.*/ +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA (BIT(8)) +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_M (BIT(8)) +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_S 8 +/* EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE (BIT(3)) +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_M (BIT(3)) +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V 0x1 +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S 3 +/* EXTMEM_PRO_DCACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache memory size.0: 8KB 1: 16KB*/ +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE (BIT(2)) +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_M (BIT(2)) +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_V 0x1 +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_S 2 +/* EXTMEM_PRO_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ +#define EXTMEM_PRO_DCACHE_ENABLE (BIT(0)) +#define EXTMEM_PRO_DCACHE_ENABLE_M (BIT(0)) +#define EXTMEM_PRO_DCACHE_ENABLE_V 0x1 +#define EXTMEM_PRO_DCACHE_ENABLE_S 0 + +#define EXTMEM_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) +/* EXTMEM_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to disable dbus2 0: enable 1: disable*/ +#define EXTMEM_PRO_DCACHE_MASK_BUS2 (BIT(2)) +#define EXTMEM_PRO_DCACHE_MASK_BUS2_M (BIT(2)) +#define EXTMEM_PRO_DCACHE_MASK_BUS2_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS2_S 2 +/* EXTMEM_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable dbus1 0: enable 1: disable*/ +#define EXTMEM_PRO_DCACHE_MASK_BUS1 (BIT(1)) +#define EXTMEM_PRO_DCACHE_MASK_BUS1_M (BIT(1)) +#define EXTMEM_PRO_DCACHE_MASK_BUS1_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS1_S 1 +/* EXTMEM_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable dbus0 0: enable 1: disable*/ +#define EXTMEM_PRO_DCACHE_MASK_BUS0 (BIT(0)) +#define EXTMEM_PRO_DCACHE_MASK_BUS0_M (BIT(0)) +#define EXTMEM_PRO_DCACHE_MASK_BUS0_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS0_S 0 +#define EXTMEM_PRO_DCACHE_MASK_DRAM0 EXTMEM_PRO_DCACHE_MASK_BUS0 +#define EXTMEM_PRO_DCACHE_MASK_DRAM1 EXTMEM_PRO_DCACHE_MASK_BUS1 +#define EXTMEM_PRO_DCACHE_MASK_DPORT EXTMEM_PRO_DCACHE_MASK_BUS2 + +#define EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) +/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd + 1: power up*/ +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_S 2 +/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd + 1: power down*/ +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_S 1 +/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of dcache tag memory. 1: + close gating 0: open clock gating.*/ +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S 0 + +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x00C) +/* EXTMEM_PRO_DCACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ +/*description: The bits are used to configure the first start virtual address + of data locking which is combined with PRO_DCACHE_LOCK0_SIZE_REG*/ +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_M ((EXTMEM_PRO_DCACHE_LOCK0_ADDR_V)<<(EXTMEM_PRO_DCACHE_LOCK0_ADDR_S)) +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_S 0 + +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x010) +/* EXTMEM_PRO_DCACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the first length of data locking + which is combined with PRO_DCACHE_LOCK0_ADDR_REG*/ +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE 0x0000FFFF +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_M ((EXTMEM_PRO_DCACHE_LOCK0_SIZE_V)<<(EXTMEM_PRO_DCACHE_LOCK0_SIZE_S)) +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_V 0xFFFF +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_S 0 + +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) +/* EXTMEM_PRO_DCACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ +/*description: The bits are used to configure the second start virtual address + of data locking which is combined with PRO_DCACHE_LOCK1_SIZE_REG*/ +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_M ((EXTMEM_PRO_DCACHE_LOCK1_ADDR_V)<<(EXTMEM_PRO_DCACHE_LOCK1_ADDR_S)) +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_S 0 + +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) +/* EXTMEM_PRO_DCACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the second length of data locking + which is combined with PRO_DCACHE_LOCK1_ADDR_REG*/ +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE 0x0000FFFF +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_M ((EXTMEM_PRO_DCACHE_LOCK1_SIZE_V)<<(EXTMEM_PRO_DCACHE_LOCK1_SIZE_S)) +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_V 0xFFFF +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_S 0 + +#define EXTMEM_PRO_DCACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x01C) +/* EXTMEM_PRO_DCACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + invalidate flush clean lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1.*/ +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_M ((EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V)<<(EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S)) +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S 0 + +#define EXTMEM_PRO_DCACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x020) +/* EXTMEM_PRO_DCACHE_MEMSYNC_SIZE : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: The bits are used to configure the length for invalidate flush + clean lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0.*/ +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE 0x0007FFFF +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_M ((EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V)<<(EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S)) +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V 0x7FFFF +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S 0 + +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x024) +/* EXTMEM_PRO_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_M ((EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x028) +/* EXTMEM_PRO_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of manual pre-load + operation. 1: descending 0: ascending.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER (BIT(10)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_M (BIT(10)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_S 10 +/* EXTMEM_PRO_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[9:0] ;default: 10'h200 ; */ +/*description: The bits are used to configure the length for manual pre-load + operation. It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG..*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE 0x000003FF +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_M ((EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S)) +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V 0x3FF +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x02C) +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bits are used to enable the first section for conditional + pre-load operation.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_S 9 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bits are used to enable the second section for conditional + pre-load operation.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_S 8 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The bits are used to configure the numbers of the cache block + for the issuing conditional pre-load operation.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V 0x3 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S 6 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */ +/*description: The bits are used to configure trigger conditions for conditional + pre-load. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V 0x3 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S 4 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of conditional pre-load + operation. 1: descending 0: ascending.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER (BIT(3)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_M (BIT(3)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_S 3 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V 0x3 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S 1 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Reserved.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE (BIT(0)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_M (BIT(0)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_V 0x1 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_S 0 + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x030) +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x034) +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ +/*description: The bits are used to configure the length of the first section + for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ +/*description: The bits are used to configure the length of the second section + for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena.*/ +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_PRO_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) +/* EXTMEM_PRO_ICACHE_LOCK_DONE : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The bit is used to indicate lock operation is finished.*/ +#define EXTMEM_PRO_ICACHE_LOCK_DONE (BIT(25)) +#define EXTMEM_PRO_ICACHE_LOCK_DONE_M (BIT(25)) +#define EXTMEM_PRO_ICACHE_LOCK_DONE_V 0x1 +#define EXTMEM_PRO_ICACHE_LOCK_DONE_S 25 +/* EXTMEM_PRO_ICACHE_LOCK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared + by hardware after lock operation done.*/ +#define EXTMEM_PRO_ICACHE_LOCK_ENA (BIT(24)) +#define EXTMEM_PRO_ICACHE_LOCK_ENA_M (BIT(24)) +#define EXTMEM_PRO_ICACHE_LOCK_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_LOCK_ENA_S 24 +/* EXTMEM_PRO_ICACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The bit is used to indicate unlock operation is finished.*/ +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE (BIT(23)) +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_M (BIT(23)) +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_V 0x1 +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_S 23 +/* EXTMEM_PRO_ICACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared + by hardware after unlock operation done.*/ +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA (BIT(22)) +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_M (BIT(22)) +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_S 22 +/* EXTMEM_PRO_ICACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The bit is used to indicate preload operation is finished.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE (BIT(21)) +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_M (BIT(21)) +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_S 21 +/* EXTMEM_PRO_ICACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The bit is used to enable preload operation. It will be cleared + by hardware after preload operation done.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA (BIT(20)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_M (BIT(20)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_S 20 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The bit is used to indicate conditional-preload operation is finished.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE (BIT(19)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_M (BIT(19)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_S 19 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The bit is used to enable and disable conditional-preload operation. + It is combined with pre_dcache_autoload_done. 1: enable 0: disable.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA (BIT(18)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_M (BIT(18)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_S 18 +/* EXTMEM_PRO_ICACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The bit is used to enable pre-lock operation which is combined + with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG.*/ +#define EXTMEM_PRO_ICACHE_LOCK1_EN (BIT(15)) +#define EXTMEM_PRO_ICACHE_LOCK1_EN_M (BIT(15)) +#define EXTMEM_PRO_ICACHE_LOCK1_EN_V 0x1 +#define EXTMEM_PRO_ICACHE_LOCK1_EN_S 15 +/* EXTMEM_PRO_ICACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The bit is used to enable pre-lock operation which is combined + with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG.*/ +#define EXTMEM_PRO_ICACHE_LOCK0_EN (BIT(14)) +#define EXTMEM_PRO_ICACHE_LOCK0_EN_M (BIT(14)) +#define EXTMEM_PRO_ICACHE_LOCK0_EN_V 0x1 +#define EXTMEM_PRO_ICACHE_LOCK0_EN_S 14 +/* EXTMEM_PRO_ICACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to indicate invalidate operation is finished.*/ +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE (BIT(9)) +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_M (BIT(9)) +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_V 0x1 +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_S 9 +/* EXTMEM_PRO_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared + by hardware after invalidate operation done.*/ +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA (BIT(8)) +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_M (BIT(8)) +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S 8 +/* EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE (BIT(3)) +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_M (BIT(3)) +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_V 0x1 +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_S 3 +/* EXTMEM_PRO_ICACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache memory size.0: 8KB 1: 16KB*/ +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE (BIT(2)) +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_M (BIT(2)) +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_V 0x1 +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_S 2 +/* EXTMEM_PRO_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ +#define EXTMEM_PRO_ICACHE_ENABLE (BIT(0)) +#define EXTMEM_PRO_ICACHE_ENABLE_M (BIT(0)) +#define EXTMEM_PRO_ICACHE_ENABLE_V 0x1 +#define EXTMEM_PRO_ICACHE_ENABLE_S 0 + +#define EXTMEM_PRO_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x044) +/* EXTMEM_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to disable ibus2 0: enable 1: disable*/ +#define EXTMEM_PRO_ICACHE_MASK_BUS2 (BIT(2)) +#define EXTMEM_PRO_ICACHE_MASK_BUS2_M (BIT(2)) +#define EXTMEM_PRO_ICACHE_MASK_BUS2_V 0x1 +#define EXTMEM_PRO_ICACHE_MASK_BUS2_S 2 +/* EXTMEM_PRO_ICACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable ibus1 0: enable 1: disable*/ +#define EXTMEM_PRO_ICACHE_MASK_BUS1 (BIT(1)) +#define EXTMEM_PRO_ICACHE_MASK_BUS1_M (BIT(1)) +#define EXTMEM_PRO_ICACHE_MASK_BUS1_V 0x1 +#define EXTMEM_PRO_ICACHE_MASK_BUS1_S 1 +/* EXTMEM_PRO_ICACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable ibus0 0: enable 1: disable*/ +#define EXTMEM_PRO_ICACHE_MASK_BUS0 (BIT(0)) +#define EXTMEM_PRO_ICACHE_MASK_BUS0_M (BIT(0)) +#define EXTMEM_PRO_ICACHE_MASK_BUS0_V 0x1 +#define EXTMEM_PRO_ICACHE_MASK_BUS0_S 0 +#define EXTMEM_PRO_ICACHE_MASK_IRAM0 EXTMEM_PRO_ICACHE_MASK_BUS0 +#define EXTMEM_PRO_ICACHE_MASK_IRAM1 EXTMEM_PRO_ICACHE_MASK_BUS1 +#define EXTMEM_PRO_ICACHE_MASK_DROM0 EXTMEM_PRO_ICACHE_MASK_BUS2 + +#define EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x048) +/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp 1: power up*/ +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_S 2 +/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp + 1: power down*/ +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_S 1 +/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of icache tag memory. 1: + close gating 0: open clock gating.*/ +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S 0 + +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x04C) +/* EXTMEM_PRO_ICACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ +/*description: The bits are used to configure the first start virtual address + of data locking which is combined with PRO_ICACHE_LOCK0_SIZE_REG*/ +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_M ((EXTMEM_PRO_ICACHE_LOCK0_ADDR_V)<<(EXTMEM_PRO_ICACHE_LOCK0_ADDR_S)) +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_S 0 + +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x050) +/* EXTMEM_PRO_ICACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the first length of data locking + which is combined with PRO_ICACHE_LOCK0_ADDR_REG*/ +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE 0x0000FFFF +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_M ((EXTMEM_PRO_ICACHE_LOCK0_SIZE_V)<<(EXTMEM_PRO_ICACHE_LOCK0_SIZE_S)) +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_V 0xFFFF +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_S 0 + +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x054) +/* EXTMEM_PRO_ICACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */ +/*description: The bits are used to configure the second start virtual address + of data locking which is combined with PRO_ICACHE_LOCK1_SIZE_REG*/ +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_M ((EXTMEM_PRO_ICACHE_LOCK1_ADDR_V)<<(EXTMEM_PRO_ICACHE_LOCK1_ADDR_S)) +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_S 0 + +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x058) +/* EXTMEM_PRO_ICACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the second length of data locking + which is combined with PRO_ICACHE_LOCK1_ADDR_REG*/ +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE 0x0000FFFF +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_M ((EXTMEM_PRO_ICACHE_LOCK1_SIZE_V)<<(EXTMEM_PRO_ICACHE_LOCK1_SIZE_S)) +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_V 0xFFFF +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_S 0 + +#define EXTMEM_PRO_ICACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x05C) +/* EXTMEM_PRO_ICACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + invalidate flush clean lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1.*/ +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_M ((EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V)<<(EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S)) +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S 0 + +#define EXTMEM_PRO_ICACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x060) +/* EXTMEM_PRO_ICACHE_MEMSYNC_SIZE : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: The bits are used to configure the length for invalidate flush + clean lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0.*/ +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE 0x0007FFFF +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_M ((EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V)<<(EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S)) +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V 0x7FFFF +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S 0 + +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x064) +/* EXTMEM_PRO_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_M ((EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x068) +/* EXTMEM_PRO_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of manual pre-load + operation. 1: descending 0: ascending.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER (BIT(10)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_M (BIT(10)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_S 10 +/* EXTMEM_PRO_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[9:0] ;default: 10'h200 ; */ +/*description: The bits are used to configure the length for manual pre-load + operation. It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG..*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE 0x000003FF +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_M ((EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S)) +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V 0x3FF +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x06C) +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bits are used to enable the first section for conditional + pre-load operation.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_S 9 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bits are used to enable the second section for conditional + pre-load operation.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_S 8 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The bits are used to configure the numbers of the cache block + for the issuing conditional pre-load operation.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V 0x3 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S 6 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */ +/*description: The bits are used to configure trigger conditions for conditional + pre-load. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V 0x3 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S 4 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of conditional pre-load + operation. 1: descending 0: ascending.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER (BIT(3)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_M (BIT(3)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_S 3 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V 0x3 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S 1 +/* EXTMEM_PRO_ICACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Reserved.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE (BIT(0)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_M (BIT(0)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_V 0x1 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_S 0 + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x070) +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x074) +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ +/*description: The bits are used to configure the length of the first section + for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE 0x00FFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x078) +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x07C) +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */ +/*description: The bits are used to configure the length of the second section + for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena.*/ +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE 0x00FFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFF +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_IC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x080) +/* EXTMEM_IC_PRELOAD_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of issued pre-load which + include manual pre-load and conditional pre-load.*/ +#define EXTMEM_IC_PRELOAD_CNT 0x0000FFFF +#define EXTMEM_IC_PRELOAD_CNT_M ((EXTMEM_IC_PRELOAD_CNT_V)<<(EXTMEM_IC_PRELOAD_CNT_S)) +#define EXTMEM_IC_PRELOAD_CNT_V 0xFFFF +#define EXTMEM_IC_PRELOAD_CNT_S 0 + +#define EXTMEM_IC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x084) +/* EXTMEM_IC_PRELOAD_MISS_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of missed pre-load which + include manual pre-load and conditional pre-load.*/ +#define EXTMEM_IC_PRELOAD_MISS_CNT 0x0000FFFF +#define EXTMEM_IC_PRELOAD_MISS_CNT_M ((EXTMEM_IC_PRELOAD_MISS_CNT_V)<<(EXTMEM_IC_PRELOAD_MISS_CNT_S)) +#define EXTMEM_IC_PRELOAD_MISS_CNT_V 0xFFFF +#define EXTMEM_IC_PRELOAD_MISS_CNT_S 0 + +#define EXTMEM_IBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x088) +/* EXTMEM_IBUS2_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of the abandoned ibus2 access.*/ +#define EXTMEM_IBUS2_ABANDON_CNT 0x0000FFFF +#define EXTMEM_IBUS2_ABANDON_CNT_M ((EXTMEM_IBUS2_ABANDON_CNT_V)<<(EXTMEM_IBUS2_ABANDON_CNT_S)) +#define EXTMEM_IBUS2_ABANDON_CNT_V 0xFFFF +#define EXTMEM_IBUS2_ABANDON_CNT_S 0 + +#define EXTMEM_IBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x08C) +/* EXTMEM_IBUS1_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of the abandoned ibus1 access.*/ +#define EXTMEM_IBUS1_ABANDON_CNT 0x0000FFFF +#define EXTMEM_IBUS1_ABANDON_CNT_M ((EXTMEM_IBUS1_ABANDON_CNT_V)<<(EXTMEM_IBUS1_ABANDON_CNT_S)) +#define EXTMEM_IBUS1_ABANDON_CNT_V 0xFFFF +#define EXTMEM_IBUS1_ABANDON_CNT_S 0 + +#define EXTMEM_IBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x090) +/* EXTMEM_IBUS0_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of the abandoned ibus0 access.*/ +#define EXTMEM_IBUS0_ABANDON_CNT 0x0000FFFF +#define EXTMEM_IBUS0_ABANDON_CNT_M ((EXTMEM_IBUS0_ABANDON_CNT_V)<<(EXTMEM_IBUS0_ABANDON_CNT_S)) +#define EXTMEM_IBUS0_ABANDON_CNT_V 0xFFFF +#define EXTMEM_IBUS0_ABANDON_CNT_S 0 + +#define EXTMEM_IBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x094) +/* EXTMEM_IBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused by ibus2 access.*/ +#define EXTMEM_IBUS2_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS2_ACS_MISS_CNT_M ((EXTMEM_IBUS2_ACS_MISS_CNT_V)<<(EXTMEM_IBUS2_ACS_MISS_CNT_S)) +#define EXTMEM_IBUS2_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS2_ACS_MISS_CNT_S 0 + +#define EXTMEM_IBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x098) +/* EXTMEM_IBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused by ibus1 access.*/ +#define EXTMEM_IBUS1_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS1_ACS_MISS_CNT_M ((EXTMEM_IBUS1_ACS_MISS_CNT_V)<<(EXTMEM_IBUS1_ACS_MISS_CNT_S)) +#define EXTMEM_IBUS1_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS1_ACS_MISS_CNT_S 0 + +#define EXTMEM_IBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x09C) +/* EXTMEM_IBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused by ibus0 access.*/ +#define EXTMEM_IBUS0_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS0_ACS_MISS_CNT_M ((EXTMEM_IBUS0_ACS_MISS_CNT_V)<<(EXTMEM_IBUS0_ACS_MISS_CNT_S)) +#define EXTMEM_IBUS0_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS0_ACS_MISS_CNT_S 0 + +#define EXTMEM_IBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A0) +/* EXTMEM_IBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of ibus2 access icache.*/ +#define EXTMEM_IBUS2_ACS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS2_ACS_CNT_M ((EXTMEM_IBUS2_ACS_CNT_V)<<(EXTMEM_IBUS2_ACS_CNT_S)) +#define EXTMEM_IBUS2_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS2_ACS_CNT_S 0 + +#define EXTMEM_IBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A4) +/* EXTMEM_IBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of ibus1 access icache.*/ +#define EXTMEM_IBUS1_ACS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS1_ACS_CNT_M ((EXTMEM_IBUS1_ACS_CNT_V)<<(EXTMEM_IBUS1_ACS_CNT_S)) +#define EXTMEM_IBUS1_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS1_ACS_CNT_S 0 + +#define EXTMEM_IBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0A8) +/* EXTMEM_IBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of ibus0 access icache.*/ +#define EXTMEM_IBUS0_ACS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS0_ACS_CNT_M ((EXTMEM_IBUS0_ACS_CNT_V)<<(EXTMEM_IBUS0_ACS_CNT_S)) +#define EXTMEM_IBUS0_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS0_ACS_CNT_S 0 + +#define EXTMEM_DC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x0AC) +/* EXTMEM_DC_PRELOAD_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of issued pre-load which + include manual pre-load and conditional pre-load.*/ +#define EXTMEM_DC_PRELOAD_CNT 0x0000FFFF +#define EXTMEM_DC_PRELOAD_CNT_M ((EXTMEM_DC_PRELOAD_CNT_V)<<(EXTMEM_DC_PRELOAD_CNT_S)) +#define EXTMEM_DC_PRELOAD_CNT_V 0xFFFF +#define EXTMEM_DC_PRELOAD_CNT_S 0 + +#define EXTMEM_DC_PRELOAD_EVICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B0) +/* EXTMEM_DC_PRELOAD_EVICT_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of cache evictions by pre-load + which include manual pre-load and conditional pre-load.*/ +#define EXTMEM_DC_PRELOAD_EVICT_CNT 0x0000FFFF +#define EXTMEM_DC_PRELOAD_EVICT_CNT_M ((EXTMEM_DC_PRELOAD_EVICT_CNT_V)<<(EXTMEM_DC_PRELOAD_EVICT_CNT_S)) +#define EXTMEM_DC_PRELOAD_EVICT_CNT_V 0xFFFF +#define EXTMEM_DC_PRELOAD_EVICT_CNT_S 0 + +#define EXTMEM_DC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B4) +/* EXTMEM_DC_PRELOAD_MISS_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of missed pre-load which + include manual pre-load and conditional pre-load.*/ +#define EXTMEM_DC_PRELOAD_MISS_CNT 0x0000FFFF +#define EXTMEM_DC_PRELOAD_MISS_CNT_M ((EXTMEM_DC_PRELOAD_MISS_CNT_V)<<(EXTMEM_DC_PRELOAD_MISS_CNT_S)) +#define EXTMEM_DC_PRELOAD_MISS_CNT_V 0xFFFF +#define EXTMEM_DC_PRELOAD_MISS_CNT_S 0 + +#define EXTMEM_DBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0B8) +/* EXTMEM_DBUS2_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of the abandoned dbus2 access.*/ +#define EXTMEM_DBUS2_ABANDON_CNT 0x0000FFFF +#define EXTMEM_DBUS2_ABANDON_CNT_M ((EXTMEM_DBUS2_ABANDON_CNT_V)<<(EXTMEM_DBUS2_ABANDON_CNT_S)) +#define EXTMEM_DBUS2_ABANDON_CNT_V 0xFFFF +#define EXTMEM_DBUS2_ABANDON_CNT_S 0 + +#define EXTMEM_DBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0BC) +/* EXTMEM_DBUS1_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of the abandoned dbus1 access.*/ +#define EXTMEM_DBUS1_ABANDON_CNT 0x0000FFFF +#define EXTMEM_DBUS1_ABANDON_CNT_M ((EXTMEM_DBUS1_ABANDON_CNT_V)<<(EXTMEM_DBUS1_ABANDON_CNT_S)) +#define EXTMEM_DBUS1_ABANDON_CNT_V 0xFFFF +#define EXTMEM_DBUS1_ABANDON_CNT_S 0 + +#define EXTMEM_DBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C0) +/* EXTMEM_DBUS0_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to count the number of the abandoned dbus0 access.*/ +#define EXTMEM_DBUS0_ABANDON_CNT 0x0000FFFF +#define EXTMEM_DBUS0_ABANDON_CNT_M ((EXTMEM_DBUS0_ABANDON_CNT_V)<<(EXTMEM_DBUS0_ABANDON_CNT_S)) +#define EXTMEM_DBUS0_ABANDON_CNT_V 0xFFFF +#define EXTMEM_DBUS0_ABANDON_CNT_S 0 + +#define EXTMEM_DBUS2_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C4) +/* EXTMEM_DBUS2_ACS_WB_CNT : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The bits are used to count the number of cache evictions by dbus2 access cache.*/ +#define EXTMEM_DBUS2_ACS_WB_CNT 0x000FFFFF +#define EXTMEM_DBUS2_ACS_WB_CNT_M ((EXTMEM_DBUS2_ACS_WB_CNT_V)<<(EXTMEM_DBUS2_ACS_WB_CNT_S)) +#define EXTMEM_DBUS2_ACS_WB_CNT_V 0xFFFFF +#define EXTMEM_DBUS2_ACS_WB_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C8) +/* EXTMEM_DBUS1_ACS_WB_CNT : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The bits are used to count the number of cache evictions by dbus1 access cache.*/ +#define EXTMEM_DBUS1_ACS_WB_CNT 0x000FFFFF +#define EXTMEM_DBUS1_ACS_WB_CNT_M ((EXTMEM_DBUS1_ACS_WB_CNT_V)<<(EXTMEM_DBUS1_ACS_WB_CNT_S)) +#define EXTMEM_DBUS1_ACS_WB_CNT_V 0xFFFFF +#define EXTMEM_DBUS1_ACS_WB_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0x0CC) +/* EXTMEM_DBUS0_ACS_WB_CNT : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: The bits are used to count the number of cache evictions by dbus0 access cache.*/ +#define EXTMEM_DBUS0_ACS_WB_CNT 0x000FFFFF +#define EXTMEM_DBUS0_ACS_WB_CNT_M ((EXTMEM_DBUS0_ACS_WB_CNT_V)<<(EXTMEM_DBUS0_ACS_WB_CNT_S)) +#define EXTMEM_DBUS0_ACS_WB_CNT_V 0xFFFFF +#define EXTMEM_DBUS0_ACS_WB_CNT_S 0 + +#define EXTMEM_DBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D0) +/* EXTMEM_DBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused by dbus2 access.*/ +#define EXTMEM_DBUS2_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS2_ACS_MISS_CNT_M ((EXTMEM_DBUS2_ACS_MISS_CNT_V)<<(EXTMEM_DBUS2_ACS_MISS_CNT_S)) +#define EXTMEM_DBUS2_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS2_ACS_MISS_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D4) +/* EXTMEM_DBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused by dbus1 access.*/ +#define EXTMEM_DBUS1_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_ACS_MISS_CNT_M ((EXTMEM_DBUS1_ACS_MISS_CNT_V)<<(EXTMEM_DBUS1_ACS_MISS_CNT_S)) +#define EXTMEM_DBUS1_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_ACS_MISS_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D8) +/* EXTMEM_DBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused by dbus0 access.*/ +#define EXTMEM_DBUS0_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_ACS_MISS_CNT_M ((EXTMEM_DBUS0_ACS_MISS_CNT_V)<<(EXTMEM_DBUS0_ACS_MISS_CNT_S)) +#define EXTMEM_DBUS0_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_ACS_MISS_CNT_S 0 + +#define EXTMEM_DBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0DC) +/* EXTMEM_DBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of dbus2 access dcache.*/ +#define EXTMEM_DBUS2_ACS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS2_ACS_CNT_M ((EXTMEM_DBUS2_ACS_CNT_V)<<(EXTMEM_DBUS2_ACS_CNT_S)) +#define EXTMEM_DBUS2_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS2_ACS_CNT_S 0 + +#define EXTMEM_DBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0E0) +/* EXTMEM_DBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of dbus1 access dcache.*/ +#define EXTMEM_DBUS1_ACS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS1_ACS_CNT_M ((EXTMEM_DBUS1_ACS_CNT_V)<<(EXTMEM_DBUS1_ACS_CNT_S)) +#define EXTMEM_DBUS1_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS1_ACS_CNT_S 0 + +#define EXTMEM_DBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0E4) +/* EXTMEM_DBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of dbus0 access dcache.*/ +#define EXTMEM_DBUS0_ACS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS0_ACS_CNT_M ((EXTMEM_DBUS0_ACS_CNT_V)<<(EXTMEM_DBUS0_ACS_CNT_S)) +#define EXTMEM_DBUS0_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS0_ACS_CNT_S 0 + +#define EXTMEM_CACHE_DBG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0E8) +/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(19)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(19)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 19 +/* EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by illegal writing lock registers + of dcache while dcache is busy to issue lock sync or pre-load operations.*/ +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA (BIT(18)) +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_M (BIT(18)) +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_S 18 +/* EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by illegal writing sync registers + of dcache while dcache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA (BIT(17)) +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_M (BIT(17)) +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S 17 +/* EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by illegal writing preload + registers of dcache while dcache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA (BIT(16)) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_M (BIT(16)) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_S 16 +/* EXTMEM_DCACHE_REJECT_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_DCACHE_REJECT_INT_ENA (BIT(15)) +#define EXTMEM_DCACHE_REJECT_INT_ENA_M (BIT(15)) +#define EXTMEM_DCACHE_REJECT_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_REJECT_INT_ENA_S 15 +/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dcache trying to write flash.*/ +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(14)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(14)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 14 +/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by manual pre-load configurations fault.*/ +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(13)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_M (BIT(13)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x1 +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_S 13 +/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by manual sync configurations fault.*/ +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA (BIT(12)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_M (BIT(12)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_V 0x1 +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_S 12 +/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dbus counter overflow.*/ +#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(11)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(11)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 11 +/* EXTMEM_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access dcache while + the corresponding dbus is disabled which include speculative access.*/ +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA (BIT(10)) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(10)) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_S 10 +/* EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by illegal writing lock registers + of icache while icache is busy to issue lock sync or pre-load operations.*/ +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA (BIT(9)) +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_M (BIT(9)) +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_S 9 +/* EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by illegal writing sync registers + of icache while icache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA (BIT(8)) +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_M (BIT(8)) +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S 8 +/* EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by illegal writing preload + registers of icache while icache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA (BIT(7)) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_M (BIT(7)) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_S 7 +/* EXTMEM_ICACHE_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_ICACHE_REJECT_INT_ENA (BIT(6)) +#define EXTMEM_ICACHE_REJECT_INT_ENA_M (BIT(6)) +#define EXTMEM_ICACHE_REJECT_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_REJECT_INT_ENA_S 6 +/* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by manual pre-load configurations fault.*/ +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(5)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_M (BIT(5)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x1 +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S 5 +/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by manual sync configurations fault.*/ +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA (BIT(4)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_M (BIT(4)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_V 0x1 +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_S 4 +/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by ibus counter overflow.*/ +#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(3)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(3)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 3 +/* EXTMEM_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access icache while + the corresponding ibus is disabled which include speculative access.*/ +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA (BIT(2)) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(2)) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S 2 +/* EXTMEM_CACHE_DBG_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to activate the cache track function. 1: enable 0: disable.*/ +#define EXTMEM_CACHE_DBG_EN (BIT(0)) +#define EXTMEM_CACHE_DBG_EN_M (BIT(0)) +#define EXTMEM_CACHE_DBG_EN_V 0x1 +#define EXTMEM_CACHE_DBG_EN_S 0 + +#define EXTMEM_CACHE_DBG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0EC) +/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(13)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(13)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 13 +/* EXTMEM_DCACHE_SET_ILG_INT_CLR : WOD ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by illegal writing lock registers + of dcache while dcache is busy to issue lock sync or pre-load operations.*/ +#define EXTMEM_DCACHE_SET_ILG_INT_CLR (BIT(12)) +#define EXTMEM_DCACHE_SET_ILG_INT_CLR_M (BIT(12)) +#define EXTMEM_DCACHE_SET_ILG_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_SET_ILG_INT_CLR_S 12 +/* EXTMEM_DCACHE_REJECT_INT_CLR : WOD ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_DCACHE_REJECT_INT_CLR (BIT(11)) +#define EXTMEM_DCACHE_REJECT_INT_CLR_M (BIT(11)) +#define EXTMEM_DCACHE_REJECT_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_REJECT_INT_CLR_S 11 +/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dcache trying to write flash.*/ +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(10)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (BIT(10)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 10 +/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR : WOD ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by manual pre-load configurations fault.*/ +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(9)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_M (BIT(9)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x1 +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S 9 +/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by manual sync configurations fault.*/ +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR (BIT(8)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_M (BIT(8)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_V 0x1 +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_S 8 +/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dbus counter overflow.*/ +#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(7)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(7)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 7 +/* EXTMEM_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access dcache while + the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR (BIT(6)) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(6)) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S 6 +/* EXTMEM_ICACHE_SET_ILG_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by illegal writing lock registers + of icache while icache is busy to issue lock sync or pre-load operations.*/ +#define EXTMEM_ICACHE_SET_ILG_INT_CLR (BIT(5)) +#define EXTMEM_ICACHE_SET_ILG_INT_CLR_M (BIT(5)) +#define EXTMEM_ICACHE_SET_ILG_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_SET_ILG_INT_CLR_S 5 +/* EXTMEM_ICACHE_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_ICACHE_REJECT_INT_CLR (BIT(4)) +#define EXTMEM_ICACHE_REJECT_INT_CLR_M (BIT(4)) +#define EXTMEM_ICACHE_REJECT_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_REJECT_INT_CLR_S 4 +/* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by manual pre-load configurations fault.*/ +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(3)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_M (BIT(3)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x1 +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S 3 +/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by manual sync configurations fault.*/ +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR (BIT(2)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_M (BIT(2)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_V 0x1 +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_S 2 +/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by ibus counter overflow.*/ +#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(1)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(1)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 1 +/* EXTMEM_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access icache while + the corresponding ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S 0 + +#define EXTMEM_CACHE_DBG_STATUS0_REG (DR_REG_EXTMEM_BASE + 0x0F0) +/* EXTMEM_ICACHE_SET_LOCK_ILG_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by illegal writing lock + registers of icache while icache is busy to issue lock sync or pre-load operations.*/ +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST (BIT(24)) +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_M (BIT(24)) +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_V 0x1 +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_S 24 +/* EXTMEM_ICACHE_SET_SYNC_ILG_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by illegal writing sync + registers of icache while icache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST (BIT(23)) +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_M (BIT(23)) +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_V 0x1 +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_S 23 +/* EXTMEM_ICACHE_SET_PRELOAD_ILG_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by illegal writing preload + registers of icache while icache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST (BIT(22)) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_M (BIT(22)) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V 0x1 +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S 22 +/* EXTMEM_ICACHE_REJECT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_ICACHE_REJECT_ST (BIT(21)) +#define EXTMEM_ICACHE_REJECT_ST_M (BIT(21)) +#define EXTMEM_ICACHE_REJECT_ST_V 0x1 +#define EXTMEM_ICACHE_REJECT_ST_S 21 +/* EXTMEM_IC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by manual pre-load configurations fault.*/ +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST (BIT(20)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_M (BIT(20)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_V 0x1 +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_S 20 +/* EXTMEM_IC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by manual sync configurations fault.*/ +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST (BIT(19)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_M (BIT(19)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_V 0x1 +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_S 19 +/* EXTMEM_IC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by pre-load counter overflow.*/ +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST (BIT(18)) +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_M (BIT(18)) +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_V 0x1 +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_S 18 +/* EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by pre-load miss counter overflow.*/ +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST (BIT(16)) +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_M (BIT(16)) +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_S 16 +/* EXTMEM_IBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus2 abandon counter overflow.*/ +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST (BIT(14)) +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_M (BIT(14)) +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S 14 +/* EXTMEM_IBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus1 abandon counter overflow.*/ +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST (BIT(13)) +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_M (BIT(13)) +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_S 13 +/* EXTMEM_IBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus0 abandon counter overflow.*/ +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST (BIT(12)) +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_M (BIT(12)) +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_S 12 +/* EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus2 miss counter overflow.*/ +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_M (BIT(10)) +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S 10 +/* EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus1 miss counter overflow.*/ +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_M (BIT(9)) +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_S 9 +/* EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus0 miss counter overflow.*/ +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_M (BIT(8)) +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_S 8 +/* EXTMEM_IBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus2 counter overflow.*/ +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST (BIT(6)) +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_M (BIT(6)) +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_S 6 +/* EXTMEM_IBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus1 counter overflow.*/ +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST (BIT(5)) +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_M (BIT(5)) +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_S 5 +/* EXTMEM_IBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus0 counter overflow.*/ +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST (BIT(4)) +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_M (BIT(4)) +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_S 4 +/* EXTMEM_IBUS2_ACS_MSK_ICACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the ibus2 is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST (BIT(2)) +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_M (BIT(2)) +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S 2 +/* EXTMEM_IBUS1_ACS_MSK_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the ibus1 is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST (BIT(1)) +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_M (BIT(1)) +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_S 1 +/* EXTMEM_IBUS0_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the ibus0 is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST (BIT(0)) +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_M (BIT(0)) +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_S 0 + +#define EXTMEM_CACHE_DBG_STATUS1_REG (DR_REG_EXTMEM_BASE + 0x0F4) +/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(30)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(30)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_ST_S 30 +/* EXTMEM_DCACHE_SET_LOCK_ILG_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by illegal writing lock + registers of icache while icache is busy to issue lock sync or pre-load operations.*/ +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST (BIT(29)) +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_M (BIT(29)) +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_V 0x1 +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_S 29 +/* EXTMEM_DCACHE_SET_SYNC_ILG_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by illegal writing sync + registers of icache while icache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST (BIT(28)) +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_M (BIT(28)) +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_V 0x1 +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_S 28 +/* EXTMEM_DCACHE_SET_PRELOAD_ILG_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by illegal writing preload + registers of icache while icache is busy to issue lock sync and pre-load operations.*/ +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST (BIT(27)) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_M (BIT(27)) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V 0x1 +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S 27 +/* EXTMEM_DCACHE_REJECT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_DCACHE_REJECT_ST (BIT(26)) +#define EXTMEM_DCACHE_REJECT_ST_M (BIT(26)) +#define EXTMEM_DCACHE_REJECT_ST_V 0x1 +#define EXTMEM_DCACHE_REJECT_ST_S 26 +/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dcache trying to write flash.*/ +#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(25)) +#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (BIT(25)) +#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x1 +#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 25 +/* EXTMEM_DC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by manual pre-load configurations fault.*/ +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST (BIT(24)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_M (BIT(24)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V 0x1 +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S 24 +/* EXTMEM_DC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by manual sync configurations fault.*/ +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST (BIT(23)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_M (BIT(23)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_V 0x1 +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_S 23 +/* EXTMEM_DC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by pre-load counter overflow.*/ +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST (BIT(22)) +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_M (BIT(22)) +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_V 0x1 +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_S 22 +/* EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by pre-load eviction counter overflow.*/ +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST (BIT(21)) +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_M (BIT(21)) +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V 0x1 +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S 21 +/* EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by pre-load miss counter overflow.*/ +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST (BIT(20)) +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_M (BIT(20)) +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_S 20 +/* EXTMEM_DBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus2 abandon counter overflow.*/ +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST (BIT(18)) +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_M (BIT(18)) +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_S 18 +/* EXTMEM_DBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus1 abandon counter overflow.*/ +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST (BIT(17)) +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_M (BIT(17)) +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S 17 +/* EXTMEM_DBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus0 abandon counter overflow.*/ +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST (BIT(16)) +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_M (BIT(16)) +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_S 16 +/* EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus2 eviction counter overflow.*/ +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST (BIT(14)) +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_M (BIT(14)) +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_S 14 +/* EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus1 eviction counter overflow.*/ +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST (BIT(13)) +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_M (BIT(13)) +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S 13 +/* EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus0 eviction counter overflow.*/ +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST (BIT(12)) +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_M (BIT(12)) +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_S 12 +/* EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus2 miss counter overflow.*/ +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_M (BIT(10)) +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_S 10 +/* EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus1 miss counter overflow.*/ +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_M (BIT(9)) +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S 9 +/* EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus0 miss counter overflow.*/ +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_M (BIT(8)) +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_S 8 +/* EXTMEM_DBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus2 counter overflow.*/ +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST (BIT(6)) +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_M (BIT(6)) +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_S 6 +/* EXTMEM_DBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus1 counter overflow.*/ +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST (BIT(5)) +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_M (BIT(5)) +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_S 5 +/* EXTMEM_DBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus0 counter overflow.*/ +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST (BIT(4)) +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_M (BIT(4)) +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_S 4 +/* EXTMEM_DBUS2_ACS_MSK_DCACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access dcache while + the dbus2 is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST (BIT(2)) +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_M (BIT(2)) +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_V 0x1 +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_S 2 +/* EXTMEM_DBUS1_ACS_MSK_DCACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access dcache while + the dbus1 is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST (BIT(1)) +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_M (BIT(1)) +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V 0x1 +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S 1 +/* EXTMEM_DBUS0_ACS_MSK_DCACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access dcache while + the dbus0 is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST (BIT(0)) +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_M (BIT(0)) +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_V 0x1 +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_S 0 + +#define EXTMEM_PRO_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0F8) +/* EXTMEM_PRO_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG + IC_PRELOAD_MISS_CNT_REG IBUS0-2_ABANDON_CNT_REG IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG.*/ +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR (BIT(1)) +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_M (BIT(1)) +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_V 0x1 +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_S 1 +/* EXTMEM_PRO_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG + DC_PRELOAD_EVICT_CNT_REG DC_PRELOAD_MISS_CNT_REG DBUS0-2_ABANDON_CNT_REG DBUS0-2_ACS_WB_CNT_REG DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG.*/ +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR (BIT(0)) +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_M (BIT(0)) +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V 0x1 +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S 0 + +#define EXTMEM_PRO_DCACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x0FC) +/* EXTMEM_PRO_DCACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access dcache + when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_PRO_DCACHE_CPU_ATTR 0x00000007 +#define EXTMEM_PRO_DCACHE_CPU_ATTR_M ((EXTMEM_PRO_DCACHE_CPU_ATTR_V)<<(EXTMEM_PRO_DCACHE_CPU_ATTR_S)) +#define EXTMEM_PRO_DCACHE_CPU_ATTR_V 0x7 +#define EXTMEM_PRO_DCACHE_CPU_ATTR_S 3 +/* EXTMEM_PRO_DCACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of data from external + memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_PRO_DCACHE_TAG_ATTR 0x00000007 +#define EXTMEM_PRO_DCACHE_TAG_ATTR_M ((EXTMEM_PRO_DCACHE_TAG_ATTR_V)<<(EXTMEM_PRO_DCACHE_TAG_ATTR_S)) +#define EXTMEM_PRO_DCACHE_TAG_ATTR_V 0x7 +#define EXTMEM_PRO_DCACHE_TAG_ATTR_S 0 + +#define EXTMEM_PRO_DCACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x100) +/* EXTMEM_PRO_DCACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address of CPU access + dcache when authentication fail.*/ +#define EXTMEM_PRO_DCACHE_CPU_VADDR 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_CPU_VADDR_M ((EXTMEM_PRO_DCACHE_CPU_VADDR_V)<<(EXTMEM_PRO_DCACHE_CPU_VADDR_S)) +#define EXTMEM_PRO_DCACHE_CPU_VADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_DCACHE_CPU_VADDR_S 0 + +#define EXTMEM_PRO_ICACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x104) +/* EXTMEM_PRO_ICACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access icache + when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ +#define EXTMEM_PRO_ICACHE_CPU_ATTR 0x00000007 +#define EXTMEM_PRO_ICACHE_CPU_ATTR_M ((EXTMEM_PRO_ICACHE_CPU_ATTR_V)<<(EXTMEM_PRO_ICACHE_CPU_ATTR_S)) +#define EXTMEM_PRO_ICACHE_CPU_ATTR_V 0x7 +#define EXTMEM_PRO_ICACHE_CPU_ATTR_S 3 +/* EXTMEM_PRO_ICACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of data from external + memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_PRO_ICACHE_TAG_ATTR 0x00000007 +#define EXTMEM_PRO_ICACHE_TAG_ATTR_M ((EXTMEM_PRO_ICACHE_TAG_ATTR_V)<<(EXTMEM_PRO_ICACHE_TAG_ATTR_S)) +#define EXTMEM_PRO_ICACHE_TAG_ATTR_V 0x7 +#define EXTMEM_PRO_ICACHE_TAG_ATTR_S 0 + +#define EXTMEM_PRO_ICACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x108) +/* EXTMEM_PRO_ICACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address of CPU access + icache when authentication fail.*/ +#define EXTMEM_PRO_ICACHE_CPU_VADDR 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_CPU_VADDR_M ((EXTMEM_PRO_ICACHE_CPU_VADDR_V)<<(EXTMEM_PRO_ICACHE_CPU_VADDR_S)) +#define EXTMEM_PRO_ICACHE_CPU_VADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_ICACHE_CPU_VADDR_S 0 + +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x10C) +/* EXTMEM_PRO_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:17] ;default: 3'h0 ; */ +/*description: The bits are used to indicate the operations which cause mmu + fault occurrence. 0: default 1: cpu miss 2: preload miss 3: flush 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx*/ +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE 0x00000007 +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_M ((EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S)) +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V 0x7 +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S 17 +/* EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[16:0] ;default: 17'h0 ; */ +/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT 0x0001FFFF +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S)) +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V 0x1FFFF +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S 0 + +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x110) +/* EXTMEM_PRO_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address which cause mmu fault..*/ +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S)) +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S 0 + +#define EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x114) +/* EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable wrap around mode when read data from spiram.*/ +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_M (BIT(1)) +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_V 0x1 +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_S 1 +/* EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable wrap around mode when read data from flash.*/ +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND (BIT(0)) +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_V 0x1 +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_S 0 + +#define EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x118) +/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_V 0x1 +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_S 2 +/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_V 0x1 +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_S 1 +/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable clock gating to save power when access + mmu memory 0: enable 1: disable*/ +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_V 0x1 +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_S 0 + +#define EXTMEM_PRO_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x11C) +/* EXTMEM_PRO_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */ +/*description: The bit is used to indicate dcache main fsm is in idle state + or not. 1: in idle state 0: not in idle state*/ +#define EXTMEM_PRO_DCACHE_STATE 0x00000FFF +#define EXTMEM_PRO_DCACHE_STATE_M ((EXTMEM_PRO_DCACHE_STATE_V)<<(EXTMEM_PRO_DCACHE_STATE_S)) +#define EXTMEM_PRO_DCACHE_STATE_V 0xFFF +#define EXTMEM_PRO_DCACHE_STATE_S 12 +/* EXTMEM_PRO_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: The bit is used to indicate icache main fsm is in idle state + or not. 1: in idle state 0: not in idle state*/ +#define EXTMEM_PRO_ICACHE_STATE 0x00000FFF +#define EXTMEM_PRO_ICACHE_STATE_M ((EXTMEM_PRO_ICACHE_STATE_V)<<(EXTMEM_PRO_ICACHE_STATE_S)) +#define EXTMEM_PRO_ICACHE_STATE_V 0xFFF +#define EXTMEM_PRO_ICACHE_STATE_S 0 + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x120) +/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 +/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x124) +/* EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of encrypt and decrypt + clock. 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S 2 +/* EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of decrypt clock. 1: close + gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_M (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_S 1 +/* EXTMEM_CLK_FORCE_ON_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of encrypt clock. 1: close + gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_M (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S 0 + +#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) +/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (BIT(0)) +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x1 +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 + +#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12C) +/* EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by dcache pre-load done.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR (BIT(5)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_M (BIT(5)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_V 0x1 +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_S 5 +/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by dcache pre-load done.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA (BIT(4)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_M (BIT(4)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S 4 +/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by dcache pre-load done.*/ +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST (BIT(3)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_M (BIT(3)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_V 0x1 +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_S 3 +/* EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by icache pre-load done.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR (BIT(2)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_V 0x1 +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_S 2 +/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by icache pre-load done.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA (BIT(1)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S 1 +/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by icache pre-load done.*/ +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST (BIT(0)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_M (BIT(0)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_V 0x1 +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_S 0 + +#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x130) +/* EXTMEM_PRO_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by dcache sync done.*/ +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR (BIT(5)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_M (BIT(5)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_V 0x1 +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_S 5 +/* EXTMEM_PRO_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by dcache sync done.*/ +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA (BIT(4)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_M (BIT(4)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V 0x1 +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S 4 +/* EXTMEM_PRO_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by dcache sync done.*/ +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST (BIT(3)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_M (BIT(3)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_V 0x1 +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_S 3 +/* EXTMEM_PRO_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by icache sync done.*/ +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR (BIT(2)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_M (BIT(2)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_V 0x1 +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_S 2 +/* EXTMEM_PRO_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by icache sync done.*/ +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA (BIT(1)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_M (BIT(1)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V 0x1 +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S 1 +/* EXTMEM_PRO_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by icache sync done.*/ +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST (BIT(0)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_M (BIT(0)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_V 0x1 +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_S 0 + +#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x134) +/* EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable checking mmu entry fault by sync operation.*/ +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 +/* EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable checking mmu entry fault by preload operation.*/ +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 + +#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x138) /* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ +/*description: Reserved.*/ #define EXTMEM_CLK_EN (BIT(0)) #define EXTMEM_CLK_EN_M (BIT(0)) #define EXTMEM_CLK_EN_V 0x1 #define EXTMEM_CLK_EN_S 0 #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) -/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810250 ; */ -/*description: */ +/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1904180 ; */ +/*description: Reserved.*/ #define EXTMEM_DATE 0x0FFFFFFF #define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) #define EXTMEM_DATE_V 0xFFFFFFF diff --git a/components/soc/esp32s2beta/include/soc/gpio_reg.h b/components/soc/esp32s2beta/include/soc/gpio_reg.h index 03ed89292d..a7fd4c6230 100644 --- a/components/soc/esp32s2beta/include/soc/gpio_reg.h +++ b/components/soc/esp32s2beta/include/soc/gpio_reg.h @@ -83,7 +83,7 @@ extern "C" { /* GPIO_OUT1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ /*description: */ #define GPIO_OUT1_DATA 0x003FFFFF -#define GPIO_OUT1_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) #define GPIO_OUT1_DATA_V 0x3FFFFF #define GPIO_OUT1_DATA_S 0 @@ -2664,7 +2664,7 @@ extern "C" { #define GPIO_STATUS_INTERRUPT_NEXT_S 0 #define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) -/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ /*description: */ #define GPIO_STATUS_INTERRUPT_NEXT1 0x003FFFFF #define GPIO_STATUS_INTERRUPT_NEXT1_M ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S)) @@ -9204,7 +9204,7 @@ extern "C" { #define GPIO_CLK_EN_S 0 #define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) -/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809040 ; */ +/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905061 ; */ /*description: */ #define GPIO_DATE 0x0FFFFFFF #define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/gpio_sig_map.h b/components/soc/esp32s2beta/include/soc/gpio_sig_map.h index 6215328d18..8247a4227c 100644 --- a/components/soc/esp32s2beta/include/soc/gpio_sig_map.h +++ b/components/soc/esp32s2beta/include/soc/gpio_sig_map.h @@ -4,285 +4,316 @@ // you may not use this file except in compliance with the License. // You may obtain a copy of the License at -#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX -#define CLK_I2S_IDX CLK_I2S_MUX_IDX +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SIG_MAP_H_ +#define _SOC_GPIO_SIG_MAP_H_ +#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX +#define CLK_I2S_IDX CLK_I2S_MUX_IDX +#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX -#define SPIQ_IN_IDX 0 -#define SPIQ_OUT_IDX 0 -#define SPID_IN_IDX 1 -#define SPID_OUT_IDX 1 -#define SPIHD_IN_IDX 2 -#define SPIHD_OUT_IDX 2 -#define SPIWP_IN_IDX 3 -#define SPIWP_OUT_IDX 3 -#define SPICLK_OUT_MUX_IDX 4 -#define SPICS0_OUT_IDX 5 -#define SPICS1_OUT_IDX 6 -#define FSPICD_OUT_IDX 9 -#define SPI3_CD_OUT_IDX 10 -#define SPI4_CD_OUT_IDX 11 -#define U0RXD_IN_IDX 14 -#define U0TXD_OUT_IDX 14 -#define U0CTS_IN_IDX 15 -#define U0RTS_OUT_IDX 15 -#define U0DSR_IN_IDX 16 -#define U0DTR_OUT_IDX 16 -#define U1RXD_IN_IDX 17 -#define U1TXD_OUT_IDX 17 -#define U1CTS_IN_IDX 18 -#define U1RTS_OUT_IDX 18 -#define U1DSR_IN_IDX 21 -#define U1DTR_OUT_IDX 21 -#define I2S0O_BCK_IN_IDX 23 -#define I2S0O_BCK_OUT_IDX 23 -#define I2S0O_WS_IN_IDX 25 -#define I2S0O_WS_OUT_IDX 25 -#define I2S0I_BCK_IN_IDX 27 -#define I2S0I_BCK_OUT_IDX 27 -#define I2S0I_WS_IN_IDX 28 -#define I2S0I_WS_OUT_IDX 28 -#define I2CEXT0_SCL_IN_IDX 29 -#define I2CEXT0_SCL_OUT_IDX 29 -#define I2CEXT0_SDA_IN_IDX 30 -#define I2CEXT0_SDA_OUT_IDX 30 -#define SDIO_TOHOST_INT_OUT_IDX 31 -#define GPIO_BT_ACTIVE_IDX 37 -#define GPIO_BT_PRIORITY_IDX 38 -#define PCNT_SIG_CH0_IN0_IDX 39 -#define GPIO_WLAN_PRIO_IDX 39 -#define PCNT_SIG_CH1_IN0_IDX 40 -#define GPIO_WLAN_ACTIVE_IDX 40 -#define PCNT_CTRL_CH0_IN0_IDX 41 -#define BB_DIAG0_IDX 41 -#define PCNT_CTRL_CH1_IN0_IDX 42 -#define BB_DIAG1_IDX 42 -#define PCNT_SIG_CH0_IN1_IDX 43 -#define BB_DIAG2_IDX 43 -#define PCNT_SIG_CH1_IN1_IDX 44 -#define BB_DIAG3_IDX 44 -#define PCNT_CTRL_CH0_IN1_IDX 45 -#define BB_DIAG4_IDX 45 -#define PCNT_CTRL_CH1_IN1_IDX 46 -#define BB_DIAG5_IDX 46 -#define PCNT_SIG_CH0_IN2_IDX 47 -#define BB_DIAG6_IDX 47 -#define PCNT_SIG_CH1_IN2_IDX 48 -#define BB_DIAG7_IDX 48 -#define PCNT_CTRL_CH0_IN2_IDX 49 -#define BB_DIAG8_IDX 49 -#define PCNT_CTRL_CH1_IN2_IDX 50 -#define BB_DIAG9_IDX 50 -#define PCNT_SIG_CH0_IN3_IDX 51 -#define BB_DIAG10_IDX 51 -#define PCNT_SIG_CH1_IN3_IDX 52 -#define BB_DIAG11_IDX 52 -#define PCNT_CTRL_CH0_IN3_IDX 53 -#define BB_DIAG12_IDX 53 -#define PCNT_CTRL_CH1_IN3_IDX 54 -#define BB_DIAG13_IDX 54 -#define BB_DIAG14_IDX 55 -#define BB_DIAG15_IDX 56 -#define BB_DIAG16_IDX 57 -#define BB_DIAG17_IDX 58 -#define BB_DIAG18_IDX 59 -#define BB_DIAG19_IDX 60 -#define USB_EXTPHY_VP_IDX 61 -#define USB_EXTPHY_OEN_IDX 61 -#define USB_EXTPHY_VM_IDX 62 -#define USB_EXTPHY_SPEED_IDX 62 -#define USB_EXTPHY_RCV_IDX 63 -#define USB_EXTPHY_VPO_IDX 63 -#define USB_OTG_IDDIG_IN_IDX 64 -#define USB_EXTPHY_VMO_IDX 64 -#define USB_OTG_AVALID_IN_IDX 65 -#define USB_EXTPHY_SUSPND_IDX 65 -#define USB_SRP_BVALID_IN_IDX 66 -#define USB_OTG_IDPULLUP_IDX 66 -#define USB_OTG_VBUSVALID_IN_IDX 67 -#define USB_OTG_DPPULLDOWN_IDX 67 -#define USB_SRP_SESSEND_IN_IDX 68 -#define USB_OTG_DMPULLDOWN_IDX 68 -#define USB_OTG_DRVVBUS_IDX 69 -#define USB_SRP_CHRGVBUS_IDX 70 -#define USB_SRP_DISCHRGVBUS_IDX 71 -#define SPI3_CLK_IN_IDX 72 -#define SPI3_CLK_OUT_MUX_IDX 72 -#define SPI3_Q_IN_IDX 73 -#define SPI3_Q_OUT_IDX 73 -#define SPI3_D_IN_IDX 74 -#define SPI3_D_OUT_IDX 74 -#define SPI3_HD_IN_IDX 75 -#define SPI3_HD_OUT_IDX 75 -#define SPI3_CS0_IN_IDX 76 -#define SPI3_CS0_OUT_IDX 76 -#define SPI3_CS1_OUT_IDX 77 -#define SPI3_CS2_OUT_IDX 78 -#define LEDC_LS_SIG_OUT0_IDX 79 -#define LEDC_LS_SIG_OUT1_IDX 80 -#define LEDC_LS_SIG_OUT2_IDX 81 -#define LEDC_LS_SIG_OUT3_IDX 82 -#define RMT_SIG_IN0_IDX 83 -#define LEDC_LS_SIG_OUT4_IDX 83 -#define RMT_SIG_IN1_IDX 84 -#define LEDC_LS_SIG_OUT5_IDX 84 -#define RMT_SIG_IN2_IDX 85 -#define LEDC_LS_SIG_OUT6_IDX 85 -#define RMT_SIG_IN3_IDX 86 -#define LEDC_LS_SIG_OUT7_IDX 86 -#define RMT_SIG_OUT0_IDX 87 -#define RMT_SIG_OUT1_IDX 88 -#define RMT_SIG_OUT2_IDX 89 -#define RMT_SIG_OUT3_IDX 90 -#define EXT_ADC_START_IDX 93 -#define I2CEXT1_SCL_IN_IDX 95 -#define I2CEXT1_SCL_OUT_IDX 95 -#define I2CEXT1_SDA_IN_IDX 96 -#define I2CEXT1_SDA_OUT_IDX 96 -#define GPIO_SD0_OUT_IDX 100 -#define GPIO_SD1_OUT_IDX 101 -#define GPIO_SD2_OUT_IDX 102 -#define GPIO_SD3_OUT_IDX 103 -#define GPIO_SD4_OUT_IDX 104 -#define GPIO_SD5_OUT_IDX 105 -#define GPIO_SD6_OUT_IDX 106 -#define GPIO_SD7_OUT_IDX 107 -#define SPI4_CLK_IN_IDX 108 -#define SPI4_CLK_OUT_MUX_IDX 108 -#define SPI4_Q_IN_IDX 109 -#define SPI4_Q_OUT_IDX 109 -#define SPI4_D_IN_IDX 110 -#define SPI4_D_OUT_IDX 110 -#define SPI4_HD_IN_IDX 111 -#define SPI4_HD_OUT_IDX 111 -#define SPI4_CS0_IN_IDX 112 -#define SPI4_CS0_OUT_IDX 112 -#define SPI4_CS1_OUT_IDX 113 -#define SPI4_CS2_OUT_IDX 114 -#define FSPICLK_IN_IDX 115 -#define FSPICLK_OUT_MUX_IDX 115 -#define FSPIQ_IN_IDX 116 -#define FSPIQ_OUT_IDX 116 -#define FSPID_IN_IDX 117 -#define FSPID_OUT_IDX 117 -#define FSPIHD_IN_IDX 118 -#define FSPIHD_OUT_IDX 118 -#define FSPIWP_IN_IDX 119 -#define FSPIWP_OUT_IDX 119 -#define FSPICS0_IN_IDX 120 -#define FSPICS0_OUT_IDX 120 -#define FSPICS1_OUT_IDX 121 -#define FSPICS2_OUT_IDX 122 -#define CAN_RX_IDX 123 -#define CAN_TX_IDX 123 -#define CAN_BUS_OFF_ON_IDX 124 -#define CAN_CLKOUT_IDX 125 -#define SUBSPICLK_OUT_MUX_IDX 126 -#define SUBSPIQ_IN_IDX 127 -#define SUBSPIQ_OUT_IDX 127 -#define SUBSPID_IN_IDX 128 -#define SUBSPID_OUT_IDX 128 -#define SUBSPIHD_IN_IDX 129 -#define SUBSPIHD_OUT_IDX 129 -#define SUBSPIWP_IN_IDX 130 -#define SUBSPIWP_OUT_IDX 130 -#define SUBSPICS0_OUT_IDX 131 -#define SUBSPICS1_OUT_IDX 132 -#define FSPIDQS_OUT_IDX 133 -#define SPI3_DQS_OUT_IDX 134 -#define SPI4_DQS_OUT_IDX 135 -#define I2S0I_DATA_IN0_IDX 143 -#define I2S0O_DATA_OUT0_IDX 143 -#define I2S0I_DATA_IN1_IDX 144 -#define I2S0O_DATA_OUT1_IDX 144 -#define I2S0I_DATA_IN2_IDX 145 -#define I2S0O_DATA_OUT2_IDX 145 -#define I2S0I_DATA_IN3_IDX 146 -#define I2S0O_DATA_OUT3_IDX 146 -#define I2S0I_DATA_IN4_IDX 147 -#define I2S0O_DATA_OUT4_IDX 147 -#define I2S0I_DATA_IN5_IDX 148 -#define I2S0O_DATA_OUT5_IDX 148 -#define I2S0I_DATA_IN6_IDX 149 -#define I2S0O_DATA_OUT6_IDX 149 -#define I2S0I_DATA_IN7_IDX 150 -#define I2S0O_DATA_OUT7_IDX 150 -#define I2S0I_DATA_IN8_IDX 151 -#define I2S0O_DATA_OUT8_IDX 151 -#define I2S0I_DATA_IN9_IDX 152 -#define I2S0O_DATA_OUT9_IDX 152 -#define I2S0I_DATA_IN10_IDX 153 -#define I2S0O_DATA_OUT10_IDX 153 -#define I2S0I_DATA_IN11_IDX 154 -#define I2S0O_DATA_OUT11_IDX 154 -#define I2S0I_DATA_IN12_IDX 155 -#define I2S0O_DATA_OUT12_IDX 155 -#define I2S0I_DATA_IN13_IDX 156 -#define I2S0O_DATA_OUT13_IDX 156 -#define I2S0I_DATA_IN14_IDX 157 -#define I2S0O_DATA_OUT14_IDX 157 -#define I2S0I_DATA_IN15_IDX 158 -#define I2S0O_DATA_OUT15_IDX 158 -#define I2S0O_DATA_OUT16_IDX 159 -#define I2S0O_DATA_OUT17_IDX 160 -#define I2S0O_DATA_OUT18_IDX 161 -#define I2S0O_DATA_OUT19_IDX 162 -#define I2S0O_DATA_OUT20_IDX 163 -#define I2S0O_DATA_OUT21_IDX 164 -#define I2S0O_DATA_OUT22_IDX 165 -#define I2S0O_DATA_OUT23_IDX 166 -#define I2S0I_H_SYNC_IDX 193 -#define I2S0I_V_SYNC_IDX 194 -#define I2S0I_H_ENABLE_IDX 195 -#define PCMFSYNC_IN_IDX 203 -#define BT_AUDIO0_IRQ_IDX 203 -#define PCMCLK_IN_IDX 204 -#define BT_AUDIO1_IRQ_IDX 204 -#define PCMDIN_IDX 205 -#define BT_AUDIO2_IRQ_IDX 205 -#define RW_WAKEUP_REQ_IDX 206 -#define BLE_AUDIO0_IRQ_IDX 206 -#define BLE_AUDIO1_IRQ_IDX 207 -#define BLE_AUDIO2_IRQ_IDX 208 -#define PCMFSYNC_OUT_IDX 209 -#define PCMCLK_OUT_IDX 210 -#define PCMDOUT_IDX 211 -#define BLE_AUDIO_SYNC0_P_IDX 212 -#define BLE_AUDIO_SYNC1_P_IDX 213 -#define BLE_AUDIO_SYNC2_P_IDX 214 -#define ANT_SEL0_IDX 215 -#define ANT_SEL1_IDX 216 -#define ANT_SEL2_IDX 217 -#define ANT_SEL3_IDX 218 -#define ANT_SEL4_IDX 219 -#define ANT_SEL5_IDX 220 -#define ANT_SEL6_IDX 221 -#define ANT_SEL7_IDX 222 -#define SIG_IN_FUNC_223_IDX 223 -#define SIG_IN_FUNC223_IDX 223 -#define SIG_IN_FUNC_224_IDX 224 -#define SIG_IN_FUNC224_IDX 224 -#define SIG_IN_FUNC_225_IDX 225 -#define SIG_IN_FUNC225_IDX 225 -#define SIG_IN_FUNC_226_IDX 226 -#define SIG_IN_FUNC226_IDX 226 -#define SIG_IN_FUNC_227_IDX 227 -#define SIG_IN_FUNC227_IDX 227 -#define PRO_ALONEGPIO_IN0_IDX 235 -#define PRO_ALONEGPIO_OUT0_IDX 235 -#define PRO_ALONEGPIO_IN1_IDX 236 -#define PRO_ALONEGPIO_OUT1_IDX 236 -#define PRO_ALONEGPIO_IN2_IDX 237 -#define PRO_ALONEGPIO_OUT2_IDX 237 -#define PRO_ALONEGPIO_IN3_IDX 238 -#define PRO_ALONEGPIO_OUT3_IDX 238 -#define PRO_ALONEGPIO_IN4_IDX 239 -#define PRO_ALONEGPIO_OUT4_IDX 239 -#define PRO_ALONEGPIO_IN5_IDX 240 -#define PRO_ALONEGPIO_OUT5_IDX 240 -#define PRO_ALONEGPIO_IN6_IDX 241 -#define PRO_ALONEGPIO_OUT6_IDX 241 -#define PRO_ALONEGPIO_IN7_IDX 242 -#define PRO_ALONEGPIO_OUT7_IDX 242 -#define CLK_I2S_MUX_IDX 251 -#define SIG_GPIO_OUT_IDX 256 -#define GPIO_MAP_DATE_IDX 0x18102600 +#define SPIQ_IN_IDX 0 +#define SPIQ_OUT_IDX 0 +#define SPID_IN_IDX 1 +#define SPID_OUT_IDX 1 +#define SPIHD_IN_IDX 2 +#define SPIHD_OUT_IDX 2 +#define SPIWP_IN_IDX 3 +#define SPIWP_OUT_IDX 3 +#define SPICLK_OUT_MUX_IDX 4 +#define SPICS0_OUT_IDX 5 +#define SPICS1_OUT_IDX 6 +#define SPID4_IN_IDX 7 +#define SPID4_OUT_IDX 7 +#define SPID5_IN_IDX 8 +#define SPID5_OUT_IDX 8 +#define SPID6_IN_IDX 9 +#define SPID6_OUT_IDX 9 +#define SPID7_IN_IDX 10 +#define SPID7_OUT_IDX 10 +#define SPIDQS_IN_IDX 11 +#define SPIDQS_OUT_IDX 11 +#define U0RXD_IN_IDX 14 +#define U0TXD_OUT_IDX 14 +#define U0CTS_IN_IDX 15 +#define U0RTS_OUT_IDX 15 +#define U0DSR_IN_IDX 16 +#define U0DTR_OUT_IDX 16 +#define U1RXD_IN_IDX 17 +#define U1TXD_OUT_IDX 17 +#define U1CTS_IN_IDX 18 +#define U1RTS_OUT_IDX 18 +#define U1DSR_IN_IDX 21 +#define U1DTR_OUT_IDX 21 +#define I2S0O_BCK_IN_IDX 23 +#define I2S0O_BCK_OUT_IDX 23 +#define I2S0O_WS_IN_IDX 25 +#define I2S0O_WS_OUT_IDX 25 +#define I2S0I_BCK_IN_IDX 27 +#define I2S0I_BCK_OUT_IDX 27 +#define I2S0I_WS_IN_IDX 28 +#define I2S0I_WS_OUT_IDX 28 +#define I2CEXT0_SCL_IN_IDX 29 +#define I2CEXT0_SCL_OUT_IDX 29 +#define I2CEXT0_SDA_IN_IDX 30 +#define I2CEXT0_SDA_OUT_IDX 30 +#define SDIO_TOHOST_INT_OUT_IDX 31 +#define GPIO_BT_ACTIVE_IDX 37 +#define GPIO_BT_PRIORITY_IDX 38 +#define PCNT_SIG_CH0_IN0_IDX 39 +#define GPIO_WLAN_PRIO_IDX 39 +#define PCNT_SIG_CH1_IN0_IDX 40 +#define GPIO_WLAN_ACTIVE_IDX 40 +#define PCNT_CTRL_CH0_IN0_IDX 41 +#define BB_DIAG0_IDX 41 +#define PCNT_CTRL_CH1_IN0_IDX 42 +#define BB_DIAG1_IDX 42 +#define PCNT_SIG_CH0_IN1_IDX 43 +#define BB_DIAG2_IDX 43 +#define PCNT_SIG_CH1_IN1_IDX 44 +#define BB_DIAG3_IDX 44 +#define PCNT_CTRL_CH0_IN1_IDX 45 +#define BB_DIAG4_IDX 45 +#define PCNT_CTRL_CH1_IN1_IDX 46 +#define BB_DIAG5_IDX 46 +#define PCNT_SIG_CH0_IN2_IDX 47 +#define BB_DIAG6_IDX 47 +#define PCNT_SIG_CH1_IN2_IDX 48 +#define BB_DIAG7_IDX 48 +#define PCNT_CTRL_CH0_IN2_IDX 49 +#define BB_DIAG8_IDX 49 +#define PCNT_CTRL_CH1_IN2_IDX 50 +#define BB_DIAG9_IDX 50 +#define PCNT_SIG_CH0_IN3_IDX 51 +#define BB_DIAG10_IDX 51 +#define PCNT_SIG_CH1_IN3_IDX 52 +#define BB_DIAG11_IDX 52 +#define PCNT_CTRL_CH0_IN3_IDX 53 +#define BB_DIAG12_IDX 53 +#define PCNT_CTRL_CH1_IN3_IDX 54 +#define BB_DIAG13_IDX 54 +#define BB_DIAG14_IDX 55 +#define BB_DIAG15_IDX 56 +#define BB_DIAG16_IDX 57 +#define BB_DIAG17_IDX 58 +#define BB_DIAG18_IDX 59 +#define BB_DIAG19_IDX 60 +#define USB_EXTPHY_VP_IDX 61 +#define USB_EXTPHY_OEN_IDX 61 +#define USB_EXTPHY_VM_IDX 62 +#define USB_EXTPHY_SPEED_IDX 62 +#define USB_EXTPHY_RCV_IDX 63 +#define USB_EXTPHY_VPO_IDX 63 +#define USB_OTG_IDDIG_IN_IDX 64 +#define USB_EXTPHY_VMO_IDX 64 +#define USB_OTG_AVALID_IN_IDX 65 +#define USB_EXTPHY_SUSPND_IDX 65 +#define USB_SRP_BVALID_IN_IDX 66 +#define USB_OTG_IDPULLUP_IDX 66 +#define USB_OTG_VBUSVALID_IN_IDX 67 +#define USB_OTG_DPPULLDOWN_IDX 67 +#define USB_SRP_SESSEND_IN_IDX 68 +#define USB_OTG_DMPULLDOWN_IDX 68 +#define USB_OTG_DRVVBUS_IDX 69 +#define USB_SRP_CHRGVBUS_IDX 70 +#define USB_SRP_DISCHRGVBUS_IDX 71 +#define SPI3_CLK_IN_IDX 72 +#define SPI3_CLK_OUT_MUX_IDX 72 +#define SPI3_Q_IN_IDX 73 +#define SPI3_Q_OUT_IDX 73 +#define SPI3_D_IN_IDX 74 +#define SPI3_D_OUT_IDX 74 +#define SPI3_HD_IN_IDX 75 +#define SPI3_HD_OUT_IDX 75 +#define SPI3_CS0_IN_IDX 76 +#define SPI3_CS0_OUT_IDX 76 +#define SPI3_CS1_OUT_IDX 77 +#define SPI3_CS2_OUT_IDX 78 +#define LEDC_LS_SIG_OUT0_IDX 79 +#define LEDC_LS_SIG_OUT1_IDX 80 +#define LEDC_LS_SIG_OUT2_IDX 81 +#define LEDC_LS_SIG_OUT3_IDX 82 +#define RMT_SIG_IN0_IDX 83 +#define LEDC_LS_SIG_OUT4_IDX 83 +#define RMT_SIG_IN1_IDX 84 +#define LEDC_LS_SIG_OUT5_IDX 84 +#define RMT_SIG_IN2_IDX 85 +#define LEDC_LS_SIG_OUT6_IDX 85 +#define RMT_SIG_IN3_IDX 86 +#define LEDC_LS_SIG_OUT7_IDX 86 +#define RMT_SIG_OUT0_IDX 87 +#define RMT_SIG_OUT1_IDX 88 +#define RMT_SIG_OUT2_IDX 89 +#define RMT_SIG_OUT3_IDX 90 +#define EXT_ADC_START_IDX 93 +#define I2CEXT1_SCL_IN_IDX 95 +#define I2CEXT1_SCL_OUT_IDX 95 +#define I2CEXT1_SDA_IN_IDX 96 +#define I2CEXT1_SDA_OUT_IDX 96 +#define GPIO_SD0_OUT_IDX 100 +#define GPIO_SD1_OUT_IDX 101 +#define GPIO_SD2_OUT_IDX 102 +#define GPIO_SD3_OUT_IDX 103 +#define GPIO_SD4_OUT_IDX 104 +#define GPIO_SD5_OUT_IDX 105 +#define GPIO_SD6_OUT_IDX 106 +#define GPIO_SD7_OUT_IDX 107 +#define FSPICLK_IN_IDX 108 +#define FSPICLK_OUT_MUX_IDX 108 +#define FSPIQ_IN_IDX 109 +#define FSPIQ_OUT_IDX 109 +#define FSPID_IN_IDX 110 +#define FSPID_OUT_IDX 110 +#define FSPIHD_IN_IDX 111 +#define FSPIHD_OUT_IDX 111 +#define FSPIWP_IN_IDX 112 +#define FSPIWP_OUT_IDX 112 +#define FSPIIO4_IN_IDX 113 +#define FSPIIO4_OUT_IDX 113 +#define FSPIIO5_IN_IDX 114 +#define FSPIIO5_OUT_IDX 114 +#define FSPIIO6_IN_IDX 115 +#define FSPIIO6_OUT_IDX 115 +#define FSPIIO7_IN_IDX 116 +#define FSPIIO7_OUT_IDX 116 +#define FSPICS0_IN_IDX 117 +#define FSPICS0_OUT_IDX 117 +#define FSPICS1_OUT_IDX 118 +#define FSPICS2_OUT_IDX 119 +#define FSPICS3_OUT_IDX 120 +#define FSPICS4_OUT_IDX 121 +#define FSPICS5_OUT_IDX 122 +#define CAN_RX_IDX 123 +#define CAN_TX_IDX 123 +#define CAN_BUS_OFF_ON_IDX 124 +#define CAN_CLKOUT_IDX 125 +#define SUBSPICLK_OUT_MUX_IDX 126 +#define SUBSPIQ_IN_IDX 127 +#define SUBSPIQ_OUT_IDX 127 +#define SUBSPID_IN_IDX 128 +#define SUBSPID_OUT_IDX 128 +#define SUBSPIHD_IN_IDX 129 +#define SUBSPIHD_OUT_IDX 129 +#define SUBSPIWP_IN_IDX 130 +#define SUBSPIWP_OUT_IDX 130 +#define SUBSPICS0_OUT_IDX 131 +#define SUBSPICS1_OUT_IDX 132 +#define FSPIDQS_OUT_IDX 133 +#define FSPI_HSYNC_OUT_IDX 134 +#define FSPI_VSYNC_OUT_IDX 135 +#define FSPI_DE_OUT_IDX 136 +#define FSPICD_OUT_IDX 137 +#define SPI3_CD_OUT_IDX 139 +#define SPI3_DQS_OUT_IDX 140 +#define I2S0I_DATA_IN0_IDX 143 +#define I2S0O_DATA_OUT0_IDX 143 +#define I2S0I_DATA_IN1_IDX 144 +#define I2S0O_DATA_OUT1_IDX 144 +#define I2S0I_DATA_IN2_IDX 145 +#define I2S0O_DATA_OUT2_IDX 145 +#define I2S0I_DATA_IN3_IDX 146 +#define I2S0O_DATA_OUT3_IDX 146 +#define I2S0I_DATA_IN4_IDX 147 +#define I2S0O_DATA_OUT4_IDX 147 +#define I2S0I_DATA_IN5_IDX 148 +#define I2S0O_DATA_OUT5_IDX 148 +#define I2S0I_DATA_IN6_IDX 149 +#define I2S0O_DATA_OUT6_IDX 149 +#define I2S0I_DATA_IN7_IDX 150 +#define I2S0O_DATA_OUT7_IDX 150 +#define I2S0I_DATA_IN8_IDX 151 +#define I2S0O_DATA_OUT8_IDX 151 +#define I2S0I_DATA_IN9_IDX 152 +#define I2S0O_DATA_OUT9_IDX 152 +#define I2S0I_DATA_IN10_IDX 153 +#define I2S0O_DATA_OUT10_IDX 153 +#define I2S0I_DATA_IN11_IDX 154 +#define I2S0O_DATA_OUT11_IDX 154 +#define I2S0I_DATA_IN12_IDX 155 +#define I2S0O_DATA_OUT12_IDX 155 +#define I2S0I_DATA_IN13_IDX 156 +#define I2S0O_DATA_OUT13_IDX 156 +#define I2S0I_DATA_IN14_IDX 157 +#define I2S0O_DATA_OUT14_IDX 157 +#define I2S0I_DATA_IN15_IDX 158 +#define I2S0O_DATA_OUT15_IDX 158 +#define I2S0O_DATA_OUT16_IDX 159 +#define I2S0O_DATA_OUT17_IDX 160 +#define I2S0O_DATA_OUT18_IDX 161 +#define I2S0O_DATA_OUT19_IDX 162 +#define I2S0O_DATA_OUT20_IDX 163 +#define I2S0O_DATA_OUT21_IDX 164 +#define I2S0O_DATA_OUT22_IDX 165 +#define I2S0O_DATA_OUT23_IDX 166 +#define SUBSPID4_IN_IDX 167 +#define SUBSPID4_OUT_IDX 167 +#define SUBSPID5_IN_IDX 168 +#define SUBSPID5_OUT_IDX 168 +#define SUBSPID6_IN_IDX 169 +#define SUBSPID6_OUT_IDX 169 +#define SUBSPID7_IN_IDX 170 +#define SUBSPID7_OUT_IDX 170 +#define SUBSPIDQS_IN_IDX 171 +#define SUBSPIDQS_OUT_IDX 171 +#define I2S0I_H_SYNC_IDX 193 +#define I2S0I_V_SYNC_IDX 194 +#define I2S0I_H_ENABLE_IDX 195 +#define PCMFSYNC_IN_IDX 203 +#define BT_AUDIO0_IRQ_IDX 203 +#define PCMCLK_IN_IDX 204 +#define BT_AUDIO1_IRQ_IDX 204 +#define PCMDIN_IDX 205 +#define BT_AUDIO2_IRQ_IDX 205 +#define RW_WAKEUP_REQ_IDX 206 +#define BLE_AUDIO0_IRQ_IDX 206 +#define BLE_AUDIO1_IRQ_IDX 207 +#define BLE_AUDIO2_IRQ_IDX 208 +#define PCMFSYNC_OUT_IDX 209 +#define PCMCLK_OUT_IDX 210 +#define PCMDOUT_IDX 211 +#define BLE_AUDIO_SYNC0_P_IDX 212 +#define BLE_AUDIO_SYNC1_P_IDX 213 +#define BLE_AUDIO_SYNC2_P_IDX 214 +#define ANT_SEL0_IDX 215 +#define ANT_SEL1_IDX 216 +#define ANT_SEL2_IDX 217 +#define ANT_SEL3_IDX 218 +#define ANT_SEL4_IDX 219 +#define ANT_SEL5_IDX 220 +#define ANT_SEL6_IDX 221 +#define ANT_SEL7_IDX 222 +#define SIG_IN_FUNC_223_IDX 223 +#define SIG_IN_FUNC223_IDX 223 +#define SIG_IN_FUNC_224_IDX 224 +#define SIG_IN_FUNC224_IDX 224 +#define SIG_IN_FUNC_225_IDX 225 +#define SIG_IN_FUNC225_IDX 225 +#define SIG_IN_FUNC_226_IDX 226 +#define SIG_IN_FUNC226_IDX 226 +#define SIG_IN_FUNC_227_IDX 227 +#define SIG_IN_FUNC227_IDX 227 +#define PRO_ALONEGPIO_IN0_IDX 235 +#define PRO_ALONEGPIO_OUT0_IDX 235 +#define PRO_ALONEGPIO_IN1_IDX 236 +#define PRO_ALONEGPIO_OUT1_IDX 236 +#define PRO_ALONEGPIO_IN2_IDX 237 +#define PRO_ALONEGPIO_OUT2_IDX 237 +#define PRO_ALONEGPIO_IN3_IDX 238 +#define PRO_ALONEGPIO_OUT3_IDX 238 +#define PRO_ALONEGPIO_IN4_IDX 239 +#define PRO_ALONEGPIO_OUT4_IDX 239 +#define PRO_ALONEGPIO_IN5_IDX 240 +#define PRO_ALONEGPIO_OUT5_IDX 240 +#define PRO_ALONEGPIO_IN6_IDX 241 +#define PRO_ALONEGPIO_OUT6_IDX 241 +#define PRO_ALONEGPIO_IN7_IDX 242 +#define PRO_ALONEGPIO_OUT7_IDX 242 +#define CLK_I2S_MUX_IDX 251 +#define SIG_GPIO_OUT_IDX 256 +#define GPIO_MAP_DATE_IDX 0x1904100 +#endif /* _SOC_GPIO_SIG_MAP_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/gpio_struct.h b/components/soc/esp32s2beta/include/soc/gpio_struct.h index cb6f2f5e28..70e82ee1fe 100644 --- a/components/soc/esp32s2beta/include/soc/gpio_struct.h +++ b/components/soc/esp32s2beta/include/soc/gpio_struct.h @@ -18,10 +18,10 @@ extern "C" { #endif typedef volatile struct { - uint32_t bt_select; /**/ - uint32_t out; /**/ - uint32_t out_w1ts; /**/ - uint32_t out_w1tc; /**/ + uint32_t bt_select; /**/ + uint32_t out; /**/ + uint32_t out_w1ts; /**/ + uint32_t out_w1tc; /**/ union { struct { uint32_t data: 22; @@ -50,9 +50,9 @@ typedef volatile struct { }; uint32_t val; } sdio_select; - uint32_t enable; /**/ - uint32_t enable_w1ts; /**/ - uint32_t enable_w1tc; /**/ + uint32_t enable; /**/ + uint32_t enable_w1ts; /**/ + uint32_t enable_w1tc; /**/ union { struct { uint32_t data: 22; @@ -81,7 +81,7 @@ typedef volatile struct { }; uint32_t val; } strap; - uint32_t in; /**/ + uint32_t in; /**/ union { struct { uint32_t data: 22; @@ -89,9 +89,9 @@ typedef volatile struct { }; uint32_t val; } in1; - uint32_t status; /**/ - uint32_t status_w1ts; /**/ - uint32_t status_w1tc; /**/ + uint32_t status; /**/ + uint32_t status_w1ts; /**/ + uint32_t status_w1tc; /**/ union { struct { uint32_t intr_st: 22; @@ -113,9 +113,9 @@ typedef volatile struct { }; uint32_t val; } status1_w1tc; - uint32_t pcpu_int; /**/ - uint32_t pcpu_nmi_int; /**/ - uint32_t cpusdio_int; /**/ + uint32_t pcpu_int; /**/ + uint32_t pcpu_nmi_int; /**/ + uint32_t cpusdio_int; /**/ union { struct { uint32_t intr: 22; diff --git a/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h b/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h index cccd2fbeef..b3832eb6b0 100644 --- a/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h +++ b/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h @@ -42,37 +42,123 @@ /* Interrupt registers */ #define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818) #define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C) +#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) + +#define SHA_MODE_SHA1 0 +#define SHA_MODE_SHA224 1 +#define SHA_MODE_SHA256 2 +#define SHA_MODE_SHA384 3 +#define SHA_MODE_SHA512 4 +#define SHA_MODE_SHA512_224 5 +#define SHA_MODE_SHA512_256 6 +#define SHA_MODE_SHA512_T 7 /* SHA acceleration registers */ #define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00) - -#define SHA_MODE_SHA1 0 -#define SHA_MODE_SHA224 1 -#define SHA_MODE_SHA256 2 -#define SHA_MODE_SHA384 3 -#define SHA_MODE_SHA512 4 -#define SHA_MODE_SHA512_224 5 -#define SHA_MODE_SHA512_256 6 -#define SHA_MODE_SHA512_T 7 - #define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04) #define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08) -#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x0c) -#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x10) -#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x14) +#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C) +#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10) +#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14) +#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18) +#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C) +#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20) +#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24) +#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28) #define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40) -#define SHA_M_BASE ((DR_REG_SHA_BASE) + 0x80) +#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80) + +/* AES Block operation modes */ +#define AES_BLOCK_MODE_ECB 0 +#define AES_BLOCK_MODE_CBC 1 +#define AES_BLOCK_MODE_OFB 2 +#define AES_BLOCK_MODE_CTR 3 +#define AES_BLOCK_MODE_CFB8 4 +#define AES_BLOCK_MODE_CFB128 5 +#define AES_BLOCK_MODE_GCM 6 + +/* AES Block operation modes (used with DMA) */ +#define AES_BLOCK_MODE_ECB 0 +#define AES_BLOCK_MODE_CBC 1 +#define AES_BLOCK_MODE_OFB 2 +#define AES_BLOCK_MODE_CTR 3 +#define AES_BLOCK_MODE_CFB8 4 +#define AES_BLOCK_MODE_CFB128 5 +#define AES_BLOCK_MODE_GCM 6 /* AES acceleration registers */ #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40) #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44) #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48) #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c) +#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) +#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) +#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) +#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) +#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) +#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) +#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) +#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) +#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) +#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) + +#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) +#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) +#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) +#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) +#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) +#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) +#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) #define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00) #define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20) #define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) +#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) +#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60) +#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) +#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) + +#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) +#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) +#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) + +/* AES_STATE_REG values */ +#define AES_STATE_IDLE 0 +#define AES_STATE_BUSY 1 +#define AES_STATE_DONE 2 + + +/* Crypto DMA */ +#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) +#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) +#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08) +#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C) +#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10) +#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14) +#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18) +#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C) +#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20) +#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24) +#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28) +#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C) +#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30) +#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34) +#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38) +#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C) +#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40) +#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44) +#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48) +#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C) +#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50) +#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54) +#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58) +#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C) +#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60) +#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64) +#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC) /* HMAC Module */ #define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) @@ -88,20 +174,68 @@ #define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68) #define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c) - #define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80) #define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0) #define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0) +#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4) /* AES-XTS registers */ -#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x80) -#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0xC0) -#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0xC4) -#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0xC8) +#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x100) +#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0x140) +#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0x144) +#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0x148) -#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0xCC) -#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0xD0) -#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0xD4) -#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0xD8) +#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0x14C) +#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0x150) +#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0x154) +#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0x158) + +/* Digital Signature registers*/ +#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) +#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 ) +#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 ) +#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 ) + +#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00) +#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04) +#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08) + +#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C) +#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10) +#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14) + +#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0) +#define DS_QUERY_CHECK_INVALID_PADDING (1<<1) + +#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20) + +/* Crypto DMA */ +#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) +#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) +#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08) +#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C) +#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10) +#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14) +#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18) +#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C) +#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20) +#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24) +#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28) +#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C) +#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30) +#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34) +#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38) +#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C) +#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40) +#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44) +#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48) +#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C) +#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50) +#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54) +#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58) +#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C) +#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60) +#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64) +#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC) #endif diff --git a/components/soc/esp32s2beta/include/soc/i2c_reg.h b/components/soc/esp32s2beta/include/soc/i2c_reg.h index 66f04502a2..b9d56180ba 100644 --- a/components/soc/esp32s2beta/include/soc/i2c_reg.h +++ b/components/soc/esp32s2beta/include/soc/i2c_reg.h @@ -21,7 +21,7 @@ extern "C" { #include "soc.h" #define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the low level width of SCL clock.*/ +/*description: */ #define I2C_SCL_LOW_PERIOD 0x00003FFF #define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) #define I2C_SCL_LOW_PERIOD_V 0x3FFF @@ -47,34 +47,31 @@ extern "C" { #define I2C_ARBITRATION_EN_V 0x1 #define I2C_ARBITRATION_EN_S 9 /* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: This is the clock gating control bit for reading or writing registers.*/ +/*description: */ #define I2C_CLK_EN (BIT(8)) #define I2C_CLK_EN_M (BIT(8)) #define I2C_CLK_EN_V 0x1 #define I2C_CLK_EN_S 8 /* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: This bit is used to control the storage mode for received datas. - 1: receive data from most significant bit 0: receive data from least significant bit*/ +/*description: */ #define I2C_RX_LSB_FIRST (BIT(7)) #define I2C_RX_LSB_FIRST_M (BIT(7)) #define I2C_RX_LSB_FIRST_V 0x1 #define I2C_RX_LSB_FIRST_S 7 /* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This bit is used to control the sending mode for data need to - be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ +/*description: */ #define I2C_TX_LSB_FIRST (BIT(6)) #define I2C_TX_LSB_FIRST_M (BIT(6)) #define I2C_TX_LSB_FIRST_V 0x1 #define I2C_TX_LSB_FIRST_S 6 /* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to start sending data in txfifo.*/ +/*description: */ #define I2C_TRANS_START (BIT(5)) #define I2C_TRANS_START_M (BIT(5)) #define I2C_TRANS_START_V 0x1 #define I2C_TRANS_START_S 5 /* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to configure the module as i2c master clear this - bit to configure the module as i2c slave.*/ +/*description: */ #define I2C_MS_MODE (BIT(4)) #define I2C_MS_MODE_M (BIT(4)) #define I2C_MS_MODE_V 0x1 @@ -86,22 +83,19 @@ extern "C" { #define I2C_ACK_LEVEL_V 0x1 #define I2C_ACK_LEVEL_S 3 /* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to sample data in SCL low level. clear this bit - to sample data in SCL high level.*/ +/*description: */ #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_V 0x1 #define I2C_SAMPLE_SCL_LEVEL_S 2 /* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 1: normally ouput scl clock 0: exchange the function of scl_o - and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ +/*description: */ #define I2C_SCL_FORCE_OUT (BIT(1)) #define I2C_SCL_FORCE_OUT_M (BIT(1)) #define I2C_SCL_FORCE_OUT_V 0x1 #define I2C_SCL_FORCE_OUT_S 1 /* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: normally ouput sda data 0: exchange the function of sda_o - and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ +/*description: */ #define I2C_SDA_FORCE_OUT (BIT(0)) #define I2C_SDA_FORCE_OUT_M (BIT(0)) #define I2C_SDA_FORCE_OUT_V 0x1 @@ -109,71 +103,67 @@ extern "C" { #define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) /* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: This register stores the value of state machine to produce SCL. - 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ +/*description: */ #define I2C_SCL_STATE_LAST 0x00000007 #define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) #define I2C_SCL_STATE_LAST_V 0x7 #define I2C_SCL_STATE_LAST_S 28 /* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: This register stores the value of state machine for i2c module. - 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ +/*description: */ #define I2C_SCL_MAIN_STATE_LAST 0x00000007 #define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) #define I2C_SCL_MAIN_STATE_LAST_V 0x7 #define I2C_SCL_MAIN_STATE_LAST_S 24 /* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ -/*description: This register stores the amount of received data in ram.*/ +/*description: */ #define I2C_TXFIFO_CNT 0x0000003F #define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) #define I2C_TXFIFO_CNT_V 0x3F #define I2C_TXFIFO_CNT_S 18 /* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: This register represent the amount of data need to send.*/ +/*description: */ #define I2C_RXFIFO_CNT 0x0000003F #define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) #define I2C_RXFIFO_CNT_V 0x3F #define I2C_RXFIFO_CNT_S 8 /* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register changes to high level when one byte is transferred.*/ +/*description: */ #define I2C_BYTE_TRANS (BIT(6)) #define I2C_BYTE_TRANS_M (BIT(6)) #define I2C_BYTE_TRANS_V 0x1 #define I2C_BYTE_TRANS_S 6 /* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: when configured as i2c slave and the address send by master - is equal to slave's address then this bit will be high level.*/ +/*description: */ #define I2C_SLAVE_ADDRESSED (BIT(5)) #define I2C_SLAVE_ADDRESSED_M (BIT(5)) #define I2C_SLAVE_ADDRESSED_V 0x1 #define I2C_SLAVE_ADDRESSED_S 5 /* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ +/*description: */ #define I2C_BUS_BUSY (BIT(4)) #define I2C_BUS_BUSY_M (BIT(4)) #define I2C_BUS_BUSY_V 0x1 #define I2C_BUS_BUSY_S 4 /* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: when I2C lost control of SDA line this register changes to high level.*/ +/*description: */ #define I2C_ARB_LOST (BIT(3)) #define I2C_ARB_LOST_M (BIT(3)) #define I2C_ARB_LOST_V 0x1 #define I2C_ARB_LOST_S 3 /* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: when I2C takes more than time_out_reg clocks to receive a data - then this register changes to high level.*/ +/*description: */ #define I2C_TIME_OUT (BIT(2)) #define I2C_TIME_OUT_M (BIT(2)) #define I2C_TIME_OUT_V 0x1 #define I2C_TIME_OUT_S 2 /* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: when in slave mode 1: master read slave 0: master write slave.*/ +/*description: */ #define I2C_SLAVE_RW (BIT(1)) #define I2C_SLAVE_RW_M (BIT(1)) #define I2C_SLAVE_RW_V 0x1 #define I2C_SLAVE_RW_S 1 /* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register stores the value of ACK bit.*/ +/*description: */ #define I2C_ACK_REC (BIT(0)) #define I2C_ACK_REC_M (BIT(0)) #define I2C_ACK_REC_V 0x1 @@ -195,14 +185,13 @@ extern "C" { #define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) /* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This register is used to enable slave 10bit address mode.*/ +/*description: */ #define I2C_ADDR_10BIT_EN (BIT(31)) #define I2C_ADDR_10BIT_EN_M (BIT(31)) #define I2C_ADDR_10BIT_EN_V 0x1 #define I2C_ADDR_10BIT_EN_S 31 /* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: when configured as i2c slave this register is used to configure - slave's address.*/ +/*description: */ #define I2C_SLAVE_ADDR 0x00007FFF #define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) #define I2C_SLAVE_ADDR_V 0x7FFF @@ -234,29 +223,25 @@ extern "C" { #define I2C_RX_UPDATE_V 0x1 #define I2C_RX_UPDATE_S 20 /* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: This is the offset address of the last sending data as described - in nonfifo_tx_thres register.*/ +/*description: */ #define I2C_TXFIFO_END_ADDR 0x0000001F #define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) #define I2C_TXFIFO_END_ADDR_V 0x1F #define I2C_TXFIFO_END_ADDR_S 15 /* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: This is the offset address of the first sending data as described - in nonfifo_tx_thres register.*/ +/*description: */ #define I2C_TXFIFO_START_ADDR 0x0000001F #define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) #define I2C_TXFIFO_START_ADDR_V 0x1F #define I2C_TXFIFO_START_ADDR_S 10 /* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This is the offset address of the first receiving data as described - in nonfifo_rx_thres_register.*/ +/*description: */ #define I2C_RXFIFO_END_ADDR 0x0000001F #define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) #define I2C_RXFIFO_END_ADDR_V 0x1F #define I2C_RXFIFO_END_ADDR_S 5 /* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This is the offset address of the last receiving data as described - in nonfifo_rx_thres_register.*/ +/*description: */ #define I2C_RXFIFO_START_ADDR 0x0000001F #define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) #define I2C_RXFIFO_START_ADDR_V 0x1F @@ -264,46 +249,43 @@ extern "C" { #define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) /* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ -/*description: when I2C sends more than nonfifo_tx_thres data it will produce - tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ +/*description: */ #define I2C_NONFIFO_TX_THRES 0x0000003F #define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) #define I2C_NONFIFO_TX_THRES_V 0x3F #define I2C_NONFIFO_TX_THRES_S 20 /* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ -/*description: when I2C receives more than nonfifo_rx_thres data it will produce - rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ +/*description: */ #define I2C_NONFIFO_RX_THRES 0x0000003F #define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) #define I2C_NONFIFO_RX_THRES_V 0x3F #define I2C_NONFIFO_RX_THRES_S 14 /* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to reset tx fifo when using apb fifo access.*/ +/*description: */ #define I2C_TX_FIFO_RST (BIT(13)) #define I2C_TX_FIFO_RST_M (BIT(13)) #define I2C_TX_FIFO_RST_V 0x1 #define I2C_TX_FIFO_RST_S 13 /* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to reset rx fifo when using apb fifo access.*/ +/*description: */ #define I2C_RX_FIFO_RST (BIT(12)) #define I2C_RX_FIFO_RST_M (BIT(12)) #define I2C_RX_FIFO_RST_V 0x1 #define I2C_RX_FIFO_RST_S 12 /* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: When this bit is set to 1 then the byte after address represent - the offset address of I2C Slave's ram.*/ +/*description: */ #define I2C_FIFO_ADDR_CFG_EN (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_V 0x1 #define I2C_FIFO_ADDR_CFG_EN_S 11 /* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to enble apb nonfifo access.*/ +/*description: */ #define I2C_NONFIFO_EN (BIT(10)) #define I2C_NONFIFO_EN_M (BIT(10)) #define I2C_NONFIFO_EN_V 0x1 #define I2C_NONFIFO_EN_S 10 /* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ -/*description: Config txfifo empty threhd value when using apb fifo access*/ +/*description: */ #define I2C_TXFIFO_EMPTY_THRHD 0x0000001F #define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) #define I2C_TXFIFO_EMPTY_THRHD_V 0x1F @@ -319,7 +301,7 @@ extern "C" { #define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) /* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: The register represent the byte data read from rxfifo when use apb fifo access*/ +/*description: */ #define I2C_FIFO_RDATA 0x000000FF #define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) #define I2C_FIFO_RDATA_V 0xFF @@ -345,90 +327,79 @@ extern "C" { #define I2C_SCL_ST_TO_INT_RAW_V 0x1 #define I2C_SCL_ST_TO_INT_RAW_S 13 /* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when - I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ +/*description: */ #define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 #define I2C_TX_SEND_EMPTY_INT_RAW_S 12 /* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when - I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ +/*description: */ #define I2C_RX_REC_FULL_INT_RAW (BIT(11)) #define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) #define I2C_RX_REC_FULL_INT_RAW_V 0x1 #define I2C_RX_REC_FULL_INT_RAW_S 11 /* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for ack_err_int interrupt. when - I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ +/*description: */ #define I2C_ACK_ERR_INT_RAW (BIT(10)) #define I2C_ACK_ERR_INT_RAW_M (BIT(10)) #define I2C_ACK_ERR_INT_RAW_V 0x1 #define I2C_ACK_ERR_INT_RAW_S 10 /* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for trans_start_int interrupt. when - I2C sends the START bit it will produce trans_start_int interrupt.*/ +/*description: */ #define I2C_TRANS_START_INT_RAW (BIT(9)) #define I2C_TRANS_START_INT_RAW_M (BIT(9)) #define I2C_TRANS_START_INT_RAW_V 0x1 #define I2C_TRANS_START_INT_RAW_S 9 /* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for time_out_int interrupt. when - I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ +/*description: */ #define I2C_TIME_OUT_INT_RAW (BIT(8)) #define I2C_TIME_OUT_INT_RAW_M (BIT(8)) #define I2C_TIME_OUT_INT_RAW_V 0x1 #define I2C_TIME_OUT_INT_RAW_S 8 /* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for trans_complete_int interrupt. - when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ +/*description: */ #define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 #define I2C_TRANS_COMPLETE_INT_RAW_S 7 /* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for master_tra_comp_int interrupt. - when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ +/*description: */ #define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 #define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 /* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when - I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ +/*description: */ #define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 #define I2C_ARBITRATION_LOST_INT_RAW_S 5 /* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for slave_tran_comp_int interrupt. - when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ +/*description: */ #define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 #define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 /* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for end_detect_int interrupt. when - I2C deals with the END command it will produce end_detect_int interrupt.*/ +/*description: */ #define I2C_END_DETECT_INT_RAW (BIT(3)) #define I2C_END_DETECT_INT_RAW_M (BIT(3)) #define I2C_END_DETECT_INT_RAW_V 0x1 #define I2C_END_DETECT_INT_RAW_S 3 /* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for receiving data overflow when - use apb fifo access.*/ +/*description: */ #define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_RAW_V 0x1 #define I2C_RXFIFO_OVF_INT_RAW_S 2 /* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ +/*description: */ #define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 #define I2C_TXFIFO_EMPTY_INT_RAW_S 1 /* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ +/*description: */ #define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) #define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) #define I2C_RXFIFO_FULL_INT_RAW_V 0x1 @@ -454,79 +425,79 @@ extern "C" { #define I2C_SCL_ST_TO_INT_CLR_V 0x1 #define I2C_SCL_ST_TO_INT_CLR_S 13 /* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear the tx_send_empty_int interrupt.*/ +/*description: */ #define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 #define I2C_TX_SEND_EMPTY_INT_CLR_S 12 /* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rx_rec_full_int interrupt.*/ +/*description: */ #define I2C_RX_REC_FULL_INT_CLR (BIT(11)) #define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) #define I2C_RX_REC_FULL_INT_CLR_V 0x1 #define I2C_RX_REC_FULL_INT_CLR_S 11 /* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear the ack_err_int interrupt.*/ +/*description: */ #define I2C_ACK_ERR_INT_CLR (BIT(10)) #define I2C_ACK_ERR_INT_CLR_M (BIT(10)) #define I2C_ACK_ERR_INT_CLR_V 0x1 #define I2C_ACK_ERR_INT_CLR_S 10 /* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the trans_start_int interrupt.*/ +/*description: */ #define I2C_TRANS_START_INT_CLR (BIT(9)) #define I2C_TRANS_START_INT_CLR_M (BIT(9)) #define I2C_TRANS_START_INT_CLR_V 0x1 #define I2C_TRANS_START_INT_CLR_S 9 /* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the time_out_int interrupt.*/ +/*description: */ #define I2C_TIME_OUT_INT_CLR (BIT(8)) #define I2C_TIME_OUT_INT_CLR_M (BIT(8)) #define I2C_TIME_OUT_INT_CLR_V 0x1 #define I2C_TIME_OUT_INT_CLR_S 8 /* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the trans_complete_int interrupt.*/ +/*description: */ #define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 #define I2C_TRANS_COMPLETE_INT_CLR_S 7 /* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear the master_tran_comp interrupt.*/ +/*description: */ #define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 #define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 /* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the arbitration_lost_int interrupt.*/ +/*description: */ #define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 #define I2C_ARBITRATION_LOST_INT_CLR_S 5 /* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ +/*description: */ #define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 #define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 /* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the end_detect_int interrupt.*/ +/*description: */ #define I2C_END_DETECT_INT_CLR (BIT(3)) #define I2C_END_DETECT_INT_CLR_M (BIT(3)) #define I2C_END_DETECT_INT_CLR_V 0x1 #define I2C_END_DETECT_INT_CLR_S 3 /* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ +/*description: */ #define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_CLR_V 0x1 #define I2C_RXFIFO_OVF_INT_CLR_S 2 /* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear the txfifo_empty_int interrupt.*/ +/*description: */ #define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 #define I2C_TXFIFO_EMPTY_INT_CLR_S 1 /* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear the rxfifo_full_int interrupt.*/ +/*description: */ #define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) #define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) #define I2C_RXFIFO_FULL_INT_CLR_V 0x1 @@ -552,79 +523,79 @@ extern "C" { #define I2C_SCL_ST_TO_INT_ENA_V 0x1 #define I2C_SCL_ST_TO_INT_ENA_S 13 /* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The enable bit for tx_send_empty_int interrupt.*/ +/*description: */ #define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 #define I2C_TX_SEND_EMPTY_INT_ENA_S 12 /* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The enable bit for rx_rec_full_int interrupt.*/ +/*description: */ #define I2C_RX_REC_FULL_INT_ENA (BIT(11)) #define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) #define I2C_RX_REC_FULL_INT_ENA_V 0x1 #define I2C_RX_REC_FULL_INT_ENA_S 11 /* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The enable bit for ack_err_int interrupt.*/ +/*description: */ #define I2C_ACK_ERR_INT_ENA (BIT(10)) #define I2C_ACK_ERR_INT_ENA_M (BIT(10)) #define I2C_ACK_ERR_INT_ENA_V 0x1 #define I2C_ACK_ERR_INT_ENA_S 10 /* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The enable bit for trans_start_int interrupt.*/ +/*description: */ #define I2C_TRANS_START_INT_ENA (BIT(9)) #define I2C_TRANS_START_INT_ENA_M (BIT(9)) #define I2C_TRANS_START_INT_ENA_V 0x1 #define I2C_TRANS_START_INT_ENA_S 9 /* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for time_out_int interrupt.*/ +/*description: */ #define I2C_TIME_OUT_INT_ENA (BIT(8)) #define I2C_TIME_OUT_INT_ENA_M (BIT(8)) #define I2C_TIME_OUT_INT_ENA_V 0x1 #define I2C_TIME_OUT_INT_ENA_S 8 /* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for trans_complete_int interrupt.*/ +/*description: */ #define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 #define I2C_TRANS_COMPLETE_INT_ENA_S 7 /* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for master_tran_comp_int interrupt.*/ +/*description: */ #define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 #define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 /* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for arbitration_lost_int interrupt.*/ +/*description: */ #define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 #define I2C_ARBITRATION_LOST_INT_ENA_S 5 /* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for slave_tran_comp_int interrupt.*/ +/*description: */ #define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 #define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 /* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for end_detect_int interrupt.*/ +/*description: */ #define I2C_END_DETECT_INT_ENA (BIT(3)) #define I2C_END_DETECT_INT_ENA_M (BIT(3)) #define I2C_END_DETECT_INT_ENA_V 0x1 #define I2C_END_DETECT_INT_ENA_S 3 /* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for rxfifo_ovf_int interrupt.*/ +/*description: */ #define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_ENA_V 0x1 #define I2C_RXFIFO_OVF_INT_ENA_S 2 /* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for txfifo_empty_int interrupt.*/ +/*description: */ #define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 #define I2C_TXFIFO_EMPTY_INT_ENA_S 1 /* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for rxfifo_full_int interrupt.*/ +/*description: */ #define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) #define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) #define I2C_RXFIFO_FULL_INT_ENA_V 0x1 @@ -650,79 +621,79 @@ extern "C" { #define I2C_SCL_ST_TO_INT_ST_V 0x1 #define I2C_SCL_ST_TO_INT_ST_S 13 /* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The masked interrupt status for tx_send_empty_int interrupt.*/ +/*description: */ #define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) #define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 #define I2C_TX_SEND_EMPTY_INT_ST_S 12 /* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rx_rec_full_int interrupt.*/ +/*description: */ #define I2C_RX_REC_FULL_INT_ST (BIT(11)) #define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) #define I2C_RX_REC_FULL_INT_ST_V 0x1 #define I2C_RX_REC_FULL_INT_ST_S 11 /* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The masked interrupt status for ack_err_int interrupt.*/ +/*description: */ #define I2C_ACK_ERR_INT_ST (BIT(10)) #define I2C_ACK_ERR_INT_ST_M (BIT(10)) #define I2C_ACK_ERR_INT_ST_V 0x1 #define I2C_ACK_ERR_INT_ST_S 10 /* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The masked interrupt status for trans_start_int interrupt.*/ +/*description: */ #define I2C_TRANS_START_INT_ST (BIT(9)) #define I2C_TRANS_START_INT_ST_M (BIT(9)) #define I2C_TRANS_START_INT_ST_V 0x1 #define I2C_TRANS_START_INT_ST_S 9 /* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The masked interrupt status for time_out_int interrupt.*/ +/*description: */ #define I2C_TIME_OUT_INT_ST (BIT(8)) #define I2C_TIME_OUT_INT_ST_M (BIT(8)) #define I2C_TIME_OUT_INT_ST_V 0x1 #define I2C_TIME_OUT_INT_ST_S 8 /* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The masked interrupt status for trans_complete_int interrupt.*/ +/*description: */ #define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) #define I2C_TRANS_COMPLETE_INT_ST_V 0x1 #define I2C_TRANS_COMPLETE_INT_ST_S 7 /* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The masked interrupt status for master_tran_comp_int interrupt.*/ +/*description: */ #define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) #define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 #define I2C_MASTER_TRAN_COMP_INT_ST_S 6 /* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The masked interrupt status for arbitration_lost_int interrupt.*/ +/*description: */ #define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) #define I2C_ARBITRATION_LOST_INT_ST_V 0x1 #define I2C_ARBITRATION_LOST_INT_ST_S 5 /* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ +/*description: */ #define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) #define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 #define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 /* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status for end_detect_int interrupt.*/ +/*description: */ #define I2C_END_DETECT_INT_ST (BIT(3)) #define I2C_END_DETECT_INT_ST_M (BIT(3)) #define I2C_END_DETECT_INT_ST_V 0x1 #define I2C_END_DETECT_INT_ST_S 3 /* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ +/*description: */ #define I2C_RXFIFO_OVF_INT_ST (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) #define I2C_RXFIFO_OVF_INT_ST_V 0x1 #define I2C_RXFIFO_OVF_INT_ST_S 2 /* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status for txfifo_empty_int interrupt.*/ +/*description: */ #define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) #define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 #define I2C_TXFIFO_EMPTY_INT_ST_S 1 /* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status for rxfifo_full_int interrupt.*/ +/*description: */ #define I2C_RXFIFO_FULL_INT_ST (BIT(0)) #define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) #define I2C_RXFIFO_FULL_INT_ST_V 0x1 @@ -730,8 +701,7 @@ extern "C" { #define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) /* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num I2C used to - hold the data after the negedge of SCL.*/ +/*description: */ #define I2C_SDA_HOLD_TIME 0x000003FF #define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) #define I2C_SDA_HOLD_TIME_V 0x3FF @@ -739,8 +709,7 @@ extern "C" { #define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) /* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num I2C used to - sample data on SDA after the posedge of SCL*/ +/*description: */ #define I2C_SDA_SAMPLE_TIME 0x000003FF #define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) #define I2C_SDA_SAMPLE_TIME_V 0x3FF @@ -754,7 +723,7 @@ extern "C" { #define I2C_SCL_WAIT_HIGH_PERIOD_V 0x3FFF #define I2C_SCL_WAIT_HIGH_PERIOD_S 14 /* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the clock num during SCL is low level.*/ +/*description: */ #define I2C_SCL_HIGH_PERIOD 0x00003FFF #define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) #define I2C_SCL_HIGH_PERIOD_V 0x3FFF @@ -762,8 +731,7 @@ extern "C" { #define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) /* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ -/*description: This register is used to configure the clock num between the - negedge of SDA and negedge of SCL for start mark.*/ +/*description: */ #define I2C_SCL_START_HOLD_TIME 0x000003FF #define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) #define I2C_SCL_START_HOLD_TIME_V 0x3FF @@ -771,8 +739,7 @@ extern "C" { #define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) /* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ -/*description: This register is used to configure the clock num between the - posedge of SCL and the negedge of SDA for restart mark.*/ +/*description: */ #define I2C_SCL_RSTART_SETUP_TIME 0x000003FF #define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) #define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF @@ -780,7 +747,7 @@ extern "C" { #define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) /* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This register is used to configure the clock num after the STOP bit's posedge.*/ +/*description: */ #define I2C_SCL_STOP_HOLD_TIME 0x00003FFF #define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) #define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF @@ -788,8 +755,7 @@ extern "C" { #define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) /* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register is used to configure the clock num between the - posedge of SCL and the posedge of SDA.*/ +/*description: */ #define I2C_SCL_STOP_SETUP_TIME 0x000003FF #define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) #define I2C_SCL_STOP_SETUP_TIME_V 0x3FF @@ -797,14 +763,13 @@ extern "C" { #define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) /* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SCL.*/ +/*description: */ #define I2C_SCL_FILTER_EN (BIT(3)) #define I2C_SCL_FILTER_EN_M (BIT(3)) #define I2C_SCL_FILTER_EN_V 0x1 #define I2C_SCL_FILTER_EN_S 3 /* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: When input SCL's pulse width is smaller than this register value - I2C ignores this pulse.*/ +/*description: */ #define I2C_SCL_FILTER_THRES 0x00000007 #define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) #define I2C_SCL_FILTER_THRES_V 0x7 @@ -812,14 +777,13 @@ extern "C" { #define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) /* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SDA.*/ +/*description: */ #define I2C_SDA_FILTER_EN (BIT(3)) #define I2C_SDA_FILTER_EN_M (BIT(3)) #define I2C_SDA_FILTER_EN_V 0x1 #define I2C_SDA_FILTER_EN_S 3 /* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: When input SCL's pulse width is smaller than this register value - I2C ignores this pulse.*/ +/*description: */ #define I2C_SDA_FILTER_THRES 0x00000007 #define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) #define I2C_SDA_FILTER_THRES_V 0x7 @@ -827,14 +791,13 @@ extern "C" { #define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) /* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command0 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND0_DONE (BIT(31)) #define I2C_COMMAND0_DONE_M (BIT(31)) #define I2C_COMMAND0_DONE_V 0x1 #define I2C_COMMAND0_DONE_S 31 /* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command0. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND0 0x00003FFF #define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) #define I2C_COMMAND0_V 0x3FFF @@ -842,14 +805,13 @@ extern "C" { #define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) /* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command1 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND1_DONE (BIT(31)) #define I2C_COMMAND1_DONE_M (BIT(31)) #define I2C_COMMAND1_DONE_V 0x1 #define I2C_COMMAND1_DONE_S 31 /* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command1. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND1 0x00003FFF #define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) #define I2C_COMMAND1_V 0x3FFF @@ -857,14 +819,13 @@ extern "C" { #define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) /* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command2 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND2_DONE (BIT(31)) #define I2C_COMMAND2_DONE_M (BIT(31)) #define I2C_COMMAND2_DONE_V 0x1 #define I2C_COMMAND2_DONE_S 31 /* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command2. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND2 0x00003FFF #define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) #define I2C_COMMAND2_V 0x3FFF @@ -872,14 +833,13 @@ extern "C" { #define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) /* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command3 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND3_DONE (BIT(31)) #define I2C_COMMAND3_DONE_M (BIT(31)) #define I2C_COMMAND3_DONE_V 0x1 #define I2C_COMMAND3_DONE_S 31 /* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command3. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND3 0x00003FFF #define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) #define I2C_COMMAND3_V 0x3FFF @@ -887,14 +847,13 @@ extern "C" { #define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) /* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command4 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND4_DONE (BIT(31)) #define I2C_COMMAND4_DONE_M (BIT(31)) #define I2C_COMMAND4_DONE_V 0x1 #define I2C_COMMAND4_DONE_S 31 /* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command4. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND4 0x00003FFF #define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) #define I2C_COMMAND4_V 0x3FFF @@ -902,14 +861,13 @@ extern "C" { #define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) /* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command5 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND5_DONE (BIT(31)) #define I2C_COMMAND5_DONE_M (BIT(31)) #define I2C_COMMAND5_DONE_V 0x1 #define I2C_COMMAND5_DONE_S 31 /* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command5. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND5 0x00003FFF #define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) #define I2C_COMMAND5_V 0x3FFF @@ -917,14 +875,13 @@ extern "C" { #define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) /* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command6 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND6_DONE (BIT(31)) #define I2C_COMMAND6_DONE_M (BIT(31)) #define I2C_COMMAND6_DONE_V 0x1 #define I2C_COMMAND6_DONE_S 31 /* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command6. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND6 0x00003FFF #define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) #define I2C_COMMAND6_V 0x3FFF @@ -932,14 +889,13 @@ extern "C" { #define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) /* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command7 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND7_DONE (BIT(31)) #define I2C_COMMAND7_DONE_M (BIT(31)) #define I2C_COMMAND7_DONE_V 0x1 #define I2C_COMMAND7_DONE_S 31 /* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command7. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND7 0x00003FFF #define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) #define I2C_COMMAND7_V 0x3FFF @@ -947,14 +903,13 @@ extern "C" { #define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) /* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command8 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND8_DONE (BIT(31)) #define I2C_COMMAND8_DONE_M (BIT(31)) #define I2C_COMMAND8_DONE_V 0x1 #define I2C_COMMAND8_DONE_S 31 /* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command8. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND8 0x00003FFF #define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) #define I2C_COMMAND8_V 0x3FFF @@ -962,14 +917,13 @@ extern "C" { #define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) /* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command9 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND9_DONE (BIT(31)) #define I2C_COMMAND9_DONE_M (BIT(31)) #define I2C_COMMAND9_DONE_V 0x1 #define I2C_COMMAND9_DONE_S 31 /* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command9. It consists of three part. op_code - is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND9 0x00003FFF #define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) #define I2C_COMMAND9_V 0x3FFF @@ -977,14 +931,13 @@ extern "C" { #define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) /* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command10 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND10_DONE (BIT(31)) #define I2C_COMMAND10_DONE_M (BIT(31)) #define I2C_COMMAND10_DONE_V 0x1 #define I2C_COMMAND10_DONE_S 31 /* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command10. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND10 0x00003FFF #define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) #define I2C_COMMAND10_V 0x3FFF @@ -992,14 +945,13 @@ extern "C" { #define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) /* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command11 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND11_DONE (BIT(31)) #define I2C_COMMAND11_DONE_M (BIT(31)) #define I2C_COMMAND11_DONE_V 0x1 #define I2C_COMMAND11_DONE_S 31 /* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command11. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND11 0x00003FFF #define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) #define I2C_COMMAND11_V 0x3FFF @@ -1007,14 +959,13 @@ extern "C" { #define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) /* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command12 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND12_DONE (BIT(31)) #define I2C_COMMAND12_DONE_M (BIT(31)) #define I2C_COMMAND12_DONE_V 0x1 #define I2C_COMMAND12_DONE_S 31 /* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command12. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND12 0x00003FFF #define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) #define I2C_COMMAND12_V 0x3FFF @@ -1022,14 +973,13 @@ extern "C" { #define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) /* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command13 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND13_DONE (BIT(31)) #define I2C_COMMAND13_DONE_M (BIT(31)) #define I2C_COMMAND13_DONE_V 0x1 #define I2C_COMMAND13_DONE_S 31 /* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command13. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND13 0x00003FFF #define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) #define I2C_COMMAND13_V 0x3FFF @@ -1037,14 +987,13 @@ extern "C" { #define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) /* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command14 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND14_DONE (BIT(31)) #define I2C_COMMAND14_DONE_M (BIT(31)) #define I2C_COMMAND14_DONE_V 0x1 #define I2C_COMMAND14_DONE_S 31 /* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command14. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND14 0x00003FFF #define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) #define I2C_COMMAND14_V 0x3FFF @@ -1052,14 +1001,13 @@ extern "C" { #define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) /* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command15 is done in I2C Master mode this bit changes to high level.*/ +/*description: */ #define I2C_COMMAND15_DONE (BIT(31)) #define I2C_COMMAND15_DONE_M (BIT(31)) #define I2C_COMMAND15_DONE_V 0x1 #define I2C_COMMAND15_DONE_S 31 /* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command15. It consists of three part. - op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ +/*description: */ #define I2C_COMMAND15 0x00003FFF #define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) #define I2C_COMMAND15_V 0x3FFF diff --git a/components/soc/esp32s2beta/include/soc/i2s_reg.h b/components/soc/esp32s2beta/include/soc/i2s_reg.h index aa64b2ba1a..62283f2b29 100644 --- a/components/soc/esp32s2beta/include/soc/i2s_reg.h +++ b/components/soc/esp32s2beta/include/soc/i2s_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -203,6 +203,12 @@ extern "C" { #define I2S_TX_RESET_S 0 #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) +/* I2S_V_SYNC_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_v_sync_int interrupt*/ +#define I2S_V_SYNC_INT_RAW (BIT(17)) +#define I2S_V_SYNC_INT_RAW_M (BIT(17)) +#define I2S_V_SYNC_INT_RAW_V 0x1 +#define I2S_V_SYNC_INT_RAW_S 17 /* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ /*description: The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/ #define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) @@ -307,6 +313,12 @@ extern "C" { #define I2S_RX_TAKE_DATA_INT_RAW_S 0 #define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) +/* I2S_V_SYNC_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_v_sync_int interrupt*/ +#define I2S_V_SYNC_INT_ST (BIT(17)) +#define I2S_V_SYNC_INT_ST_M (BIT(17)) +#define I2S_V_SYNC_INT_ST_V 0x1 +#define I2S_V_SYNC_INT_ST_S 17 /* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ /*description: The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/ #define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) @@ -411,6 +423,12 @@ extern "C" { #define I2S_RX_TAKE_DATA_INT_ST_S 0 #define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) +/* I2S_V_SYNC_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_v_sync_int interrupt*/ +#define I2S_V_SYNC_INT_ENA (BIT(17)) +#define I2S_V_SYNC_INT_ENA_M (BIT(17)) +#define I2S_V_SYNC_INT_ENA_V 0x1 +#define I2S_V_SYNC_INT_ENA_S 17 /* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ /*description: The interrupt enable bit for the i2s_out_total_eof_int interrupt*/ #define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) @@ -515,6 +533,12 @@ extern "C" { #define I2S_RX_TAKE_DATA_INT_ENA_S 0 #define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) +/* I2S_V_SYNC_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_v_sync_int interrupt*/ +#define I2S_V_SYNC_INT_CLR (BIT(17)) +#define I2S_V_SYNC_INT_CLR_M (BIT(17)) +#define I2S_V_SYNC_INT_CLR_V 0x1 +#define I2S_V_SYNC_INT_CLR_S 17 /* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ /*description: Set this bit to clear the i2s_out_total_eof_int interrupt*/ #define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) @@ -952,6 +976,13 @@ extern "C" { #define I2S_OUTLINK_DSCR_BF1_S 0 #define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) +/* I2S_EXT_MEM_BK_SIZE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: DMA access external memory block size. 0: 16 bytes 1: 32 + bytes 2:64 bytes 3:reserved*/ +#define I2S_EXT_MEM_BK_SIZE 0x00000003 +#define I2S_EXT_MEM_BK_SIZE_M ((I2S_EXT_MEM_BK_SIZE_V)<<(I2S_EXT_MEM_BK_SIZE_S)) +#define I2S_EXT_MEM_BK_SIZE_V 0x3 +#define I2S_EXT_MEM_BK_SIZE_S 14 /* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ /*description: don't use*/ #define I2S_MEM_TRANS_EN (BIT(13)) @@ -1168,226 +1199,6 @@ extern "C" { #define I2S_LC_FIFO_TIMEOUT_V 0xFF #define I2S_LC_FIFO_TIMEOUT_S 0 -#define I2S_CVSD_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0080) -/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */ -/*description: don't use*/ -#define I2S_CVSD_Y_MIN 0x0000FFFF -#define I2S_CVSD_Y_MIN_M ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S)) -#define I2S_CVSD_Y_MIN_V 0xFFFF -#define I2S_CVSD_Y_MIN_S 16 -/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */ -/*description: don't use*/ -#define I2S_CVSD_Y_MAX 0x0000FFFF -#define I2S_CVSD_Y_MAX_M ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S)) -#define I2S_CVSD_Y_MAX_V 0xFFFF -#define I2S_CVSD_Y_MAX_S 0 - -#define I2S_CVSD_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0084) -/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ -/*description: don't use*/ -#define I2S_CVSD_SIGMA_MIN 0x0000FFFF -#define I2S_CVSD_SIGMA_MIN_M ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S)) -#define I2S_CVSD_SIGMA_MIN_V 0xFFFF -#define I2S_CVSD_SIGMA_MIN_S 16 -/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */ -/*description: don't use*/ -#define I2S_CVSD_SIGMA_MAX 0x0000FFFF -#define I2S_CVSD_SIGMA_MAX_M ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S)) -#define I2S_CVSD_SIGMA_MAX_V 0xFFFF -#define I2S_CVSD_SIGMA_MAX_S 0 - -#define I2S_CVSD_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0088) -/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */ -/*description: don't use*/ -#define I2S_CVSD_H 0x00000007 -#define I2S_CVSD_H_M ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S)) -#define I2S_CVSD_H_V 0x7 -#define I2S_CVSD_H_S 16 -/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */ -/*description: don't use*/ -#define I2S_CVSD_BETA 0x000003FF -#define I2S_CVSD_BETA_M ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S)) -#define I2S_CVSD_BETA_V 0x3FF -#define I2S_CVSD_BETA_S 6 -/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */ -/*description: don't use*/ -#define I2S_CVSD_J 0x00000007 -#define I2S_CVSD_J_M ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S)) -#define I2S_CVSD_J_V 0x7 -#define I2S_CVSD_J_S 3 -/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */ -/*description: don't use*/ -#define I2S_CVSD_K 0x00000007 -#define I2S_CVSD_K_M ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S)) -#define I2S_CVSD_K_V 0x7 -#define I2S_CVSD_K_S 0 - -#define I2S_PLC_CONF0_REG(i) (REG_I2S_BASE(i) + 0x008C) -/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ -/*description: don't use*/ -#define I2S_N_MIN_ERR 0x00000007 -#define I2S_N_MIN_ERR_M ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S)) -#define I2S_N_MIN_ERR_V 0x7 -#define I2S_N_MIN_ERR_S 25 -/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */ -/*description: don't use*/ -#define I2S_PACK_LEN_8K 0x0000001F -#define I2S_PACK_LEN_8K_M ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S)) -#define I2S_PACK_LEN_8K_V 0x1F -#define I2S_PACK_LEN_8K_S 20 -/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */ -/*description: don't use*/ -#define I2S_MAX_SLIDE_SAMPLE 0x000000FF -#define I2S_MAX_SLIDE_SAMPLE_M ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S)) -#define I2S_MAX_SLIDE_SAMPLE_V 0xFF -#define I2S_MAX_SLIDE_SAMPLE_S 12 -/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */ -/*description: don't use*/ -#define I2S_SHIFT_RATE 0x00000007 -#define I2S_SHIFT_RATE_M ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S)) -#define I2S_SHIFT_RATE_V 0x7 -#define I2S_SHIFT_RATE_S 9 -/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */ -/*description: don't use*/ -#define I2S_N_ERR_SEG 0x00000007 -#define I2S_N_ERR_SEG_M ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S)) -#define I2S_N_ERR_SEG_V 0x7 -#define I2S_N_ERR_SEG_S 6 -/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */ -/*description: don't use*/ -#define I2S_GOOD_PACK_MAX 0x0000003F -#define I2S_GOOD_PACK_MAX_M ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S)) -#define I2S_GOOD_PACK_MAX_V 0x3F -#define I2S_GOOD_PACK_MAX_S 0 - -#define I2S_PLC_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0090) -/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */ -/*description: don't use*/ -#define I2S_SLIDE_WIN_LEN 0x000000FF -#define I2S_SLIDE_WIN_LEN_M ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S)) -#define I2S_SLIDE_WIN_LEN_V 0xFF -#define I2S_SLIDE_WIN_LEN_S 24 -/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */ -/*description: don't use*/ -#define I2S_BAD_OLA_WIN2_PARA 0x000000FF -#define I2S_BAD_OLA_WIN2_PARA_M ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S)) -#define I2S_BAD_OLA_WIN2_PARA_V 0xFF -#define I2S_BAD_OLA_WIN2_PARA_S 16 -/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */ -/*description: don't use*/ -#define I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F -#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S)) -#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V 0xF -#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12 -/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */ -/*description: don't use*/ -#define I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F -#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S)) -#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V 0xF -#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8 -/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */ -/*description: don't use*/ -#define I2S_BAD_CEF_ATTEN_PARA 0x000000FF -#define I2S_BAD_CEF_ATTEN_PARA_M ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S)) -#define I2S_BAD_CEF_ATTEN_PARA_V 0xFF -#define I2S_BAD_CEF_ATTEN_PARA_S 0 - -#define I2S_PLC_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0094) -/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */ -/*description: don't use*/ -#define I2S_MIN_PERIOD 0x0000001F -#define I2S_MIN_PERIOD_M ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S)) -#define I2S_MIN_PERIOD_V 0x1F -#define I2S_MIN_PERIOD_S 2 -/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: don't use*/ -#define I2S_CVSD_SEG_MOD 0x00000003 -#define I2S_CVSD_SEG_MOD_M ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S)) -#define I2S_CVSD_SEG_MOD_V 0x3 -#define I2S_CVSD_SEG_MOD_S 0 - -#define I2S_ESCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0098) -/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: don't use*/ -#define I2S_PLC2DMA_EN (BIT(12)) -#define I2S_PLC2DMA_EN_M (BIT(12)) -#define I2S_PLC2DMA_EN_V 0x1 -#define I2S_PLC2DMA_EN_S 12 -/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: don't use*/ -#define I2S_PLC_EN (BIT(11)) -#define I2S_PLC_EN_M (BIT(11)) -#define I2S_PLC_EN_V 0x1 -#define I2S_PLC_EN_S 11 -/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: don't use*/ -#define I2S_CVSD_DEC_RESET (BIT(10)) -#define I2S_CVSD_DEC_RESET_M (BIT(10)) -#define I2S_CVSD_DEC_RESET_V 0x1 -#define I2S_CVSD_DEC_RESET_S 10 -/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: don't use*/ -#define I2S_CVSD_DEC_START (BIT(9)) -#define I2S_CVSD_DEC_START_M (BIT(9)) -#define I2S_CVSD_DEC_START_V 0x1 -#define I2S_CVSD_DEC_START_S 9 -/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: don't use*/ -#define I2S_ESCO_CVSD_INF_EN (BIT(8)) -#define I2S_ESCO_CVSD_INF_EN_M (BIT(8)) -#define I2S_ESCO_CVSD_INF_EN_V 0x1 -#define I2S_ESCO_CVSD_INF_EN_S 8 -/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */ -/*description: don't use*/ -#define I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F -#define I2S_ESCO_CVSD_PACK_LEN_8K_M ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S)) -#define I2S_ESCO_CVSD_PACK_LEN_8K_V 0x1F -#define I2S_ESCO_CVSD_PACK_LEN_8K_S 3 -/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: don't use*/ -#define I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2)) -#define I2S_ESCO_CVSD_DEC_PACK_ERR_M (BIT(2)) -#define I2S_ESCO_CVSD_DEC_PACK_ERR_V 0x1 -#define I2S_ESCO_CVSD_DEC_PACK_ERR_S 2 -/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: don't use*/ -#define I2S_ESCO_CHAN_MOD (BIT(1)) -#define I2S_ESCO_CHAN_MOD_M (BIT(1)) -#define I2S_ESCO_CHAN_MOD_V 0x1 -#define I2S_ESCO_CHAN_MOD_S 1 -/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: don't use*/ -#define I2S_ESCO_EN (BIT(0)) -#define I2S_ESCO_EN_M (BIT(0)) -#define I2S_ESCO_EN_V 0x1 -#define I2S_ESCO_EN_S 0 - -#define I2S_SCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x009c) -/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */ -/*description: don't use*/ -#define I2S_CVSD_ENC_RESET (BIT(3)) -#define I2S_CVSD_ENC_RESET_M (BIT(3)) -#define I2S_CVSD_ENC_RESET_V 0x1 -#define I2S_CVSD_ENC_RESET_S 3 -/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */ -/*description: don't use*/ -#define I2S_CVSD_ENC_START (BIT(2)) -#define I2S_CVSD_ENC_START_M (BIT(2)) -#define I2S_CVSD_ENC_START_V 0x1 -#define I2S_CVSD_ENC_START_S 2 -/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: don't use*/ -#define I2S_SCO_NO_I2S_EN (BIT(1)) -#define I2S_SCO_NO_I2S_EN_M (BIT(1)) -#define I2S_SCO_NO_I2S_EN_V 0x1 -#define I2S_SCO_NO_I2S_EN_S 1 -/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: don't use*/ -#define I2S_SCO_WITH_I2S_EN (BIT(0)) -#define I2S_SCO_WITH_I2S_EN_M (BIT(0)) -#define I2S_SCO_WITH_I2S_EN_V 0x1 -#define I2S_SCO_WITH_I2S_EN_S 0 - #define I2S_CONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0) /* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ /*description: don't use*/ @@ -1430,6 +1241,24 @@ extern "C" { #define I2S_TX_PCM_CONF_S 0 #define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4) +/* I2S_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define I2S_DMA_RAM_CLK_FO (BIT(6)) +#define I2S_DMA_RAM_CLK_FO_M (BIT(6)) +#define I2S_DMA_RAM_CLK_FO_V 0x1 +#define I2S_DMA_RAM_CLK_FO_S 6 +/* I2S_DMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'h1 ; */ +/*description: */ +#define I2S_DMA_RAM_FORCE_PU (BIT(5)) +#define I2S_DMA_RAM_FORCE_PU_M (BIT(5)) +#define I2S_DMA_RAM_FORCE_PU_V 0x1 +#define I2S_DMA_RAM_FORCE_PU_S 5 +/* I2S_DMA_RAM_FORCE_PD : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define I2S_DMA_RAM_FORCE_PD (BIT(4)) +#define I2S_DMA_RAM_FORCE_PD_M (BIT(4)) +#define I2S_DMA_RAM_FORCE_PD_V 0x1 +#define I2S_DMA_RAM_FORCE_PD_S 4 /* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */ /*description: */ #define I2S_PLC_MEM_FORCE_PU (BIT(3)) @@ -1590,127 +1419,16 @@ extern "C" { #define I2S_TX_BCK_DIV_NUM_V 0x3F #define I2S_TX_BCK_DIV_NUM_S 0 -#define I2S_PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b4) -/* I2S_RX_PDM_WAY_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ -/*description: 0/1 pdm rx use one-way*/ -#define I2S_RX_PDM_WAY_MODE 0x00000003 -#define I2S_RX_PDM_WAY_MODE_M ((I2S_RX_PDM_WAY_MODE_V)<<(I2S_RX_PDM_WAY_MODE_S)) -#define I2S_RX_PDM_WAY_MODE_V 0x3 -#define I2S_RX_PDM_WAY_MODE_S 30 -/* I2S_TX_PDM_WAY_MODE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ -/*description: 0/1 pdm rx use one-way*/ -#define I2S_TX_PDM_WAY_MODE 0x00000003 -#define I2S_TX_PDM_WAY_MODE_M ((I2S_TX_PDM_WAY_MODE_V)<<(I2S_TX_PDM_WAY_MODE_S)) -#define I2S_TX_PDM_WAY_MODE_V 0x3 -#define I2S_TX_PDM_WAY_MODE_S 28 -/* I2S_TX_PDM_CHAN_MOD : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ -/*description: pdm tx channel mode*/ -#define I2S_TX_PDM_CHAN_MOD 0x00000003 -#define I2S_TX_PDM_CHAN_MOD_M ((I2S_TX_PDM_CHAN_MOD_V)<<(I2S_TX_PDM_CHAN_MOD_S)) -#define I2S_TX_PDM_CHAN_MOD_V 0x3 -#define I2S_TX_PDM_CHAN_MOD_S 26 -/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */ -/*description: Set this bit to enable tx pdm hp filter bypass*/ -#define I2S_TX_PDM_HP_BYPASS (BIT(25)) -#define I2S_TX_PDM_HP_BYPASS_M (BIT(25)) -#define I2S_TX_PDM_HP_BYPASS_V 0x1 -#define I2S_TX_PDM_HP_BYPASS_S 25 -/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */ -/*description: PDM down-sampling rate for filter group1 in receiver mode. 0: - downsample rate = 64 1:downsample rate = 128*/ -#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24)) -#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(24)) -#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 -#define I2S_RX_PDM_SINC_DSR_16_EN_S 24 -/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */ -/*description: Adjust size of input signal to filter module. 0: divided by 2 - 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/ -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22 -/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */ -/*description: Adjust size of input signal to filter module. 0: divided by 2 - 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/ -#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) -#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_SINC_IN_SHIFT_S 20 -/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */ -/*description: Adjust size of input signal to filter module. 0: divided by 2 - 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/ -#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) -#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_LP_IN_SHIFT_S 18 -/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */ -/*description: Adjust size of input signal to filter module. 0: divided by 2 - 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/ -#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 -#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) -#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 -#define I2S_TX_PDM_HP_IN_SHIFT_S 16 -/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: set to 0*/ -#define I2S_TX_PDM_PRESCALE 0x000000FF -#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) -#define I2S_TX_PDM_PRESCALE_V 0xFF -#define I2S_TX_PDM_PRESCALE_S 8 -/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */ -/*description: upsample rate = 64 * reg_tx_pdm_sinc_osr2*/ -#define I2S_TX_PDM_SINC_OSR2 0x0000000F -#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) -#define I2S_TX_PDM_SINC_OSR2_V 0xF -#define I2S_TX_PDM_SINC_OSR2_S 4 -/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: Set this bit to enable PDM-to-PCM converter*/ -#define I2S_PDM2PCM_CONV_EN (BIT(3)) -#define I2S_PDM2PCM_CONV_EN_M (BIT(3)) -#define I2S_PDM2PCM_CONV_EN_V 0x1 -#define I2S_PDM2PCM_CONV_EN_S 3 -/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: Set this bit to enable PCM-to-PDM converter*/ -#define I2S_PCM2PDM_CONV_EN (BIT(2)) -#define I2S_PCM2PDM_CONV_EN_M (BIT(2)) -#define I2S_PCM2PDM_CONV_EN_V 0x1 -#define I2S_PCM2PDM_CONV_EN_S 2 -/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to enable receiver PDM mode*/ -#define I2S_RX_PDM_EN (BIT(1)) -#define I2S_RX_PDM_EN_M (BIT(1)) -#define I2S_RX_PDM_EN_V 0x1 -#define I2S_RX_PDM_EN_S 1 -/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to enable transmitter PDM mode*/ -#define I2S_TX_PDM_EN (BIT(0)) -#define I2S_TX_PDM_EN_M (BIT(0)) -#define I2S_TX_PDM_EN_V 0x1 -#define I2S_TX_PDM_EN_S 0 - -#define I2S_PDM_FREQ_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b8) -/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */ -/*description: PCM-to-PDM converter PDM frequency parameter*/ -#define I2S_TX_PDM_FP 0x000003FF -#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) -#define I2S_TX_PDM_FP_V 0x3FF -#define I2S_TX_PDM_FP_S 10 -/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */ -/*description: PCM-to-PDM converter PCM frequency parameter*/ -#define I2S_TX_PDM_FS 0x000003FF -#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) -#define I2S_TX_PDM_FS_V 0x3FF -#define I2S_TX_PDM_FS_S 0 - #define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc) /* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: i2s_tx is idle state*/ +/*description: */ #define I2S_TX_IDLE (BIT(0)) #define I2S_TX_IDLE_M (BIT(0)) #define I2S_TX_IDLE_V 0x1 #define I2S_TX_IDLE_S 0 #define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc) -/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h18092900 ; */ +/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h19052500 ; */ /*description: */ #define I2S_I2SDATE 0xFFFFFFFF #define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/i2s_struct.h b/components/soc/esp32s2beta/include/soc/i2s_struct.h index 5be4b18d9e..7b2ea7a74c 100644 --- a/components/soc/esp32s2beta/include/soc/i2s_struct.h +++ b/components/soc/esp32s2beta/include/soc/i2s_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -250,7 +250,8 @@ typedef volatile struct { uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/ uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/ uint32_t mem_trans_en: 1; /*don't use*/ - uint32_t reserved14: 18; + uint32_t ext_mem_bk_size: 2; /*DMA access external memory block size. 0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/ + uint32_t reserved16: 16; }; uint32_t val; } lc_conf; @@ -503,4 +504,4 @@ extern i2s_dev_t I2S1; } #endif -#endif /* _SOC_I2S_STRUCT_H_ */ \ No newline at end of file +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/interrupt_reg.h b/components/soc/esp32s2beta/include/soc/interrupt_reg.h index d04f22928b..1b4ba60974 100644 --- a/components/soc/esp32s2beta/include/soc/interrupt_reg.h +++ b/components/soc/esp32s2beta/include/soc/interrupt_reg.h @@ -459,15 +459,23 @@ extern "C" { #define DPORT_PRO_RSA_INTR_MAP_V 0x1F #define DPORT_PRO_RSA_INTR_MAP_S 0 -#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0DC) -/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define DPORT_PRO_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0DC) +/* DPORT_PRO_SHA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F -#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) -#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F -#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 +#define DPORT_PRO_SHA_INTR_MAP 0x0000001F +#define DPORT_PRO_SHA_INTR_MAP_M ((DPORT_PRO_SHA_INTR_MAP_V)<<(DPORT_PRO_SHA_INTR_MAP_S)) +#define DPORT_PRO_SHA_INTR_MAP_V 0x1F +#define DPORT_PRO_SHA_INTR_MAP_S 0 -#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E0) +#define DPORT_PRO_AES_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E0) +/* DPORT_PRO_AES_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_AES_INTR_MAP 0x0000001F +#define DPORT_PRO_AES_INTR_MAP_M ((DPORT_PRO_AES_INTR_MAP_V)<<(DPORT_PRO_AES_INTR_MAP_S)) +#define DPORT_PRO_AES_INTR_MAP_V 0x1F +#define DPORT_PRO_AES_INTR_MAP_S 0 + +#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E4) /* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F @@ -475,7 +483,7 @@ extern "C" { #define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F #define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 -#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E4) +#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E8) /* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F @@ -483,7 +491,7 @@ extern "C" { #define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F #define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 -#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0E8) +#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0EC) /* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_WDG_INT_MAP 0x0000001F @@ -491,7 +499,7 @@ extern "C" { #define DPORT_PRO_WDG_INT_MAP_V 0x1F #define DPORT_PRO_WDG_INT_MAP_S 0 -#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0EC) +#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F0) /* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TIMER_INT1_MAP 0x0000001F @@ -499,7 +507,7 @@ extern "C" { #define DPORT_PRO_TIMER_INT1_MAP_V 0x1F #define DPORT_PRO_TIMER_INT1_MAP_S 0 -#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F0) +#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F4) /* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TIMER_INT2_MAP 0x0000001F @@ -507,7 +515,7 @@ extern "C" { #define DPORT_PRO_TIMER_INT2_MAP_V 0x1F #define DPORT_PRO_TIMER_INT2_MAP_S 0 -#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F4) +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F8) /* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F @@ -515,7 +523,7 @@ extern "C" { #define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0F8) +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0FC) /* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F @@ -523,7 +531,7 @@ extern "C" { #define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0FC) +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100) /* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F @@ -531,7 +539,7 @@ extern "C" { #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100) +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104) /* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F @@ -539,7 +547,7 @@ extern "C" { #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104) +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108) /* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F @@ -547,7 +555,7 @@ extern "C" { #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108) +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10C) /* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F @@ -555,7 +563,7 @@ extern "C" { #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10C) +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110) /* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F @@ -563,7 +571,7 @@ extern "C" { #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 -#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110) +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114) /* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F @@ -571,7 +579,7 @@ extern "C" { #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 -#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114) +#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118) /* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F @@ -579,7 +587,7 @@ extern "C" { #define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F #define DPORT_PRO_CACHE_IA_INT_MAP_S 0 -#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118) +#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11C) /* DPORT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP 0x0000001F @@ -587,7 +595,7 @@ extern "C" { #define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V 0x1F #define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S 0 -#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11C) +#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120) /* DPORT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP 0x0000001F @@ -595,7 +603,7 @@ extern "C" { #define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V 0x1F #define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S 0 -#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120) +#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124) /* DPORT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP 0x0000001F @@ -603,7 +611,7 @@ extern "C" { #define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V 0x1F #define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S 0 -#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124) +#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128) /* DPORT_PRO_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_ASSIST_DEBUG_INTR_MAP 0x0000001F @@ -611,7 +619,7 @@ extern "C" { #define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V 0x1F #define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128) +#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12C) /* DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP 0x0000001F @@ -619,7 +627,7 @@ extern "C" { #define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12C) +#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130) /* DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP 0x0000001F @@ -627,7 +635,7 @@ extern "C" { #define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130) +#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134) /* DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0x0000001F @@ -635,7 +643,7 @@ extern "C" { #define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134) +#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138) /* DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0x0000001F @@ -643,7 +651,7 @@ extern "C" { #define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138) +#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13C) /* DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP 0x0000001F @@ -651,7 +659,7 @@ extern "C" { #define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13C) +#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140) /* DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP 0x0000001F @@ -659,7 +667,7 @@ extern "C" { #define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140) +#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144) /* DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0x0000001F @@ -667,7 +675,7 @@ extern "C" { #define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S 0 -#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144) +#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148) /* DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ #define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0x0000001F @@ -675,21 +683,13 @@ extern "C" { #define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V 0x1F #define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S 0 -#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148) -/* DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14C) +/* DPORT_PRO_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /*description: */ -#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP 0x0000001F -#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_M ((DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V)<<(DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S)) -#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V 0x1F -#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S 0 - -#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14C) -/* DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ -/*description: */ -#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP 0x0000001F -#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_M ((DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V)<<(DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S)) -#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V 0x1F -#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S 0 +#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_M ((DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_V)<<(DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_S)) +#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define DPORT_PRO_SPI_MEM_REJECT_INTR_MAP_S 0 #define DPORT_PRO_DMA_COPY_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x150) /* DPORT_PRO_DMA_COPY_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ @@ -715,7 +715,71 @@ extern "C" { #define DPORT_PRO_SPI_INTR_4_MAP_V 0x1F #define DPORT_PRO_SPI_INTR_4_MAP_S 0 -#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x15C) +#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x15C) +/* DPORT_PRO_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_M ((DPORT_PRO_DCACHE_PRELOAD_INT_MAP_V)<<(DPORT_PRO_DCACHE_PRELOAD_INT_MAP_S)) +#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_V 0x1F +#define DPORT_PRO_DCACHE_PRELOAD_INT_MAP_S 0 + +#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x160) +/* DPORT_PRO_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_M ((DPORT_PRO_ICACHE_PRELOAD_INT_MAP_V)<<(DPORT_PRO_ICACHE_PRELOAD_INT_MAP_S)) +#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define DPORT_PRO_ICACHE_PRELOAD_INT_MAP_S 0 + +#define DPORT_PRO_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x164) +/* DPORT_PRO_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_APB_ADC_INT_MAP 0x0000001F +#define DPORT_PRO_APB_ADC_INT_MAP_M ((DPORT_PRO_APB_ADC_INT_MAP_V)<<(DPORT_PRO_APB_ADC_INT_MAP_S)) +#define DPORT_PRO_APB_ADC_INT_MAP_V 0x1F +#define DPORT_PRO_APB_ADC_INT_MAP_S 0 + +#define DPORT_PRO_CRYPTO_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x168) +/* DPORT_PRO_CRYPTO_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CRYPTO_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_CRYPTO_DMA_INT_MAP_M ((DPORT_PRO_CRYPTO_DMA_INT_MAP_V)<<(DPORT_PRO_CRYPTO_DMA_INT_MAP_S)) +#define DPORT_PRO_CRYPTO_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_CRYPTO_DMA_INT_MAP_S 0 + +#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x16C) +/* DPORT_PRO_CPU_PERI_ERROR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP 0x0000001F +#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_M ((DPORT_PRO_CPU_PERI_ERROR_INT_MAP_V)<<(DPORT_PRO_CPU_PERI_ERROR_INT_MAP_S)) +#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_V 0x1F +#define DPORT_PRO_CPU_PERI_ERROR_INT_MAP_S 0 + +#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x170) +/* DPORT_PRO_APB_PERI_ERROR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_APB_PERI_ERROR_INT_MAP 0x0000001F +#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_M ((DPORT_PRO_APB_PERI_ERROR_INT_MAP_V)<<(DPORT_PRO_APB_PERI_ERROR_INT_MAP_S)) +#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_V 0x1F +#define DPORT_PRO_APB_PERI_ERROR_INT_MAP_S 0 + +#define DPORT_PRO_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x174) +/* DPORT_PRO_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_DCACHE_SYNC_INT_MAP 0x0000001F +#define DPORT_PRO_DCACHE_SYNC_INT_MAP_M ((DPORT_PRO_DCACHE_SYNC_INT_MAP_V)<<(DPORT_PRO_DCACHE_SYNC_INT_MAP_S)) +#define DPORT_PRO_DCACHE_SYNC_INT_MAP_V 0x1F +#define DPORT_PRO_DCACHE_SYNC_INT_MAP_S 0 + +#define DPORT_PRO_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x178) +/* DPORT_PRO_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define DPORT_PRO_ICACHE_SYNC_INT_MAP 0x0000001F +#define DPORT_PRO_ICACHE_SYNC_INT_MAP_M ((DPORT_PRO_ICACHE_SYNC_INT_MAP_V)<<(DPORT_PRO_ICACHE_SYNC_INT_MAP_S)) +#define DPORT_PRO_ICACHE_SYNC_INT_MAP_V 0x1F +#define DPORT_PRO_ICACHE_SYNC_INT_MAP_S 0 + +#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_INTERRUPT_BASE + 0x17C) /* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF @@ -723,7 +787,7 @@ extern "C" { #define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_0_S 0 -#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x160) +#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_INTERRUPT_BASE + 0x180) /* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF @@ -731,7 +795,7 @@ extern "C" { #define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_1_S 0 -#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_INTERRUPT_BASE + 0x164) +#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_INTERRUPT_BASE + 0x184) /* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF @@ -739,7 +803,7 @@ extern "C" { #define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_2_S 0 -#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x168) +#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x188) /* DPORT_PRO_NMI_MASK_HW : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define DPORT_PRO_NMI_MASK_HW (BIT(1)) @@ -754,7 +818,7 @@ extern "C" { #define INTERRUPT_CLK_EN_S 0 #define INTERRUPT_DATE_REG (DR_REG_INTERRUPT_BASE + 0xFFC) -/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809110 ; */ +/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1904180 ; */ /*description: */ #define INTERRUPT_DATE 0x0FFFFFFF #define INTERRUPT_DATE_M ((INTERRUPT_DATE_V)<<(INTERRUPT_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/io_mux_reg.h b/components/soc/esp32s2beta/include/soc/io_mux_reg.h index da10d62d9d..b9de086724 100644 --- a/components/soc/esp32s2beta/include/soc/io_mux_reg.h +++ b/components/soc/esp32s2beta/include/soc/io_mux_reg.h @@ -131,7 +131,7 @@ #define PIN_FUNC_GPIO 1 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDOWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) #define U1RXD_GPIO_NUM 18 @@ -139,18 +139,18 @@ #define U0RXD_GPIO_NUM 44 #define U0TXD_GPIO_NUM 43 -#define SPI_CLK_GPIO_NUM 30 -#define SPI_Q_GPIO_NUM 31 -#define SPI_D_GPIO_NUM 32 +#define SPI_CS1_GPIO_NUM 26 +#define SPI_HD_GPIO_NUM 27 +#define SPI_WP_GPIO_NUM 28 #define SPI_CS0_GPIO_NUM 29 -#define SPI_HD_GPIO_NUM 27 -#define SPI_WP_GPIO_NUM 28 -#define SD_CLK_GPIO_NUM 12 -#define SD_CMD_GPIO_NUM 11 -#define SD_DATA0_GPIO_NUM 13 -#define SD_DATA1_GPIO_NUM 14 -#define SD_DATA2_GPIO_NUM 9 -#define SD_DATA3_GPIO_NUM 10 +#define SPI_CLK_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 31 +#define SPI_D_GPIO_NUM 32 +#define SPI_D4_GPIO_NUM 33 +#define SPI_D5_GPIO_NUM 34 +#define SPI_D6_GPIO_NUM 35 +#define SPI_D7_GPIO_NUM 36 +#define SPI_DQS_GPIO_NUM 37 #define MAX_RTC_GPIO_NUM 21 #define MAX_PAD_GPIO_NUM 46 @@ -158,6 +158,18 @@ #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE #define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + + #define CLK_OUT3 0xf #define CLK_OUT3_V CLK_OUT3 #define CLK_OUT3_S 8 @@ -209,40 +221,45 @@ #define FUNC_GPIO8_GPIO8_0 0 #define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO9_FSPIHD 4 #define FUNC_GPIO9_SUBSPIHD 3 -#define FUNC_GPIO9_FSPIHD 2 #define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_SD_DATA2 0 +#define FUNC_GPIO9_GPIO9_0 0 #define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO10_FSPICS0 4 #define FUNC_GPIO10_SUBSPICS0 3 -#define FUNC_GPIO10_FSPICS0 2 +#define FUNC_GPIO10_FSPIIO4 2 #define FUNC_GPIO10_GPIO10 1 -#define FUNC_GPIO10_SD_DATA3 0 +#define FUNC_GPIO10_GPIO10_0 0 #define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30) +#define FUNC_GPIO11_FSPID 4 #define FUNC_GPIO11_SUBSPID 3 -#define FUNC_GPIO11_FSPID 2 +#define FUNC_GPIO11_FSPIIO5 2 #define FUNC_GPIO11_GPIO11 1 -#define FUNC_GPIO11_SD_CMD 0 +#define FUNC_GPIO11_GPIO11_0 0 #define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34) +#define FUNC_GPIO12_FSPICLK 4 #define FUNC_GPIO12_SUBSPICLK 3 -#define FUNC_GPIO12_FSPICLK 2 +#define FUNC_GPIO12_FSPIIO6 2 #define FUNC_GPIO12_GPIO12 1 -#define FUNC_GPIO12_SD_CLK 0 +#define FUNC_GPIO12_GPIO12_0 0 #define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38) +#define FUNC_GPIO13_FSPIQ 4 #define FUNC_GPIO13_SUBSPIQ 3 -#define FUNC_GPIO13_FSPIQ 2 +#define FUNC_GPIO13_FSPIIO7 2 #define FUNC_GPIO13_GPIO13 1 -#define FUNC_GPIO13_SD_DATA0 0 +#define FUNC_GPIO13_GPIO13_0 0 #define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c) +#define FUNC_GPIO14_FSPIWP 4 #define FUNC_GPIO14_SUBSPIWP 3 -#define FUNC_GPIO14_FSPIWP 2 +#define FUNC_GPIO14_FSPIDQS 2 #define FUNC_GPIO14_GPIO14 1 -#define FUNC_GPIO14_SD_DATA1 0 +#define FUNC_GPIO14_GPIO14_0 0 #define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40) #define FUNC_XTAL_32K_P_U0RTS 2 @@ -310,40 +327,45 @@ #define FUNC_SPID_SPID 0 #define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) +#define FUNC_GPIO33_SPIIO4 4 #define FUNC_GPIO33_SUBSPIHD 3 -#define FUNC_GPIO33_SD_DATA2 2 +#define FUNC_GPIO33_FSPIHD 2 #define FUNC_GPIO33_GPIO33 1 -#define FUNC_GPIO33_FSPIHD 0 +#define FUNC_GPIO33_GPIO33_0 0 #define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO34_SPIIO5 4 #define FUNC_GPIO34_SUBSPICS0 3 -#define FUNC_GPIO34_SD_DATA3 2 +#define FUNC_GPIO34_FSPICS0 2 #define FUNC_GPIO34_GPIO34 1 -#define FUNC_GPIO34_FSPICS0 0 +#define FUNC_GPIO34_GPIO34_0 0 #define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO35_SPIIO6 4 #define FUNC_GPIO35_SUBSPID 3 -#define FUNC_GPIO35_SD_CMD 2 +#define FUNC_GPIO35_FSPID 2 #define FUNC_GPIO35_GPIO35 1 -#define FUNC_GPIO35_FSPID 0 +#define FUNC_GPIO35_GPIO35_0 0 #define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) +#define FUNC_GPIO36_SPIIO7 4 #define FUNC_GPIO36_SUBSPICLK 3 -#define FUNC_GPIO36_SD_CLK 2 +#define FUNC_GPIO36_FSPICLK 2 #define FUNC_GPIO36_GPIO36 1 -#define FUNC_GPIO36_FSPICLK 0 +#define FUNC_GPIO36_GPIO36_0 0 #define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) +#define FUNC_GPIO37_SPIDQS 4 #define FUNC_GPIO37_SUBSPIQ 3 -#define FUNC_GPIO37_SD_DATA0 2 +#define FUNC_GPIO37_FSPIQ 2 #define FUNC_GPIO37_GPIO37 1 -#define FUNC_GPIO37_FSPIQ 0 +#define FUNC_GPIO37_GPIO37_0 0 #define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) #define FUNC_GPIO38_SUBSPIWP 3 -#define FUNC_GPIO38_SD_DATA1 2 +#define FUNC_GPIO38_FSPIWP 2 #define FUNC_GPIO38_GPIO38 1 -#define FUNC_GPIO38_FSPIWP 0 +#define FUNC_GPIO38_GPIO38_0 0 #define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0) #define FUNC_MTCK_SUBSPICS1 3 @@ -386,6 +408,6 @@ #define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) #define IO_MUX_DATE 0xFFFFFFFF #define IO_MUX_DATE_S 0 -#define IO_MUX_DATE_VERSION 0x1809060 +#define IO_MUX_DATE_VERSION 0x1907160 #endif diff --git a/components/soc/esp32s2beta/include/soc/ledc_reg.h b/components/soc/esp32s2beta/include/soc/ledc_reg.h index 1110b9987f..15abacb870 100644 --- a/components/soc/esp32s2beta/include/soc/ledc_reg.h +++ b/components/soc/esp32s2beta/include/soc/ledc_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -20,12 +20,6 @@ extern "C" { #endif #include "soc.h" #define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) -/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (BIT(31)) -#define LEDC_CLK_EN_V 0x1 -#define LEDC_CLK_EN_S 31 /* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_RESET_ST_LSCH0 (BIT(17)) @@ -1546,6 +1540,12 @@ extern "C" { #define LEDC_LSTIMER0_OVF_INT_CLR_S 0 #define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 /* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: */ #define LEDC_APB_CLK_SEL 0x00000003 @@ -1554,7 +1554,7 @@ extern "C" { #define LEDC_APB_CLK_SEL_S 0 #define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC) -/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072700 ; */ +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */ /*description: */ #define LEDC_DATE 0xFFFFFFFF #define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) @@ -1565,4 +1565,8 @@ extern "C" { } #endif -#endif /*_SOC_LEDC_REG_H_ */ \ No newline at end of file + + +#endif /*_SOC_LEDC_REG_H_ */ + + diff --git a/components/soc/esp32s2beta/include/soc/ledc_struct.h b/components/soc/esp32s2beta/include/soc/ledc_struct.h index 471a1cd878..4f11399076 100644 --- a/components/soc/esp32s2beta/include/soc/ledc_struct.h +++ b/components/soc/esp32s2beta/include/soc/ledc_struct.h @@ -1,9 +1,9 @@ -// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -13,7 +13,6 @@ // limitations under the License. #ifndef _SOC_LEDC_STRUCT_H_ #define _SOC_LEDC_STRUCT_H_ - #ifdef __cplusplus extern "C" { #endif @@ -38,32 +37,32 @@ typedef volatile struct { } conf0; union { struct { - uint32_t hpoint: 14; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ - uint32_t reserved14: 16; + uint32_t hpoint: 14; + uint32_t reserved14: 18; }; uint32_t val; } hpoint; union { struct { - uint32_t duty: 19; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ - uint32_t reserved19: 11; + uint32_t duty: 19; + uint32_t reserved19:13; }; uint32_t val; } duty; union { struct { - uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ - uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ - uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ - uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ - uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + uint32_t duty_scale: 10; + uint32_t duty_cycle: 10; + uint32_t duty_num: 10; + uint32_t duty_inc: 1; + uint32_t duty_start: 1; }; uint32_t val; } conf1; union { struct { - uint32_t duty_read: 19; /*This register represents the current duty of the output signal for high speed channel.*/ - uint32_t reserved19: 11; + uint32_t duty_read: 19; + uint32_t reserved19:13; }; uint32_t val; } duty_rd; @@ -85,8 +84,8 @@ typedef volatile struct { } conf; union { struct { - uint32_t timer_cnt: 14; /*software can read this register to get the current counter value in high speed timer*/ - uint32_t reserved14: 16; + uint32_t timer_cnt: 14; + uint32_t reserved14: 18; }; uint32_t val; } value; @@ -94,105 +93,105 @@ typedef volatile struct { } timer_group[1]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ union { struct { - uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ - uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ - uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ - uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ - uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ - uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ - uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ - uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ - uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ - uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ - uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ - uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved20: 12; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_raw; union { struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t duty_chng_end_lsch6: 1; - uint32_t duty_chng_end_lsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved20: 12; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_st; union { struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t duty_chng_end_lsch6: 1; - uint32_t duty_chng_end_lsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved20: 12; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_ena; union { struct { - uint32_t lstimer0_ovf: 1; - uint32_t lstimer1_ovf: 1; - uint32_t lstimer2_ovf: 1; - uint32_t lstimer3_ovf: 1; - uint32_t duty_chng_end_lsch0: 1; - uint32_t duty_chng_end_lsch1: 1; - uint32_t duty_chng_end_lsch2: 1; - uint32_t duty_chng_end_lsch3: 1; - uint32_t duty_chng_end_lsch4: 1; - uint32_t duty_chng_end_lsch5: 1; - uint32_t duty_chng_end_lsch6: 1; - uint32_t duty_chng_end_lsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved20: 12; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_clr; @@ -203,32 +202,19 @@ typedef volatile struct { }; uint32_t val; } conf; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t date; /*This register represents the version .*/ + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ } ledc_dev_t; extern ledc_dev_t LEDC; - #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2beta/include/soc/mcpwm_reg.h b/components/soc/esp32s2beta/include/soc/mcpwm_reg.h new file mode 100644 index 0000000000..1dce94d469 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/mcpwm_reg.h @@ -0,0 +1,3028 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_MCPWM_REG_H_ +#define _SOC_MCPWM_REG_H_ +#include "soc.h" + +#define REG_MCPWM_BASE(i) (DR_REG_PWM_BASE + i * (0xE000)) +#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) +/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ +#define MCPWM_CLK_PRESCALE 0x000000FF +#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S)) +#define MCPWM_CLK_PRESCALE_V 0xFF +#define MCPWM_CLK_PRESCALE_S 0 + +#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0004) +/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: Update method for active reg of PWM timer0 period 0: immediate + 1: TEZ 2: sync 3: TEZ or sync. TEZ here and below means timer equal zero event*/ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: Period shadow reg of PWM timer0*/ +#define MCPWM_TIMER0_PERIOD 0x0000FFFF +#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S)) +#define MCPWM_TIMER0_PERIOD_V 0xFFFF +#define MCPWM_TIMER0_PERIOD_S 8 +/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ +#define MCPWM_TIMER0_PRESCALE 0x000000FF +#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S)) +#define MCPWM_TIMER0_PRESCALE_V 0xFF +#define MCPWM_TIMER0_PRESCALE_S 0 + +#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0008) +/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: PWM timer0 working mode 0: freeze 1: increase mod 2: decrease + mod 3: up-down mod*/ +#define MCPWM_TIMER0_MOD 0x00000003 +#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S)) +#define MCPWM_TIMER0_MOD_V 0x3 +#define MCPWM_TIMER0_MOD_S 3 +/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP + 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ +#define MCPWM_TIMER0_START 0x00000007 +#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S)) +#define MCPWM_TIMER0_START_V 0x7 +#define MCPWM_TIMER0_START_S 0 + +#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x000c) +/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: Phase for timer reload on sync event*/ +#define MCPWM_TIMER0_PHASE 0x0001FFFF +#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S)) +#define MCPWM_TIMER0_PHASE_V 0x1FFFF +#define MCPWM_TIMER0_PHASE_S 4 +/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S)) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Toggling this bit will trigger a software sync*/ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_V 0x1 +#define MCPWM_TIMER0_SYNC_SW_S 1 +/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set timer reload with phase on sync input event is enabled*/ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_V 0x1 +#define MCPWM_TIMER0_SYNCI_EN_S 0 + +#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0010) +/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Current PWM timer0 counter direction 0: increment 1: decrement*/ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_V 0x1 +#define MCPWM_TIMER0_DIRECTION_S 16 +/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Current PWM timer0 counter value*/ +#define MCPWM_TIMER0_VALUE 0x0000FFFF +#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S)) +#define MCPWM_TIMER0_VALUE_V 0xFFFF +#define MCPWM_TIMER0_VALUE_S 0 + +#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0014) +/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: Update method for active reg of PWM timer1 period 0: immediate + 1: TEZ 2: sync 3: TEZ or sync*/ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: Period shadow reg of PWM timer1*/ +#define MCPWM_TIMER1_PERIOD 0x0000FFFF +#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S)) +#define MCPWM_TIMER1_PERIOD_V 0xFFFF +#define MCPWM_TIMER1_PERIOD_S 8 +/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/ +#define MCPWM_TIMER1_PRESCALE 0x000000FF +#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S)) +#define MCPWM_TIMER1_PRESCALE_V 0xFF +#define MCPWM_TIMER1_PRESCALE_S 0 + +#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0018) +/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: PWM timer1 working mode 0: freeze 1: increase mod 2: decrease + mod 3: up-down mod*/ +#define MCPWM_TIMER1_MOD 0x00000003 +#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S)) +#define MCPWM_TIMER1_MOD_V 0x3 +#define MCPWM_TIMER1_MOD_S 3 +/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: PWM timer1 start and stop control. 0: stop @ TEZ 1: stop @ TEP + 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ +#define MCPWM_TIMER1_START 0x00000007 +#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S)) +#define MCPWM_TIMER1_START_V 0x7 +#define MCPWM_TIMER1_START_S 0 + +#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x001c) +/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: Phase for timer reload on sync event*/ +#define MCPWM_TIMER1_PHASE 0x0001FFFF +#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S)) +#define MCPWM_TIMER1_PHASE_V 0x1FFFF +#define MCPWM_TIMER1_PHASE_S 4 +/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: PWM timer1 synco selection 0: synci 1: TEZ 2: TEP else 0*/ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S)) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Toggling this bit will trigger a software sync*/ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_V 0x1 +#define MCPWM_TIMER1_SYNC_SW_S 1 +/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set timer reload with phase on sync input event is enabled*/ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_V 0x1 +#define MCPWM_TIMER1_SYNCI_EN_S 0 + +#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0020) +/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Current PWM timer1 counter direction 0: increment 1: decrement*/ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_V 0x1 +#define MCPWM_TIMER1_DIRECTION_S 16 +/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Current PWM timer1 counter value*/ +#define MCPWM_TIMER1_VALUE 0x0000FFFF +#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S)) +#define MCPWM_TIMER1_VALUE_V 0xFFFF +#define MCPWM_TIMER1_VALUE_S 0 + +#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0024) +/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: Update method for active reg of PWM timer2 period 0: immediate + 1: TEZ 2: sync 3: TEZ or sync*/ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: Period shadow reg of PWM timer2*/ +#define MCPWM_TIMER2_PERIOD 0x0000FFFF +#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S)) +#define MCPWM_TIMER2_PERIOD_V 0xFFFF +#define MCPWM_TIMER2_PERIOD_S 8 +/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/ +#define MCPWM_TIMER2_PRESCALE 0x000000FF +#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S)) +#define MCPWM_TIMER2_PRESCALE_V 0xFF +#define MCPWM_TIMER2_PRESCALE_S 0 + +#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0028) +/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: PWM timer2 working mode 0: freeze 1: increase mod 2: decrease + mod 3: up-down mod*/ +#define MCPWM_TIMER2_MOD 0x00000003 +#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S)) +#define MCPWM_TIMER2_MOD_V 0x3 +#define MCPWM_TIMER2_MOD_S 3 +/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: PWM timer2 start and stop control. 0: stop @ TEZ 1: stop @ TEP + 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP.*/ +#define MCPWM_TIMER2_START 0x00000007 +#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S)) +#define MCPWM_TIMER2_START_V 0x7 +#define MCPWM_TIMER2_START_S 0 + +#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x002c) +/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: Phase for timer reload on sync event*/ +#define MCPWM_TIMER2_PHASE 0x0001FFFF +#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S)) +#define MCPWM_TIMER2_PHASE_V 0x1FFFF +#define MCPWM_TIMER2_PHASE_S 4 +/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: PWM timer2 synco selection 0: synci 1: TEZ 2: TEP else 0*/ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S)) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Toggling this bit will trigger a software sync*/ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_V 0x1 +#define MCPWM_TIMER2_SYNC_SW_S 1 +/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: When set timer reload with phase on sync input event is enabled*/ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_V 0x1 +#define MCPWM_TIMER2_SYNCI_EN_S 0 + +#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0030) +/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Current PWM timer2 counter direction 0: increment 1: decrement*/ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_V 0x1 +#define MCPWM_TIMER2_DIRECTION_S 16 +/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Current PWM timer2 counter value*/ +#define MCPWM_TIMER2_VALUE 0x0000FFFF +#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S)) +#define MCPWM_TIMER2_VALUE_V 0xFFFF +#define MCPWM_TIMER2_VALUE_S 0 + +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0034) +/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: Onvert SYNC2 from GPIO matrix*/ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 +/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Invert SYNC1 from GPIO matrix*/ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Invert SYNC0 from GPIO matrix*/ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ +/*description: Select sync input for PWM timer2 1: PWM timer0 synco 2: PWM + timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ +#define MCPWM_TIMER2_SYNCISEL 0x00000007 +#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S)) +#define MCPWM_TIMER2_SYNCISEL_V 0x7 +#define MCPWM_TIMER2_SYNCISEL_S 6 +/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ +/*description: Select sync input for PWM timer1 1: PWM timer0 synco 2: PWM + timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ +#define MCPWM_TIMER1_SYNCISEL 0x00000007 +#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S)) +#define MCPWM_TIMER1_SYNCISEL_V 0x7 +#define MCPWM_TIMER1_SYNCISEL_S 3 +/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: Select sync input for PWM timer0 1: PWM timer0 synco 2: PWM + timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix other values: no sync input selected*/ +#define MCPWM_TIMER0_SYNCISEL 0x00000007 +#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S)) +#define MCPWM_TIMER0_SYNCISEL_V 0x7 +#define MCPWM_TIMER0_SYNCISEL_S 0 + +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x0038) +/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Select which PWM timer's is the timing reference for PWM operator2 + 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S)) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR2_TIMERSEL_S 4 +/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Select which PWM timer's is the timing reference for PWM operator1 + 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S)) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Select which PWM timer's is the timing reference for PWM operator0 + 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S)) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR0_TIMERSEL_S 0 + +#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x003c) +/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 0 time stamp + B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN0_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_GEN0_B_SHDW_FULL_V 0x1 +#define MCPWM_GEN0_B_SHDW_FULL_S 9 +/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 0 time stamp + A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN0_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_GEN0_A_SHDW_FULL_V 0x1 +#define MCPWM_GEN0_A_SHDW_FULL_S 8 +/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 0 time stamp B's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN0_B_UPMETHOD 0x0000000F +#define MCPWM_GEN0_B_UPMETHOD_M ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S)) +#define MCPWM_GEN0_B_UPMETHOD_V 0xF +#define MCPWM_GEN0_B_UPMETHOD_S 4 +/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 0 time stamp A's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN0_A_UPMETHOD 0x0000000F +#define MCPWM_GEN0_A_UPMETHOD_M ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S)) +#define MCPWM_GEN0_A_UPMETHOD_V 0xF +#define MCPWM_GEN0_A_UPMETHOD_S 0 + +#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0040) +/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 0 time stamp A's shadow reg*/ +#define MCPWM_GEN0_A 0x0000FFFF +#define MCPWM_GEN0_A_M ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S)) +#define MCPWM_GEN0_A_V 0xFFFF +#define MCPWM_GEN0_A_S 0 + +#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x0044) +/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 0 time stamp B's shadow reg*/ +#define MCPWM_GEN0_B 0x0000FFFF +#define MCPWM_GEN0_B_M ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S)) +#define MCPWM_GEN0_B_V 0xFFFF +#define MCPWM_GEN0_B_S 0 + +#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0048) +/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: Source selection for PWM generator 0 event_t1 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN0_T1_SEL 0x00000007 +#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S)) +#define MCPWM_GEN0_T1_SEL_V 0x7 +#define MCPWM_GEN0_T1_SEL_S 7 +/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: Source selection for PWM generator 0 event_t0 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN0_T0_SEL 0x00000007 +#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S)) +#define MCPWM_GEN0_T0_SEL_V 0x7 +#define MCPWM_GEN0_T0_SEL_S 4 +/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 0's active reg of configuration. + 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S)) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x004c) +/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM0B 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM0B a + toggle will trigger a force event*/ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_V 0x1 +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM0A 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM0A a + toggle will trigger a force event*/ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_V 0x1 +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM0B. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM0A. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: Update method for continuous software force of PWM generator0. + 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x0050) +/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN0_A_DT1 0x00000003 +#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S)) +#define MCPWM_GEN0_A_DT1_V 0x3 +#define MCPWM_GEN0_A_DT1_S 22 +/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN0_A_DT0 0x00000003 +#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S)) +#define MCPWM_GEN0_A_DT0_V 0x3 +#define MCPWM_GEN0_A_DT0_S 20 +/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN0_A_DTEB 0x00000003 +#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S)) +#define MCPWM_GEN0_A_DTEB_V 0x3 +#define MCPWM_GEN0_A_DTEB_S 18 +/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN0_A_DTEA 0x00000003 +#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S)) +#define MCPWM_GEN0_A_DTEA_V 0x3 +#define MCPWM_GEN0_A_DTEA_S 16 +/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN0_A_DTEP 0x00000003 +#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S)) +#define MCPWM_GEN0_A_DTEP_V 0x3 +#define MCPWM_GEN0_A_DTEP_S 14 +/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN0_A_DTEZ 0x00000003 +#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S)) +#define MCPWM_GEN0_A_DTEZ_V 0x3 +#define MCPWM_GEN0_A_DTEZ_S 12 +/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN0_A_UT1 0x00000003 +#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S)) +#define MCPWM_GEN0_A_UT1_V 0x3 +#define MCPWM_GEN0_A_UT1_S 10 +/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN0_A_UT0 0x00000003 +#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S)) +#define MCPWM_GEN0_A_UT0_V 0x3 +#define MCPWM_GEN0_A_UT0_S 8 +/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEB when timer increasing*/ +#define MCPWM_GEN0_A_UTEB 0x00000003 +#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S)) +#define MCPWM_GEN0_A_UTEB_V 0x3 +#define MCPWM_GEN0_A_UTEB_S 6 +/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEA when timer increasing*/ +#define MCPWM_GEN0_A_UTEA 0x00000003 +#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S)) +#define MCPWM_GEN0_A_UTEA_V 0x3 +#define MCPWM_GEN0_A_UTEA_S 4 +/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEP when timer increasing*/ +#define MCPWM_GEN0_A_UTEP 0x00000003 +#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S)) +#define MCPWM_GEN0_A_UTEP_V 0x3 +#define MCPWM_GEN0_A_UTEP_S 2 +/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM0A triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN0_A_UTEZ 0x00000003 +#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S)) +#define MCPWM_GEN0_A_UTEZ_V 0x3 +#define MCPWM_GEN0_A_UTEZ_S 0 + +#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x0054) +/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN0_B_DT1 0x00000003 +#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S)) +#define MCPWM_GEN0_B_DT1_V 0x3 +#define MCPWM_GEN0_B_DT1_S 22 +/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN0_B_DT0 0x00000003 +#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S)) +#define MCPWM_GEN0_B_DT0_V 0x3 +#define MCPWM_GEN0_B_DT0_S 20 +/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN0_B_DTEB 0x00000003 +#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S)) +#define MCPWM_GEN0_B_DTEB_V 0x3 +#define MCPWM_GEN0_B_DTEB_S 18 +/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN0_B_DTEA 0x00000003 +#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S)) +#define MCPWM_GEN0_B_DTEA_V 0x3 +#define MCPWM_GEN0_B_DTEA_S 16 +/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN0_B_DTEP 0x00000003 +#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S)) +#define MCPWM_GEN0_B_DTEP_V 0x3 +#define MCPWM_GEN0_B_DTEP_S 14 +/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN0_B_DTEZ 0x00000003 +#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S)) +#define MCPWM_GEN0_B_DTEZ_V 0x3 +#define MCPWM_GEN0_B_DTEZ_S 12 +/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN0_B_UT1 0x00000003 +#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S)) +#define MCPWM_GEN0_B_UT1_V 0x3 +#define MCPWM_GEN0_B_UT1_S 10 +/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN0_B_UT0 0x00000003 +#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S)) +#define MCPWM_GEN0_B_UT0_V 0x3 +#define MCPWM_GEN0_B_UT0_S 8 +/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEB when timer increasing*/ +#define MCPWM_GEN0_B_UTEB 0x00000003 +#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S)) +#define MCPWM_GEN0_B_UTEB_V 0x3 +#define MCPWM_GEN0_B_UTEB_S 6 +/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEA when timer increasing*/ +#define MCPWM_GEN0_B_UTEA 0x00000003 +#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S)) +#define MCPWM_GEN0_B_UTEA_V 0x3 +#define MCPWM_GEN0_B_UTEA_S 4 +/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEP when timer increasing*/ +#define MCPWM_GEN0_B_UTEP 0x00000003 +#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S)) +#define MCPWM_GEN0_B_UTEP_V 0x3 +#define MCPWM_GEN0_B_UTEP_S 2 +/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM0B triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN0_B_UTEZ 0x00000003 +#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S)) +#define MCPWM_GEN0_B_UTEZ_V 0x3 +#define MCPWM_GEN0_B_UTEZ_S 0 + +#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0058) +/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Dead time generator 0 clock selection. 0: PWM_clk 1: PT_clk*/ +#define MCPWM_DT0_CLK_SEL (BIT(17)) +#define MCPWM_DT0_CLK_SEL_M (BIT(17)) +#define MCPWM_DT0_CLK_SEL_V 0x1 +#define MCPWM_DT0_CLK_SEL_S 17 +/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: S0 in documentation*/ +#define MCPWM_DT0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DT0_B_OUTBYPASS_V 0x1 +#define MCPWM_DT0_B_OUTBYPASS_S 16 +/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: S1 in documentation*/ +#define MCPWM_DT0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DT0_A_OUTBYPASS_V 0x1 +#define MCPWM_DT0_A_OUTBYPASS_S 15 +/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: S3 in documentation*/ +#define MCPWM_DT0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DT0_FED_OUTINVERT_V 0x1 +#define MCPWM_DT0_FED_OUTINVERT_S 14 +/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: S2 in documentation*/ +#define MCPWM_DT0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DT0_RED_OUTINVERT_V 0x1 +#define MCPWM_DT0_RED_OUTINVERT_S 13 +/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: S5 in documentation*/ +#define MCPWM_DT0_FED_INSEL (BIT(12)) +#define MCPWM_DT0_FED_INSEL_M (BIT(12)) +#define MCPWM_DT0_FED_INSEL_V 0x1 +#define MCPWM_DT0_FED_INSEL_S 12 +/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: S4 in documentation*/ +#define MCPWM_DT0_RED_INSEL (BIT(11)) +#define MCPWM_DT0_RED_INSEL_M (BIT(11)) +#define MCPWM_DT0_RED_INSEL_V 0x1 +#define MCPWM_DT0_RED_INSEL_S 11 +/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: S7 in documentation*/ +#define MCPWM_DT0_B_OUTSWAP (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DT0_B_OUTSWAP_V 0x1 +#define MCPWM_DT0_B_OUTSWAP_S 10 +/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: S6 in documentation*/ +#define MCPWM_DT0_A_OUTSWAP (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DT0_A_OUTSWAP_V 0x1 +#define MCPWM_DT0_A_OUTSWAP_S 9 +/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect + on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ +#define MCPWM_DT0_DEB_MODE (BIT(8)) +#define MCPWM_DT0_DEB_MODE_M (BIT(8)) +#define MCPWM_DT0_DEB_MODE_V 0x1 +#define MCPWM_DT0_DEB_MODE_S 8 +/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for RED (rising edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT0_RED_UPMETHOD 0x0000000F +#define MCPWM_DT0_RED_UPMETHOD_M ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S)) +#define MCPWM_DT0_RED_UPMETHOD_V 0xF +#define MCPWM_DT0_RED_UPMETHOD_S 4 +/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for FED (falling edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT0_FED_UPMETHOD 0x0000000F +#define MCPWM_DT0_FED_UPMETHOD_M ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S)) +#define MCPWM_DT0_FED_UPMETHOD_V 0xF +#define MCPWM_DT0_FED_UPMETHOD_S 0 + +#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x005c) +/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for FED*/ +#define MCPWM_DT0_FED 0x0000FFFF +#define MCPWM_DT0_FED_M ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S)) +#define MCPWM_DT0_FED_V 0xFFFF +#define MCPWM_DT0_FED_S 0 + +#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0060) +/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for RED*/ +#define MCPWM_DT0_RED 0x0000FFFF +#define MCPWM_DT0_RED_M ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S)) +#define MCPWM_DT0_RED_V 0xFFFF +#define MCPWM_DT0_RED_S 0 + +#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0064) +/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: When set invert the input of PWM0A and PWM0B for this submodule*/ +#define MCPWM_CARRIER0_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_M (BIT(13)) +#define MCPWM_CARRIER0_IN_INVERT_V 0x1 +#define MCPWM_CARRIER0_IN_INVERT_S 13 +/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: When set invert the output of PWM0A and PWM0B for this submodule*/ +#define MCPWM_CARRIER0_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_M (BIT(12)) +#define MCPWM_CARRIER0_OUT_INVERT_V 0x1 +#define MCPWM_CARRIER0_OUT_INVERT_S 12 +/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Width of the fist pulse in number of periods of the carrier*/ +#define MCPWM_CARRIER0_OSHWTH 0x0000000F +#define MCPWM_CARRIER0_OSHWTH_M ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S)) +#define MCPWM_CARRIER0_OSHWTH_V 0xF +#define MCPWM_CARRIER0_OSHWTH_S 8 +/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ +#define MCPWM_CARRIER0_DUTY 0x00000007 +#define MCPWM_CARRIER0_DUTY_M ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S)) +#define MCPWM_CARRIER0_DUTY_V 0x7 +#define MCPWM_CARRIER0_DUTY_S 5 +/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk + = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ +#define MCPWM_CARRIER0_PRESCALE 0x0000000F +#define MCPWM_CARRIER0_PRESCALE_M ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S)) +#define MCPWM_CARRIER0_PRESCALE_V 0xF +#define MCPWM_CARRIER0_PRESCALE_S 1 +/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set carrier0 function is enabled. When cleared carrier0 is bypassed*/ +#define MCPWM_CARRIER0_EN (BIT(0)) +#define MCPWM_CARRIER0_EN_M (BIT(0)) +#define MCPWM_CARRIER0_EN_V 0x1 +#define MCPWM_CARRIER0_EN_S 0 + +#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0068) +/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0B when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_OST_U 0x00000003 +#define MCPWM_FH0_B_OST_U_M ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S)) +#define MCPWM_FH0_B_OST_U_V 0x3 +#define MCPWM_FH0_B_OST_U_S 22 +/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0B when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_OST_D 0x00000003 +#define MCPWM_FH0_B_OST_D_M ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S)) +#define MCPWM_FH0_B_OST_D_V 0x3 +#define MCPWM_FH0_B_OST_D_S 20 +/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_CBC_U 0x00000003 +#define MCPWM_FH0_B_CBC_U_M ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S)) +#define MCPWM_FH0_B_CBC_U_V 0x3 +#define MCPWM_FH0_B_CBC_U_S 18 +/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_B_CBC_D 0x00000003 +#define MCPWM_FH0_B_CBC_D_M ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S)) +#define MCPWM_FH0_B_CBC_D_V 0x3 +#define MCPWM_FH0_B_CBC_D_S 16 +/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0A when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_OST_U 0x00000003 +#define MCPWM_FH0_A_OST_U_M ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S)) +#define MCPWM_FH0_A_OST_U_V 0x3 +#define MCPWM_FH0_A_OST_U_S 14 +/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM0A when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_OST_D 0x00000003 +#define MCPWM_FH0_A_OST_D_M ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S)) +#define MCPWM_FH0_A_OST_D_V 0x3 +#define MCPWM_FH0_A_OST_D_S 12 +/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_CBC_U 0x00000003 +#define MCPWM_FH0_A_CBC_U_M ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S)) +#define MCPWM_FH0_A_CBC_U_V 0x3 +#define MCPWM_FH0_A_CBC_U_S 10 +/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH0_A_CBC_D 0x00000003 +#define MCPWM_FH0_A_CBC_D_M ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S)) +#define MCPWM_FH0_A_CBC_D_V 0x3 +#define MCPWM_FH0_A_CBC_D_S 8 +/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F0_OST (BIT(7)) +#define MCPWM_FH0_F0_OST_M (BIT(7)) +#define MCPWM_FH0_F0_OST_V 0x1 +#define MCPWM_FH0_F0_OST_S 7 +/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F1_OST (BIT(6)) +#define MCPWM_FH0_F1_OST_M (BIT(6)) +#define MCPWM_FH0_F1_OST_V 0x1 +#define MCPWM_FH0_F1_OST_S 6 +/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F2_OST (BIT(5)) +#define MCPWM_FH0_F2_OST_M (BIT(5)) +#define MCPWM_FH0_F2_OST_V 0x1 +#define MCPWM_FH0_F2_OST_S 5 +/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_SW_OST (BIT(4)) +#define MCPWM_FH0_SW_OST_M (BIT(4)) +#define MCPWM_FH0_SW_OST_V 0x1 +#define MCPWM_FH0_SW_OST_S 4 +/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F0_CBC (BIT(3)) +#define MCPWM_FH0_F0_CBC_M (BIT(3)) +#define MCPWM_FH0_F0_CBC_V 0x1 +#define MCPWM_FH0_F0_CBC_S 3 +/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F1_CBC (BIT(2)) +#define MCPWM_FH0_F1_CBC_M (BIT(2)) +#define MCPWM_FH0_F1_CBC_V 0x1 +#define MCPWM_FH0_F1_CBC_S 2 +/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH0_F2_CBC (BIT(1)) +#define MCPWM_FH0_F2_CBC_M (BIT(1)) +#define MCPWM_FH0_F2_CBC_V 0x1 +#define MCPWM_FH0_F2_CBC_S 1 +/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Enable register for software force cycle-by-cycle mode action. + 0: disable 1: enable*/ +#define MCPWM_FH0_SW_CBC (BIT(0)) +#define MCPWM_FH0_SW_CBC_M (BIT(0)) +#define MCPWM_FH0_SW_CBC_V 0x1 +#define MCPWM_FH0_SW_CBC_S 0 + +#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x006c) +/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) triggers a + one-shot mode action*/ +#define MCPWM_FH0_FORCE_OST (BIT(4)) +#define MCPWM_FH0_FORCE_OST_M (BIT(4)) +#define MCPWM_FH0_FORCE_OST_V 0x1 +#define MCPWM_FH0_FORCE_OST_S 4 +/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle triggers a cycle-by-cycle mode action*/ +#define MCPWM_FH0_FORCE_CBC (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_M (BIT(3)) +#define MCPWM_FH0_FORCE_CBC_V 0x1 +#define MCPWM_FH0_FORCE_CBC_S 3 +/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ +#define MCPWM_FH0_CBCPULSE 0x00000003 +#define MCPWM_FH0_CBCPULSE_M ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S)) +#define MCPWM_FH0_CBCPULSE_V 0x3 +#define MCPWM_FH0_CBCPULSE_S 1 +/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: A toggle will clear on going one-shot mode action*/ +#define MCPWM_FH0_CLR_OST (BIT(0)) +#define MCPWM_FH0_CLR_OST_M (BIT(0)) +#define MCPWM_FH0_CLR_OST_V 0x1 +#define MCPWM_FH0_CLR_OST_S 0 + +#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0070) +/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ +#define MCPWM_FH0_OST_ON (BIT(1)) +#define MCPWM_FH0_OST_ON_M (BIT(1)) +#define MCPWM_FH0_OST_ON_V 0x1 +#define MCPWM_FH0_OST_ON_S 1 +/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ +#define MCPWM_FH0_CBC_ON (BIT(0)) +#define MCPWM_FH0_CBC_ON_M (BIT(0)) +#define MCPWM_FH0_CBC_ON_V 0x1 +#define MCPWM_FH0_CBC_ON_S 0 + +#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0074) +/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 1 time stamp + B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN1_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_GEN1_B_SHDW_FULL_V 0x1 +#define MCPWM_GEN1_B_SHDW_FULL_S 9 +/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 1 time stamp + A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN1_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_GEN1_A_SHDW_FULL_V 0x1 +#define MCPWM_GEN1_A_SHDW_FULL_S 8 +/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 1 time stamp B's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN1_B_UPMETHOD 0x0000000F +#define MCPWM_GEN1_B_UPMETHOD_M ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S)) +#define MCPWM_GEN1_B_UPMETHOD_V 0xF +#define MCPWM_GEN1_B_UPMETHOD_S 4 +/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 1 time stamp A's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN1_A_UPMETHOD 0x0000000F +#define MCPWM_GEN1_A_UPMETHOD_M ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S)) +#define MCPWM_GEN1_A_UPMETHOD_V 0xF +#define MCPWM_GEN1_A_UPMETHOD_S 0 + +#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x0078) +/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 1 time stamp A's shadow reg*/ +#define MCPWM_GEN1_A 0x0000FFFF +#define MCPWM_GEN1_A_M ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S)) +#define MCPWM_GEN1_A_V 0xFFFF +#define MCPWM_GEN1_A_S 0 + +#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x007c) +/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 1 time stamp B's shadow reg*/ +#define MCPWM_GEN1_B 0x0000FFFF +#define MCPWM_GEN1_B_M ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S)) +#define MCPWM_GEN1_B_V 0xFFFF +#define MCPWM_GEN1_B_S 0 + +#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0080) +/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate1 event_t1 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN1_T1_SEL 0x00000007 +#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S)) +#define MCPWM_GEN1_T1_SEL_V 0x7 +#define MCPWM_GEN1_T1_SEL_S 7 +/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate1 event_t0 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN1_T0_SEL 0x00000007 +#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S)) +#define MCPWM_GEN1_T0_SEL_V 0x7 +#define MCPWM_GEN1_T0_SEL_S 4 +/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generate1's active reg of configuration. + 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S)) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x0084) +/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM1B 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM1B a + toggle will trigger a force event*/ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_V 0x1 +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM1A 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM1A a + toggle will trigger a force event*/ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_V 0x1 +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM1B. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM1A. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: Update method for continuous software force of PWM generator1. + 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x0088) +/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN1_A_DT1 0x00000003 +#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S)) +#define MCPWM_GEN1_A_DT1_V 0x3 +#define MCPWM_GEN1_A_DT1_S 22 +/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN1_A_DT0 0x00000003 +#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S)) +#define MCPWM_GEN1_A_DT0_V 0x3 +#define MCPWM_GEN1_A_DT0_S 20 +/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN1_A_DTEB 0x00000003 +#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S)) +#define MCPWM_GEN1_A_DTEB_V 0x3 +#define MCPWM_GEN1_A_DTEB_S 18 +/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN1_A_DTEA 0x00000003 +#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S)) +#define MCPWM_GEN1_A_DTEA_V 0x3 +#define MCPWM_GEN1_A_DTEA_S 16 +/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN1_A_DTEP 0x00000003 +#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S)) +#define MCPWM_GEN1_A_DTEP_V 0x3 +#define MCPWM_GEN1_A_DTEP_S 14 +/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN1_A_DTEZ 0x00000003 +#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S)) +#define MCPWM_GEN1_A_DTEZ_V 0x3 +#define MCPWM_GEN1_A_DTEZ_S 12 +/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN1_A_UT1 0x00000003 +#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S)) +#define MCPWM_GEN1_A_UT1_V 0x3 +#define MCPWM_GEN1_A_UT1_S 10 +/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN1_A_UT0 0x00000003 +#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S)) +#define MCPWM_GEN1_A_UT0_V 0x3 +#define MCPWM_GEN1_A_UT0_S 8 +/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEB when timer increasing*/ +#define MCPWM_GEN1_A_UTEB 0x00000003 +#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S)) +#define MCPWM_GEN1_A_UTEB_V 0x3 +#define MCPWM_GEN1_A_UTEB_S 6 +/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEA when timer increasing*/ +#define MCPWM_GEN1_A_UTEA 0x00000003 +#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S)) +#define MCPWM_GEN1_A_UTEA_V 0x3 +#define MCPWM_GEN1_A_UTEA_S 4 +/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEP when timer increasing*/ +#define MCPWM_GEN1_A_UTEP 0x00000003 +#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S)) +#define MCPWM_GEN1_A_UTEP_V 0x3 +#define MCPWM_GEN1_A_UTEP_S 2 +/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM1A triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN1_A_UTEZ 0x00000003 +#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S)) +#define MCPWM_GEN1_A_UTEZ_V 0x3 +#define MCPWM_GEN1_A_UTEZ_S 0 + +#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x008c) +/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN1_B_DT1 0x00000003 +#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S)) +#define MCPWM_GEN1_B_DT1_V 0x3 +#define MCPWM_GEN1_B_DT1_S 22 +/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN1_B_DT0 0x00000003 +#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S)) +#define MCPWM_GEN1_B_DT0_V 0x3 +#define MCPWM_GEN1_B_DT0_S 20 +/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN1_B_DTEB 0x00000003 +#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S)) +#define MCPWM_GEN1_B_DTEB_V 0x3 +#define MCPWM_GEN1_B_DTEB_S 18 +/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN1_B_DTEA 0x00000003 +#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S)) +#define MCPWM_GEN1_B_DTEA_V 0x3 +#define MCPWM_GEN1_B_DTEA_S 16 +/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN1_B_DTEP 0x00000003 +#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S)) +#define MCPWM_GEN1_B_DTEP_V 0x3 +#define MCPWM_GEN1_B_DTEP_S 14 +/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN1_B_DTEZ 0x00000003 +#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S)) +#define MCPWM_GEN1_B_DTEZ_V 0x3 +#define MCPWM_GEN1_B_DTEZ_S 12 +/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN1_B_UT1 0x00000003 +#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S)) +#define MCPWM_GEN1_B_UT1_V 0x3 +#define MCPWM_GEN1_B_UT1_S 10 +/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN1_B_UT0 0x00000003 +#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S)) +#define MCPWM_GEN1_B_UT0_V 0x3 +#define MCPWM_GEN1_B_UT0_S 8 +/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEB when timer increasing*/ +#define MCPWM_GEN1_B_UTEB 0x00000003 +#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S)) +#define MCPWM_GEN1_B_UTEB_V 0x3 +#define MCPWM_GEN1_B_UTEB_S 6 +/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEA when timer increasing*/ +#define MCPWM_GEN1_B_UTEA 0x00000003 +#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S)) +#define MCPWM_GEN1_B_UTEA_V 0x3 +#define MCPWM_GEN1_B_UTEA_S 4 +/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEP when timer increasing*/ +#define MCPWM_GEN1_B_UTEP 0x00000003 +#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S)) +#define MCPWM_GEN1_B_UTEP_V 0x3 +#define MCPWM_GEN1_B_UTEP_S 2 +/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM1B triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN1_B_UTEZ 0x00000003 +#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S)) +#define MCPWM_GEN1_B_UTEZ_V 0x3 +#define MCPWM_GEN1_B_UTEZ_S 0 + +#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0090) +/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ +#define MCPWM_DT1_CLK_SEL (BIT(17)) +#define MCPWM_DT1_CLK_SEL_M (BIT(17)) +#define MCPWM_DT1_CLK_SEL_V 0x1 +#define MCPWM_DT1_CLK_SEL_S 17 +/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: S0 in documentation*/ +#define MCPWM_DT1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DT1_B_OUTBYPASS_V 0x1 +#define MCPWM_DT1_B_OUTBYPASS_S 16 +/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: S1 in documentation*/ +#define MCPWM_DT1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DT1_A_OUTBYPASS_V 0x1 +#define MCPWM_DT1_A_OUTBYPASS_S 15 +/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: S3 in documentation*/ +#define MCPWM_DT1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DT1_FED_OUTINVERT_V 0x1 +#define MCPWM_DT1_FED_OUTINVERT_S 14 +/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: S2 in documentation*/ +#define MCPWM_DT1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DT1_RED_OUTINVERT_V 0x1 +#define MCPWM_DT1_RED_OUTINVERT_S 13 +/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: S5 in documentation*/ +#define MCPWM_DT1_FED_INSEL (BIT(12)) +#define MCPWM_DT1_FED_INSEL_M (BIT(12)) +#define MCPWM_DT1_FED_INSEL_V 0x1 +#define MCPWM_DT1_FED_INSEL_S 12 +/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: S4 in documentation*/ +#define MCPWM_DT1_RED_INSEL (BIT(11)) +#define MCPWM_DT1_RED_INSEL_M (BIT(11)) +#define MCPWM_DT1_RED_INSEL_V 0x1 +#define MCPWM_DT1_RED_INSEL_S 11 +/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: S7 in documentation*/ +#define MCPWM_DT1_B_OUTSWAP (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DT1_B_OUTSWAP_V 0x1 +#define MCPWM_DT1_B_OUTSWAP_S 10 +/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: S6 in documentation*/ +#define MCPWM_DT1_A_OUTSWAP (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DT1_A_OUTSWAP_V 0x1 +#define MCPWM_DT1_A_OUTSWAP_S 9 +/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect + on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ +#define MCPWM_DT1_DEB_MODE (BIT(8)) +#define MCPWM_DT1_DEB_MODE_M (BIT(8)) +#define MCPWM_DT1_DEB_MODE_V 0x1 +#define MCPWM_DT1_DEB_MODE_S 8 +/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for RED (rising edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT1_RED_UPMETHOD 0x0000000F +#define MCPWM_DT1_RED_UPMETHOD_M ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S)) +#define MCPWM_DT1_RED_UPMETHOD_V 0xF +#define MCPWM_DT1_RED_UPMETHOD_S 4 +/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for FED (falling edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT1_FED_UPMETHOD 0x0000000F +#define MCPWM_DT1_FED_UPMETHOD_M ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S)) +#define MCPWM_DT1_FED_UPMETHOD_V 0xF +#define MCPWM_DT1_FED_UPMETHOD_S 0 + +#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0094) +/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for FED*/ +#define MCPWM_DT1_FED 0x0000FFFF +#define MCPWM_DT1_FED_M ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S)) +#define MCPWM_DT1_FED_V 0xFFFF +#define MCPWM_DT1_FED_S 0 + +#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0098) +/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for RED*/ +#define MCPWM_DT1_RED 0x0000FFFF +#define MCPWM_DT1_RED_M ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S)) +#define MCPWM_DT1_RED_V 0xFFFF +#define MCPWM_DT1_RED_S 0 + +#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x009c) +/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: When set invert the input of PWM1A and PWM1B for this submodule*/ +#define MCPWM_CARRIER1_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_M (BIT(13)) +#define MCPWM_CARRIER1_IN_INVERT_V 0x1 +#define MCPWM_CARRIER1_IN_INVERT_S 13 +/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: When set invert the output of PWM1A and PWM1B for this submodule*/ +#define MCPWM_CARRIER1_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_M (BIT(12)) +#define MCPWM_CARRIER1_OUT_INVERT_V 0x1 +#define MCPWM_CARRIER1_OUT_INVERT_S 12 +/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Width of the fist pulse in number of periods of the carrier*/ +#define MCPWM_CARRIER1_OSHWTH 0x0000000F +#define MCPWM_CARRIER1_OSHWTH_M ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S)) +#define MCPWM_CARRIER1_OSHWTH_V 0xF +#define MCPWM_CARRIER1_OSHWTH_S 8 +/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/ +#define MCPWM_CARRIER1_DUTY 0x00000007 +#define MCPWM_CARRIER1_DUTY_M ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S)) +#define MCPWM_CARRIER1_DUTY_V 0x7 +#define MCPWM_CARRIER1_DUTY_S 5 +/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk + = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/ +#define MCPWM_CARRIER1_PRESCALE 0x0000000F +#define MCPWM_CARRIER1_PRESCALE_M ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S)) +#define MCPWM_CARRIER1_PRESCALE_V 0xF +#define MCPWM_CARRIER1_PRESCALE_S 1 +/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set carrier1 function is enabled. When cleared carrier1 is bypassed*/ +#define MCPWM_CARRIER1_EN (BIT(0)) +#define MCPWM_CARRIER1_EN_M (BIT(0)) +#define MCPWM_CARRIER1_EN_V 0x1 +#define MCPWM_CARRIER1_EN_S 0 + +#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00a0) +/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1B when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_OST_U 0x00000003 +#define MCPWM_FH1_B_OST_U_M ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S)) +#define MCPWM_FH1_B_OST_U_V 0x3 +#define MCPWM_FH1_B_OST_U_S 22 +/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1B when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_OST_D 0x00000003 +#define MCPWM_FH1_B_OST_D_M ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S)) +#define MCPWM_FH1_B_OST_D_V 0x3 +#define MCPWM_FH1_B_OST_D_S 20 +/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_CBC_U 0x00000003 +#define MCPWM_FH1_B_CBC_U_M ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S)) +#define MCPWM_FH1_B_CBC_U_V 0x3 +#define MCPWM_FH1_B_CBC_U_S 18 +/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_B_CBC_D 0x00000003 +#define MCPWM_FH1_B_CBC_D_M ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S)) +#define MCPWM_FH1_B_CBC_D_V 0x3 +#define MCPWM_FH1_B_CBC_D_S 16 +/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1A when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_OST_U 0x00000003 +#define MCPWM_FH1_A_OST_U_M ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S)) +#define MCPWM_FH1_A_OST_U_V 0x3 +#define MCPWM_FH1_A_OST_U_S 14 +/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM1A when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_OST_D 0x00000003 +#define MCPWM_FH1_A_OST_D_M ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S)) +#define MCPWM_FH1_A_OST_D_V 0x3 +#define MCPWM_FH1_A_OST_D_S 12 +/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_CBC_U 0x00000003 +#define MCPWM_FH1_A_CBC_U_M ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S)) +#define MCPWM_FH1_A_CBC_U_V 0x3 +#define MCPWM_FH1_A_CBC_U_S 10 +/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH1_A_CBC_D 0x00000003 +#define MCPWM_FH1_A_CBC_D_M ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S)) +#define MCPWM_FH1_A_CBC_D_V 0x3 +#define MCPWM_FH1_A_CBC_D_S 8 +/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F0_OST (BIT(7)) +#define MCPWM_FH1_F0_OST_M (BIT(7)) +#define MCPWM_FH1_F0_OST_V 0x1 +#define MCPWM_FH1_F0_OST_S 7 +/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F1_OST (BIT(6)) +#define MCPWM_FH1_F1_OST_M (BIT(6)) +#define MCPWM_FH1_F1_OST_V 0x1 +#define MCPWM_FH1_F1_OST_S 6 +/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F2_OST (BIT(5)) +#define MCPWM_FH1_F2_OST_M (BIT(5)) +#define MCPWM_FH1_F2_OST_V 0x1 +#define MCPWM_FH1_F2_OST_S 5 +/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_SW_OST (BIT(4)) +#define MCPWM_FH1_SW_OST_M (BIT(4)) +#define MCPWM_FH1_SW_OST_V 0x1 +#define MCPWM_FH1_SW_OST_S 4 +/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F0_CBC (BIT(3)) +#define MCPWM_FH1_F0_CBC_M (BIT(3)) +#define MCPWM_FH1_F0_CBC_V 0x1 +#define MCPWM_FH1_F0_CBC_S 3 +/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F1_CBC (BIT(2)) +#define MCPWM_FH1_F1_CBC_M (BIT(2)) +#define MCPWM_FH1_F1_CBC_V 0x1 +#define MCPWM_FH1_F1_CBC_S 2 +/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH1_F2_CBC (BIT(1)) +#define MCPWM_FH1_F2_CBC_M (BIT(1)) +#define MCPWM_FH1_F2_CBC_V 0x1 +#define MCPWM_FH1_F2_CBC_S 1 +/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Enable register for software force cycle-by-cycle mode action. + 0: disable 1: enable*/ +#define MCPWM_FH1_SW_CBC (BIT(0)) +#define MCPWM_FH1_SW_CBC_M (BIT(0)) +#define MCPWM_FH1_SW_CBC_V 0x1 +#define MCPWM_FH1_SW_CBC_S 0 + +#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00a4) +/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) triggers a + one-shot mode action*/ +#define MCPWM_FH1_FORCE_OST (BIT(4)) +#define MCPWM_FH1_FORCE_OST_M (BIT(4)) +#define MCPWM_FH1_FORCE_OST_V 0x1 +#define MCPWM_FH1_FORCE_OST_S 4 +/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle triggers a cycle-by-cycle mode action*/ +#define MCPWM_FH1_FORCE_CBC (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_M (BIT(3)) +#define MCPWM_FH1_FORCE_CBC_V 0x1 +#define MCPWM_FH1_FORCE_CBC_S 3 +/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ +#define MCPWM_FH1_CBCPULSE 0x00000003 +#define MCPWM_FH1_CBCPULSE_M ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S)) +#define MCPWM_FH1_CBCPULSE_V 0x3 +#define MCPWM_FH1_CBCPULSE_S 1 +/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: A toggle will clear on going one-shot mode action*/ +#define MCPWM_FH1_CLR_OST (BIT(0)) +#define MCPWM_FH1_CLR_OST_M (BIT(0)) +#define MCPWM_FH1_CLR_OST_V 0x1 +#define MCPWM_FH1_CLR_OST_S 0 + +#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00a8) +/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ +#define MCPWM_FH1_OST_ON (BIT(1)) +#define MCPWM_FH1_OST_ON_M (BIT(1)) +#define MCPWM_FH1_OST_ON_V 0x1 +#define MCPWM_FH1_OST_ON_S 1 +/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ +#define MCPWM_FH1_CBC_ON (BIT(0)) +#define MCPWM_FH1_CBC_ON_M (BIT(0)) +#define MCPWM_FH1_CBC_ON_V 0x1 +#define MCPWM_FH1_CBC_ON_S 0 + +#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00ac) +/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 2 time stamp + B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN2_B_SHDW_FULL (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_GEN2_B_SHDW_FULL_V 0x1 +#define MCPWM_GEN2_B_SHDW_FULL_S 9 +/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set PWM generator 2 time stamp + A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ +#define MCPWM_GEN2_A_SHDW_FULL (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_GEN2_A_SHDW_FULL_V 0x1 +#define MCPWM_GEN2_A_SHDW_FULL_S 8 +/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 2 time stamp B's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN2_B_UPMETHOD 0x0000000F +#define MCPWM_GEN2_B_UPMETHOD_M ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S)) +#define MCPWM_GEN2_B_UPMETHOD_V 0xF +#define MCPWM_GEN2_B_UPMETHOD_S 4 +/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generator 2 time stamp A's active reg. + 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_GEN2_A_UPMETHOD 0x0000000F +#define MCPWM_GEN2_A_UPMETHOD_M ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S)) +#define MCPWM_GEN2_A_UPMETHOD_V 0xF +#define MCPWM_GEN2_A_UPMETHOD_S 0 + +#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x00b0) +/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 2 time stamp A's shadow reg*/ +#define MCPWM_GEN2_A 0x0000FFFF +#define MCPWM_GEN2_A_M ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S)) +#define MCPWM_GEN2_A_V 0xFFFF +#define MCPWM_GEN2_A_S 0 + +#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x00b4) +/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: PWM generator 2 time stamp B's shadow reg*/ +#define MCPWM_GEN2_B 0x0000FFFF +#define MCPWM_GEN2_B_M ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S)) +#define MCPWM_GEN2_B_V 0xFFFF +#define MCPWM_GEN2_B_S 0 + +#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00b8) +/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate2 event_t1 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN2_T1_SEL 0x00000007 +#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S)) +#define MCPWM_GEN2_T1_SEL_V 0x7 +#define MCPWM_GEN2_T1_SEL_S 7 +/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: Source selection for PWM generate2 event_t0 take effect immediately + 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ +#define MCPWM_GEN2_T0_SEL 0x00000007 +#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S)) +#define MCPWM_GEN2_T0_SEL_V 0x7 +#define MCPWM_GEN2_T0_SEL_S 4 +/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for PWM generate2's active reg of configuration. + 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: disable update*/ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S)) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x00bc) +/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM2B 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM2B a + toggle will trigger a force event*/ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_V 0x1 +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: Non-continuous immediate software force mode for PWM2A 0: disabled + 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Non-continuous immediate software force trigger for PWM2A a + toggle will trigger a force event*/ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_V 0x1 +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM2B. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Continuous software force mode for PWM2A. 0: disabled 1: low + 2: high 3: disabled*/ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: Update method for continuous software force of PWM generator2. + 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0x00c0) +/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN2_A_DT1 0x00000003 +#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S)) +#define MCPWM_GEN2_A_DT1_V 0x3 +#define MCPWM_GEN2_A_DT1_S 22 +/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN2_A_DT0 0x00000003 +#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S)) +#define MCPWM_GEN2_A_DT0_V 0x3 +#define MCPWM_GEN2_A_DT0_S 20 +/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN2_A_DTEB 0x00000003 +#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S)) +#define MCPWM_GEN2_A_DTEB_V 0x3 +#define MCPWM_GEN2_A_DTEB_S 18 +/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN2_A_DTEA 0x00000003 +#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S)) +#define MCPWM_GEN2_A_DTEA_V 0x3 +#define MCPWM_GEN2_A_DTEA_S 16 +/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN2_A_DTEP 0x00000003 +#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S)) +#define MCPWM_GEN2_A_DTEP_V 0x3 +#define MCPWM_GEN2_A_DTEP_S 14 +/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN2_A_DTEZ 0x00000003 +#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S)) +#define MCPWM_GEN2_A_DTEZ_V 0x3 +#define MCPWM_GEN2_A_DTEZ_S 12 +/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN2_A_UT1 0x00000003 +#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S)) +#define MCPWM_GEN2_A_UT1_V 0x3 +#define MCPWM_GEN2_A_UT1_S 10 +/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN2_A_UT0 0x00000003 +#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S)) +#define MCPWM_GEN2_A_UT0_V 0x3 +#define MCPWM_GEN2_A_UT0_S 8 +/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEB when timer increasing*/ +#define MCPWM_GEN2_A_UTEB 0x00000003 +#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S)) +#define MCPWM_GEN2_A_UTEB_V 0x3 +#define MCPWM_GEN2_A_UTEB_S 6 +/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEA when timer increasing*/ +#define MCPWM_GEN2_A_UTEA 0x00000003 +#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S)) +#define MCPWM_GEN2_A_UTEA_V 0x3 +#define MCPWM_GEN2_A_UTEA_S 4 +/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEP when timer increasing*/ +#define MCPWM_GEN2_A_UTEP 0x00000003 +#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S)) +#define MCPWM_GEN2_A_UTEP_V 0x3 +#define MCPWM_GEN2_A_UTEP_S 2 +/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM2A triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN2_A_UTEZ 0x00000003 +#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S)) +#define MCPWM_GEN2_A_UTEZ_V 0x3 +#define MCPWM_GEN2_A_UTEZ_S 0 + +#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0x00c4) +/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t1 when timer decreasing. + 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN2_B_DT1 0x00000003 +#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S)) +#define MCPWM_GEN2_B_DT1_V 0x3 +#define MCPWM_GEN2_B_DT1_S 22 +/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/ +#define MCPWM_GEN2_B_DT0 0x00000003 +#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S)) +#define MCPWM_GEN2_B_DT0_V 0x3 +#define MCPWM_GEN2_B_DT0_S 20 +/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEB when timer decreasing*/ +#define MCPWM_GEN2_B_DTEB 0x00000003 +#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S)) +#define MCPWM_GEN2_B_DTEB_V 0x3 +#define MCPWM_GEN2_B_DTEB_S 18 +/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEA when timer decreasing*/ +#define MCPWM_GEN2_B_DTEA 0x00000003 +#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S)) +#define MCPWM_GEN2_B_DTEA_V 0x3 +#define MCPWM_GEN2_B_DTEA_S 16 +/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEP when timer decreasing*/ +#define MCPWM_GEN2_B_DTEP 0x00000003 +#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S)) +#define MCPWM_GEN2_B_DTEP_V 0x3 +#define MCPWM_GEN2_B_DTEP_S 14 +/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/ +#define MCPWM_GEN2_B_DTEZ 0x00000003 +#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S)) +#define MCPWM_GEN2_B_DTEZ_V 0x3 +#define MCPWM_GEN2_B_DTEZ_S 12 +/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t1 when timer increasing*/ +#define MCPWM_GEN2_B_UT1 0x00000003 +#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S)) +#define MCPWM_GEN2_B_UT1_V 0x3 +#define MCPWM_GEN2_B_UT1_S 10 +/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event_t0 when timer increasing*/ +#define MCPWM_GEN2_B_UT0 0x00000003 +#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S)) +#define MCPWM_GEN2_B_UT0_V 0x3 +#define MCPWM_GEN2_B_UT0_S 8 +/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEB when timer increasing*/ +#define MCPWM_GEN2_B_UTEB 0x00000003 +#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S)) +#define MCPWM_GEN2_B_UTEB_V 0x3 +#define MCPWM_GEN2_B_UTEB_S 6 +/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEA when timer increasing*/ +#define MCPWM_GEN2_B_UTEA 0x00000003 +#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S)) +#define MCPWM_GEN2_B_UTEA_V 0x3 +#define MCPWM_GEN2_B_UTEA_S 4 +/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEP when timer increasing*/ +#define MCPWM_GEN2_B_UTEP 0x00000003 +#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S)) +#define MCPWM_GEN2_B_UTEP_V 0x3 +#define MCPWM_GEN2_B_UTEP_S 2 +/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: Action on PWM2B triggered by event TEZ when timer increasing*/ +#define MCPWM_GEN2_B_UTEZ 0x00000003 +#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S)) +#define MCPWM_GEN2_B_UTEZ_V 0x3 +#define MCPWM_GEN2_B_UTEZ_S 0 + +#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00c8) +/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Dead time generator 1 clock selection. 0: PWM_clk 1: PT_clk*/ +#define MCPWM_DT2_CLK_SEL (BIT(17)) +#define MCPWM_DT2_CLK_SEL_M (BIT(17)) +#define MCPWM_DT2_CLK_SEL_V 0x1 +#define MCPWM_DT2_CLK_SEL_S 17 +/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: S0 in documentation*/ +#define MCPWM_DT2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DT2_B_OUTBYPASS_V 0x1 +#define MCPWM_DT2_B_OUTBYPASS_S 16 +/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: S1 in documentation*/ +#define MCPWM_DT2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DT2_A_OUTBYPASS_V 0x1 +#define MCPWM_DT2_A_OUTBYPASS_S 15 +/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: S3 in documentation*/ +#define MCPWM_DT2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DT2_FED_OUTINVERT_V 0x1 +#define MCPWM_DT2_FED_OUTINVERT_S 14 +/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: S2 in documentation*/ +#define MCPWM_DT2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DT2_RED_OUTINVERT_V 0x1 +#define MCPWM_DT2_RED_OUTINVERT_S 13 +/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: S5 in documentation*/ +#define MCPWM_DT2_FED_INSEL (BIT(12)) +#define MCPWM_DT2_FED_INSEL_M (BIT(12)) +#define MCPWM_DT2_FED_INSEL_V 0x1 +#define MCPWM_DT2_FED_INSEL_S 12 +/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: S4 in documentation*/ +#define MCPWM_DT2_RED_INSEL (BIT(11)) +#define MCPWM_DT2_RED_INSEL_M (BIT(11)) +#define MCPWM_DT2_RED_INSEL_V 0x1 +#define MCPWM_DT2_RED_INSEL_S 11 +/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: S7 in documentation*/ +#define MCPWM_DT2_B_OUTSWAP (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DT2_B_OUTSWAP_V 0x1 +#define MCPWM_DT2_B_OUTSWAP_S 10 +/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: S6 in documentation*/ +#define MCPWM_DT2_A_OUTSWAP (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DT2_A_OUTSWAP_V 0x1 +#define MCPWM_DT2_A_OUTSWAP_S 9 +/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: S8 in documentation dual-edge B mode 0: FED/RED take effect + on different path separately 1: FED/RED take effect on B path A out is in bypass or normal operation mode*/ +#define MCPWM_DT2_DEB_MODE (BIT(8)) +#define MCPWM_DT2_DEB_MODE_M (BIT(8)) +#define MCPWM_DT2_DEB_MODE_V 0x1 +#define MCPWM_DT2_DEB_MODE_S 8 +/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: Update method for RED (rising edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT2_RED_UPMETHOD 0x0000000F +#define MCPWM_DT2_RED_UPMETHOD_M ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S)) +#define MCPWM_DT2_RED_UPMETHOD_V 0xF +#define MCPWM_DT2_RED_UPMETHOD_S 4 +/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: Update method for FED (falling edge delay) active reg. 0: immediate + bit0: TEZ bit1: TEP bit2: sync bit3: disable update*/ +#define MCPWM_DT2_FED_UPMETHOD 0x0000000F +#define MCPWM_DT2_FED_UPMETHOD_M ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S)) +#define MCPWM_DT2_FED_UPMETHOD_V 0xF +#define MCPWM_DT2_FED_UPMETHOD_S 0 + +#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00cc) +/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for FED*/ +#define MCPWM_DT2_FED 0x0000FFFF +#define MCPWM_DT2_FED_M ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S)) +#define MCPWM_DT2_FED_V 0xFFFF +#define MCPWM_DT2_FED_S 0 + +#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d0) +/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: Shadow reg for RED*/ +#define MCPWM_DT2_RED 0x0000FFFF +#define MCPWM_DT2_RED_M ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S)) +#define MCPWM_DT2_RED_V 0xFFFF +#define MCPWM_DT2_RED_S 0 + +#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d4) +/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: When set invert the input of PWM2A and PWM2B for this submodule*/ +#define MCPWM_CARRIER2_IN_INVERT (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_M (BIT(13)) +#define MCPWM_CARRIER2_IN_INVERT_V 0x1 +#define MCPWM_CARRIER2_IN_INVERT_S 13 +/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: When set invert the output of PWM2A and PWM2B for this submodule*/ +#define MCPWM_CARRIER2_OUT_INVERT (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_M (BIT(12)) +#define MCPWM_CARRIER2_OUT_INVERT_V 0x1 +#define MCPWM_CARRIER2_OUT_INVERT_S 12 +/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: Width of the fist pulse in number of periods of the carrier*/ +#define MCPWM_CARRIER2_OSHWTH 0x0000000F +#define MCPWM_CARRIER2_OSHWTH_M ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S)) +#define MCPWM_CARRIER2_OSHWTH_V 0xF +#define MCPWM_CARRIER2_OSHWTH_S 8 +/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/ +#define MCPWM_CARRIER2_DUTY 0x00000007 +#define MCPWM_CARRIER2_DUTY_M ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S)) +#define MCPWM_CARRIER2_DUTY_V 0x7 +#define MCPWM_CARRIER2_DUTY_S 5 +/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk + = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/ +#define MCPWM_CARRIER2_PRESCALE 0x0000000F +#define MCPWM_CARRIER2_PRESCALE_M ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S)) +#define MCPWM_CARRIER2_PRESCALE_V 0xF +#define MCPWM_CARRIER2_PRESCALE_S 1 +/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set carrier2 function is enabled. When cleared carrier2 is bypassed*/ +#define MCPWM_CARRIER2_EN (BIT(0)) +#define MCPWM_CARRIER2_EN_M (BIT(0)) +#define MCPWM_CARRIER2_EN_V 0x1 +#define MCPWM_CARRIER2_EN_S 0 + +#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00d8) +/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2B when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_OST_U 0x00000003 +#define MCPWM_FH2_B_OST_U_M ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S)) +#define MCPWM_FH2_B_OST_U_V 0x3 +#define MCPWM_FH2_B_OST_U_S 22 +/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2B when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_OST_D 0x00000003 +#define MCPWM_FH2_B_OST_D_M ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S)) +#define MCPWM_FH2_B_OST_D_V 0x3 +#define MCPWM_FH2_B_OST_D_S 20 +/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_CBC_U 0x00000003 +#define MCPWM_FH2_B_CBC_U_M ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S)) +#define MCPWM_FH2_B_CBC_U_V 0x3 +#define MCPWM_FH2_B_CBC_U_S 18 +/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_B_CBC_D 0x00000003 +#define MCPWM_FH2_B_CBC_D_M ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S)) +#define MCPWM_FH2_B_CBC_D_V 0x3 +#define MCPWM_FH2_B_CBC_D_S 16 +/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2A when fault event occurs and timer + is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_OST_U 0x00000003 +#define MCPWM_FH2_A_OST_U_M ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S)) +#define MCPWM_FH2_A_OST_U_V 0x3 +#define MCPWM_FH2_A_OST_U_S 14 +/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: One-shot mode action on PWM2A when fault event occurs and timer + is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_OST_D 0x00000003 +#define MCPWM_FH2_A_OST_D_M ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S)) +#define MCPWM_FH2_A_OST_D_V 0x3 +#define MCPWM_FH2_A_OST_D_S 12 +/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and + timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_CBC_U 0x00000003 +#define MCPWM_FH2_A_CBC_U_M ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S)) +#define MCPWM_FH2_A_CBC_U_V 0x3 +#define MCPWM_FH2_A_CBC_U_S 10 +/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and + timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_FH2_A_CBC_D 0x00000003 +#define MCPWM_FH2_A_CBC_D_M ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S)) +#define MCPWM_FH2_A_CBC_D_V 0x3 +#define MCPWM_FH2_A_CBC_D_S 8 +/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: event_f0 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F0_OST (BIT(7)) +#define MCPWM_FH2_F0_OST_M (BIT(7)) +#define MCPWM_FH2_F0_OST_V 0x1 +#define MCPWM_FH2_F0_OST_S 7 +/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: event_f1 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F1_OST (BIT(6)) +#define MCPWM_FH2_F1_OST_M (BIT(6)) +#define MCPWM_FH2_F1_OST_V 0x1 +#define MCPWM_FH2_F1_OST_S 6 +/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: event_f2 will trigger one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F2_OST (BIT(5)) +#define MCPWM_FH2_F2_OST_M (BIT(5)) +#define MCPWM_FH2_F2_OST_V 0x1 +#define MCPWM_FH2_F2_OST_S 5 +/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Enable register for software force one-shot mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_SW_OST (BIT(4)) +#define MCPWM_FH2_SW_OST_M (BIT(4)) +#define MCPWM_FH2_SW_OST_V 0x1 +#define MCPWM_FH2_SW_OST_S 4 +/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F0_CBC (BIT(3)) +#define MCPWM_FH2_F0_CBC_M (BIT(3)) +#define MCPWM_FH2_F0_CBC_V 0x1 +#define MCPWM_FH2_F0_CBC_S 3 +/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F1_CBC (BIT(2)) +#define MCPWM_FH2_F1_CBC_M (BIT(2)) +#define MCPWM_FH2_F1_CBC_V 0x1 +#define MCPWM_FH2_F1_CBC_S 2 +/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable 1: enable*/ +#define MCPWM_FH2_F2_CBC (BIT(1)) +#define MCPWM_FH2_F2_CBC_M (BIT(1)) +#define MCPWM_FH2_F2_CBC_V 0x1 +#define MCPWM_FH2_F2_CBC_S 1 +/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Enable register for software force cycle-by-cycle mode action. + 0: disable 1: enable*/ +#define MCPWM_FH2_SW_CBC (BIT(0)) +#define MCPWM_FH2_SW_CBC_M (BIT(0)) +#define MCPWM_FH2_SW_CBC_V 0x1 +#define MCPWM_FH2_SW_CBC_S 0 + +#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00dc) +/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) triggers a + one-shot mode action*/ +#define MCPWM_FH2_FORCE_OST (BIT(4)) +#define MCPWM_FH2_FORCE_OST_M (BIT(4)) +#define MCPWM_FH2_FORCE_OST_V 0x1 +#define MCPWM_FH2_FORCE_OST_S 4 +/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle triggers a cycle-by-cycle mode action*/ +#define MCPWM_FH2_FORCE_CBC (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_M (BIT(3)) +#define MCPWM_FH2_FORCE_CBC_V 0x1 +#define MCPWM_FH2_FORCE_CBC_S 3 +/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ bit1:TEP*/ +#define MCPWM_FH2_CBCPULSE 0x00000003 +#define MCPWM_FH2_CBCPULSE_M ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S)) +#define MCPWM_FH2_CBCPULSE_V 0x3 +#define MCPWM_FH2_CBCPULSE_S 1 +/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: A toggle will clear on going one-shot mode action*/ +#define MCPWM_FH2_CLR_OST (BIT(0)) +#define MCPWM_FH2_CLR_OST_M (BIT(0)) +#define MCPWM_FH2_CLR_OST_V 0x1 +#define MCPWM_FH2_CLR_OST_S 0 + +#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00e0) +/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an one-shot mode action is on going*/ +#define MCPWM_FH2_OST_ON (BIT(1)) +#define MCPWM_FH2_OST_ON_M (BIT(1)) +#define MCPWM_FH2_OST_ON_V 0x1 +#define MCPWM_FH2_OST_ON_S 1 +/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set an cycle-by-cycle mode action is on going*/ +#define MCPWM_FH2_CBC_ON (BIT(0)) +#define MCPWM_FH2_CBC_ON_M (BIT(0)) +#define MCPWM_FH2_CBC_ON_V 0x1 +#define MCPWM_FH2_CBC_ON_S 0 + +#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0x00e4) +/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set event_f2 is on going*/ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (BIT(8)) +#define MCPWM_EVENT_F2_V 0x1 +#define MCPWM_EVENT_F2_S 8 +/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set event_f1 is on going*/ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (BIT(7)) +#define MCPWM_EVENT_F1_V 0x1 +#define MCPWM_EVENT_F1_S 7 +/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ +/*description: Set and reset by hardware. If set event_f0 is on going*/ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (BIT(6)) +#define MCPWM_EVENT_F0_V 0x1 +#define MCPWM_EVENT_F0_S 6 +/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. + 0: level low 1: level high*/ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (BIT(5)) +#define MCPWM_F2_POLE_V 0x1 +#define MCPWM_F2_POLE_S 5 +/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. + 0: level low 1: level high*/ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (BIT(4)) +#define MCPWM_F1_POLE_V 0x1 +#define MCPWM_F1_POLE_S 4 +/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. + 0: level low 1: level high*/ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (BIT(3)) +#define MCPWM_F0_POLE_V 0x1 +#define MCPWM_F0_POLE_S 3 +/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: Set to enable generation of event_f2*/ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (BIT(2)) +#define MCPWM_F2_EN_V 0x1 +#define MCPWM_F2_EN_S 2 +/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Set to enable generation of event_f1*/ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (BIT(1)) +#define MCPWM_F1_EN_V 0x1 +#define MCPWM_F1_EN_S 1 +/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Set to enable generation of event_f0*/ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (BIT(0)) +#define MCPWM_F0_EN_V 0x1 +#define MCPWM_F0_EN_S 0 + +#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00e8) +/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ +/*description: Set this bit to force a capture timer sync capture timer is + loaded with value in phase register.*/ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (BIT(5)) +#define MCPWM_CAP_SYNC_SW_V 0x1 +#define MCPWM_CAP_SYNC_SW_S 5 +/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: Capture module sync input selection. 0: none 1: timer0 synco + 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ +#define MCPWM_CAP_SYNCI_SEL 0x00000007 +#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S)) +#define MCPWM_CAP_SYNCI_SEL_V 0x7 +#define MCPWM_CAP_SYNCI_SEL_S 2 +/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: When set capture timer sync is enabled.*/ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_V 0x1 +#define MCPWM_CAP_SYNCI_EN_S 1 +/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture timer incrementing under APB_clk is enabled.*/ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (BIT(0)) +#define MCPWM_CAP_TIMER_EN_V 0x1 +#define MCPWM_CAP_TIMER_EN_S 0 + +#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0x00ec) +/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Phase value for capture timer sync operation.*/ +#define MCPWM_CAP_PHASE 0xFFFFFFFF +#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S)) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFF +#define MCPWM_CAP_PHASE_S 0 + +#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f0) +/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a software forced capture on channel 0*/ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (BIT(12)) +#define MCPWM_CAP0_SW_V 0x1 +#define MCPWM_CAP0_SW_S 12 +/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: When set CAP0 form GPIO matrix is inverted before prescale*/ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_V 0x1 +#define MCPWM_CAP0_IN_INVERT_S 11 +/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: Value of prescale on possitive edge of CAP0. Prescale value = + PWM_CAP0_PRESCALE + 1*/ +#define MCPWM_CAP0_PRESCALE 0x000000FF +#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S)) +#define MCPWM_CAP0_PRESCALE_V 0xFF +#define MCPWM_CAP0_PRESCALE_S 3 +/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: Edge of capture on channel 0 after prescale. bit0: negedge cap + en bit1: posedge cap en*/ +#define MCPWM_CAP0_MODE 0x00000003 +#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S)) +#define MCPWM_CAP0_MODE_V 0x3 +#define MCPWM_CAP0_MODE_S 1 +/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture on channel 0 is enabled*/ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (BIT(0)) +#define MCPWM_CAP0_EN_V 0x1 +#define MCPWM_CAP0_EN_S 0 + +#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f4) +/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a software forced capture on channel 1*/ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (BIT(12)) +#define MCPWM_CAP1_SW_V 0x1 +#define MCPWM_CAP1_SW_S 12 +/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: When set CAP1 form GPIO matrix is inverted before prescale*/ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_V 0x1 +#define MCPWM_CAP1_IN_INVERT_S 11 +/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: Value of prescale on possitive edge of CAP1. Prescale value = + PWM_CAP1_PRESCALE + 1*/ +#define MCPWM_CAP1_PRESCALE 0x000000FF +#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S)) +#define MCPWM_CAP1_PRESCALE_V 0xFF +#define MCPWM_CAP1_PRESCALE_S 3 +/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: Edge of capture on channel 1 after prescale. bit0: negedge cap + en bit1: posedge cap en*/ +#define MCPWM_CAP1_MODE 0x00000003 +#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S)) +#define MCPWM_CAP1_MODE_V 0x3 +#define MCPWM_CAP1_MODE_S 1 +/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture on channel 1 is enabled*/ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (BIT(0)) +#define MCPWM_CAP1_EN_V 0x1 +#define MCPWM_CAP1_EN_S 0 + +#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f8) +/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a software forced capture on channel 2*/ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (BIT(12)) +#define MCPWM_CAP2_SW_V 0x1 +#define MCPWM_CAP2_SW_S 12 +/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: When set CAP2 form GPIO matrix is inverted before prescale*/ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_V 0x1 +#define MCPWM_CAP2_IN_INVERT_S 11 +/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: Value of prescale on possitive edge of CAP2. Prescale value = + PWM_CAP2_PRESCALE + 1*/ +#define MCPWM_CAP2_PRESCALE 0x000000FF +#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S)) +#define MCPWM_CAP2_PRESCALE_V 0xFF +#define MCPWM_CAP2_PRESCALE_S 3 +/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: Edge of capture on channel 2 after prescale. bit0: negedge cap + en bit1: posedge cap en*/ +#define MCPWM_CAP2_MODE 0x00000003 +#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S)) +#define MCPWM_CAP2_MODE_V 0x3 +#define MCPWM_CAP2_MODE_S 1 +/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: When set capture on channel 2 is enabled*/ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (BIT(0)) +#define MCPWM_CAP2_EN_V 0x1 +#define MCPWM_CAP2_EN_S 0 + +#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0x00fc) +/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Value of last capture on channel 0*/ +#define MCPWM_CAP0_VALUE 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S)) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_S 0 + +#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x0100) +/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Value of last capture on channel 1*/ +#define MCPWM_CAP1_VALUE 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S)) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_S 0 + +#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x0104) +/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: Value of last capture on channel 2*/ +#define MCPWM_CAP2_VALUE 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S)) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_S 0 + +#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0108) +/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ +/*description: Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (BIT(2)) +#define MCPWM_CAP2_EDGE_V 0x1 +#define MCPWM_CAP2_EDGE_S 2 +/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (BIT(1)) +#define MCPWM_CAP1_EDGE_V 0x1 +#define MCPWM_CAP1_EDGE_S 1 +/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (BIT(0)) +#define MCPWM_CAP0_EDGE_V 0x1 +#define MCPWM_CAP0_EDGE_S 0 + +#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x010c) +/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of active registers in PWM operator 2*/ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (BIT(7)) +#define MCPWM_OP2_FORCE_UP_V 0x1 +#define MCPWM_OP2_FORCE_UP_S 7 +/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers + in PWM operator 2 are enabled*/ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (BIT(6)) +#define MCPWM_OP2_UP_EN_V 0x1 +#define MCPWM_OP2_UP_EN_S 6 +/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of active registers in PWM operator 1*/ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (BIT(5)) +#define MCPWM_OP1_FORCE_UP_V 0x1 +#define MCPWM_OP1_FORCE_UP_S 5 +/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ +/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers + in PWM operator 1 are enabled*/ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (BIT(4)) +#define MCPWM_OP1_UP_EN_V 0x1 +#define MCPWM_OP1_UP_EN_S 4 +/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of active registers in PWM operator 0*/ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (BIT(3)) +#define MCPWM_OP0_FORCE_UP_V 0x1 +#define MCPWM_OP0_FORCE_UP_S 3 +/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ +/*description: When set and PWM_GLOBAL_UP_EN is set update of active registers + in PWM operator 0 are enabled*/ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (BIT(2)) +#define MCPWM_OP0_UP_EN_V 0x1 +#define MCPWM_OP0_UP_EN_S 2 +/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: A toggle (software negation of value of this bit) will trigger + a forced update of all active registers in MCPWM module*/ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_V 0x1 +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: The global enable of update of all active registers in MCPWM module*/ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_V 0x1 +#define MCPWM_GLOBAL_UP_EN_S 0 + +#define MCMCPWM_INT_ENA_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0110) +/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (BIT(29)) +#define MCPWM_CAP2_INT_ENA_V 0x1 +#define MCPWM_CAP2_INT_ENA_S 29 +/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (BIT(28)) +#define MCPWM_CAP1_INT_ENA_V 0x1 +#define MCPWM_CAP1_INT_ENA_S 28 +/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (BIT(27)) +#define MCPWM_CAP0_INT_ENA_V 0x1 +#define MCPWM_CAP0_INT_ENA_S 27 +/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_ENA (BIT(26)) +#define MCPWM_FH2_OST_INT_ENA_M (BIT(26)) +#define MCPWM_FH2_OST_INT_ENA_V 0x1 +#define MCPWM_FH2_OST_INT_ENA_S 26 +/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_ENA (BIT(25)) +#define MCPWM_FH1_OST_INT_ENA_M (BIT(25)) +#define MCPWM_FH1_OST_INT_ENA_V 0x1 +#define MCPWM_FH1_OST_INT_ENA_S 25 +/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_ENA (BIT(24)) +#define MCPWM_FH0_OST_INT_ENA_M (BIT(24)) +#define MCPWM_FH0_OST_INT_ENA_V 0x1 +#define MCPWM_FH0_OST_INT_ENA_S 24 +/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_ENA (BIT(23)) +#define MCPWM_FH2_CBC_INT_ENA_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_ENA_V 0x1 +#define MCPWM_FH2_CBC_INT_ENA_S 23 +/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_ENA (BIT(22)) +#define MCPWM_FH1_CBC_INT_ENA_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_ENA_V 0x1 +#define MCPWM_FH1_CBC_INT_ENA_S 22 +/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_ENA (BIT(21)) +#define MCPWM_FH0_CBC_INT_ENA_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_ENA_V 0x1 +#define MCPWM_FH0_CBC_INT_ENA_S 21 +/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_ENA (BIT(20)) +#define MCPWM_OP2_TEB_INT_ENA_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_ENA_V 0x1 +#define MCPWM_OP2_TEB_INT_ENA_S 20 +/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_ENA (BIT(19)) +#define MCPWM_OP1_TEB_INT_ENA_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_ENA_V 0x1 +#define MCPWM_OP1_TEB_INT_ENA_S 19 +/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_ENA (BIT(18)) +#define MCPWM_OP0_TEB_INT_ENA_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_ENA_V 0x1 +#define MCPWM_OP0_TEB_INT_ENA_S 18 +/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_ENA (BIT(17)) +#define MCPWM_OP2_TEA_INT_ENA_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_ENA_V 0x1 +#define MCPWM_OP2_TEA_INT_ENA_S 17 +/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_ENA (BIT(16)) +#define MCPWM_OP1_TEA_INT_ENA_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_ENA_V 0x1 +#define MCPWM_OP1_TEA_INT_ENA_S 16 +/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_ENA (BIT(15)) +#define MCPWM_OP0_TEA_INT_ENA_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_ENA_V 0x1 +#define MCPWM_OP0_TEA_INT_ENA_S 15 +/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_V 0x1 +#define MCPWM_FAULT2_INT_ENA_S 11 +/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_V 0x1 +#define MCPWM_FAULT1_INT_ENA_S 10 +/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: The enable bit for interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_V 0x1 +#define MCPWM_FAULT0_INT_ENA_S 9 +/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The enable bit for interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 + +#define MCMCPWM_INT_RAW_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0114) +/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (BIT(29)) +#define MCPWM_CAP2_INT_RAW_V 0x1 +#define MCPWM_CAP2_INT_RAW_S 29 +/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (BIT(28)) +#define MCPWM_CAP1_INT_RAW_V 0x1 +#define MCPWM_CAP1_INT_RAW_S 28 +/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (BIT(27)) +#define MCPWM_CAP0_INT_RAW_V 0x1 +#define MCPWM_CAP0_INT_RAW_S 27 +/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_RAW (BIT(26)) +#define MCPWM_FH2_OST_INT_RAW_M (BIT(26)) +#define MCPWM_FH2_OST_INT_RAW_V 0x1 +#define MCPWM_FH2_OST_INT_RAW_S 26 +/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_RAW (BIT(25)) +#define MCPWM_FH1_OST_INT_RAW_M (BIT(25)) +#define MCPWM_FH1_OST_INT_RAW_V 0x1 +#define MCPWM_FH1_OST_INT_RAW_S 25 +/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_RAW (BIT(24)) +#define MCPWM_FH0_OST_INT_RAW_M (BIT(24)) +#define MCPWM_FH0_OST_INT_RAW_V 0x1 +#define MCPWM_FH0_OST_INT_RAW_S 24 +/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_RAW (BIT(23)) +#define MCPWM_FH2_CBC_INT_RAW_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_RAW_V 0x1 +#define MCPWM_FH2_CBC_INT_RAW_S 23 +/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_RAW (BIT(22)) +#define MCPWM_FH1_CBC_INT_RAW_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_RAW_V 0x1 +#define MCPWM_FH1_CBC_INT_RAW_S 22 +/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_RAW (BIT(21)) +#define MCPWM_FH0_CBC_INT_RAW_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_RAW_V 0x1 +#define MCPWM_FH0_CBC_INT_RAW_S 21 +/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_RAW (BIT(20)) +#define MCPWM_OP2_TEB_INT_RAW_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_RAW_V 0x1 +#define MCPWM_OP2_TEB_INT_RAW_S 20 +/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_RAW (BIT(19)) +#define MCPWM_OP1_TEB_INT_RAW_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_RAW_V 0x1 +#define MCPWM_OP1_TEB_INT_RAW_S 19 +/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_RAW (BIT(18)) +#define MCPWM_OP0_TEB_INT_RAW_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_RAW_V 0x1 +#define MCPWM_OP0_TEB_INT_RAW_S 18 +/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_RAW (BIT(17)) +#define MCPWM_OP2_TEA_INT_RAW_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_RAW_V 0x1 +#define MCPWM_OP2_TEA_INT_RAW_S 17 +/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_RAW (BIT(16)) +#define MCPWM_OP1_TEA_INT_RAW_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_RAW_V 0x1 +#define MCPWM_OP1_TEA_INT_RAW_S 16 +/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_RAW (BIT(15)) +#define MCPWM_OP0_TEA_INT_RAW_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_RAW_V 0x1 +#define MCPWM_OP0_TEA_INT_RAW_S 15 +/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_V 0x1 +#define MCPWM_FAULT2_INT_RAW_S 11 +/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_V 0x1 +#define MCPWM_FAULT1_INT_RAW_S 10 +/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: The raw status bit for interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_V 0x1 +#define MCPWM_FAULT0_INT_RAW_S 9 +/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The raw status bit for interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 + +#define MCMCPWM_INT_ST_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0118) +/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (BIT(29)) +#define MCPWM_CAP2_INT_ST_V 0x1 +#define MCPWM_CAP2_INT_ST_S 29 +/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (BIT(28)) +#define MCPWM_CAP1_INT_ST_V 0x1 +#define MCPWM_CAP1_INT_ST_S 28 +/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (BIT(27)) +#define MCPWM_CAP0_INT_ST_V 0x1 +#define MCPWM_CAP0_INT_ST_S 27 +/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_ST (BIT(26)) +#define MCPWM_FH2_OST_INT_ST_M (BIT(26)) +#define MCPWM_FH2_OST_INT_ST_V 0x1 +#define MCPWM_FH2_OST_INT_ST_S 26 +/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_ST (BIT(25)) +#define MCPWM_FH1_OST_INT_ST_M (BIT(25)) +#define MCPWM_FH1_OST_INT_ST_V 0x1 +#define MCPWM_FH1_OST_INT_ST_S 25 +/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_ST (BIT(24)) +#define MCPWM_FH0_OST_INT_ST_M (BIT(24)) +#define MCPWM_FH0_OST_INT_ST_V 0x1 +#define MCPWM_FH0_OST_INT_ST_S 24 +/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_ST (BIT(23)) +#define MCPWM_FH2_CBC_INT_ST_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_ST_V 0x1 +#define MCPWM_FH2_CBC_INT_ST_S 23 +/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_ST (BIT(22)) +#define MCPWM_FH1_CBC_INT_ST_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_ST_V 0x1 +#define MCPWM_FH1_CBC_INT_ST_S 22 +/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by an cycle-by-cycle + mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_ST (BIT(21)) +#define MCPWM_FH0_CBC_INT_ST_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_ST_V 0x1 +#define MCPWM_FH0_CBC_INT_ST_S 21 +/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_ST (BIT(20)) +#define MCPWM_OP2_TEB_INT_ST_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_ST_V 0x1 +#define MCPWM_OP2_TEB_INT_ST_S 20 +/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_ST (BIT(19)) +#define MCPWM_OP1_TEB_INT_ST_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_ST_V 0x1 +#define MCPWM_OP1_TEB_INT_ST_S 19 +/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_ST (BIT(18)) +#define MCPWM_OP0_TEB_INT_ST_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_ST_V 0x1 +#define MCPWM_OP0_TEB_INT_ST_S 18 +/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_ST (BIT(17)) +#define MCPWM_OP2_TEA_INT_ST_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_ST_V 0x1 +#define MCPWM_OP2_TEA_INT_ST_S 17 +/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_ST (BIT(16)) +#define MCPWM_OP1_TEA_INT_ST_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_ST_V 0x1 +#define MCPWM_OP1_TEA_INT_ST_S 16 +/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_ST (BIT(15)) +#define MCPWM_OP0_TEA_INT_ST_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_ST_V 0x1 +#define MCPWM_OP0_TEA_INT_ST_S 15 +/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (BIT(11)) +#define MCPWM_FAULT2_INT_ST_V 0x1 +#define MCPWM_FAULT2_INT_ST_S 11 +/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (BIT(10)) +#define MCPWM_FAULT1_INT_ST_V 0x1 +#define MCPWM_FAULT1_INT_ST_S 10 +/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: The masked status bit for interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (BIT(9)) +#define MCPWM_FAULT0_INT_ST_V 0x1 +#define MCPWM_FAULT0_INT_ST_S 9 +/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The masked status bit for interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ST_S 0 + +#define MCMCPWM_INT_CLR_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x011c) +/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by captureon channel 2*/ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (BIT(29)) +#define MCPWM_CAP2_INT_CLR_V 0x1 +#define MCPWM_CAP2_INT_CLR_S 29 +/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by captureon channel 1*/ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (BIT(28)) +#define MCPWM_CAP1_INT_CLR_V 0x1 +#define MCPWM_CAP1_INT_CLR_S 28 +/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by captureon channel 0*/ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (BIT(27)) +#define MCPWM_CAP0_INT_CLR_V 0x1 +#define MCPWM_CAP0_INT_CLR_S 27 +/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/ +#define MCPWM_FH2_OST_INT_CLR (BIT(26)) +#define MCPWM_FH2_OST_INT_CLR_M (BIT(26)) +#define MCPWM_FH2_OST_INT_CLR_V 0x1 +#define MCPWM_FH2_OST_INT_CLR_S 26 +/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH1_OST_INT_CLR (BIT(25)) +#define MCPWM_FH1_OST_INT_CLR_M (BIT(25)) +#define MCPWM_FH1_OST_INT_CLR_V 0x1 +#define MCPWM_FH1_OST_INT_CLR_S 25 +/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/ +#define MCPWM_FH0_OST_INT_CLR (BIT(24)) +#define MCPWM_FH0_OST_INT_CLR_M (BIT(24)) +#define MCPWM_FH0_OST_INT_CLR_V 0x1 +#define MCPWM_FH0_OST_INT_CLR_S 24 +/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle + mode action on PWM2*/ +#define MCPWM_FH2_CBC_INT_CLR (BIT(23)) +#define MCPWM_FH2_CBC_INT_CLR_M (BIT(23)) +#define MCPWM_FH2_CBC_INT_CLR_V 0x1 +#define MCPWM_FH2_CBC_INT_CLR_S 23 +/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle + mode action on PWM1*/ +#define MCPWM_FH1_CBC_INT_CLR (BIT(22)) +#define MCPWM_FH1_CBC_INT_CLR_M (BIT(22)) +#define MCPWM_FH1_CBC_INT_CLR_V 0x1 +#define MCPWM_FH1_CBC_INT_CLR_S 22 +/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle + mode action on PWM0*/ +#define MCPWM_FH0_CBC_INT_CLR (BIT(21)) +#define MCPWM_FH0_CBC_INT_CLR_M (BIT(21)) +#define MCPWM_FH0_CBC_INT_CLR_V 0x1 +#define MCPWM_FH0_CBC_INT_CLR_S 21 +/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/ +#define MCPWM_OP2_TEB_INT_CLR (BIT(20)) +#define MCPWM_OP2_TEB_INT_CLR_M (BIT(20)) +#define MCPWM_OP2_TEB_INT_CLR_V 0x1 +#define MCPWM_OP2_TEB_INT_CLR_S 20 +/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/ +#define MCPWM_OP1_TEB_INT_CLR (BIT(19)) +#define MCPWM_OP1_TEB_INT_CLR_M (BIT(19)) +#define MCPWM_OP1_TEB_INT_CLR_V 0x1 +#define MCPWM_OP1_TEB_INT_CLR_S 19 +/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/ +#define MCPWM_OP0_TEB_INT_CLR (BIT(18)) +#define MCPWM_OP0_TEB_INT_CLR_M (BIT(18)) +#define MCPWM_OP0_TEB_INT_CLR_V 0x1 +#define MCPWM_OP0_TEB_INT_CLR_S 18 +/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/ +#define MCPWM_OP2_TEA_INT_CLR (BIT(17)) +#define MCPWM_OP2_TEA_INT_CLR_M (BIT(17)) +#define MCPWM_OP2_TEA_INT_CLR_V 0x1 +#define MCPWM_OP2_TEA_INT_CLR_S 17 +/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/ +#define MCPWM_OP1_TEA_INT_CLR (BIT(16)) +#define MCPWM_OP1_TEA_INT_CLR_M (BIT(16)) +#define MCPWM_OP1_TEA_INT_CLR_V 0x1 +#define MCPWM_OP1_TEA_INT_CLR_S 16 +/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/ +#define MCPWM_OP0_TEA_INT_CLR (BIT(15)) +#define MCPWM_OP0_TEA_INT_CLR_M (BIT(15)) +#define MCPWM_OP0_TEA_INT_CLR_V 0x1 +#define MCPWM_OP0_TEA_INT_CLR_S 15 +/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f2 ends*/ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f1 ends*/ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f0 ends*/ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f2 starts*/ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_V 0x1 +#define MCPWM_FAULT2_INT_CLR_S 11 +/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f1 starts*/ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_V 0x1 +#define MCPWM_FAULT1_INT_CLR_S 10 +/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: Set this bit to clear interrupt triggered when event_f0 starts*/ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_V 0x1 +#define MCPWM_FAULT0_INT_CLR_S 9 +/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered when timer 2 stops*/ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered when timer 1 stops*/ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Set this bit to clear interrupt triggered when timer 0 stops*/ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 + +#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x0120) +/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: Force clock on for this reg file*/ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (BIT(0)) +#define MCPWM_CLK_EN_V 0x1 +#define MCPWM_CLK_EN_S 0 + +#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x0124) +/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ +/*description: Version of this reg file*/ +#define MCPWM_DATE 0x0FFFFFFF +#define MCPWM_DATE_M ((MCPWM_DATE_V)<<(MCPWM_DATE_S)) +#define MCPWM_DATE_V 0xFFFFFFF +#define MCPWM_DATE_S 0 + + + + +#endif /*_SOC_MCPWM_REG_H_ */ + + diff --git a/components/soc/esp32s2beta/include/soc/mcpwm_struct.h b/components/soc/esp32s2beta/include/soc/mcpwm_struct.h new file mode 100644 index 0000000000..f41d40c644 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/mcpwm_struct.h @@ -0,0 +1,462 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_MCPWM_STRUCT_H__ +#define _SOC_MCPWM_STRUCT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/ + uint32_t reserved8: 24; + }; + uint32_t val; + }clk_cfg; + struct { + union { + struct { + uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/ + uint32_t period: 16; /*period shadow reg of PWM timer0*/ + uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/ + uint32_t reserved26: 6; + }; + uint32_t val; + }period; + union { + struct { + uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/ + uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/ + uint32_t reserved5: 27; + }; + uint32_t val; + }mode; + union { + struct { + uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/ + uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/ + uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/ + uint32_t timer_phase: 17; /*phase for timer reload on sync event*/ + uint32_t reserved21: 11; + }; + uint32_t val; + }sync; + union { + struct { + uint32_t value: 16; /*current PWM timer0 counter value*/ + uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/ + uint32_t reserved17: 15; + }; + uint32_t val; + }status; + }timer[3]; + + + union { + struct { + uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ + uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ + uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/ + uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/ + uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/ + uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/ + uint32_t reserved12: 20; + }; + uint32_t val; + }timer_synci_cfg; + union { + struct { + uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/ + uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/ + uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/ + uint32_t reserved6: 26; + }; + uint32_t val; + }timer_sel; + + + struct { + union { + struct { + uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ + uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/ + uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/ + uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/ + uint32_t reserved10: 22; + }; + uint32_t val; + }cmpr_cfg; + union { + struct { + uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/ + uint32_t reserved16:16; + }; + uint32_t val; + }cmpr_value[2]; + union { + struct { + uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/ + uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ + uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/ + uint32_t reserved10: 22; + }; + uint32_t val; + }gen_cfg0; + union { + struct { + uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/ + uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/ + uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/ + uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/ + uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/ + uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/ + uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/ + uint32_t reserved16: 16; + }; + uint32_t val; + }gen_force; + union { + struct { + uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/ + uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/ + uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/ + uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/ + uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/ + uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/ + uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/ + uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/ + uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/ + uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/ + uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/ + uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/ + uint32_t reserved24: 8; + }; + uint32_t val; + }generator[2]; + union { + struct { + uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ + uint32_t a_outswap: 1; /*S6 in documentation*/ + uint32_t b_outswap: 1; /*S7 in documentation*/ + uint32_t red_insel: 1; /*S4 in documentation*/ + uint32_t fed_insel: 1; /*S5 in documentation*/ + uint32_t red_outinvert: 1; /*S2 in documentation*/ + uint32_t fed_outinvert: 1; /*S3 in documentation*/ + uint32_t a_outbypass: 1; /*S1 in documentation*/ + uint32_t b_outbypass: 1; /*S0 in documentation*/ + uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/ + uint32_t reserved18: 14; + }; + uint32_t val; + }db_cfg; + union { + struct { + uint32_t fed: 16; /*Shadow reg for FED*/ + uint32_t reserved16:16; + }; + uint32_t val; + }db_fed_cfg; + union { + struct { + uint32_t red: 16; /*Shadow reg for RED*/ + uint32_t reserved16:16; + }; + uint32_t val; + }db_red_cfg; + union { + struct { + uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/ + uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/ + uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/ + uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/ + uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/ + uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/ + uint32_t reserved14: 18; + }; + uint32_t val; + }carrier_cfg; + union { + struct { + uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/ + uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/ + uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t reserved24: 8; + }; + uint32_t val; + }tz_cfg0; + union { + struct { + uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/ + uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/ + uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/ + uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/ + uint32_t reserved5: 27; + }; + uint32_t val; + }tz_cfg1; + union { + struct { + uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/ + uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/ + uint32_t reserved2: 30; + }; + uint32_t val; + }tz_status; + }channel[3]; + + union { + struct { + uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/ + uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/ + uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/ + uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ + uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ + uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/ + uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/ + uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/ + uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/ + uint32_t reserved9: 23; + }; + uint32_t val; + }fault_detect; + union { + struct { + uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/ + uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/ + uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/ + uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + }cap_timer_cfg; + uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/ + union { + struct { + uint32_t en: 1; /*When set capture on channel 0 is enabled*/ + uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/ + uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/ + uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/ + uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/ + uint32_t reserved13: 19; + }; + uint32_t val; + }cap_cfg_ch[3]; + uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/ + union { + struct { + uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/ + uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/ + uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/ + uint32_t reserved3: 29; + }; + uint32_t val; + }cap_status; + union { + struct { + uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/ + uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/ + uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/ + uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/ + uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/ + uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/ + uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/ + uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/ + uint32_t reserved8: 24; + }; + uint32_t val; + }update_cfg; + union { + struct { + uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_ena; + union { + struct { + uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_raw; + union { + struct { + uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_st; + union { + struct { + uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/ + uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/ + uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/ + uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/ + uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/ + uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/ + uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/ + uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/ + uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/ + uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/ + uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/ + uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/ + uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/ + uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/ + uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/ + uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/ + uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/ + uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/ + uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/ + uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/ + uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/ + uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/ + uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/ + uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/ + uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/ + uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/ + uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/ + uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + }int_clr; + union { + struct { + uint32_t clk_en: 1; /*Force clock on for this reg file*/ + uint32_t reserved1: 31; + }; + uint32_t val; + }reg_clk; + union { + struct { + uint32_t date: 28; /*Version of this reg file*/ + uint32_t reserved28: 4; + }; + uint32_t val; + }version; +} mcpwm_dev_t; +extern mcpwm_dev_t MCPWM0; +extern mcpwm_dev_t MCPWM1; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_MCPWM_STRUCT_H__ */ diff --git a/components/soc/esp32s2beta/include/soc/pcnt_struct.h b/components/soc/esp32s2beta/include/soc/pcnt_struct.h index 3b986cb1bd..b0c811f9cb 100644 --- a/components/soc/esp32s2beta/include/soc/pcnt_struct.h +++ b/components/soc/esp32s2beta/include/soc/pcnt_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -18,116 +18,137 @@ extern "C" { #endif typedef volatile struct { - struct{ + struct { union { struct { - uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ - uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ - uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ - uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ - uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ - uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ - uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ - uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ - uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ - uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ - uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ - uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ - uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ - uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ - uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t filter_thres: 10; + uint32_t filter_en: 1; + uint32_t thr_zero_en: 1; + uint32_t thr_h_lim_en: 1; + uint32_t thr_l_lim_en: 1; + uint32_t thr_thres0_en: 1; + uint32_t thr_thres1_en: 1; + uint32_t ch0_neg_mode: 2; + uint32_t ch0_pos_mode: 2; + uint32_t ch0_hctrl_mode: 2; + uint32_t ch0_lctrl_mode: 2; + uint32_t ch1_neg_mode: 2; + uint32_t ch1_pos_mode: 2; + uint32_t ch1_hctrl_mode: 2; + uint32_t ch1_lctrl_mode: 2; }; uint32_t val; } conf0; union { struct { - uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ - uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ + uint32_t cnt_thres0: 16; + uint32_t cnt_thres1: 16; }; uint32_t val; } conf1; union { struct { - uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ - uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ + uint32_t cnt_h_lim: 16; + uint32_t cnt_l_lim: 16; }; uint32_t val; } conf2; } conf_unit[4]; union { struct { - uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ - uint32_t reserved16: 16; + uint32_t cnt_val: 16; + uint32_t reserved16: 16; }; uint32_t val; } cnt_unit[4]; union { struct { - uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ - uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ - uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ - uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; }; uint32_t val; } int_raw; union { struct { - uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/ - uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ - uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ - uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; }; uint32_t val; } int_st; union { struct { - uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/ - uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ - uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ - uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; }; uint32_t val; } int_ena; union { struct { - uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/ - uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ - uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ - uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ - uint32_t reserved4: 28; + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; }; uint32_t val; } int_clr; union { struct { - uint32_t cnt_mode:2; /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ - uint32_t thres1_lat:1; /* counter value equals to thresh1*/ - uint32_t thres0_lat:1; /* counter value equals to thresh0*/ - uint32_t l_lim_lat:1; /* counter value reaches h_lim*/ - uint32_t h_lim_lat:1; /* counter value reaches l_lim*/ - uint32_t zero_lat:1; /* counter value equals zero*/ - uint32_t reserved7:25; + uint32_t cnt_mode: 2; + uint32_t thres1_lat: 1; + uint32_t thres0_lat: 1; + uint32_t l_lim_lat: 1; + uint32_t h_lim_lat: 1; + uint32_t zero_lat: 1; + uint32_t reserved7: 25; }; uint32_t val; } status_unit[4]; union { struct { - uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ - uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ - uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ - uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ - uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ - uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ - uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ - uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ - uint32_t clk_en: 1; - uint32_t reserved9: 13; + uint32_t cnt_rst_u0: 1; + uint32_t cnt_pause_u0: 1; + uint32_t cnt_rst_u1: 1; + uint32_t cnt_pause_u1: 1; + uint32_t cnt_rst_u2: 1; + uint32_t cnt_pause_u2: 1; + uint32_t cnt_rst_u3: 1; + uint32_t cnt_pause_u3: 1; + uint32_t reserved8: 8; + uint32_t clk_en: 1; + uint32_t reserved17: 15; }; uint32_t val; } ctrl; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; uint32_t reserved_b4; uint32_t reserved_b8; uint32_t reserved_bc; diff --git a/components/soc/esp32s2beta/include/soc/periph_defs.h b/components/soc/esp32s2beta/include/soc/periph_defs.h index 099c28845b..d0b69710ba 100644 --- a/components/soc/esp32s2beta/include/soc/periph_defs.h +++ b/components/soc/esp32s2beta/include/soc/periph_defs.h @@ -23,7 +23,11 @@ typedef enum { PERIPH_LEDC_MODULE = 0, PERIPH_UART0_MODULE, PERIPH_UART1_MODULE, +#ifdef CONFIG_CHIP_IS_ESP32 + PERIPH_UART2_MODULE, +#else PERIPH_USB_MODULE, +#endif PERIPH_I2C0_MODULE, PERIPH_I2C1_MODULE, PERIPH_I2S0_MODULE, @@ -57,6 +61,111 @@ typedef enum { PERIPH_BT_LC_MODULE, } periph_module_t; +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ + ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ + + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ + ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ + ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/ + ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ + + ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ + ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ + ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ + ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ + ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ + ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/ + ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_CAN_INTR_SOURCE , /**< interrupt of can, level*/ + + ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ + ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ + ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ + ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ + ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ + ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ + + ETS_TG0_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ + ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ + ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ + ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ + ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/ + ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/ + ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/ + ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/ + ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/ + + ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal APB access, LEVEL*/ + ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA RX access, LEVEL*/ + ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/ + ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/ + ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/ + ETS_ICACHE_PRELOAD_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_DCACHE_PRELOAD_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/ + ETS_CPU_PERI_ERROR_INTR_SOURCE, /**< interrupt of CPU peripherals error, LEVEL*/ + ETS_APB_PERI_ERROR_INTR_SOURCE, /**< interrupt of APB peripherals error, LEVEL*/ + ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ + ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ + +} periph_interrput_t; + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2beta/include/soc/rmt_reg.h b/components/soc/esp32s2beta/include/soc/rmt_reg.h index 1beeac4fd5..b1ff759a9e 100644 --- a/components/soc/esp32s2beta/include/soc/rmt_reg.h +++ b/components/soc/esp32s2beta/include/soc/rmt_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -28,18 +28,6 @@ extern "C" { #define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) #define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0010) -/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 -/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define RMT_MEM_PD (BIT(30)) -#define RMT_MEM_PD_M (BIT(30)) -#define RMT_MEM_PD_V 0x1 -#define RMT_MEM_PD_S 30 /* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */ /*description: */ #define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) @@ -52,6 +40,12 @@ extern "C" { #define RMT_CARRIER_EN_CH0_M (BIT(28)) #define RMT_CARRIER_EN_CH0_V 0x1 #define RMT_CARRIER_EN_CH0_S 28 +/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH0_M (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH0_V 0x1 +#define RMT_CARRIER_EFF_EN_CH0_S 27 /* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */ /*description: */ #define RMT_MEM_SIZE_CH0 0x00000007 @@ -96,6 +90,12 @@ extern "C" { #define RMT_REF_ALWAYS_ON_CH0_M (BIT(17)) #define RMT_REF_ALWAYS_ON_CH0_V 0x1 #define RMT_REF_ALWAYS_ON_CH0_S 17 +/* RMT_CHK_RX_CARRIER_EN_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH0_M (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH0_V 0x1 +#define RMT_CHK_RX_CARRIER_EN_CH0_S 16 /* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ /*description: */ #define RMT_RX_FILTER_THRES_CH0 0x000000FF @@ -164,6 +164,12 @@ extern "C" { #define RMT_CARRIER_EN_CH1_M (BIT(28)) #define RMT_CARRIER_EN_CH1_V 0x1 #define RMT_CARRIER_EN_CH1_S 28 +/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH1_M (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH1_V 0x1 +#define RMT_CARRIER_EFF_EN_CH1_S 27 /* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */ /*description: */ #define RMT_MEM_SIZE_CH1 0x00000007 @@ -208,6 +214,12 @@ extern "C" { #define RMT_REF_ALWAYS_ON_CH1_M (BIT(17)) #define RMT_REF_ALWAYS_ON_CH1_V 0x1 #define RMT_REF_ALWAYS_ON_CH1_S 17 +/* RMT_CHK_RX_CARRIER_EN_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CHK_RX_CARRIER_EN_CH1 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH1_M (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH1_V 0x1 +#define RMT_CHK_RX_CARRIER_EN_CH1_S 16 /* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ /*description: */ #define RMT_RX_FILTER_THRES_CH1 0x000000FF @@ -276,6 +288,12 @@ extern "C" { #define RMT_CARRIER_EN_CH2_M (BIT(28)) #define RMT_CARRIER_EN_CH2_V 0x1 #define RMT_CARRIER_EN_CH2_S 28 +/* RMT_CARRIER_EFF_EN_CH2 : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH2 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH2_M (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH2_V 0x1 +#define RMT_CARRIER_EFF_EN_CH2_S 27 /* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */ /*description: */ #define RMT_MEM_SIZE_CH2 0x00000007 @@ -320,6 +338,12 @@ extern "C" { #define RMT_REF_ALWAYS_ON_CH2_M (BIT(17)) #define RMT_REF_ALWAYS_ON_CH2_V 0x1 #define RMT_REF_ALWAYS_ON_CH2_S 17 +/* RMT_CHK_RX_CARRIER_EN_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CHK_RX_CARRIER_EN_CH2 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH2_M (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH2_V 0x1 +#define RMT_CHK_RX_CARRIER_EN_CH2_S 16 /* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ /*description: */ #define RMT_RX_FILTER_THRES_CH2 0x000000FF @@ -388,6 +412,12 @@ extern "C" { #define RMT_CARRIER_EN_CH3_M (BIT(28)) #define RMT_CARRIER_EN_CH3_V 0x1 #define RMT_CARRIER_EN_CH3_S 28 +/* RMT_CARRIER_EFF_EN_CH3 : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH3 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH3_M (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH3_V 0x1 +#define RMT_CARRIER_EFF_EN_CH3_S 27 /* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[26:24] ;default: 3'h1 ; */ /*description: */ #define RMT_MEM_SIZE_CH3 0x00000007 @@ -432,6 +462,12 @@ extern "C" { #define RMT_REF_ALWAYS_ON_CH3_M (BIT(17)) #define RMT_REF_ALWAYS_ON_CH3_V 0x1 #define RMT_REF_ALWAYS_ON_CH3_S 17 +/* RMT_CHK_RX_CARRIER_EN_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CHK_RX_CARRIER_EN_CH3 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH3_M (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH3_V 0x1 +#define RMT_CHK_RX_CARRIER_EN_CH3_S 16 /* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */ /*description: */ #define RMT_RX_FILTER_THRES_CH3 0x000000FF @@ -1392,6 +1428,30 @@ extern "C" { #define RMT_TX_LIM_CH3_S 0 #define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x0080) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FORCE_PU (BIT(4)) +#define RMT_MEM_FORCE_PU_M (BIT(4)) +#define RMT_MEM_FORCE_PU_V 0x1 +#define RMT_MEM_FORCE_PU_S 4 +/* RMT_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FORCE_PD (BIT(3)) +#define RMT_MEM_FORCE_PD_M (BIT(3)) +#define RMT_MEM_FORCE_PD_V 0x1 +#define RMT_MEM_FORCE_PD_S 3 +/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_CLK_FORCE_ON (BIT(2)) +#define RMT_MEM_CLK_FORCE_ON_M (BIT(2)) +#define RMT_MEM_CLK_FORCE_ON_V 0x1 +#define RMT_MEM_CLK_FORCE_ON_S 2 /* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define RMT_MEM_TX_WRAP_EN (BIT(1)) @@ -1463,8 +1523,64 @@ extern "C" { #define RMT_REF_CNT_RST_CH0_V 0x1 #define RMT_REF_CNT_RST_CH0_S 0 +#define RMT_CH0_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x008c) +/* RMT_CARRIER_HIGH_THRES_CH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH0_M ((RMT_CARRIER_HIGH_THRES_CH0_V)<<(RMT_CARRIER_HIGH_THRES_CH0_S)) +#define RMT_CARRIER_HIGH_THRES_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH0_S 16 +/* RMT_CARRIER_LOW_THRES_CH0 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH0_M ((RMT_CARRIER_LOW_THRES_CH0_V)<<(RMT_CARRIER_LOW_THRES_CH0_S)) +#define RMT_CARRIER_LOW_THRES_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH0_S 0 + +#define RMT_CH1_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0090) +/* RMT_CARRIER_HIGH_THRES_CH1 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH1_M ((RMT_CARRIER_HIGH_THRES_CH1_V)<<(RMT_CARRIER_HIGH_THRES_CH1_S)) +#define RMT_CARRIER_HIGH_THRES_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH1_S 16 +/* RMT_CARRIER_LOW_THRES_CH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH1_M ((RMT_CARRIER_LOW_THRES_CH1_V)<<(RMT_CARRIER_LOW_THRES_CH1_S)) +#define RMT_CARRIER_LOW_THRES_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH1_S 0 + +#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0094) +/* RMT_CARRIER_HIGH_THRES_CH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH2_M ((RMT_CARRIER_HIGH_THRES_CH2_V)<<(RMT_CARRIER_HIGH_THRES_CH2_S)) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 +/* RMT_CARRIER_LOW_THRES_CH2 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH2_M ((RMT_CARRIER_LOW_THRES_CH2_V)<<(RMT_CARRIER_LOW_THRES_CH2_S)) +#define RMT_CARRIER_LOW_THRES_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH2_S 0 + +#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0098) +/* RMT_CARRIER_HIGH_THRES_CH3 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH3_M ((RMT_CARRIER_HIGH_THRES_CH3_V)<<(RMT_CARRIER_HIGH_THRES_CH3_S)) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 +/* RMT_CARRIER_LOW_THRES_CH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH3_M ((RMT_CARRIER_LOW_THRES_CH3_V)<<(RMT_CARRIER_LOW_THRES_CH3_S)) +#define RMT_CARRIER_LOW_THRES_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH3_S 0 + #define RMT_DATE_REG (DR_REG_RMT_BASE + 0x0fc) -/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */ +/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */ /*description: */ #define RMT_DATE 0xFFFFFFFF #define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) @@ -1474,7 +1590,7 @@ extern "C" { #ifdef __cplusplus } #endif -#define RMT_CHANNEL_MEM(i) (DR_REG_RMT_BASE + 0x400 + 64 * 4 * (i)) + #endif /*_SOC_RMT_REG_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/rmt_struct.h b/components/soc/esp32s2beta/include/soc/rmt_struct.h index e42bc746fc..08ef95750e 100644 --- a/components/soc/esp32s2beta/include/soc/rmt_struct.h +++ b/components/soc/esp32s2beta/include/soc/rmt_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -28,7 +28,7 @@ typedef volatile struct { uint32_t div_cnt: 8; uint32_t idle_thres: 16; uint32_t mem_size: 3; - uint32_t reserved27: 1; + uint32_t carrier_eff_en: 1; uint32_t carrier_en: 1; uint32_t carrier_out_lv: 1; uint32_t mem_pd: 1; @@ -38,21 +38,22 @@ typedef volatile struct { } conf0; union { struct { - uint32_t tx_start: 1; - uint32_t rx_en: 1; - uint32_t mem_wr_rst: 1; - uint32_t mem_rd_rst: 1; - uint32_t apb_mem_rst: 1; - uint32_t mem_owner: 1; - uint32_t tx_conti_mode: 1; - uint32_t rx_filter_en: 1; - uint32_t rx_filter_thres: 8; - uint32_t reserved16: 1; - uint32_t ref_always_on: 1; - uint32_t idle_out_lv: 1; - uint32_t idle_out_en: 1; - uint32_t tx_stop: 1; - uint32_t reserved21: 11; + uint32_t tx_start: 1; + uint32_t rx_en: 1; + uint32_t mem_wr_rst: 1; + uint32_t mem_rd_rst: 1; + uint32_t apb_mem_rst: 1; + uint32_t mem_owner: 1; + uint32_t tx_conti_mode: 1; + uint32_t rx_filter_en: 1; + uint32_t rx_filter_thres: 8; + uint32_t chk_rx_carrier_en: 1; + uint32_t ref_always_on: 1; + uint32_t idle_out_lv: 1; + uint32_t idle_out_en: 1; + uint32_t tx_stop: 1; + uint32_t carrier_per: 5; + uint32_t reserved26: 6; }; uint32_t val; } conf1; @@ -232,14 +233,66 @@ typedef volatile struct { }; uint32_t val; } ref_cnt_rst; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; + union { + struct { + uint32_t carrier_low_num_ch0: 15; + uint32_t carrier_high_num_ch0:15; + uint32_t reserved30: 2; + }; + uint32_t val; + } ch0_rx_carrier_st; + union { + struct { + uint32_t carrier_low_thres_ch0: 16; + uint32_t carrier_high_thres_ch0:16; + }; + uint32_t val; + } ch0_rx_carrier_rm; + union { + struct { + uint32_t carrier_low_num_ch1: 15; + uint32_t carrier_high_num_ch1:15; + uint32_t reserved30: 2; + }; + uint32_t val; + } ch1_rx_carrier_st; + union { + struct { + uint32_t carrier_low_thres_ch1: 16; + uint32_t carrier_high_thres_ch1:16; + }; + uint32_t val; + } ch1_rx_carrier_rm; + union { + struct { + uint32_t carrier_low_num_ch2: 15; + uint32_t carrier_high_num_ch2:15; + uint32_t reserved30: 2; + }; + uint32_t val; + } ch2_rx_carrier_st; + union { + struct { + uint32_t carrier_low_thres_ch2: 16; + uint32_t carrier_high_thres_ch2:16; + }; + uint32_t val; + } ch2_rx_carrier_rm; + union { + struct { + uint32_t carrier_low_num_ch3: 15; + uint32_t carrier_high_num_ch3:15; + uint32_t reserved30: 2; + }; + uint32_t val; + } ch3_rx_carrier_st; + union { + struct { + uint32_t carrier_low_thres_ch3: 16; + uint32_t carrier_high_thres_ch3:16; + }; + uint32_t val; + } ch3_rx_carrier_rm; uint32_t reserved_ac; uint32_t reserved_b0; uint32_t reserved_b4; diff --git a/components/soc/esp32s2beta/include/soc/rtc.h b/components/soc/esp32s2beta/include/soc/rtc.h index d88fe56c06..f14c77650e 100644 --- a/components/soc/esp32s2beta/include/soc/rtc.h +++ b/components/soc/esp32s2beta/include/soc/rtc.h @@ -51,6 +51,79 @@ extern "C" { * - rtc_init: initialization */ +#define MHZ (1000000) + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +#define RTC_SLOW_CLK_FREQ_150K 150000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + +#define DELAY_FAST_CLK_SWITCH 3 +#define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + +/* Number of 8M/256 clock cycles to use for XTAL frequency estimation. + * 10 cycles will take approximately 300 microseconds. + */ +#define XTAL_FREQ_EST_CYCLES 10 + +/* Core voltage needs to be increased in two cases: + * 1. running at 240 MHz + * 2. running with 80MHz Flash frequency + */ +#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 +#else +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 +#endif +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 + +#define APLL_SDM_STOP_VAL_1 0x09 +#define APLL_SDM_STOP_VAL_2_REV0 0x69 +#define APLL_SDM_STOP_VAL_2_REV1 0x49 +#define APLL_CAL_DELAY_1 0x0f +#define APLL_CAL_DELAY_2 0x3f +#define APLL_CAL_DELAY_3 0x1f /** * @brief Possible main XTAL frequency values. @@ -72,6 +145,7 @@ typedef enum { RTC_CPU_FREQ_2M = 4, //!< 2 MHz RTC_CPU_320M_80M = 5, //!< for test RTC_CPU_320M_160M = 6, //!< for test + RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset } rtc_cpu_freq_t; /** @@ -94,6 +168,11 @@ typedef enum { /* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ #define RTC_FAST_CLK_FREQ_APPROX 8500000 +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + /** * @brief Clock source to be calibrated using rtc_clk_cal function */ @@ -131,6 +210,64 @@ typedef struct { .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ } +typedef struct { + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +} x32k_config_t; + +#define X32K_CONFIG_DEFAULT() { \ + .dac = 1, \ + .dres = 3, \ + .dgm = 0, \ + .dbuf = 1, \ +} + +#if 0 +#define X32K_CONFIG_BOOTSTRAP_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 0, \ +} + +typedef struct { + x32k_config_t x32k_cfg; + uint32_t bt_lpck_div_num : 12; + uint32_t bt_lpck_div_a : 12; + uint32_t bt_lpck_div_b : 12; +} x32k_bootstrap_config_t; + +#define X32K_BOOTSTRAP_CONFIG_DEFAULT() { \ + .x32k_cfg = X32K_CONFIG_BOOTSTRAP_DEFAULT(), \ + .bt_lpck_div_num = 2441, \ + .bt_lpck_div_a = 32, \ + .bt_lpck_div_b = 13, \ +} +#endif + +typedef struct { + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t rtc_powerup_cycles : 7; + uint16_t rtc_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t rtc_mem_powerup_cycles : 7; + uint16_t rtc_mem_wait_cycles : 9; +} rtc_init_config_t; + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .rtc_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + void rtc_clk_divider_set(uint32_t div); void rtc_clk_8m_divider_set(uint32_t div); @@ -356,8 +493,6 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq); */ uint32_t rtc_clk_apb_freq_get(void); -#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal - uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); /** @@ -494,10 +629,10 @@ typedef struct { .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \ .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ .deep_slp_reject = 1, \ .light_slp_reject = 1 \ @@ -617,9 +752,6 @@ typedef struct { */ void rtc_init(rtc_config_t cfg); -#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO -#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO - /** * Structure describing vddsdio configuration */ diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h index bdf0d5bbc8..ac336c8b20 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h @@ -79,60 +79,12 @@ extern "C" { #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 #define RTC_CNTL_XTL_FORCE_ISO_S 23 -/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ -/*description: BIAS_CORE force power up*/ -#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) -#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) -#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 -#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 -/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: BIAS_CORE force power down*/ -#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) -#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) -#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 -#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 -/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: BIAS_CORE follow CK8M*/ -#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) -#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) -#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 -#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 -/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ -/*description: BIAS_I2C force power up*/ -#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) -#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 -/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: BIAS_I2C force power down*/ -#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) -#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 -/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: BIAS_I2C follow CK8M*/ -#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) -#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) -#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 -#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 -/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: BIAS_SLEEP force no sleep*/ -#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) -#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) -#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 -#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 -/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: BIAS_SLEEP force sleep*/ -#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) -#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) -#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 -#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 -/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: BIAS_SLEEP follow CK8M*/ -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ /*description: crystall force power up*/ #define RTC_CNTL_XTL_FORCE_PU (BIT(13)) @@ -217,7 +169,7 @@ extern "C" { #define RTC_CNTL_SLP_VAL_LO_S 0 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) -/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ /*description: timer alarm enable bit*/ #define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) @@ -230,19 +182,13 @@ extern "C" { #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF #define RTC_CNTL_SLP_VAL_HI_S 0 -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000c) +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ /*description: Set 1: to update register with RTC timer*/ #define RTC_CNTL_TIME_UPDATE (BIT(31)) #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) #define RTC_CNTL_TIME_UPDATE_V 0x1 #define RTC_CNTL_TIME_UPDATE_S 31 -/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: To indicate the register is updated*/ -#define RTC_CNTL_TIME_VALID (BIT(30)) -#define RTC_CNTL_TIME_VALID_M (BIT(30)) -#define RTC_CNTL_TIME_VALID_V 0x1 -#define RTC_CNTL_TIME_VALID_S 30 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ /*description: enable to record system reset time*/ #define RTC_CNTL_TIMER_SYS_RST (BIT(29)) @@ -322,28 +268,25 @@ extern "C" { #define RTC_CNTL_SW_CPU_INT_V 0x1 #define RTC_CNTL_SW_CPU_INT_S 0 -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001c) +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ /*description: PLL wait cycles in slow_clk_rtc*/ #define RTC_CNTL_PLL_BUF_WAIT 0x000000FF #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF #define RTC_CNTL_PLL_BUF_WAIT_S 24 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 100 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ /*description: XTAL wait cycles in slow_clk_rtc*/ #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ /*description: CK8M wait cycles in slow_clk_rtc*/ #define RTC_CNTL_CK8M_WAIT 0x000000FF #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ /*description: CPU stall wait cycles in fast_clk_rtc*/ #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F @@ -424,7 +367,7 @@ extern "C" { #define RTC_CNTL_WAIT_TIMER_V 0x1FF #define RTC_CNTL_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002c) +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) /* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ /*description: */ #define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F @@ -508,6 +451,36 @@ extern "C" { #define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) #define RTC_CNTL_PLLA_FORCE_PD_V 0x1 #define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_SAR_I2C_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_FORCE_PU_S 22 +/* RTC_CNTL_SAR_I2C_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21)) +#define RTC_CNTL_SAR_I2C_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_SAR_I2C_FORCE_PD_S 21 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ @@ -535,35 +508,35 @@ extern "C" { #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003c) -/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: enable filter for gpio wakeup event*/ -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(30)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(30)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 30 -/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[29:15] ;default: 15'b1100 ; */ +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ /*description: wakeup enable bitmap*/ -#define RTC_CNTL_WAKEUP_ENA 0x00007FFF +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) -#define RTC_CNTL_WAKEUP_ENA_V 0x7FFF +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF #define RTC_CNTL_WAKEUP_ENA_S 15 -/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[14:0] ;default: 15'h0 ; */ -/*description: wakeup cause*/ -#define RTC_CNTL_WAKEUP_CAUSE 0x00007FFF -#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FFF -#define RTC_CNTL_WAKEUP_CAUSE_S 0 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ +/*description: enable cocpu trap interrupt*/ #define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt*/ +/*description: enable xtal32k_dead interrupt*/ #define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 @@ -634,12 +607,12 @@ extern "C" { #define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_S 5 -/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable RTC time valid interrupt*/ -#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: enable RTC WDT interrupt*/ #define RTC_CNTL_WDT_INT_ENA (BIT(3)) @@ -666,6 +639,18 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: touch timeout interrupt raw*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 /* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ /*description: cocpu trap interrupt raw*/ #define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) @@ -744,12 +729,12 @@ extern "C" { #define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 #define RTC_CNTL_ULP_CP_INT_RAW_S 5 -/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: RTC time valid interrupt raw*/ -#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: RTC WDT interrupt raw*/ #define RTC_CNTL_WDT_INT_RAW (BIT(3)) @@ -776,6 +761,18 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ /*description: cocpu trap interrupt state*/ #define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) @@ -854,12 +851,12 @@ extern "C" { #define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ST_V 0x1 #define RTC_CNTL_ULP_CP_INT_ST_S 5 -/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: RTC time valid interrupt state*/ -#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_ST_S 4 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ /*description: RTC WDT interrupt state*/ #define RTC_CNTL_WDT_INT_ST (BIT(3)) @@ -885,7 +882,19 @@ extern "C" { #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004c) +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Clear touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 /* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ /*description: Clear cocpu trap interrupt state*/ #define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) @@ -964,12 +973,12 @@ extern "C" { #define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 #define RTC_CNTL_ULP_CP_INT_CLR_S 5 -/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Clear RTC time valid interrupt state*/ -#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ /*description: Clear RTC WDT interrupt state*/ #define RTC_CNTL_WDT_INT_CLR (BIT(3)) @@ -1019,7 +1028,7 @@ extern "C" { #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH2_S 0 -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005c) +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH3 0xFFFFFFFF @@ -1046,11 +1055,17 @@ extern "C" { #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 -/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[22:17] ;default: 6'd3 ; */ +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ /*description: DAC_XTAL_32K*/ -#define RTC_CNTL_DAC_XTAL_32K 0x0000003F +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) -#define RTC_CNTL_DAC_XTAL_32K_V 0x3F +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 #define RTC_CNTL_DAC_XTAL_32K_S 17 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: XPD_XTAL_32K*/ @@ -1144,6 +1159,12 @@ extern "C" { #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ @@ -1158,20 +1179,14 @@ extern "C" { #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 -/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:15] ;default: 15'd0 ; */ +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:13] ;default: 16'd0 ; */ /*description: sleep reject enable*/ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x00007FFF +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0001FFFF #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) -#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x7FFF -#define RTC_CNTL_SLEEP_REJECT_ENA_S 15 -/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ -/*description: sleep reject cause*/ -#define RTC_CNTL_REJECT_CAUSE 0x00007FFF -#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) -#define RTC_CNTL_REJECT_CAUSE_V 0x7FFF -#define RTC_CNTL_REJECT_CAUSE_S 0 +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x1FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 13 -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006c) +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ /*description: */ #define RTC_CNTL_CPUPERIOD_SEL 0x00000003 @@ -1224,7 +1239,7 @@ extern "C" { #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 -#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.2 +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.3 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) @@ -1308,7 +1323,7 @@ extern "C" { #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007c) +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_XPD_SDIO_REG (BIT(31)) @@ -1444,14 +1459,66 @@ extern "C" { #define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) #define RTC_CNTL_ENB_SCK_XTAL_V 0x1 #define RTC_CNTL_ENB_SCK_XTAL_S 26 -/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: DBG_ATTEN*/ -#define RTC_CNTL_DBG_ATTEN 0x0000000F -#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) -#define RTC_CNTL_DBG_ATTEN_V 0xF -#define RTC_CNTL_DBG_ATTEN_S 22 -/* reserved for driver to check */ -#define RTC_CNTL_DBG_ATTEN_DEFAULT 15 +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ @@ -1489,14 +1556,14 @@ extern "C" { * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. * Valid if RTC_CNTL_DBG_ATTEN is 0. */ -#define RTC_CNTL_DBIAS_0V90 0 -#define RTC_CNTL_DBIAS_0V95 1 -#define RTC_CNTL_DBIAS_1V00 2 -#define RTC_CNTL_DBIAS_1V05 3 -#define RTC_CNTL_DBIAS_1V10 4 -#define RTC_CNTL_DBIAS_1V15 5 -#define RTC_CNTL_DBIAS_1V20 6 -#define RTC_CNTL_DBIAS_1V25 7 +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ /*description: RTC_DBIAS during sleep*/ @@ -1510,7 +1577,6 @@ extern "C" { #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF #define RTC_CNTL_SCK_DCAP_S 14 -#define RTC_CNTL_SCK_DCAP_DEFAULT 255 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during wakeup*/ #define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 @@ -1539,16 +1605,16 @@ extern "C" { #define RTC_CNTL_PD_EN_S 20 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ /*description: rtc_peri force power up*/ -#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) -#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_PWC_FORCE_PU_V 0x1 -#define RTC_CNTL_PWC_FORCE_PU_S 19 +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 19 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ /*description: rtc_peri force power down*/ -#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) -#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_PWC_FORCE_PD_V 0x1 -#define RTC_CNTL_PWC_FORCE_PD_S 18 +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 18 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ /*description: enable power down RTC memory in sleep*/ #define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) @@ -1676,7 +1742,7 @@ extern "C" { #define RTC_CNTL_MEM_FORCE_LPD \ (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008c) +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ /*description: */ #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) @@ -2104,7 +2170,7 @@ extern "C" { #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG0_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009c) +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ /*description: */ #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF @@ -2112,7 +2178,7 @@ extern "C" { #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG1_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00a0) +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ /*description: */ #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF @@ -2120,7 +2186,7 @@ extern "C" { #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG2_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00a4) +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ /*description: */ #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF @@ -2128,7 +2194,7 @@ extern "C" { #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG3_HOLD_S 0 -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00a8) +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_WDT_FEED (BIT(31)) @@ -2136,7 +2202,7 @@ extern "C" { #define RTC_CNTL_WDT_FEED_V 0x1 #define RTC_CNTL_WDT_FEED_S 31 -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00ac) +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ /*description: */ #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF @@ -2144,8 +2210,8 @@ extern "C" { #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_S 0 -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00b0) -/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: automatically feed swd when int comes*/ #define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) @@ -2188,7 +2254,7 @@ extern "C" { #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 #define RTC_CNTL_SWD_RESET_FLAG_S 0 -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00b4) +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ /*description: swd write protect*/ #define RTC_CNTL_SWD_WKEY 0xFFFFFFFF @@ -2196,27 +2262,7 @@ extern "C" { #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_S 0 -#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0x00b8) -/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: */ -#define RTC_CNTL_DTEST_RTC 0x00000003 -#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) -#define RTC_CNTL_DTEST_RTC_V 0x3 -#define RTC_CNTL_DTEST_RTC_S 30 -/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ENT_RTC*/ -#define RTC_CNTL_ENT_RTC (BIT(29)) -#define RTC_CNTL_ENT_RTC_M (BIT(29)) -#define RTC_CNTL_ENT_RTC_V 0x1 -#define RTC_CNTL_ENT_RTC_S 29 -/* RTC_CNTL_ENT_TSENS : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: ENT_TSENS*/ -#define RTC_CNTL_ENT_TSENS (BIT(28)) -#define RTC_CNTL_ENT_TSENS_M (BIT(28)) -#define RTC_CNTL_ENT_TSENS_V 0x1 -#define RTC_CNTL_ENT_TSENS_S 28 - -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00bc) +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ /*description: */ #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F @@ -2231,7 +2277,7 @@ extern "C" { #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00c0) +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH4 0xFFFFFFFF @@ -2239,7 +2285,7 @@ extern "C" { #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH4_S 0 -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00c4) +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH5 0xFFFFFFFF @@ -2247,7 +2293,7 @@ extern "C" { #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH5_S 0 -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00c8) +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH6 0xFFFFFFFF @@ -2255,7 +2301,7 @@ extern "C" { #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH6_S 0 -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00cc) +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_SCRATCH7 0xFFFFFFFF @@ -2263,7 +2309,7 @@ extern "C" { #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_S 0 -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00d0) +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ /*description: rtc main state machine status*/ #define RTC_CNTL_MAIN_STATE 0x0000000F @@ -2433,7 +2479,7 @@ extern "C" { #define RTC_CNTL_XPD_ROM0_V 0x1 #define RTC_CNTL_XPD_ROM0_S 0 -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00d4) +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF @@ -2441,7 +2487,7 @@ extern "C" { #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF #define RTC_CNTL_LOW_POWER_DIAG1_S 0 -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00d8) +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) /* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_PAD21_HOLD (BIT(21)) @@ -2575,7 +2621,7 @@ extern "C" { #define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00dc) +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF @@ -2583,7 +2629,7 @@ extern "C" { #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF #define RTC_CNTL_DIG_PAD_HOLD_S 0 -#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00e0) +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ /*description: clear ext wakeup1 status*/ #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) @@ -2597,7 +2643,7 @@ extern "C" { #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00e4) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ /*description: ext wakeup1 status*/ #define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF @@ -2605,7 +2651,7 @@ extern "C" { #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00e8) +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) @@ -2624,6 +2670,12 @@ extern "C" { #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ /*description: enable brown out reset*/ #define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) @@ -2654,8 +2706,14 @@ extern "C" { #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 +/* RTC_CNTL_BROWN_OUT2_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: enable brown_out2 to start chip reset*/ +#define RTC_CNTL_BROWN_OUT2_ENA (BIT(0)) +#define RTC_CNTL_BROWN_OUT2_ENA_M (BIT(0)) +#define RTC_CNTL_BROWN_OUT2_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT2_ENA_S 0 -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00ec) +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: RTC timer low 32 bits*/ #define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF @@ -2663,7 +2721,7 @@ extern "C" { #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00f0) +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: RTC timer high 16 bits*/ #define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF @@ -2671,7 +2729,7 @@ extern "C" { #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00f4) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: xtal 32k watch dog backup clock factor*/ #define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF @@ -2679,7 +2737,7 @@ extern "C" { #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00f8) +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ /*description: if restarted xtal32k period is smaller than this it is regarded as stable*/ #define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F @@ -2705,7 +2763,7 @@ extern "C" { #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 -#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00fc) +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ /*description: ULP-coprocessor timer enable bit*/ #define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) @@ -2724,12 +2782,6 @@ extern "C" { #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 -/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[27:12] ;default: 16'd200 ; */ -/*description: sleep cycles for ULP-coprocessor timer*/ -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x0000FFFF -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFF -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 12 /* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ /*description: ULP-coprocessor PC initial address*/ #define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF @@ -2737,7 +2789,7 @@ extern "C" { #define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF #define RTC_CNTL_ULP_CP_PC_INIT_S 0 -#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) /* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ /*description: Write 1 to start ULP-coprocessor*/ #define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) @@ -2781,42 +2833,42 @@ extern "C" { #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 -#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0104) -/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[24] ;default: 1'b0 ; */ +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) +/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ /*description: trigger cocpu register interrupt*/ -#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(24)) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(24)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) #define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 24 -/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 +/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ /*description: done signal used by riscv to control timer.*/ -#define RTC_CNTL_COCPU_DONE (BIT(23)) -#define RTC_CNTL_COCPU_DONE_M (BIT(23)) +#define RTC_CNTL_COCPU_DONE (BIT(25)) +#define RTC_CNTL_COCPU_DONE_M (BIT(25)) #define RTC_CNTL_COCPU_DONE_V 0x1 -#define RTC_CNTL_COCPU_DONE_S 23 -/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +#define RTC_CNTL_COCPU_DONE_S 25 +/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ /*description: 1: select riscv done 0: select ulp done*/ -#define RTC_CNTL_COCPU_DONE_FORCE (BIT(22)) -#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(22)) +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) #define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 -#define RTC_CNTL_COCPU_DONE_FORCE_S 22 -/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[21] ;default: 1'b1 ; */ +#define RTC_CNTL_COCPU_DONE_FORCE_S 24 +/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ /*description: 1: old ULP 0: new riscV*/ -#define RTC_CNTL_COCPU_SEL (BIT(21)) -#define RTC_CNTL_COCPU_SEL_M (BIT(21)) +#define RTC_CNTL_COCPU_SEL (BIT(23)) +#define RTC_CNTL_COCPU_SEL_M (BIT(23)) #define RTC_CNTL_COCPU_SEL_V 0x1 -#define RTC_CNTL_COCPU_SEL_S 21 -/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +#define RTC_CNTL_COCPU_SEL_S 23 +/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ /*description: to reset cocpu*/ -#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(20)) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(20)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) #define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 -#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 20 -/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[19:14] ;default: 6'd24 ; */ +#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 +/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ /*description: time from shut cocpu to disable clk*/ -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x0000003F +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0x3F +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 /* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ /*description: to shut cocpu*/ @@ -2843,7 +2895,7 @@ extern "C" { #define RTC_CNTL_COCPU_CLK_FO_V 0x1 #define RTC_CNTL_COCPU_CLK_FO_S 0 -#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0108) +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) /* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ /*description: the meas length (in 8MHz)*/ #define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF @@ -2857,7 +2909,7 @@ extern "C" { #define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF #define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 -#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x010c) +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) /* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: touch clock enable*/ #define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) @@ -2876,6 +2928,12 @@ extern "C" { #define RTC_CNTL_TOUCH_RESET_M (BIT(29)) #define RTC_CNTL_TOUCH_RESET_V 0x1 #define RTC_CNTL_TOUCH_RESET_S 29 +/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: force touch timer done*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 /* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ /*description: when a touch pad is active sleep cycle could be divided by this number*/ #define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 @@ -2912,7 +2970,13 @@ extern "C" { #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 -/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h4 ; */ +/* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: 1:use self bias 0:use bandgap bias*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_V 0x1 +#define RTC_CNTL_TOUCH_DBIAS_S 12 +/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ /*description: TOUCH pad0 reference cap*/ #define RTC_CNTL_TOUCH_REFC 0x00000007 #define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) @@ -2943,14 +3007,14 @@ extern "C" { #define RTC_CNTL_TOUCH_DRANGE_V 0x3 #define RTC_CNTL_TOUCH_DRANGE_S 2 -#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0110) +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) /* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ /*description: select out ring pad*/ #define RTC_CNTL_TOUCH_OUT_RING 0x0000000F #define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) #define RTC_CNTL_TOUCH_OUT_RING_V 0xF #define RTC_CNTL_TOUCH_OUT_RING_S 28 -/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h4 ; */ +/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ /*description: touch7 buffer driver strength*/ #define RTC_CNTL_TOUCH_BUFDRV 0x00000007 #define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) @@ -2987,7 +3051,7 @@ extern "C" { #define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 #define RTC_CNTL_TOUCH_DENOISE_RES_S 0 -#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0114) +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) /* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ /*description: */ #define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F @@ -3007,7 +3071,7 @@ extern "C" { #define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF #define RTC_CNTL_TOUCH_SLP_TH_S 0 -#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0118) +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) /* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ /*description: approach pads total meas times*/ #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF @@ -3021,57 +3085,75 @@ extern "C" { #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 -#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011c) +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) /* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ /*description: touch filter enable*/ #define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) #define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) #define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 #define RTC_CNTL_TOUCH_FILTER_EN_S 31 -/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:29] ;default: 2'd1 ; */ +/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ /*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ -#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000003 +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 #define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) -#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x3 -#define RTC_CNTL_TOUCH_FILTER_MODE_S 29 -/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[28:26] ;default: 3'd3 ; */ +#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 +#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 +/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ /*description: debounce counter*/ #define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 #define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) #define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 -#define RTC_CNTL_TOUCH_DEBOUNCE_S 26 -/* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[25:24] ;default: 2'd1 ; */ +#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 +/* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ /*description: */ #define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 #define RTC_CNTL_TOUCH_HYSTERESIS_M ((RTC_CNTL_TOUCH_HYSTERESIS_V)<<(RTC_CNTL_TOUCH_HYSTERESIS_S)) #define RTC_CNTL_TOUCH_HYSTERESIS_V 0x3 -#define RTC_CNTL_TOUCH_HYSTERESIS_S 24 -/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[23:22] ;default: 2'd1 ; */ +#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 +/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ /*description: */ #define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 -#define RTC_CNTL_TOUCH_NOISE_THRES_S 22 -/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[21:20] ;default: 2'd1 ; */ +#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 +/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ /*description: */ #define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x3 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 20 -/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[19:16] ;default: 4'd5 ; */ +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 +/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ /*description: negative threshold counter limit*/ #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)) #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0xF -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 16 -/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[15:12] ;default: 4'd1 ; */ +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 +/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ /*description: touch jitter step*/ #define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F #define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) #define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF -#define RTC_CNTL_TOUCH_JITTER_STEP_S 12 +#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 +/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) +#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0120) +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 +/* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x1 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 /* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) @@ -3163,8 +3245,54 @@ extern "C" { #define RTC_CNTL_USB_VREFH_V 0x3 #define RTC_CNTL_USB_VREFH_S 0 -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0124) -/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810310 ; */ +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 +/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x1FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0138) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908130 ; */ /*description: */ #define RTC_CNTL_CNTL_DATE 0x0FFFFFFF #define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h index 03f2ec0f58..b9fa2b7cba 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h @@ -68,7 +68,7 @@ typedef volatile struct { uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ - uint32_t valid: 1; /*To indicate the register is updated*/ + uint32_t reserved30: 1; uint32_t update: 1; /*Set 1: to update register with RTC timer*/ }; uint32_t val; @@ -188,7 +188,7 @@ typedef volatile struct { uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_time_valid: 1; /*enable RTC time valid interrupt*/ + uint32_t reserved4: 1; uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/ uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/ @@ -212,7 +212,7 @@ typedef volatile struct { uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ - uint32_t rtc_time_valid: 1; /*RTC time valid interrupt raw*/ + uint32_t reserved4: 1; uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ uint32_t rtc_touch_done: 1; /*touch interrupt raw*/ uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/ @@ -236,7 +236,7 @@ typedef volatile struct { uint32_t slp_reject: 1; /*sleep reject interrupt state*/ uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ - uint32_t rtc_time_valid: 1; /*RTC time valid interrupt state*/ + uint32_t reserved4: 1; uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/ uint32_t rtc_touch_done: 1; /*touch done interrupt state*/ uint32_t rtc_touch_active: 1; /*touch active interrupt state*/ @@ -260,7 +260,7 @@ typedef volatile struct { uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ - uint32_t rtc_time_valid: 1; /*Clear RTC time valid interrupt state*/ + uint32_t reserved4: 1; uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/ uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/ uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/ @@ -818,10 +818,21 @@ typedef volatile struct { uint32_t usb_txp: 1; uint32_t usb_tx_en: 1; uint32_t usb_tx_en_override: 1; - uint32_t reserved17: 15; + uint32_t usb_reset_disable: 1; + uint32_t io_mux_reset_disable: 1; + uint32_t reserved19: 13; }; uint32_t val; } usb_conf; + uint32_t reserved_124; + uint32_t reserved_128; + union { + struct { + uint32_t force_download_boot: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } option1; union { struct { uint32_t date: 28; diff --git a/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h b/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h index 2a05740c08..834ee0cc83 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h @@ -50,6 +50,12 @@ extern "C" { #define RTC_I2C_RESET_M (BIT(30)) #define RTC_I2C_RESET_V 0x1 #define RTC_I2C_RESET_S 30 +/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 +#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 /* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: receive lsb first*/ #define RTC_I2C_RX_LSB_FIRST (BIT(5)) @@ -672,7 +678,7 @@ extern "C" { #define RTC_I2C_COMMAND15_S 0 #define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) -/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1711170 ; */ +/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ /*description: */ #define RTC_I2C_DATE 0x0FFFFFFF #define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h b/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h index 7f6193c17b..938df0c58f 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h @@ -171,9 +171,13 @@ typedef volatile struct { } fifo_data; union { struct { - uint32_t command: 14; /*command*/ + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ uint32_t reserved14: 17; - uint32_t done: 1; /*command_done*/ + uint32_t done: 1; /*command0_done*/ }; uint32_t val; } command[16]; diff --git a/components/soc/esp32s2beta/include/soc/rtc_io_reg.h b/components/soc/esp32s2beta/include/soc/rtc_io_reg.h index 3b5167f4e8..3561c4b31b 100644 --- a/components/soc/esp32s2beta/include/soc/rtc_io_reg.h +++ b/components/soc/esp32s2beta/include/soc/rtc_io_reg.h @@ -2265,6 +2265,20 @@ extern "C" { #define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F #define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 +#define RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xE8) +/* RTC_IO_IO_TOUCH_BUFMODE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: BUF_MODE when touch work without fsm*/ +#define RTC_IO_IO_TOUCH_BUFMODE (BIT(4)) +#define RTC_IO_IO_TOUCH_BUFMODE_M (BIT(4)) +#define RTC_IO_IO_TOUCH_BUFMODE_V 0x1 +#define RTC_IO_IO_TOUCH_BUFMODE_S 4 +/* RTC_IO_IO_TOUCH_BUFSEL : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: BUF_SEL when touch work without fsm*/ +#define RTC_IO_IO_TOUCH_BUFSEL 0x0000000F +#define RTC_IO_IO_TOUCH_BUFSEL_M ((RTC_IO_IO_TOUCH_BUFSEL_V)<<(RTC_IO_IO_TOUCH_BUFSEL_S)) +#define RTC_IO_IO_TOUCH_BUFSEL_V 0xF +#define RTC_IO_IO_TOUCH_BUFSEL_S 0 + #define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1FC) /* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1903170 ; */ /*description: */ diff --git a/components/soc/esp32s2beta/include/soc/sens_reg.h b/components/soc/esp32s2beta/include/soc/sens_reg.h index d3cdf38830..9b9052b3ab 100644 --- a/components/soc/esp32s2beta/include/soc/sens_reg.h +++ b/components/soc/esp32s2beta/include/soc/sens_reg.h @@ -1150,7 +1150,7 @@ extern "C" { #define SENS_TOUCH_PAD14_BASELINE_V 0x3FFFFF #define SENS_TOUCH_PAD14_BASELINE_S 0 -#define SENS_SAR_TOUCH_SLP_STATUS_REG (DR_REG_SENS_BASE + 0x0114) +#define SENS_SAR_TOUCH_STATUS15_REG (DR_REG_SENS_BASE + 0x0114) /* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ /*description: */ #define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 @@ -1164,7 +1164,7 @@ extern "C" { #define SENS_TOUCH_SLP_BASELINE_V 0x3FFFFF #define SENS_TOUCH_SLP_BASELINE_S 0 -#define SENS_SAR_TOUCH_APPR_STATUS_REG (DR_REG_SENS_BASE + 0x0118) +#define SENS_SAR_TOUCH_STATUS16_REG (DR_REG_SENS_BASE + 0x0118) /* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ /*description: */ #define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF diff --git a/components/soc/esp32s2beta/include/soc/sens_struct.h b/components/soc/esp32s2beta/include/soc/sens_struct.h index 080c580598..98808fc618 100644 --- a/components/soc/esp32s2beta/include/soc/sens_struct.h +++ b/components/soc/esp32s2beta/include/soc/sens_struct.h @@ -277,14 +277,6 @@ typedef volatile struct { }; uint32_t val; } sar_touch_status[14]; - union { - struct { - uint32_t touch_slp_baseline:22; - uint32_t reserved22: 7; - uint32_t touch_slp_debounce: 3; - }; - uint32_t val; - } sar_touch_slp_status; union { struct { uint32_t touch_approach_pad2_cnt: 8; @@ -293,7 +285,7 @@ typedef volatile struct { uint32_t touch_slp_approach_cnt: 8; }; uint32_t val; - } sar_touch_appr_status; + } sar_touch_status16; union { struct { uint32_t sw_fstep: 16; /*frequency step for CW generator*/ diff --git a/components/soc/esp32s2beta/include/soc/sensitive_reg.h b/components/soc/esp32s2beta/include/soc/sensitive_reg.h index cceee7bd83..ce038e593f 100644 --- a/components/soc/esp32s2beta/include/soc/sensitive_reg.h +++ b/components/soc/esp32s2beta/include/soc/sensitive_reg.h @@ -1193,7 +1193,85 @@ extern "C" { #define DPORT_PRO_I_TAG_RD_ACS_V 0x1 #define DPORT_PRO_I_TAG_RD_ACS_S 0 -#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x0EC) +#define DPORT_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x0EC) +/* DPORT_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CACHE_MMU_ACCESS_LOCK (BIT(0)) +#define DPORT_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) +#define DPORT_CACHE_MMU_ACCESS_LOCK_V 0x1 +#define DPORT_CACHE_MMU_ACCESS_LOCK_S 0 + +#define DPORT_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x0F0) +/* DPORT_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_MMU_WR_ACS (BIT(1)) +#define DPORT_PRO_MMU_WR_ACS_M (BIT(1)) +#define DPORT_PRO_MMU_WR_ACS_V 0x1 +#define DPORT_PRO_MMU_WR_ACS_S 1 +/* DPORT_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_PRO_MMU_RD_ACS (BIT(0)) +#define DPORT_PRO_MMU_RD_ACS_M (BIT(0)) +#define DPORT_PRO_MMU_RD_ACS_V 0x1 +#define DPORT_PRO_MMU_RD_ACS_S 0 + +#define DPORT_APB_PERIPHERAL_INTR_REG (DR_REG_SENSITIVE_BASE + 0x0F4) +/* DPORT_APB_PERI_BYTE_ERROR_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APB_PERI_BYTE_ERROR_INTR (BIT(2)) +#define DPORT_APB_PERI_BYTE_ERROR_INTR_M (BIT(2)) +#define DPORT_APB_PERI_BYTE_ERROR_INTR_V 0x1 +#define DPORT_APB_PERI_BYTE_ERROR_INTR_S 2 +/* DPORT_APB_PERI_BYTE_ERROR_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APB_PERI_BYTE_ERROR_EN (BIT(1)) +#define DPORT_APB_PERI_BYTE_ERROR_EN_M (BIT(1)) +#define DPORT_APB_PERI_BYTE_ERROR_EN_V 0x1 +#define DPORT_APB_PERI_BYTE_ERROR_EN_S 1 +/* DPORT_APB_PERI_BYTE_ERROR_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_APB_PERI_BYTE_ERROR_CLR (BIT(0)) +#define DPORT_APB_PERI_BYTE_ERROR_CLR_M (BIT(0)) +#define DPORT_APB_PERI_BYTE_ERROR_CLR_V 0x1 +#define DPORT_APB_PERI_BYTE_ERROR_CLR_S 0 + +#define DPORT_APB_PERIPHERAL_STATUS_REG (DR_REG_SENSITIVE_BASE + 0x0F8) +/* DPORT_APB_PERI_BYTE_ERROR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_APB_PERI_BYTE_ERROR_ADDR 0xFFFFFFFF +#define DPORT_APB_PERI_BYTE_ERROR_ADDR_M ((DPORT_APB_PERI_BYTE_ERROR_ADDR_V)<<(DPORT_APB_PERI_BYTE_ERROR_ADDR_S)) +#define DPORT_APB_PERI_BYTE_ERROR_ADDR_V 0xFFFFFFFF +#define DPORT_APB_PERI_BYTE_ERROR_ADDR_S 0 + +#define DPORT_CPU_PERIPHERAL_INTR_REG (DR_REG_SENSITIVE_BASE + 0x0FC) +/* DPORT_CPU_PERI_BYTE_ERROR_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_PERI_BYTE_ERROR_INTR (BIT(2)) +#define DPORT_CPU_PERI_BYTE_ERROR_INTR_M (BIT(2)) +#define DPORT_CPU_PERI_BYTE_ERROR_INTR_V 0x1 +#define DPORT_CPU_PERI_BYTE_ERROR_INTR_S 2 +/* DPORT_CPU_PERI_BYTE_ERROR_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_PERI_BYTE_ERROR_EN (BIT(1)) +#define DPORT_CPU_PERI_BYTE_ERROR_EN_M (BIT(1)) +#define DPORT_CPU_PERI_BYTE_ERROR_EN_V 0x1 +#define DPORT_CPU_PERI_BYTE_ERROR_EN_S 1 +/* DPORT_CPU_PERI_BYTE_ERROR_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CPU_PERI_BYTE_ERROR_CLR (BIT(0)) +#define DPORT_CPU_PERI_BYTE_ERROR_CLR_M (BIT(0)) +#define DPORT_CPU_PERI_BYTE_ERROR_CLR_V 0x1 +#define DPORT_CPU_PERI_BYTE_ERROR_CLR_S 0 + +#define DPORT_CPU_PERIPHERAL_STATUS_REG (DR_REG_SENSITIVE_BASE + 0x100) +/* DPORT_CPU_PERI_BYTE_ERROR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define DPORT_CPU_PERI_BYTE_ERROR_ADDR 0xFFFFFFFF +#define DPORT_CPU_PERI_BYTE_ERROR_ADDR_M ((DPORT_CPU_PERI_BYTE_ERROR_ADDR_V)<<(DPORT_CPU_PERI_BYTE_ERROR_ADDR_S)) +#define DPORT_CPU_PERI_BYTE_ERROR_ADDR_V 0xFFFFFFFF +#define DPORT_CPU_PERI_BYTE_ERROR_ADDR_S 0 + +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x104) /* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define SENSITIVE_CLK_EN (BIT(0)) @@ -1202,7 +1280,7 @@ extern "C" { #define SENSITIVE_CLK_EN_S 0 #define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) -/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809042 ; */ +/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905090 ; */ /*description: */ #define SENSITIVE_DATE 0x0FFFFFFF #define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/soc.h b/components/soc/esp32s2beta/include/soc/soc.h index 515f8d643f..a3badcaadc 100644 --- a/components/soc/esp32s2beta/include/soc/soc.h +++ b/components/soc/esp32s2beta/include/soc/soc.h @@ -12,15 +12,15 @@ // See the License for the specific language governing permissions and // limitations under the License. -#pragma once +#ifndef _ESP32_SOC_H_ +#define _ESP32_SOC_H_ #ifndef __ASSEMBLER__ #include #include "esp_assert.h" +#include "esp_bit_defs.h" #endif -#include - #define PRO_CPU_NUM (0) #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space @@ -29,16 +29,16 @@ #define DR_REG_SENSITIVE_BASE 0x3f4c1000 #define DR_REG_INTERRUPT_BASE 0x3f4c2000 #define DR_REG_DMA_COPY_BASE 0x3f4c3000 -#define DR_REG_EXTMEM_BASE 0x3f4c4000 -#define DR_REG_MMU_TABLE 0x3f4c5000 -#define DR_REG_ITAG_TABLE 0x3f4c6000 -#define DR_REG_DTAG_TABLE 0x3f4c7000 -#define DR_REG_AES_BASE 0x3f4c8000 -#define DR_REG_SHA_BASE 0x3f4c9000 -#define DR_REG_RSA_BASE 0x3f4ca000 -#define DR_REG_SECURE_BOOT_BASE 0x3f4cb000 -#define DR_REG_HMAC_BASE 0x3f4cc000 -#define DR_REG_DIGITAL_SINGNATURE_BASE 0x3f4cd000 +#define DR_REG_EXTMEM_BASE 0x61800000 +#define DR_REG_MMU_TABLE 0x61801000 +#define DR_REG_ITAG_TABLE 0x61802000 +#define DR_REG_DTAG_TABLE 0x61803000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 #define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 #define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 #define DR_REG_INTRUSION_BASE 0x3f4d0000 @@ -79,6 +79,7 @@ #define DR_REG_I2C1_EXT_BASE 0x3f427000 #define DR_REG_SPI4_BASE 0x3f437000 #define DR_REG_USB_WRAP_BASE 0x3f439000 +#define DR_REG_APB_SARADC_BASE 0x3f440000 #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) @@ -94,30 +95,68 @@ #define ETS_CACHED_ADDR(addr) (addr) #ifndef __ASSEMBLER__ +#define BIT(nr) (1UL << (nr)) +#else +#define BIT(nr) (1 << (nr)) +#endif + +#ifndef __ASSEMBLER__ + +#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) + +#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM ) +#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); +#else +#define ASSERT_IF_DPORT_REG(_r, OP) +#endif //write value to register -#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) +#define REG_WRITE(_r, _v) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_WRITE); \ + (*(volatile uint32_t *)(_r)) = (_v); \ + }) //read value from register -#define REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define REG_READ(_r) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_READ); \ + (*(volatile uint32_t *)(_r)); \ + }) //get bit or get bits from register -#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) +#define REG_GET_BIT(_r, _b) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) //set bit or set bits to register -#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) +#define REG_SET_BIT(_r, _b) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \ + (*(volatile uint32_t*)(_r) |= (_b)); \ + }) //clear bit or clear bits of register -#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) +#define REG_CLR_BIT(_r, _b) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \ + (*(volatile uint32_t*)(_r) &= ~(_b)); \ + }) //set bits of register controlled by mask -#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) +#define REG_SET_BITS(_r, _b, _m) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \ + (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ + }) //get field from register, uses field _S & _V to determine mask -#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V)) +#define REG_GET_FIELD(_r, _f) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) //set field of a register from variable, uses field _S & _V to determine mask -#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))) +#define REG_SET_FIELD(_r, _f, _v) ({ \ + ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \ + (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ + }) //get field value from a variable, used when _f is not left shifted by _f##_S #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) @@ -138,28 +177,52 @@ #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) //read value from register -#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) +#define READ_PERI_REG(addr) ({ \ + ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) //write value to register -#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) +#define WRITE_PERI_REG(addr, val) ({ \ + ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + }) //clear bits of register controlled by mask -#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) +#define CLEAR_PERI_REG_MASK(reg, mask) ({ \ + ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + }) //set bits of register controlled by mask -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) +#define SET_PERI_REG_MASK(reg, mask) ({ \ + ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + }) //get bits of register controlled by mask -#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) +#define GET_PERI_REG_MASK(reg, mask) ({ \ + ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \ + (READ_PERI_REG(reg) & (mask)); \ + }) //get bits of register controlled by highest bit and lowest bit -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) //set bits of register controlled by mask and shift -#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ + ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \ + (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ + }) //get field of register -#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) #endif /* !__ASSEMBLER__ */ //}} @@ -168,7 +231,7 @@ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP32_DEFAULT_CPU_FREQ_MHZ +#define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define REF_CLK_FREQ ( 1000000 ) #define UART_CLK_FREQ APB_CLK_FREQ @@ -176,14 +239,14 @@ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 40 // CPU is 80MHz -#define GPIO_MATRIX_DELAY_NS 15 +#define GPIO_MATRIX_DELAY_NS 0 //}} /* Overall memory map */ -#define SOC_DROM_LOW 0x3F000000 -#define SOC_DROM_HIGH 0x3F400000 +#define SOC_DROM_LOW 0x3F000000/*drom0 low address for icache*/ +#define SOC_DROM_HIGH 0x3FF80000/*dram0 high address for dcache*/ #define SOC_IROM_LOW 0x40080000 -#define SOC_IROM_HIGH 0x40c00000 +#define SOC_IROM_HIGH 0x40800000 #define SOC_IROM_MASK_LOW 0x40000000 #define SOC_IROM_MASK_HIGH 0x4001A100 #define SOC_IRAM_LOW 0x40020000 @@ -197,9 +260,7 @@ #define SOC_RTC_DATA_LOW 0x50000000 #define SOC_RTC_DATA_HIGH 0x50002000 #define SOC_EXTRAM_DATA_LOW 0x3F500000 -#define SOC_EXTRAM_DATA_HIGH 0x3FF90000 -#define SOC_SLOW_EXTRAM_DATA_LOW 0x61800000 -#define SOC_SLOW_EXTRAM_DATA_HIGH 0x61c00000 +#define SOC_EXTRAM_DATA_HIGH 0x3FF80000 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40020000 @@ -220,97 +281,6 @@ #define SOC_MEM_INTERNAL_LOW 0x3FF9E000 #define SOC_MEM_INTERNAL_HIGH 0x40072000 -//Interrupt hardware source table -//This table is decided by hardware, don't touch this. -#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ -#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ -#define ETS_WIFI_PWR_INTR_SOURCE 2/**< */ -#define ETS_WIFI_BB_INTR_SOURCE 3/**< interrupt of WiFi BB, level, we can do some calibartion*/ -#define ETS_BT_MAC_INTR_SOURCE 4/**< will be cancelled*/ -#define ETS_BT_BB_INTR_SOURCE 5/**< interrupt of BT BB, level*/ -#define ETS_BT_BB_NMI_SOURCE 6/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ -#define ETS_RWBT_INTR_SOURCE 7/**< interrupt of RWBT, level*/ -#define ETS_RWBLE_INTR_SOURCE 8/**< interrupt of RWBLE, level*/ -#define ETS_RWBT_NMI_SOURCE 9/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ -#define ETS_RWBLE_NMI_SOURCE 10/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ -#define ETS_SLC0_INTR_SOURCE 11/**< interrupt of SLC0, level*/ -#define ETS_SLC1_INTR_SOURCE 12/**< interrupt of SLC1, level*/ -#define ETS_UHCI0_INTR_SOURCE 13/**< interrupt of UHCI0, level*/ -#define ETS_UHCI1_INTR_SOURCE 14/**< interrupt of UHCI1, level*/ -#define ETS_TG0_T0_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ -#define ETS_TG0_T1_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ -#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ -#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP0, LACT, level*/ -#define ETS_TG1_T0_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ -#define ETS_TG1_T1_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ -#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ -#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 22/**< interrupt of TIMER_GROUP1, LACT, level*/ -#define ETS_GPIO_INTR_SOURCE 23/**< interrupt of GPIO, level*/ -#define ETS_GPIO_NMI_SOURCE 24/**< interrupt of GPIO, NMI*/ -#define ETS_GPIO_INTR_SOURCE2 25/**< interrupt of GPIO, level*/ -#define ETS_GPIO_NMI_SOURCE2 26/**< interrupt of GPIO, NMI*/ -#define ETS_DEDICATED_GPIO_INTR_SOURCE 27/**< interrupt of dedicated GPIO, level*/ -#define ETS_FROM_CPU_INTR0_SOURCE 28/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ -#define ETS_FROM_CPU_INTR1_SOURCE 29/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ -#define ETS_FROM_CPU_INTR2_SOURCE 30/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ -#define ETS_FROM_CPU_INTR3_SOURCE 31/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ -#define ETS_SPI1_INTR_SOURCE 32/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ -#define ETS_SPI2_INTR_SOURCE 33/**< interrupt of SPI2, level*/ -#define ETS_SPI3_INTR_SOURCE 34/**< interrupt of SPI3, level*/ -#define ETS_I2S0_INTR_SOURCE 35/**< interrupt of I2S0, level*/ -#define ETS_I2S1_INTR_SOURCE 36/**< interrupt of I2S1, level*/ -#define ETS_UART0_INTR_SOURCE 37/**< interrupt of UART0, level*/ -#define ETS_UART1_INTR_SOURCE 38/**< interrupt of UART1, level*/ -#define ETS_UART2_INTR_SOURCE 39/**< interrupt of UART2, level*/ -#define ETS_SDIO_HOST_INTR_SOURCE 40/**< interrupt of SD/SDIO/MMC HOST, level*/ -#define ETS_PWM0_INTR_SOURCE 41/**< interrupt of PWM0, level, Reserved*/ -#define ETS_PWM1_INTR_SOURCE 42/**< interrupt of PWM1, level, Reserved*/ -#define ETS_PWM2_INTR_SOURCE 43/**< interrupt of PWM2, level*/ -#define ETS_PWM3_INTR_SOURCE 44/**< interruot of PWM3, level*/ -#define ETS_LEDC_INTR_SOURCE 45/**< interrupt of LED PWM, level*/ -#define ETS_EFUSE_INTR_SOURCE 46/**< interrupt of efuse, level, not likely to use*/ -#define ETS_CAN_INTR_SOURCE 47/**< interrupt of can, level*/ -#define ETS_USB_INTR_SOURCE 48/**< interrupt of USB, level*/ -#define ETS_RTC_CORE_INTR_SOURCE 49/**< interrupt of rtc core, level, include rtc watchdog*/ -#define ETS_RMT_INTR_SOURCE 50/**< interrupt of remote controller, level*/ -#define ETS_PCNT_INTR_SOURCE 51/**< interrupt of pluse count, level*/ -#define ETS_I2C_EXT0_INTR_SOURCE 52/**< interrupt of I2C controller1, level*/ -#define ETS_I2C_EXT1_INTR_SOURCE 53/**< interrupt of I2C controller0, level*/ -#define ETS_RSA_INTR_SOURCE 54/**< interrupt of RSA accelerator, level*/ -#define ETS_SPI1_DMA_INTR_SOURCE 55/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ -#define ETS_SPI2_DMA_INTR_SOURCE 56/**< interrupt of SPI2 DMA, level*/ -#define ETS_SPI3_DMA_INTR_SOURCE 57/**< interrupt of SPI3 DMA, level*/ -#define ETS_WDT_INTR_SOURCE 58/**< will be cancelled*/ -#define ETS_TIMER1_INTR_SOURCE 59/**< will be cancelled*/ -#define ETS_TIMER2_INTR_SOURCE 60/**< will be cancelled*/ -#define ETS_TG0_T0_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ -#define ETS_TG0_T1_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ -#define ETS_TG0_WDT_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ -#define ETS_TG0_LACT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ -#define ETS_TG1_T0_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ -#define ETS_TG1_T1_EDGE_INTR_SOURCE 66/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ -#define ETS_TG1_WDT_EDGE_INTR_SOURCE 67/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ -#define ETS_TG1_LACT_EDGE_INTR_SOURCE 68/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ -#define ETS_CACHE_IA_INTR_SOURCE 69/**< interrupt of Cache Invalied Access, LEVEL*/ -#define ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE 70/**< interrupt of system timer 0, EDGE*/ -#define ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE 71/**< interrupt of system timer 1, EDGE*/ -#define ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE 72/**< interrupt of system timer 2, EDGE*/ -#define ETS_ASSIST_DEBUG_INTR_SOURCE 73/**< interrupt of Assist debug module, LEVEL*/ -#define ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE 74/**< interrupt of illegal IRAM1 access, LEVEL*/ -#define ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE 75/**< interrupt of illegal DRAM0 access, LEVEL*/ -#define ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE 76/**< interrupt of illegal DPORT access, LEVEL*/ -#define ETS_PMS_PRO_AHB_ILG_INTR_SOURCE 77/**< interrupt of illegal AHB access, LEVEL*/ -#define ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE 78/**< interrupt of illegal CACHE access, LEVEL*/ -#define ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE 79/**< interrupt of illegal APB access, LEVEL*/ -#define ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE 80/**< interrupt of illegal DMA RX access, LEVEL*/ -#define ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE 81/**< interrupt of illegal DMA TX access, LEVEL*/ -#define ETS_SPI0_REJECT_CACHE_INTR_SOURCE 82/**< interrupt of SPI0 Cache access rejected, LEVEL*/ -#define ETS_SPI1_REJECT_CPU_INTR_SOURCE 83/**< interrupt of SPI1 access rejected, LEVEL*/ -#define ETS_DMA_COPY_INTR_SOURCE 84/**< interrupt of DMA copy, LEVEL*/ -#define ETS_SPI4_DMA_INTR_SOURCE 85/**< interrupt of SPI4 DMA, LEVEL*/ -#define ETS_SPI4_INTR_SOURCE 86/**< interrupt of SPI4, LEVEL*/ -#define ETS_MAX_INTR_SOURCE 87/**< number of interrupt sources */ - //interrupt cpu using table, Please see the core-isa.h /************************************************************************************************************* * Intr num Level Type PRO CPU usage APP CPU uasge @@ -342,7 +312,7 @@ * 25 4 extern level CACHEERR * 26 5 extern level * 27 3 extern level Reserved Reserved - * 28 4 extern edge + * 28 4 extern edge DPORT ACCESS DPORT ACCESS * 29 3 software Reserved Reserved * 30 4 extern edge Reserved Reserved * 31 5 extern level @@ -357,11 +327,13 @@ #define ETS_FRC1_INUM 22 #define ETS_T1_WDT_INUM 24 #define ETS_CACHEERR_INUM 25 +#define ETS_DPORT_INUM 28 //CPU0 Interrupt number used in ROM, should be cancelled in SDK #define ETS_SLC_INUM 1 #define ETS_UART0_INUM 5 #define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 //CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. #define ETS_FRC_TIMER2_INUM 10 /* use edge*/ #define ETS_GPIO_INUM 4 @@ -370,3 +342,5 @@ //Invalid interrupt for number interrupt matrix #define ETS_INVALID_INUM 6 + +#endif /* _ESP32_SOC_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/spi_caps.h b/components/soc/esp32s2beta/include/soc/spi_caps.h index cb47a14d68..00d7e2ba51 100644 --- a/components/soc/esp32s2beta/include/soc/spi_caps.h +++ b/components/soc/esp32s2beta/include/soc/spi_caps.h @@ -45,5 +45,4 @@ #define SOC_SPI_SUPPORT_CD_SIG 1 // Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3 \ - || (void*)spi_dev == (void*)&GPSPI4)) +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3)) diff --git a/components/soc/esp32s2beta/include/soc/spi_mem_reg.h b/components/soc/esp32s2beta/include/soc/spi_mem_reg.h index dfe4be5ce8..ef3bab18fc 100644 --- a/components/soc/esp32s2beta/include/soc/spi_mem_reg.h +++ b/components/soc/esp32s2beta/include/soc/spi_mem_reg.h @@ -217,6 +217,12 @@ extern "C" { #define SPI_MEM_FCS_CRC_EN_M (BIT(10)) #define SPI_MEM_FCS_CRC_EN_V 0x1 #define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 /* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ /*description: Apply 4 signals during command phase 1:enable 0: disable*/ #define SPI_MEM_FCMD_QUAD (BIT(8)) @@ -229,12 +235,30 @@ extern "C" { #define SPI_MEM_FCMD_DUAL_M (BIT(7)) #define SPI_MEM_FCMD_DUAL_V 0x1 #define SPI_MEM_FCMD_DUAL_S 7 -/* SPI_MEM_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 8 signals during address phase 1:enable 0: disable*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 +/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 8 signals during read-data phase 1:enable 0: disable*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 +/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Apply 8 signals during write-data phase 1:enable 0: disable*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 +/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: In the dummy phase the signal level of spi is output by the spi controller.*/ -#define SPI_MEM_DUMMY_OUT (BIT(3)) -#define SPI_MEM_DUMMY_OUT_M (BIT(3)) -#define SPI_MEM_DUMMY_OUT_V 0x1 -#define SPI_MEM_DUMMY_OUT_S 3 +#define SPI_MEM_FDUMMY_OUT (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_V 0x1 +#define SPI_MEM_FDUMMY_OUT_S 3 #define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C) /* SPI_MEM_CS_DLY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ @@ -630,6 +654,12 @@ extern "C" { #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0xFF #define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: reserved*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 /* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ /*description: For SPI0 In the spi sram mode cache write sram for user define command*/ #define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) @@ -691,6 +721,36 @@ extern "C" { #define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 #define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x044) +/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ +#define SPI_MEM_SDUMMY_OUT (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_V 0x1 +#define SPI_MEM_SDUMMY_OUT_S 22 +/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 +/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 +/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 +/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 /* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ /*description: For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ @@ -831,561 +891,7 @@ extern "C" { #define SPI_MEM_ST_V 0x7 #define SPI_MEM_ST_S 0 -#define SPI_MEM_HOLD_REG(i) (REG_SPI_MEM_BASE(i) + 0x058) -/* SPI_MEM_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'd3 ; */ -/*description: This register is for two SPI masters to share the same cs clock - and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/ -#define SPI_MEM_HOLD_ENA 0x00000003 -#define SPI_MEM_HOLD_ENA_M ((SPI_MEM_HOLD_ENA_V)<<(SPI_MEM_HOLD_ENA_S)) -#define SPI_MEM_HOLD_ENA_V 0x3 -#define SPI_MEM_HOLD_ENA_S 0 - -#define SPI_MEM_DMA_CONF_REG(i) (REG_SPI_MEM_BASE(i) + 0x05C) -/* SPI_MEM_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: spi dma continue tx/rx data.*/ -#define SPI_MEM_DMA_CONTINUE (BIT(16)) -#define SPI_MEM_DMA_CONTINUE_M (BIT(16)) -#define SPI_MEM_DMA_CONTINUE_V 0x1 -#define SPI_MEM_DMA_CONTINUE_S 16 -/* SPI_MEM_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: spi dma write data stop when in continue tx/rx mode.*/ -#define SPI_MEM_DMA_TX_STOP (BIT(15)) -#define SPI_MEM_DMA_TX_STOP_M (BIT(15)) -#define SPI_MEM_DMA_TX_STOP_V 0x1 -#define SPI_MEM_DMA_TX_STOP_S 15 -/* SPI_MEM_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: spi dma read data stop when in continue tx/rx mode.*/ -#define SPI_MEM_DMA_RX_STOP (BIT(14)) -#define SPI_MEM_DMA_RX_STOP_M (BIT(14)) -#define SPI_MEM_DMA_RX_STOP_V 0x1 -#define SPI_MEM_DMA_RX_STOP_S 14 -/* SPI_MEM_DMA_MEM_TRANS_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: reserved*/ -#define SPI_MEM_DMA_MEM_TRANS_ENA (BIT(13)) -#define SPI_MEM_DMA_MEM_TRANS_ENA_M (BIT(13)) -#define SPI_MEM_DMA_MEM_TRANS_ENA_V 0x1 -#define SPI_MEM_DMA_MEM_TRANS_ENA_S 13 -/* SPI_MEM_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: spi dma read data from memory in burst mode.*/ -#define SPI_MEM_OUT_DATA_BURST_EN (BIT(12)) -#define SPI_MEM_OUT_DATA_BURST_EN_M (BIT(12)) -#define SPI_MEM_OUT_DATA_BURST_EN_V 0x1 -#define SPI_MEM_OUT_DATA_BURST_EN_S 12 -/* SPI_MEM_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: read descriptor use burst mode when write data to memory.*/ -#define SPI_MEM_INDSCR_BURST_EN (BIT(11)) -#define SPI_MEM_INDSCR_BURST_EN_M (BIT(11)) -#define SPI_MEM_INDSCR_BURST_EN_V 0x1 -#define SPI_MEM_INDSCR_BURST_EN_S 11 -/* SPI_MEM_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: read descriptor use burst mode when read data for memory.*/ -#define SPI_MEM_OUTDSCR_BURST_EN (BIT(10)) -#define SPI_MEM_OUTDSCR_BURST_EN_M (BIT(10)) -#define SPI_MEM_OUTDSCR_BURST_EN_V 0x1 -#define SPI_MEM_OUTDSCR_BURST_EN_S 10 -/* SPI_MEM_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: out eof flag generation mode . 1: when dma pop all data from - fifo 0:when ahb push all data to fifo.*/ -#define SPI_MEM_OUT_EOF_MODE (BIT(9)) -#define SPI_MEM_OUT_EOF_MODE_M (BIT(9)) -#define SPI_MEM_OUT_EOF_MODE_V 0x1 -#define SPI_MEM_OUT_EOF_MODE_S 9 -/* SPI_MEM_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: when the bit is set DMA continue to use the next inlink node - when the length of inlink is 0.*/ -#define SPI_MEM_OUT_AUTO_WRBACK (BIT(8)) -#define SPI_MEM_OUT_AUTO_WRBACK_M (BIT(8)) -#define SPI_MEM_OUT_AUTO_WRBACK_V 0x1 -#define SPI_MEM_OUT_AUTO_WRBACK_S 8 -/* SPI_MEM_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set bit to test out link.*/ -#define SPI_MEM_OUT_LOOP_TEST (BIT(7)) -#define SPI_MEM_OUT_LOOP_TEST_M (BIT(7)) -#define SPI_MEM_OUT_LOOP_TEST_V 0x1 -#define SPI_MEM_OUT_LOOP_TEST_S 7 -/* SPI_MEM_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set bit to test in link.*/ -#define SPI_MEM_IN_LOOP_TEST (BIT(6)) -#define SPI_MEM_IN_LOOP_TEST_M (BIT(6)) -#define SPI_MEM_IN_LOOP_TEST_V 0x1 -#define SPI_MEM_IN_LOOP_TEST_S 6 -/* SPI_MEM_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Reset spi dma ahb master.*/ -#define SPI_MEM_AHBM_RST (BIT(5)) -#define SPI_MEM_AHBM_RST_M (BIT(5)) -#define SPI_MEM_AHBM_RST_V 0x1 -#define SPI_MEM_AHBM_RST_S 5 -/* SPI_MEM_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Reset spi dma ahb master fifo pointer.*/ -#define SPI_MEM_AHBM_FIFO_RST (BIT(4)) -#define SPI_MEM_AHBM_FIFO_RST_M (BIT(4)) -#define SPI_MEM_AHBM_FIFO_RST_V 0x1 -#define SPI_MEM_AHBM_FIFO_RST_S 4 -/* SPI_MEM_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/ -#define SPI_MEM_OUT_RST (BIT(3)) -#define SPI_MEM_OUT_RST_M (BIT(3)) -#define SPI_MEM_OUT_RST_V 0x1 -#define SPI_MEM_OUT_RST_S 3 -/* SPI_MEM_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/ -#define SPI_MEM_IN_RST (BIT(2)) -#define SPI_MEM_IN_RST_M (BIT(2)) -#define SPI_MEM_IN_RST_V 0x1 -#define SPI_MEM_IN_RST_S 2 -/* SPI_MEM_DMA_TX_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: spi dma tx data enable.*/ -#define SPI_MEM_DMA_TX_ENA (BIT(1)) -#define SPI_MEM_DMA_TX_ENA_M (BIT(1)) -#define SPI_MEM_DMA_TX_ENA_V 0x1 -#define SPI_MEM_DMA_TX_ENA_S 1 -/* SPI_MEM_DMA_RX_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: spi dma rx data enable.*/ -#define SPI_MEM_DMA_RX_ENA (BIT(0)) -#define SPI_MEM_DMA_RX_ENA_M (BIT(0)) -#define SPI_MEM_DMA_RX_ENA_V 0x1 -#define SPI_MEM_DMA_RX_ENA_S 0 - -#define SPI_MEM_DMA_OUT_LINK_REG(i) (REG_SPI_MEM_BASE(i) + 0x060) -/* SPI_MEM_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set the bit to mount on new outlink descriptors.*/ -#define SPI_MEM_OUTLINK_RESTART (BIT(30)) -#define SPI_MEM_OUTLINK_RESTART_M (BIT(30)) -#define SPI_MEM_OUTLINK_RESTART_V 0x1 -#define SPI_MEM_OUTLINK_RESTART_S 30 -/* SPI_MEM_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set the bit to start to use outlink descriptor.*/ -#define SPI_MEM_OUTLINK_START (BIT(29)) -#define SPI_MEM_OUTLINK_START_M (BIT(29)) -#define SPI_MEM_OUTLINK_START_V 0x1 -#define SPI_MEM_OUTLINK_START_S 29 -/* SPI_MEM_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set the bit to stop to use outlink descriptor.*/ -#define SPI_MEM_OUTLINK_STOP (BIT(28)) -#define SPI_MEM_OUTLINK_STOP_M (BIT(28)) -#define SPI_MEM_OUTLINK_STOP_V 0x1 -#define SPI_MEM_OUTLINK_STOP_S 28 -/* SPI_MEM_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The address of the first outlink descriptor.*/ -#define SPI_MEM_OUTLINK_ADDR 0x000FFFFF -#define SPI_MEM_OUTLINK_ADDR_M ((SPI_MEM_OUTLINK_ADDR_V)<<(SPI_MEM_OUTLINK_ADDR_S)) -#define SPI_MEM_OUTLINK_ADDR_V 0xFFFFF -#define SPI_MEM_OUTLINK_ADDR_S 0 - -#define SPI_MEM_DMA_IN_LINK_REG(i) (REG_SPI_MEM_BASE(i) + 0x064) -/* SPI_MEM_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set the bit to mount on new inlink descriptors.*/ -#define SPI_MEM_INLINK_RESTART (BIT(30)) -#define SPI_MEM_INLINK_RESTART_M (BIT(30)) -#define SPI_MEM_INLINK_RESTART_V 0x1 -#define SPI_MEM_INLINK_RESTART_S 30 -/* SPI_MEM_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set the bit to start to use inlink descriptor.*/ -#define SPI_MEM_INLINK_START (BIT(29)) -#define SPI_MEM_INLINK_START_M (BIT(29)) -#define SPI_MEM_INLINK_START_V 0x1 -#define SPI_MEM_INLINK_START_S 29 -/* SPI_MEM_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set the bit to stop to use inlink descriptor.*/ -#define SPI_MEM_INLINK_STOP (BIT(28)) -#define SPI_MEM_INLINK_STOP_M (BIT(28)) -#define SPI_MEM_INLINK_STOP_V 0x1 -#define SPI_MEM_INLINK_STOP_S 28 -/* SPI_MEM_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: when the bit is set the inlink descriptor returns to the first - link node when a packet is error.*/ -#define SPI_MEM_INLINK_AUTO_RET (BIT(20)) -#define SPI_MEM_INLINK_AUTO_RET_M (BIT(20)) -#define SPI_MEM_INLINK_AUTO_RET_V 0x1 -#define SPI_MEM_INLINK_AUTO_RET_S 20 -/* SPI_MEM_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The address of the first inlink descriptor.*/ -#define SPI_MEM_INLINK_ADDR 0x000FFFFF -#define SPI_MEM_INLINK_ADDR_M ((SPI_MEM_INLINK_ADDR_V)<<(SPI_MEM_INLINK_ADDR_S)) -#define SPI_MEM_INLINK_ADDR_V 0xFFFFF -#define SPI_MEM_INLINK_ADDR_S 0 - -#define SPI_MEM_DMA_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0x068) -/* SPI_MEM_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for sending all the packets to host done.*/ -#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA_V 0x1 -#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA_S 8 -/* SPI_MEM_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for sending a packet to host done.*/ -#define SPI_MEM_OUT_EOF_INT_ENA (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_ENA_M (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_ENA_V 0x1 -#define SPI_MEM_OUT_EOF_INT_ENA_S 7 -/* SPI_MEM_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a outlink descriptor .*/ -#define SPI_MEM_OUT_DONE_INT_ENA (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_ENA_M (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_ENA_V 0x1 -#define SPI_MEM_OUT_DONE_INT_ENA_S 6 -/* SPI_MEM_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for completing receiving all the packets from host.*/ -#define SPI_MEM_IN_SUC_EOF_INT_ENA (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_ENA_M (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_ENA_V 0x1 -#define SPI_MEM_IN_SUC_EOF_INT_ENA_S 5 -/* SPI_MEM_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for receiving error.*/ -#define SPI_MEM_IN_ERR_EOF_INT_ENA (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_ENA_M (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_ENA_V 0x1 -#define SPI_MEM_IN_ERR_EOF_INT_ENA_S 4 -/* SPI_MEM_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a inlink descriptor.*/ -#define SPI_MEM_IN_DONE_INT_ENA (BIT(3)) -#define SPI_MEM_IN_DONE_INT_ENA_M (BIT(3)) -#define SPI_MEM_IN_DONE_INT_ENA_V 0x1 -#define SPI_MEM_IN_DONE_INT_ENA_S 3 -/* SPI_MEM_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for inlink descriptor error.*/ -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA_V 0x1 -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA_S 2 -/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for outlink descriptor error.*/ -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA_S 1 -/* SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for lack of enough inlink descriptors.*/ -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA_S 0 - -#define SPI_MEM_DMA_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0x06C) -/* SPI_MEM_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw bit for sending all the packets to host done.*/ -#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW_V 0x1 -#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW_S 8 -/* SPI_MEM_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw bit for sending a packet to host done.*/ -#define SPI_MEM_OUT_EOF_INT_RAW (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_RAW_M (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_RAW_V 0x1 -#define SPI_MEM_OUT_EOF_INT_RAW_S 7 -/* SPI_MEM_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a outlink descriptor.*/ -#define SPI_MEM_OUT_DONE_INT_RAW (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_RAW_M (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_RAW_V 0x1 -#define SPI_MEM_OUT_DONE_INT_RAW_S 6 -/* SPI_MEM_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit for completing receiving all the packets from host.*/ -#define SPI_MEM_IN_SUC_EOF_INT_RAW (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_RAW_M (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_RAW_V 0x1 -#define SPI_MEM_IN_SUC_EOF_INT_RAW_S 5 -/* SPI_MEM_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit for receiving error.*/ -#define SPI_MEM_IN_ERR_EOF_INT_RAW (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_RAW_M (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_RAW_V 0x1 -#define SPI_MEM_IN_ERR_EOF_INT_RAW_S 4 -/* SPI_MEM_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a inlink descriptor.*/ -#define SPI_MEM_IN_DONE_INT_RAW (BIT(3)) -#define SPI_MEM_IN_DONE_INT_RAW_M (BIT(3)) -#define SPI_MEM_IN_DONE_INT_RAW_V 0x1 -#define SPI_MEM_IN_DONE_INT_RAW_S 3 -/* SPI_MEM_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for inlink descriptor error.*/ -#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW_V 0x1 -#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW_S 2 -/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for outlink descriptor error.*/ -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW_S 1 -/* SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for lack of enough inlink descriptors.*/ -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW_S 0 - -#define SPI_MEM_DMA_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0x070) -/* SPI_MEM_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The status bit for sending all the packets to host done.*/ -#define SPI_MEM_OUT_TOTAL_EOF_INT_ST (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_ST_V 0x1 -#define SPI_MEM_OUT_TOTAL_EOF_INT_ST_S 8 -/* SPI_MEM_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The status bit for sending a packet to host done.*/ -#define SPI_MEM_OUT_EOF_INT_ST (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_ST_M (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_ST_V 0x1 -#define SPI_MEM_OUT_EOF_INT_ST_S 7 -/* SPI_MEM_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The status bit for completing usage of a outlink descriptor.*/ -#define SPI_MEM_OUT_DONE_INT_ST (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_ST_M (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_ST_V 0x1 -#define SPI_MEM_OUT_DONE_INT_ST_S 6 -/* SPI_MEM_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The status bit for completing receiving all the packets from host.*/ -#define SPI_MEM_IN_SUC_EOF_INT_ST (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_ST_M (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_ST_V 0x1 -#define SPI_MEM_IN_SUC_EOF_INT_ST_S 5 -/* SPI_MEM_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The status bit for receiving error.*/ -#define SPI_MEM_IN_ERR_EOF_INT_ST (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_ST_M (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_ST_V 0x1 -#define SPI_MEM_IN_ERR_EOF_INT_ST_S 4 -/* SPI_MEM_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for completing usage of a inlink descriptor.*/ -#define SPI_MEM_IN_DONE_INT_ST (BIT(3)) -#define SPI_MEM_IN_DONE_INT_ST_M (BIT(3)) -#define SPI_MEM_IN_DONE_INT_ST_V 0x1 -#define SPI_MEM_IN_DONE_INT_ST_S 3 -/* SPI_MEM_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for inlink descriptor error.*/ -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST_V 0x1 -#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST_S 2 -/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for outlink descriptor error.*/ -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST_S 1 -/* SPI_MEM_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for lack of enough inlink descriptors.*/ -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST_V 0x1 -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST_S 0 - -#define SPI_MEM_DMA_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0x074) -/* SPI_MEM_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The clear bit for sending all the packets to host done.*/ -#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) -#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR_V 0x1 -#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR_S 8 -/* SPI_MEM_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The clear bit for sending a packet to host done.*/ -#define SPI_MEM_OUT_EOF_INT_CLR (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_CLR_M (BIT(7)) -#define SPI_MEM_OUT_EOF_INT_CLR_V 0x1 -#define SPI_MEM_OUT_EOF_INT_CLR_S 7 -/* SPI_MEM_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a outlink descriptor.*/ -#define SPI_MEM_OUT_DONE_INT_CLR (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_CLR_M (BIT(6)) -#define SPI_MEM_OUT_DONE_INT_CLR_V 0x1 -#define SPI_MEM_OUT_DONE_INT_CLR_S 6 -/* SPI_MEM_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The clear bit for completing receiving all the packets from host.*/ -#define SPI_MEM_IN_SUC_EOF_INT_CLR (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_CLR_M (BIT(5)) -#define SPI_MEM_IN_SUC_EOF_INT_CLR_V 0x1 -#define SPI_MEM_IN_SUC_EOF_INT_CLR_S 5 -/* SPI_MEM_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The clear bit for receiving error.*/ -#define SPI_MEM_IN_ERR_EOF_INT_CLR (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_CLR_M (BIT(4)) -#define SPI_MEM_IN_ERR_EOF_INT_CLR_V 0x1 -#define SPI_MEM_IN_ERR_EOF_INT_CLR_S 4 -/* SPI_MEM_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a inlink descriptor.*/ -#define SPI_MEM_IN_DONE_INT_CLR (BIT(3)) -#define SPI_MEM_IN_DONE_INT_CLR_M (BIT(3)) -#define SPI_MEM_IN_DONE_INT_CLR_V 0x1 -#define SPI_MEM_IN_DONE_INT_CLR_S 3 -/* SPI_MEM_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for inlink descriptor error.*/ -#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) -#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR_V 0x1 -#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR_S 2 -/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for outlink descriptor error.*/ -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 -#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR_S 1 -/* SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for lack of enough inlink descriptors.*/ -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 -#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR_S 0 - -#define SPI_MEM_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x078) -/* SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The inlink descriptor address when spi dma produce receiving error.*/ -#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_S)) -#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_S 0 - -#define SPI_MEM_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x07C) -/* SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/ -#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_S)) -#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_S 0 - -#define SPI_MEM_INLINK_DSCR_REG(i) (REG_SPI_MEM_BASE(i) + 0x080) -/* SPI_MEM_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current in descriptor pointer.*/ -#define SPI_MEM_DMA_INLINK_DSCR 0xFFFFFFFF -#define SPI_MEM_DMA_INLINK_DSCR_M ((SPI_MEM_DMA_INLINK_DSCR_V)<<(SPI_MEM_DMA_INLINK_DSCR_S)) -#define SPI_MEM_DMA_INLINK_DSCR_V 0xFFFFFFFF -#define SPI_MEM_DMA_INLINK_DSCR_S 0 - -#define SPI_MEM_INLINK_DSCR_BF0_REG(i) (REG_SPI_MEM_BASE(i) + 0x084) -/* SPI_MEM_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of next in descriptor pointer.*/ -#define SPI_MEM_DMA_INLINK_DSCR_BF0 0xFFFFFFFF -#define SPI_MEM_DMA_INLINK_DSCR_BF0_M ((SPI_MEM_DMA_INLINK_DSCR_BF0_V)<<(SPI_MEM_DMA_INLINK_DSCR_BF0_S)) -#define SPI_MEM_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF -#define SPI_MEM_DMA_INLINK_DSCR_BF0_S 0 - -#define SPI_MEM_INLINK_DSCR_BF1_REG(i) (REG_SPI_MEM_BASE(i) + 0x088) -/* SPI_MEM_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current in descriptor data buffer pointer.*/ -#define SPI_MEM_DMA_INLINK_DSCR_BF1 0xFFFFFFFF -#define SPI_MEM_DMA_INLINK_DSCR_BF1_M ((SPI_MEM_DMA_INLINK_DSCR_BF1_V)<<(SPI_MEM_DMA_INLINK_DSCR_BF1_S)) -#define SPI_MEM_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF -#define SPI_MEM_DMA_INLINK_DSCR_BF1_S 0 - -#define SPI_MEM_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x08C) -/* SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The address of buffer relative to the outlink descriptor that produce eof.*/ -#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF -#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_S)) -#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF -#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_S 0 - -#define SPI_MEM_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x090) -/* SPI_MEM_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The last outlink descriptor address when spi dma produce to_eof.*/ -#define SPI_MEM_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF -#define SPI_MEM_DMA_OUT_EOF_DES_ADDR_M ((SPI_MEM_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_MEM_DMA_OUT_EOF_DES_ADDR_S)) -#define SPI_MEM_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF -#define SPI_MEM_DMA_OUT_EOF_DES_ADDR_S 0 - -#define SPI_MEM_OUTLINK_DSCR_REG(i) (REG_SPI_MEM_BASE(i) + 0x094) -/* SPI_MEM_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current out descriptor pointer.*/ -#define SPI_MEM_DMA_OUTLINK_DSCR 0xFFFFFFFF -#define SPI_MEM_DMA_OUTLINK_DSCR_M ((SPI_MEM_DMA_OUTLINK_DSCR_V)<<(SPI_MEM_DMA_OUTLINK_DSCR_S)) -#define SPI_MEM_DMA_OUTLINK_DSCR_V 0xFFFFFFFF -#define SPI_MEM_DMA_OUTLINK_DSCR_S 0 - -#define SPI_MEM_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_MEM_BASE(i) + 0x098) -/* SPI_MEM_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of next out descriptor pointer.*/ -#define SPI_MEM_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF -#define SPI_MEM_DMA_OUTLINK_DSCR_BF0_M ((SPI_MEM_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_MEM_DMA_OUTLINK_DSCR_BF0_S)) -#define SPI_MEM_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF -#define SPI_MEM_DMA_OUTLINK_DSCR_BF0_S 0 - -#define SPI_MEM_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_MEM_BASE(i) + 0x09C) -/* SPI_MEM_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: The content of current out descriptor data buffer pointer.*/ -#define SPI_MEM_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF -#define SPI_MEM_DMA_OUTLINK_DSCR_BF1_M ((SPI_MEM_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_MEM_DMA_OUTLINK_DSCR_BF1_S)) -#define SPI_MEM_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF -#define SPI_MEM_DMA_OUTLINK_DSCR_BF1_S 0 - -#define SPI_MEM_DMA_OUTSTATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A0) -/* SPI_MEM_DMA_OUTFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ -/*description: SPI dma outfifo is empty.*/ -#define SPI_MEM_DMA_OUTFIFO_EMPTY (BIT(31)) -#define SPI_MEM_DMA_OUTFIFO_EMPTY_M (BIT(31)) -#define SPI_MEM_DMA_OUTFIFO_EMPTY_V 0x1 -#define SPI_MEM_DMA_OUTFIFO_EMPTY_S 31 -/* SPI_MEM_DMA_OUTFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: SPI dma outfifo is full.*/ -#define SPI_MEM_DMA_OUTFIFO_FULL (BIT(30)) -#define SPI_MEM_DMA_OUTFIFO_FULL_M (BIT(30)) -#define SPI_MEM_DMA_OUTFIFO_FULL_V 0x1 -#define SPI_MEM_DMA_OUTFIFO_FULL_S 30 -/* SPI_MEM_DMA_OUTFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */ -/*description: The remains of SPI dma outfifo data.*/ -#define SPI_MEM_DMA_OUTFIFO_CNT 0x0000007F -#define SPI_MEM_DMA_OUTFIFO_CNT_M ((SPI_MEM_DMA_OUTFIFO_CNT_V)<<(SPI_MEM_DMA_OUTFIFO_CNT_S)) -#define SPI_MEM_DMA_OUTFIFO_CNT_V 0x7F -#define SPI_MEM_DMA_OUTFIFO_CNT_S 23 -/* SPI_MEM_DMA_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: SPI dma out data state.*/ -#define SPI_MEM_DMA_OUT_STATE 0x00000007 -#define SPI_MEM_DMA_OUT_STATE_M ((SPI_MEM_DMA_OUT_STATE_V)<<(SPI_MEM_DMA_OUT_STATE_S)) -#define SPI_MEM_DMA_OUT_STATE_V 0x7 -#define SPI_MEM_DMA_OUT_STATE_S 20 -/* SPI_MEM_DMA_OUTDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: SPI dma out descriptor state.*/ -#define SPI_MEM_DMA_OUTDSCR_STATE 0x00000003 -#define SPI_MEM_DMA_OUTDSCR_STATE_M ((SPI_MEM_DMA_OUTDSCR_STATE_V)<<(SPI_MEM_DMA_OUTDSCR_STATE_S)) -#define SPI_MEM_DMA_OUTDSCR_STATE_V 0x3 -#define SPI_MEM_DMA_OUTDSCR_STATE_S 18 -/* SPI_MEM_DMA_OUTDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: SPI dma out descriptor address.*/ -#define SPI_MEM_DMA_OUTDSCR_ADDR 0x0003FFFF -#define SPI_MEM_DMA_OUTDSCR_ADDR_M ((SPI_MEM_DMA_OUTDSCR_ADDR_V)<<(SPI_MEM_DMA_OUTDSCR_ADDR_S)) -#define SPI_MEM_DMA_OUTDSCR_ADDR_V 0x3FFFF -#define SPI_MEM_DMA_OUTDSCR_ADDR_S 0 - -#define SPI_MEM_DMA_INSTATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A4) -/* SPI_MEM_DMA_INFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ -/*description: SPI dma infifo is empty.*/ -#define SPI_MEM_DMA_INFIFO_EMPTY (BIT(31)) -#define SPI_MEM_DMA_INFIFO_EMPTY_M (BIT(31)) -#define SPI_MEM_DMA_INFIFO_EMPTY_V 0x1 -#define SPI_MEM_DMA_INFIFO_EMPTY_S 31 -/* SPI_MEM_DMA_INFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: SPI dma infifo is full.*/ -#define SPI_MEM_DMA_INFIFO_FULL (BIT(30)) -#define SPI_MEM_DMA_INFIFO_FULL_M (BIT(30)) -#define SPI_MEM_DMA_INFIFO_FULL_V 0x1 -#define SPI_MEM_DMA_INFIFO_FULL_S 30 -/* SPI_MEM_DMA_INFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */ -/*description: The remains of SPI dma infifo data.*/ -#define SPI_MEM_DMA_INFIFO_CNT 0x0000007F -#define SPI_MEM_DMA_INFIFO_CNT_M ((SPI_MEM_DMA_INFIFO_CNT_V)<<(SPI_MEM_DMA_INFIFO_CNT_S)) -#define SPI_MEM_DMA_INFIFO_CNT_V 0x7F -#define SPI_MEM_DMA_INFIFO_CNT_S 23 -/* SPI_MEM_DMA_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: SPI dma in data state.*/ -#define SPI_MEM_DMA_IN_STATE 0x00000007 -#define SPI_MEM_DMA_IN_STATE_M ((SPI_MEM_DMA_IN_STATE_V)<<(SPI_MEM_DMA_IN_STATE_S)) -#define SPI_MEM_DMA_IN_STATE_V 0x7 -#define SPI_MEM_DMA_IN_STATE_S 20 -/* SPI_MEM_DMA_INDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: SPI dma in descriptor state.*/ -#define SPI_MEM_DMA_INDSCR_STATE 0x00000003 -#define SPI_MEM_DMA_INDSCR_STATE_M ((SPI_MEM_DMA_INDSCR_STATE_V)<<(SPI_MEM_DMA_INDSCR_STATE_S)) -#define SPI_MEM_DMA_INDSCR_STATE_V 0x3 -#define SPI_MEM_DMA_INDSCR_STATE_S 18 -/* SPI_MEM_DMA_INDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: SPI dma in descriptor address.*/ -#define SPI_MEM_DMA_INDSCR_ADDR 0x0003FFFF -#define SPI_MEM_DMA_INDSCR_ADDR_M ((SPI_MEM_DMA_INDSCR_ADDR_V)<<(SPI_MEM_DMA_INDSCR_ADDR_S)) -#define SPI_MEM_DMA_INDSCR_ADDR_V 0x3FFFF -#define SPI_MEM_DMA_INDSCR_ADDR_S 0 - -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8) +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x058) /* SPI_MEM_BUF0 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF0 0xFFFFFFFF @@ -1393,7 +899,7 @@ extern "C" { #define SPI_MEM_BUF0_V 0xFFFFFFFF #define SPI_MEM_BUF0_S 0 -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC) +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x05C) /* SPI_MEM_BUF1 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF1 0xFFFFFFFF @@ -1401,7 +907,7 @@ extern "C" { #define SPI_MEM_BUF1_V 0xFFFFFFFF #define SPI_MEM_BUF1_S 0 -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B0) +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x060) /* SPI_MEM_BUF2 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF2 0xFFFFFFFF @@ -1409,7 +915,7 @@ extern "C" { #define SPI_MEM_BUF2_V 0xFFFFFFFF #define SPI_MEM_BUF2_S 0 -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B4) +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x064) /* SPI_MEM_BUF3 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF3 0xFFFFFFFF @@ -1417,7 +923,7 @@ extern "C" { #define SPI_MEM_BUF3_V 0xFFFFFFFF #define SPI_MEM_BUF3_S 0 -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B8) +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x068) /* SPI_MEM_BUF4 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF4 0xFFFFFFFF @@ -1425,7 +931,7 @@ extern "C" { #define SPI_MEM_BUF4_V 0xFFFFFFFF #define SPI_MEM_BUF4_S 0 -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x0BC) +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x06C) /* SPI_MEM_BUF5 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF5 0xFFFFFFFF @@ -1433,7 +939,7 @@ extern "C" { #define SPI_MEM_BUF5_V 0xFFFFFFFF #define SPI_MEM_BUF5_S 0 -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C0) +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x070) /* SPI_MEM_BUF6 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF6 0xFFFFFFFF @@ -1441,7 +947,7 @@ extern "C" { #define SPI_MEM_BUF6_V 0xFFFFFFFF #define SPI_MEM_BUF6_S 0 -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C4) +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x074) /* SPI_MEM_BUF7 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF7 0xFFFFFFFF @@ -1449,7 +955,7 @@ extern "C" { #define SPI_MEM_BUF7_V 0xFFFFFFFF #define SPI_MEM_BUF7_S 0 -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C8) +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x078) /* SPI_MEM_BUF8 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF8 0xFFFFFFFF @@ -1457,7 +963,7 @@ extern "C" { #define SPI_MEM_BUF8_V 0xFFFFFFFF #define SPI_MEM_BUF8_S 0 -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x0CC) +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x07C) /* SPI_MEM_BUF9 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF9 0xFFFFFFFF @@ -1465,7 +971,7 @@ extern "C" { #define SPI_MEM_BUF9_V 0xFFFFFFFF #define SPI_MEM_BUF9_S 0 -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D0) +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x080) /* SPI_MEM_BUF10 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF10 0xFFFFFFFF @@ -1473,7 +979,7 @@ extern "C" { #define SPI_MEM_BUF10_V 0xFFFFFFFF #define SPI_MEM_BUF10_S 0 -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D4) +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x084) /* SPI_MEM_BUF11 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF11 0xFFFFFFFF @@ -1481,7 +987,7 @@ extern "C" { #define SPI_MEM_BUF11_V 0xFFFFFFFF #define SPI_MEM_BUF11_S 0 -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D8) +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x088) /* SPI_MEM_BUF12 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF12 0xFFFFFFFF @@ -1489,7 +995,7 @@ extern "C" { #define SPI_MEM_BUF12_V 0xFFFFFFFF #define SPI_MEM_BUF12_S 0 -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC) +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x08C) /* SPI_MEM_BUF13 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF13 0xFFFFFFFF @@ -1497,7 +1003,7 @@ extern "C" { #define SPI_MEM_BUF13_V 0xFFFFFFFF #define SPI_MEM_BUF13_S 0 -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x0E0) +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x090) /* SPI_MEM_BUF14 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF14 0xFFFFFFFF @@ -1505,7 +1011,7 @@ extern "C" { #define SPI_MEM_BUF14_V 0xFFFFFFFF #define SPI_MEM_BUF14_S 0 -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x0E4) +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x094) /* SPI_MEM_BUF15 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: data buffer*/ #define SPI_MEM_BUF15 0xFFFFFFFF @@ -1513,7 +1019,7 @@ extern "C" { #define SPI_MEM_BUF15_V 0xFFFFFFFF #define SPI_MEM_BUF15_S 0 -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0E8) +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x098) /* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[17:10] ;default: 8'h0 ; */ /*description: The dummy cycle length when auto wait flash idle*/ #define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x000000FF @@ -1540,7 +1046,7 @@ extern "C" { #define SPI_MEM_WAITI_EN_V 0x1 #define SPI_MEM_WAITI_EN_S 0 -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0EC) +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x09C) /* SPI_MEM_FLASH_PES : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ @@ -1556,7 +1062,7 @@ extern "C" { #define SPI_MEM_FLASH_PER_V 0x1 #define SPI_MEM_FLASH_PER_S 0 -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0F0) +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A0) /* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */ /*description: Program/Erase suspend command.*/ #define SPI_MEM_FLASH_PES_COMMAND 0x000000FF @@ -1576,7 +1082,7 @@ extern "C" { #define SPI_MEM_FLASH_PES_EN_V 0x1 #define SPI_MEM_FLASH_PES_EN_S 0 -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0F4) +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A4) /* SPI_MEM_FLASH_SUS : R/W ;bitpos:[0] ;default: 1'h0 ; */ /*description: The status of flash suspend only used in SPI1.*/ #define SPI_MEM_FLASH_SUS (BIT(0)) @@ -1584,7 +1090,7 @@ extern "C" { #define SPI_MEM_FLASH_SUS_V 0x1 #define SPI_MEM_FLASH_SUS_S 0 -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0F8) +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8) /* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ /*description: add extra dummy spi clock cycle length for spi clock calibration.*/ #define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000003 @@ -1604,7 +1110,42 @@ extern "C" { #define SPI_MEM_TIMING_CLK_ENA_V 0x1 #define SPI_MEM_TIMING_CLK_ENA_S 0 -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0FC) +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 /* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ @@ -1634,7 +1175,42 @@ extern "C" { #define SPI_MEM_DIN0_MODE_V 0x7 #define SPI_MEM_DIN0_MODE_S 0 -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B0) +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 /* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ @@ -1664,7 +1240,42 @@ extern "C" { #define SPI_MEM_DIN0_NUM_V 0x3 #define SPI_MEM_DIN0_NUM_S 0 -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B4) +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUTS_MODE 0x00000007 +#define SPI_MEM_DOUTS_MODE_M ((SPI_MEM_DOUTS_MODE_V)<<(SPI_MEM_DOUTS_MODE_S)) +#define SPI_MEM_DOUTS_MODE_V 0x7 +#define SPI_MEM_DOUTS_MODE_S 24 +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT7_MODE 0x00000007 +#define SPI_MEM_DOUT7_MODE_M ((SPI_MEM_DOUT7_MODE_V)<<(SPI_MEM_DOUT7_MODE_S)) +#define SPI_MEM_DOUT7_MODE_V 0x7 +#define SPI_MEM_DOUT7_MODE_S 21 +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT6_MODE 0x00000007 +#define SPI_MEM_DOUT6_MODE_M ((SPI_MEM_DOUT6_MODE_V)<<(SPI_MEM_DOUT6_MODE_S)) +#define SPI_MEM_DOUT6_MODE_V 0x7 +#define SPI_MEM_DOUT6_MODE_S 18 +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT5_MODE 0x00000007 +#define SPI_MEM_DOUT5_MODE_M ((SPI_MEM_DOUT5_MODE_V)<<(SPI_MEM_DOUT5_MODE_S)) +#define SPI_MEM_DOUT5_MODE_V 0x7 +#define SPI_MEM_DOUT5_MODE_S 15 +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT4_MODE 0x00000007 +#define SPI_MEM_DOUT4_MODE_M ((SPI_MEM_DOUT4_MODE_V)<<(SPI_MEM_DOUT4_MODE_S)) +#define SPI_MEM_DOUT4_MODE_V 0x7 +#define SPI_MEM_DOUT4_MODE_S 12 /* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ @@ -1694,7 +1305,42 @@ extern "C" { #define SPI_MEM_DOUT0_MODE_V 0x7 #define SPI_MEM_DOUT0_MODE_S 0 -#define SPI_MEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +#define SPI_MEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B8) +/* SPI_MEM_DOUTS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DOUTS_NUM 0x00000003 +#define SPI_MEM_DOUTS_NUM_M ((SPI_MEM_DOUTS_NUM_V)<<(SPI_MEM_DOUTS_NUM_S)) +#define SPI_MEM_DOUTS_NUM_V 0x3 +#define SPI_MEM_DOUTS_NUM_S 16 +/* SPI_MEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DOUT7_NUM 0x00000003 +#define SPI_MEM_DOUT7_NUM_M ((SPI_MEM_DOUT7_NUM_V)<<(SPI_MEM_DOUT7_NUM_S)) +#define SPI_MEM_DOUT7_NUM_V 0x3 +#define SPI_MEM_DOUT7_NUM_S 14 +/* SPI_MEM_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DOUT6_NUM 0x00000003 +#define SPI_MEM_DOUT6_NUM_M ((SPI_MEM_DOUT6_NUM_V)<<(SPI_MEM_DOUT6_NUM_S)) +#define SPI_MEM_DOUT6_NUM_V 0x3 +#define SPI_MEM_DOUT6_NUM_S 12 +/* SPI_MEM_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DOUT5_NUM 0x00000003 +#define SPI_MEM_DOUT5_NUM_M ((SPI_MEM_DOUT5_NUM_V)<<(SPI_MEM_DOUT5_NUM_S)) +#define SPI_MEM_DOUT5_NUM_V 0x3 +#define SPI_MEM_DOUT5_NUM_S 10 +/* SPI_MEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DOUT4_NUM 0x00000003 +#define SPI_MEM_DOUT4_NUM_M ((SPI_MEM_DOUT4_NUM_V)<<(SPI_MEM_DOUT4_NUM_S)) +#define SPI_MEM_DOUT4_NUM_V 0x3 +#define SPI_MEM_DOUT4_NUM_S 8 /* SPI_MEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ @@ -1724,149 +1370,431 @@ extern "C" { #define SPI_MEM_DOUT0_NUM_V 0x3 #define SPI_MEM_DOUT0_NUM_S 0 -#define SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) -/* SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0BC) +/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ /*description: For sram add extra dummy spi clock cycle length for spi clock calibration.*/ -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000003 -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x3 -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/* SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000003 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x3 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: For sram the bit is used to enable timing auto-calibration for all reading operations.*/ -#define SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_SMEM_TIMING_CALI_M (BIT(1)) -#define SPI_SMEM_TIMING_CALI_V 0x1 -#define SPI_SMEM_TIMING_CALI_S 1 -/* SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 +/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: For sram the bit is used to enable timing adjust clock for all reading operations.*/ -#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_SMEM_TIMING_CLK_ENA_V 0x1 -#define SPI_SMEM_TIMING_CLK_ENA_S 0 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 -#define SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) -/* SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C0) +/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_SMEM_DIN3_MODE 0x00000007 -#define SPI_SMEM_DIN3_MODE_M ((SPI_SMEM_DIN3_MODE_V)<<(SPI_SMEM_DIN3_MODE_S)) -#define SPI_SMEM_DIN3_MODE_V 0x7 -#define SPI_SMEM_DIN3_MODE_S 9 -/* SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 +/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_SMEM_DIN2_MODE 0x00000007 -#define SPI_SMEM_DIN2_MODE_M ((SPI_SMEM_DIN2_MODE_V)<<(SPI_SMEM_DIN2_MODE_S)) -#define SPI_SMEM_DIN2_MODE_V 0x7 -#define SPI_SMEM_DIN2_MODE_S 6 -/* SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 +/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_SMEM_DIN1_MODE 0x00000007 -#define SPI_SMEM_DIN1_MODE_M ((SPI_SMEM_DIN1_MODE_V)<<(SPI_SMEM_DIN1_MODE_S)) -#define SPI_SMEM_DIN1_MODE_V 0x7 -#define SPI_SMEM_DIN1_MODE_S 3 -/* SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 +/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ -#define SPI_SMEM_DIN0_MODE 0x00000007 -#define SPI_SMEM_DIN0_MODE_M ((SPI_SMEM_DIN0_MODE_V)<<(SPI_SMEM_DIN0_MODE_S)) -#define SPI_SMEM_DIN0_MODE_V 0x7 -#define SPI_SMEM_DIN0_MODE_S 0 +#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 +/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 +/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 +/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 -#define SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) -/* SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C4) +/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 +/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DIN3_NUM 0x00000003 -#define SPI_SMEM_DIN3_NUM_M ((SPI_SMEM_DIN3_NUM_V)<<(SPI_SMEM_DIN3_NUM_S)) -#define SPI_SMEM_DIN3_NUM_V 0x3 -#define SPI_SMEM_DIN3_NUM_S 6 -/* SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 +/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DIN2_NUM 0x00000003 -#define SPI_SMEM_DIN2_NUM_M ((SPI_SMEM_DIN2_NUM_V)<<(SPI_SMEM_DIN2_NUM_S)) -#define SPI_SMEM_DIN2_NUM_V 0x3 -#define SPI_SMEM_DIN2_NUM_S 4 -/* SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 +/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DIN1_NUM 0x00000003 -#define SPI_SMEM_DIN1_NUM_M ((SPI_SMEM_DIN1_NUM_V)<<(SPI_SMEM_DIN1_NUM_S)) -#define SPI_SMEM_DIN1_NUM_V 0x3 -#define SPI_SMEM_DIN1_NUM_S 2 -/* SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 +/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DIN0_NUM 0x00000003 -#define SPI_SMEM_DIN0_NUM_M ((SPI_SMEM_DIN0_NUM_V)<<(SPI_SMEM_DIN0_NUM_S)) -#define SPI_SMEM_DIN0_NUM_V 0x3 -#define SPI_SMEM_DIN0_NUM_S 0 +#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 +/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 +/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 +/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 +/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 -#define SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) -/* SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C8) +/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_SMEM_DOUT3_MODE 0x00000007 -#define SPI_SMEM_DOUT3_MODE_M ((SPI_SMEM_DOUT3_MODE_V)<<(SPI_SMEM_DOUT3_MODE_S)) -#define SPI_SMEM_DOUT3_MODE_V 0x7 -#define SPI_SMEM_DOUT3_MODE_S 9 -/* SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUTS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M ((SPI_MEM_SPI_SMEM_DOUTS_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUTS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 24 +/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_SMEM_DOUT2_MODE 0x00000007 -#define SPI_SMEM_DOUT2_MODE_M ((SPI_SMEM_DOUT2_MODE_V)<<(SPI_SMEM_DOUT2_MODE_S)) -#define SPI_SMEM_DOUT2_MODE_V 0x7 -#define SPI_SMEM_DOUT2_MODE_S 6 -/* SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M ((SPI_MEM_SPI_SMEM_DOUT7_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 21 +/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_SMEM_DOUT1_MODE 0x00000007 -#define SPI_SMEM_DOUT1_MODE_M ((SPI_SMEM_DOUT1_MODE_V)<<(SPI_SMEM_DOUT1_MODE_S)) -#define SPI_SMEM_DOUT1_MODE_V 0x7 -#define SPI_SMEM_DOUT1_MODE_S 3 -/* SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M ((SPI_MEM_SPI_SMEM_DOUT6_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 18 +/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ -#define SPI_SMEM_DOUT0_MODE 0x00000007 -#define SPI_SMEM_DOUT0_MODE_M ((SPI_SMEM_DOUT0_MODE_V)<<(SPI_SMEM_DOUT0_MODE_S)) -#define SPI_SMEM_DOUT0_MODE_V 0x7 -#define SPI_SMEM_DOUT0_MODE_S 0 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M ((SPI_MEM_SPI_SMEM_DOUT5_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 15 +/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M ((SPI_MEM_SPI_SMEM_DOUT4_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 12 +/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M ((SPI_MEM_SPI_SMEM_DOUT3_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 9 +/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M ((SPI_MEM_SPI_SMEM_DOUT2_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M ((SPI_MEM_SPI_SMEM_DOUT1_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M ((SPI_MEM_SPI_SMEM_DOUT0_MODE_V)<<(SPI_MEM_SPI_SMEM_DOUT0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 -#define SPI_SMEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) -/* SPI_SMEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0CC) +/* SPI_MEM_SPI_SMEM_DOUTS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUTS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUTS_NUM_M ((SPI_MEM_SPI_SMEM_DOUTS_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUTS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUTS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUTS_NUM_S 16 +/* SPI_MEM_SPI_SMEM_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT7_NUM_M ((SPI_MEM_SPI_SMEM_DOUT7_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT7_NUM_S 14 +/* SPI_MEM_SPI_SMEM_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT6_NUM_M ((SPI_MEM_SPI_SMEM_DOUT6_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT6_NUM_S 12 +/* SPI_MEM_SPI_SMEM_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT5_NUM_M ((SPI_MEM_SPI_SMEM_DOUT5_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT5_NUM_S 10 +/* SPI_MEM_SPI_SMEM_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT4_NUM_M ((SPI_MEM_SPI_SMEM_DOUT4_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT4_NUM_S 8 +/* SPI_MEM_SPI_SMEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DOUT3_NUM 0x00000003 -#define SPI_SMEM_DOUT3_NUM_M ((SPI_SMEM_DOUT3_NUM_V)<<(SPI_SMEM_DOUT3_NUM_S)) -#define SPI_SMEM_DOUT3_NUM_V 0x3 -#define SPI_SMEM_DOUT3_NUM_S 6 -/* SPI_SMEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT3_NUM_M ((SPI_MEM_SPI_SMEM_DOUT3_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT3_NUM_S 6 +/* SPI_MEM_SPI_SMEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DOUT2_NUM 0x00000003 -#define SPI_SMEM_DOUT2_NUM_M ((SPI_SMEM_DOUT2_NUM_V)<<(SPI_SMEM_DOUT2_NUM_S)) -#define SPI_SMEM_DOUT2_NUM_V 0x3 -#define SPI_SMEM_DOUT2_NUM_S 4 -/* SPI_SMEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT2_NUM_M ((SPI_MEM_SPI_SMEM_DOUT2_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT2_NUM_S 4 +/* SPI_MEM_SPI_SMEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DOUT1_NUM 0x00000003 -#define SPI_SMEM_DOUT1_NUM_M ((SPI_SMEM_DOUT1_NUM_V)<<(SPI_SMEM_DOUT1_NUM_S)) -#define SPI_SMEM_DOUT1_NUM_V 0x3 -#define SPI_SMEM_DOUT1_NUM_S 2 -/* SPI_SMEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +#define SPI_MEM_SPI_SMEM_DOUT1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT1_NUM_M ((SPI_MEM_SPI_SMEM_DOUT1_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT1_NUM_S 2 +/* SPI_MEM_SPI_SMEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ -#define SPI_SMEM_DOUT0_NUM 0x00000003 -#define SPI_SMEM_DOUT0_NUM_M ((SPI_SMEM_DOUT0_NUM_V)<<(SPI_SMEM_DOUT0_NUM_S)) -#define SPI_SMEM_DOUT0_NUM_V 0x3 -#define SPI_SMEM_DOUT0_NUM_S 0 +#define SPI_MEM_SPI_SMEM_DOUT0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DOUT0_NUM_M ((SPI_MEM_SPI_SMEM_DOUT0_NUM_V)<<(SPI_MEM_SPI_SMEM_DOUT0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DOUT0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DOUT0_NUM_S 0 -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D0) +/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[27:15] ;default: 13'h1 ; */ +/*description: For spi0 spi cs signal is delayed to inactive by spi clock this + bits are combined with spi_mem_cs_hold bit.*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x00001FFF +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1FFF +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 15 +/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[14:2] ;default: 13'h1 ; */ +/*description: For spi0 (cycles-1) of prepare phase by spi clock this bits + are combined with spi_mem_cs_setup bit.*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x00001FFF +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1FFF +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 +/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 +/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D4) +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: the bits are combined with the bit spi_fmem_ddr_fdqs_loop which + used to select data strobe generating mode in ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE 0x00000003 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V)<<(SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x3 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: the data strobe is generated by SPI.*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:13] ;default: 8'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock.*/ +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x000000FF +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0xFF +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 13 +/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[12:5] ;default: 8'b1 ; */ +/*description: It is the minimum output data length in the panda device.*/ +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x000000FF +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0xFF +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi ddr mode.*/ +#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in ddr mode 0 in sdr mode*/ +#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D8) +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: the bits are combined with the bit spi_smem_ddr_fdqs_loop which + used to select data strobe generating mode in ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V)<<(SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: the data strobe is generated by SPI.*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:13] ;default: 8'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock.*/ +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x000000FF +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0xFF +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 13 +/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[12:5] ;default: 8'b1 ; */ +/*description: It is the minimum output data length in the ddr psram.*/ +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x000000FF +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0xFF +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi ddr mode.*/ +#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in ddr mode 0 in sdr mode*/ +#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC) /* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define SPI_MEM_CLK_EN (BIT(0)) @@ -1875,7 +1803,7 @@ extern "C" { #define SPI_MEM_CLK_EN_S 0 #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) -/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810250 ; */ +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905270 ; */ /*description: SPI register version.*/ #define SPI_MEM_DATE 0x0FFFFFFF #define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/spi_mem_struct.h b/components/soc/esp32s2beta/include/soc/spi_mem_struct.h index 30d47c8b9c..ec9198ac3e 100644 --- a/components/soc/esp32s2beta/include/soc/spi_mem_struct.h +++ b/components/soc/esp32s2beta/include/soc/spi_mem_struct.h @@ -42,55 +42,57 @@ typedef volatile struct { uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/ union { struct { - uint32_t reserved0: 3; /*reserved*/ - uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ - uint32_t reserved4: 3; /*reserved*/ - uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ - uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ - uint32_t reserved9: 1; /*reserved*/ - uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ - uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ - uint32_t reserved12: 1; /*reserved*/ - uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ - uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ - uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/ - uint32_t reserved16: 1; /*reserved*/ - uint32_t flash_suspending: 1; /*The status of flash suspend only used in SPI1.*/ - uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ - uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ - uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ - uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ - uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ - uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ - uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ - uint32_t reserved25: 7; /*reserved*/ + uint32_t reserved0: 3; /*reserved*/ + uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ + uint32_t fdout_oct: 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ + uint32_t fdin_oct: 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ + uint32_t faddr_oct: 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ + uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12: 1; /*reserved*/ + uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/ + uint32_t reserved16: 2; /*reserved*/ + uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ + uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t reserved25: 7; /*reserved*/ }; uint32_t val; } ctrl; union { struct { - uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ - uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ - uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/ - uint32_t reserved20: 12; /*reserved*/ + uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t cs_hold_dly_res:12; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/ + uint32_t cs_hold_dly: 12; /*SPI fsm is delayed to idle by spi clock cycles.*/ + uint32_t cs_dly_num: 2; /*spi_mem_cs signal is delayed by system clock cycles*/ + uint32_t cs_dly_mode: 2; /*The cs signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/ + uint32_t reserved30: 1; + uint32_t cs_dly_edge: 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/ }; uint32_t val; } ctrl1; union { struct { uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ - uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_mem_cs_hold bit.*/ - uint32_t cs_delay_mode: 2; /*spi_mem_cs signal is delayed by spi_mem_clk . 0: zero 1: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ - uint32_t cs_delay_num: 2; /*spi_mem_cs signal is delayed by system clock cycles*/ - uint32_t cs_delay_edge: 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/ + uint32_t cs_hold_time: 13; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t reserved26: 5; /*reserved*/ uint32_t sync_reset: 1; /*The FSM will be reset.*/ }; uint32_t val; } ctrl2; union { struct { - uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/ - uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/ + uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ uint32_t reserved24: 7; /*In the master mode it is pre-divider of spi_mem_clk.*/ uint32_t clk_equ_sysclk: 1; /*reserved*/ @@ -102,7 +104,7 @@ typedef volatile struct { uint32_t reserved0: 6; /*reserved*/ uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ - uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_mem_ck_out_edge in master mode. It is combined with spi_mem_miso_delay_mode bits.*/ + uint32_t reserved8: 1; /*reserved*/ uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/ uint32_t reserved10: 2; /*reserved*/ uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ @@ -166,7 +168,7 @@ typedef volatile struct { uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_mem_cs1 signal is from/to CS1 pin*/ uint32_t reserved2: 1; /*reserved*/ uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/ - uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/ + uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/ uint32_t cs_pol: 2; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/ uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/ uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/ @@ -204,7 +206,7 @@ typedef volatile struct { uint32_t sram_rdummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ - uint32_t reserved21: 1; /*reserved*/ + uint32_t sram_oct: 1; /*reserved*/ uint32_t sram_wdummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ uint32_t reserved30: 2; /*reserved*/ }; @@ -222,7 +224,12 @@ typedef volatile struct { uint32_t sdout_quad: 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ uint32_t saddr_quad: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ uint32_t scmd_quad: 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t reserved18:14; /*reserved*/ + uint32_t sdin_oct: 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t sdout_oct: 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t saddr_oct: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t scmd_oct: 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t sdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ + uint32_t reserved23: 9; /*reserved*/ }; uint32_t val; } sram_cmd; @@ -244,8 +251,8 @@ typedef volatile struct { } sram_dwr_cmd; union { struct { - uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/ - uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/ + uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ uint32_t cnt_n: 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ uint32_t reserved24: 7; /*reserved*/ uint32_t equ_sysclk: 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ @@ -259,152 +266,7 @@ typedef volatile struct { }; uint32_t val; } fsm; - union { - struct { - uint32_t hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/ - uint32_t reserved2: 30; /*reserved*/ - }; - uint32_t val; - } hold; - union { - struct { - uint32_t dma_rx_ena: 1; /*spi dma rx data enable.*/ - uint32_t dma_tx_ena: 1; /*spi dma tx data enable.*/ - uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ - uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ - uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/ - uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/ - uint32_t in_loop_test: 1; /*Set bit to test in link.*/ - uint32_t out_loop_test: 1; /*Set bit to test out link.*/ - uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/ - uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ - uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ - uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ - uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ - uint32_t dma_mem_trans_ena: 1; /*reserved*/ - uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ - uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ - uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ - uint32_t reserved17: 15; /*reserved*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t addr: 20; /*The address of the first outlink descriptor.*/ - uint32_t reserved20: 8; /*reserved*/ - uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/ - uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/ - uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/ - uint32_t reserved31: 1; /*reserved*/ - }; - uint32_t val; - } dma_out_link; - union { - struct { - uint32_t addr: 20; /*The address of the first inlink descriptor.*/ - uint32_t auto_ret: 1; /*when the bit is set the inlink descriptor returns to the first link node when a packet is error.*/ - uint32_t reserved21: 7; /*reserved*/ - uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/ - uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/ - uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/ - uint32_t reserved31: 1; /*reserved*/ - }; - uint32_t val; - } dma_in_link; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/ - uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/ - uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/ - uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/ - uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/ - uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ - }; - uint32_t val; - } dma_int_ena; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/ - uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/ - uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/ - uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/ - uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ - }; - uint32_t val; - } dma_int_raw; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/ - uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof: 1; /*The status bit for receiving error.*/ - uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/ - uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/ - uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ - }; - uint32_t val; - } dma_int_st; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/ - uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/ - uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/ - uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/ - uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ - }; - uint32_t val; - } dma_int_clr; - uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ - uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ - uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ - uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ - uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ - uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ - uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ - uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ - uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ - uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ - union { - struct { - uint32_t out_dscr_addr: 18; /*SPI dma out descriptor address.*/ - uint32_t out_dscr_state: 2; /*SPI dma out descriptor state.*/ - uint32_t out_state: 3; /*SPI dma out data state.*/ - uint32_t out_fifo_cnt: 7; /*The remains of SPI dma outfifo data.*/ - uint32_t out_fifo_full: 1; /*SPI dma outfifo is full.*/ - uint32_t out_fifo_empty: 1; /*SPI dma outfifo is empty.*/ - }; - uint32_t val; - } dma_out_status; - union { - struct { - uint32_t in_dscr_addr: 18; /*SPI dma in descriptor address.*/ - uint32_t in_dscr_state: 2; /*SPI dma in descriptor state.*/ - uint32_t in_state: 3; /*SPI dma in data state.*/ - uint32_t in_fifo_cnt: 7; /*The remains of SPI dma infifo data.*/ - uint32_t in_fifo_full: 1; /*SPI dma infifo is full.*/ - uint32_t in_fifo_empty: 1; /*SPI dma infifo is empty.*/ - }; - uint32_t val; - } dma_in_status; - uint32_t data_buf[16]; /*data buffer*/ + uint32_t data_buf[18]; /*data buffer*/ union { struct { uint32_t waiti_en: 1; /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/ @@ -434,41 +296,62 @@ typedef volatile struct { } flash_sus_ctrl; union { struct { - uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t reserved8: 10; /*reserved*/ - uint32_t din0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t din1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t din2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t din3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t flash_sus: 1; /*The status of flash suspend only used in SPI1.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } sus_status; + union { + struct { + uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t reserved18:14; /*reserved*/ }; uint32_t val; } din_mode; union { struct { - uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved8: 24; /*reserved*/ + uint32_t din0_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din1_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din2_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din3_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din4_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din5_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din6_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din7_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dins_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved27: 5; /*reserved*/ }; uint32_t val; } din_num; union { struct { - uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t reserved8: 10; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout5_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout6_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout7_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t douts_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t reserved18:14; /*reserved*/ }; uint32_t val; } dout_mode; @@ -478,67 +361,151 @@ typedef volatile struct { uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved8: 24; /*reserved*/ + uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t douts_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved18:14; /*reserved*/ }; uint32_t val; } dout_num; union { struct { - uint32_t sdin0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t sdin1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t sdin2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t sdin3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t reserved8: 10; - uint32_t sdin0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t sdin1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t sdin2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t sdin3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t spi_smem_timing_clk_ena: 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t spi_smem_timing_cali: 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t spi_smem_extra_dummy_cyclelen: 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reserved5: 27; }; uint32_t val; - } sdin_mode; + } spi_smem_timing_cali; union { struct { - uint32_t sdin0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t sdin1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t sdin2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t sdin3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved8: 24; /*reserved*/ + uint32_t spi_smem_din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t reserved18: 14; /*reserved*/ }; uint32_t val; - } sdin_num; + } spi_smem_din_mode; union { struct { - uint32_t sdout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t sdout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t sdout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t sdout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t reserved8: 10; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t sdout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t sdout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t sdout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t sdout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t spi_smem_din0_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din1_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din2_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din3_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din4_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din5_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din6_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din7_num: 3; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_dins_num: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t reserved27: 5; /*reserved*/ }; uint32_t val; - } sdout_mode; + } spi_smem_din_num; union { struct { - uint32_t sdout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t sdout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t sdout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t sdout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved8: 24; /*reserved*/ + uint32_t spi_smem_dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout5_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout6_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout7_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_douts_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t reserved18: 14; /*reserved*/ }; uint32_t val; - } sdout_num; + } spi_smem_dout_mode; union { struct { - uint32_t clk_en: 1; - uint32_t reserved1: 31; + uint32_t spi_smem_dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_dout4_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout5_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout6_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout7_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_douts_num: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_num; + union { + struct { + uint32_t spi_smem_cs_setup: 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ + uint32_t spi_smem_cs_hold: 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ + uint32_t spi_smem_cs_setup_time:13; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t spi_smem_cs_hold_time: 13; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } spi_smem_ac; + union { + struct { + uint32_t spi_fmem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/ + uint32_t spi_fmem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ + uint32_t spi_fmem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ + uint32_t spi_fmem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ + uint32_t spi_fmem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/ + uint32_t spi_fmem_outminbytelen: 8; /*It is the minimum output data length in the panda device.*/ + uint32_t spi_fmem_usr_ddr_dqs_thd: 8; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t spi_fmem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/ + uint32_t spi_fmem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } ddr; + union { + struct { + uint32_t spi_smem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/ + uint32_t spi_smem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ + uint32_t spi_smem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ + uint32_t spi_smem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ + uint32_t spi_smem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/ + uint32_t spi_smem_outminbytelen: 8; /*It is the minimum output data length in the ddr psram.*/ + uint32_t spi_smem_usr_ddr_dqs_thd: 8; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t spi_smem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/ + uint32_t spi_smem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } spi_smem_ddr; + union { + struct { + uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1: 31; /*reserved*/ }; uint32_t val; } clock_gate; + union { + struct { + uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ + uint32_t reserved2: 30; /*reserved*/ + }; + uint32_t val; + } spi_core_clk_sel; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; uint32_t reserved_118; uint32_t reserved_11c; uint32_t reserved_120; diff --git a/components/soc/esp32s2beta/include/soc/spi_pins.h b/components/soc/esp32s2beta/include/soc/spi_pins.h new file mode 100644 index 0000000000..fb95efe127 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/spi_pins.h @@ -0,0 +1,40 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_SPI_PINS_H_ +#define _SOC_SPI_PINS_H_ + +#define SPI_PERIPH_NUM 3 + +#define SPI_FUNC_NUM 2 +#define SPI_IOMUX_PIN_NUM_HD 27 +#define SPI_IOMUX_PIN_NUM_CS 29 +#define SPI_IOMUX_PIN_NUM_MOSI 32 +#define SPI_IOMUX_PIN_NUM_CLK 30 +#define SPI_IOMUX_PIN_NUM_MISO 31 +#define SPI_IOMUX_PIN_NUM_WP 28 +//TODO: add the next slot + +#define FSPI_FUNC_NUM 0 +#define FSPI_IOMUX_PIN_NUM_HD 9 +#define FSPI_IOMUX_PIN_NUM_CS 10 +#define FSPI_IOMUX_PIN_NUM_MOSI 11 +#define FSPI_IOMUX_PIN_NUM_CLK 12 +#define FSPI_IOMUX_PIN_NUM_MISO 13 +#define FSPI_IOMUX_PIN_NUM_WP 14 +//TODO: add the next slot + +//HSPI and VSPI have no iomux pins + +#endif \ No newline at end of file diff --git a/components/soc/esp32s2beta/include/soc/spi_reg.h b/components/soc/esp32s2beta/include/soc/spi_reg.h index 6a05e98fd8..dcb6d21077 100644 --- a/components/soc/esp32s2beta/include/soc/spi_reg.h +++ b/components/soc/esp32s2beta/include/soc/spi_reg.h @@ -19,114 +19,140 @@ extern "C" { #endif #include "soc.h" -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 ))) +#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) -/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ /*description: User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ -#define SPI_USR (BIT(18)) -#define SPI_USR_M (BIT(18)) + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (BIT(24)) #define SPI_USR_V 0x1 -#define SPI_USR_S 18 +#define SPI_USR_S 24 +/* SPI_CONF_BITLEN : R/W ;bitpos:[22:0] ;default: 23'd104 ; */ +/*description: Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/ +#define SPI_CONF_BITLEN 0x007FFFFF +#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S)) +#define SPI_CONF_BITLEN_V 0x7FFFFF +#define SPI_CONF_BITLEN_S 0 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x004) /* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: [31:8]:address to slave [7:0]:Reserved.*/ +/*description: [31:8]:address to slave [7:0]:Reserved. Can be configured in CONF state.*/ #define SPI_USR_ADDR_VALUE 0xFFFFFFFF #define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S)) #define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF #define SPI_USR_ADDR_VALUE_S 0 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) -/* SPI_DEFINE_SLV_ADDR : R/W ;bitpos:[27] ;default: 1'b1 ; */ -/*description: set spi_usr_addr and spi_usr_addr_value in spi defined slave - mode. 1: disable 0:enable.*/ -#define SPI_DEFINE_SLV_ADDR (BIT(27)) -#define SPI_DEFINE_SLV_ADDR_M (BIT(27)) -#define SPI_DEFINE_SLV_ADDR_V 0x1 -#define SPI_DEFINE_SLV_ADDR_S 27 /* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB + first. Can be configured in CONF state.*/ #define SPI_WR_BIT_ORDER (BIT(26)) #define SPI_WR_BIT_ORDER_M (BIT(26)) #define SPI_WR_BIT_ORDER_V 0x1 #define SPI_WR_BIT_ORDER_S 26 /* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured + in CONF state.*/ #define SPI_RD_BIT_ORDER (BIT(25)) #define SPI_RD_BIT_ORDER_M (BIT(25)) #define SPI_RD_BIT_ORDER_V 0x1 #define SPI_RD_BIT_ORDER_S 25 /* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +/*description: Write protect signal output when SPI is idle. 1: output high + 0: output low. Can be configured in CONF state.*/ #define SPI_WP_REG (BIT(21)) #define SPI_WP_REG_M (BIT(21)) #define SPI_WP_REG_V 0x1 #define SPI_WP_REG_S 21 -/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ -#define SPI_FREAD_QUAD (BIT(20)) -#define SPI_FREAD_QUAD_M (BIT(20)) -#define SPI_FREAD_QUAD_V 0x1 -#define SPI_FREAD_QUAD_S 20 /* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: The bit is used to set MOSI line polarity 1: high 0 low*/ +/*description: The bit is used to set MOSI line polarity 1: high 0 low. Can + be configured in CONF state.*/ #define SPI_D_POL (BIT(19)) #define SPI_D_POL_M (BIT(19)) #define SPI_D_POL_V 0x1 #define SPI_D_POL_S 19 /* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: The bit is used to set MISO line polarity 1: high 0 low*/ +/*description: The bit is used to set MISO line polarity 1: high 0 low. Can + be configured in CONF state.*/ #define SPI_Q_POL (BIT(18)) #define SPI_Q_POL_M (BIT(18)) #define SPI_Q_POL_V 0x1 #define SPI_Q_POL_S 18 +/* SPI_FREAD_OCT : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 8 signals. 1: enable + 0: disable. Can be configured in CONF state.*/ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (BIT(16)) +#define SPI_FREAD_OCT_V 0x1 +#define SPI_FREAD_OCT_S 16 +/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable + 0: disable. Can be configured in CONF state.*/ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (BIT(15)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 15 /* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +/*description: In the read operations read-data phase apply 2 signals. 1: enable + 0: disable. Can be configured in CONF state.*/ #define SPI_FREAD_DUAL (BIT(14)) #define SPI_FREAD_DUAL_M (BIT(14)) #define SPI_FREAD_DUAL_V 0x1 #define SPI_FREAD_DUAL_S 14 -/* SPI_FAST_RD_MODE : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Enable 2/4 lines addr command including read and write command.*/ -#define SPI_FAST_RD_MODE (BIT(13)) -#define SPI_FAST_RD_MODE_M (BIT(13)) -#define SPI_FAST_RD_MODE_V 0x1 -#define SPI_FAST_RD_MODE_S 13 -/* SPI_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Apply 4 signals during command phase 1:enable 0: disable*/ -#define SPI_FCMD_QUAD (BIT(8)) -#define SPI_FCMD_QUAD_M (BIT(8)) +/* SPI_FCMD_OCT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable. Can + be configured in CONF state.*/ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (BIT(10)) +#define SPI_FCMD_OCT_V 0x1 +#define SPI_FCMD_OCT_S 10 +/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable. Can + be configured in CONF state.*/ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (BIT(9)) #define SPI_FCMD_QUAD_V 0x1 -#define SPI_FCMD_QUAD_S 8 -/* SPI_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Apply 2 signals during command phase 1:enable 0: disable*/ -#define SPI_FCMD_DUAL (BIT(7)) -#define SPI_FCMD_DUAL_M (BIT(7)) +#define SPI_FCMD_QUAD_S 9 +/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 2 signals during command phase 1:enable 0: disable. Can + be configured in CONF state.*/ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (BIT(8)) #define SPI_FCMD_DUAL_V 0x1 -#define SPI_FCMD_DUAL_S 7 +#define SPI_FCMD_DUAL_S 8 +/* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state.*/ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (BIT(7)) +#define SPI_FADDR_OCT_V 0x1 +#define SPI_FADDR_OCT_S 7 /* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Apply 4 signals during addr phase 1:enable 0: disable*/ +/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state.*/ #define SPI_FADDR_QUAD (BIT(6)) #define SPI_FADDR_QUAD_M (BIT(6)) #define SPI_FADDR_QUAD_V 0x1 #define SPI_FADDR_QUAD_S 6 /* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Apply 2 signals during addr phase 1:enable 0: disable*/ +/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state.*/ #define SPI_FADDR_DUAL (BIT(5)) #define SPI_FADDR_DUAL_M (BIT(5)) #define SPI_FADDR_DUAL_V 0x1 #define SPI_FADDR_DUAL_S 5 /* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ +/*description: In the dummy phase the signal level of spi is output by the spi + controller. Can be configured in CONF state.*/ #define SPI_DUMMY_OUT (BIT(3)) #define SPI_DUMMY_OUT_M (BIT(3)) #define SPI_DUMMY_OUT_V 0x1 #define SPI_DUMMY_OUT_S 3 /* SPI_EXT_HOLD_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ /*description: Set the bit to hold spi. The bit is combined with spi_usr_prep_hold - spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/ + spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol. Can be configured in CONF state.*/ #define SPI_EXT_HOLD_EN (BIT(2)) #define SPI_EXT_HOLD_EN_M (BIT(2)) #define SPI_EXT_HOLD_EN_V 0x1 @@ -134,13 +160,14 @@ extern "C" { #define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x00C) /* SPI_CS_HOLD_DELAY : R/W ;bitpos:[19:14] ;default: 6'h1 ; */ -/*description: SPI cs signal is delayed by spi clock cycles.*/ +/*description: SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.*/ #define SPI_CS_HOLD_DELAY 0x0000003F #define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) #define SPI_CS_HOLD_DELAY_V 0x3F #define SPI_CS_HOLD_DELAY_S 14 /* SPI_W16_17_WR_ENA : R/W ;bitpos:[4] ;default: 1'h1 ; */ -/*description: 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written.*/ +/*description: 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not + be written. Can be configured in CONF state.*/ #define SPI_W16_17_WR_ENA (BIT(4)) #define SPI_W16_17_WR_ENA_M (BIT(4)) #define SPI_W16_17_WR_ENA_V 0x1 @@ -153,48 +180,45 @@ extern "C" { #define SPI_RSCK_DATA_OUT_V 0x1 #define SPI_RSCK_DATA_OUT_S 3 /* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]*/ +/*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output + data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ #define SPI_CLK_MODE_13 (BIT(2)) #define SPI_CLK_MODE_13_M (BIT(2)) #define SPI_CLK_MODE_13_V 0x1 #define SPI_CLK_MODE_13_S 2 /* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ #define SPI_CLK_MODE 0x00000003 #define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S)) #define SPI_CLK_MODE_V 0x3 #define SPI_CLK_MODE_S 0 #define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x010) -/* SPI_CS_DELAY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SPI_CS_DELAY_EDGE (BIT(31)) -#define SPI_CS_DELAY_EDGE_M (BIT(31)) -#define SPI_CS_DELAY_EDGE_V 0x1 -#define SPI_CS_DELAY_EDGE_S 31 -/* SPI_CS_DELAY_NUM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ -/*description: spi_cs signal is delayed by system clock cycles*/ +/* SPI_CS_DELAY_NUM : R/W ;bitpos:[30:29] ;default: 2'h0 ; */ +/*description: spi_cs signal is delayed by system clock cycles. Can be configured + in CONF state.*/ #define SPI_CS_DELAY_NUM 0x00000003 #define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) #define SPI_CS_DELAY_NUM_V 0x3 -#define SPI_CS_DELAY_NUM_S 28 -/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ +#define SPI_CS_DELAY_NUM_S 29 +/* SPI_CS_DELAY_MODE : R/W ;bitpos:[28:26] ;default: 3'h0 ; */ /*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge - or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ -#define SPI_CS_DELAY_MODE 0x00000003 + or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.*/ +#define SPI_CS_DELAY_MODE 0x00000007 #define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) -#define SPI_CS_DELAY_MODE_V 0x3 +#define SPI_CS_DELAY_MODE_V 0x7 #define SPI_CS_DELAY_MODE_S 26 /* SPI_CS_HOLD_TIME : R/W ;bitpos:[25:13] ;default: 13'h1 ; */ -/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/ +/*description: delay cycles of cs pin by spi clock this bits are combined with + spi_cs_hold bit. Can be configured in CONF state.*/ #define SPI_CS_HOLD_TIME 0x00001FFF #define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S)) #define SPI_CS_HOLD_TIME_V 0x1FFF #define SPI_CS_HOLD_TIME_S 13 /* SPI_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h1 ; */ /*description: (cycles-1) of prepare phase by spi clock this bits are combined - with spi_cs_setup bit.*/ + with spi_cs_setup bit. Can be configured in CONF state.*/ #define SPI_CS_SETUP_TIME 0x00001FFF #define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S)) #define SPI_CS_SETUP_TIME_V 0x1FFF @@ -203,34 +227,35 @@ extern "C" { #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x014) /* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ /*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is - divided from system clock.*/ + divided from system clock. Can be configured in CONF state.*/ #define SPI_CLK_EQU_SYSCLK (BIT(31)) #define SPI_CLK_EQU_SYSCLK_M (BIT(31)) #define SPI_CLK_EQU_SYSCLK_V 0x1 #define SPI_CLK_EQU_SYSCLK_S 31 /* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ -/*description: In the master mode it is pre-divider of spi_clk.*/ +/*description: In the master mode it is pre-divider of spi_clk. Can be configured + in CONF state.*/ #define SPI_CLKDIV_PRE 0x00001FFF #define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) #define SPI_CLKDIV_PRE_V 0x1FFF #define SPI_CLKDIV_PRE_S 18 /* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ /*description: In the master mode it is the divider of spi_clk. So spi_clk frequency - is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ + is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ #define SPI_CLKCNT_N 0x0000003F #define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) #define SPI_CLKCNT_N_V 0x3F #define SPI_CLKCNT_N_S 12 /* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ /*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In - the slave mode it must be 0.*/ + the slave mode it must be 0. Can be configured in CONF state.*/ #define SPI_CLKCNT_H 0x0000003F #define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) #define SPI_CLKCNT_H_V 0x3F #define SPI_CLKCNT_H_S 6 /* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ /*description: In the master mode it must be equal to spi_clkcnt_N. In the slave - mode it must be 0.*/ + mode it must be 0. Can be configured in CONF state.*/ #define SPI_CLKCNT_L 0x0000003F #define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) #define SPI_CLKCNT_L_V 0x3F @@ -238,131 +263,162 @@ extern "C" { #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x018) /* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation.*/ +/*description: This bit enable the command phase of an operation. Can be configured + in CONF state.*/ #define SPI_USR_COMMAND (BIT(31)) #define SPI_USR_COMMAND_M (BIT(31)) #define SPI_USR_COMMAND_V 0x1 #define SPI_USR_COMMAND_S 31 /* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation.*/ +/*description: This bit enable the address phase of an operation. Can be configured + in CONF state.*/ #define SPI_USR_ADDR (BIT(30)) #define SPI_USR_ADDR_M (BIT(30)) #define SPI_USR_ADDR_V 0x1 #define SPI_USR_ADDR_S 30 /* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: This bit enable the dummy phase of an operation.*/ +/*description: This bit enable the dummy phase of an operation. Can be configured + in CONF state.*/ #define SPI_USR_DUMMY (BIT(29)) #define SPI_USR_DUMMY_M (BIT(29)) #define SPI_USR_DUMMY_V 0x1 #define SPI_USR_DUMMY_S 29 /* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: This bit enable the read-data phase of an operation.*/ +/*description: This bit enable the read-data phase of an operation. Can be configured + in CONF state.*/ #define SPI_USR_MISO (BIT(28)) #define SPI_USR_MISO_M (BIT(28)) #define SPI_USR_MISO_V 0x1 #define SPI_USR_MISO_S 28 /* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This bit enable the write-data phase of an operation.*/ +/*description: This bit enable the write-data phase of an operation. Can be + configured in CONF state.*/ #define SPI_USR_MOSI (BIT(27)) #define SPI_USR_MOSI_M (BIT(27)) #define SPI_USR_MOSI_V 0x1 #define SPI_USR_MOSI_S 27 /* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: spi clock is disable in dummy phase when the bit is enable.*/ +/*description: spi clock is disable in dummy phase when the bit is enable. Can + be configured in CONF state.*/ #define SPI_USR_DUMMY_IDLE (BIT(26)) #define SPI_USR_DUMMY_IDLE_M (BIT(26)) #define SPI_USR_DUMMY_IDLE_V 0x1 #define SPI_USR_DUMMY_IDLE_S 26 /* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ /*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable.*/ + 1: enable 0: disable. Can be configured in CONF state.*/ #define SPI_USR_MOSI_HIGHPART (BIT(25)) #define SPI_USR_MOSI_HIGHPART_M (BIT(25)) #define SPI_USR_MOSI_HIGHPART_V 0x1 #define SPI_USR_MOSI_HIGHPART_S 25 /* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ /*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable.*/ + 1: enable 0: disable. Can be configured in CONF state.*/ #define SPI_USR_MISO_HIGHPART (BIT(24)) #define SPI_USR_MISO_HIGHPART_M (BIT(24)) #define SPI_USR_MISO_HIGHPART_V 0x1 #define SPI_USR_MISO_HIGHPART_S 24 /* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit.*/ +/*description: spi is hold at prepare state the bit are combined with spi_usr_hold_pol + bit. Can be configured in CONF state.*/ #define SPI_USR_PREP_HOLD (BIT(23)) #define SPI_USR_PREP_HOLD_M (BIT(23)) #define SPI_USR_PREP_HOLD_V 0x1 #define SPI_USR_PREP_HOLD_S 23 /* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: spi is hold at command state the bit are combined with spi_usr_hold_pol bit.*/ +/*description: spi is hold at command state the bit are combined with spi_usr_hold_pol + bit. Can be configured in CONF state.*/ #define SPI_USR_CMD_HOLD (BIT(22)) #define SPI_USR_CMD_HOLD_M (BIT(22)) #define SPI_USR_CMD_HOLD_V 0x1 #define SPI_USR_CMD_HOLD_S 22 /* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: spi is hold at address state the bit are combined with spi_usr_hold_pol bit.*/ +/*description: spi is hold at address state the bit are combined with spi_usr_hold_pol + bit. Can be configured in CONF state.*/ #define SPI_USR_ADDR_HOLD (BIT(21)) #define SPI_USR_ADDR_HOLD_M (BIT(21)) #define SPI_USR_ADDR_HOLD_V 0x1 #define SPI_USR_ADDR_HOLD_S 21 /* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit.*/ +/*description: spi is hold at dummy state the bit are combined with spi_usr_hold_pol + bit. Can be configured in CONF state.*/ #define SPI_USR_DUMMY_HOLD (BIT(20)) #define SPI_USR_DUMMY_HOLD_M (BIT(20)) #define SPI_USR_DUMMY_HOLD_V 0x1 #define SPI_USR_DUMMY_HOLD_S 20 /* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: spi is hold at data in state the bit are combined with spi_usr_hold_pol bit.*/ +/*description: spi is hold at data in state the bit are combined with spi_usr_hold_pol + bit. Can be configured in CONF state.*/ #define SPI_USR_DIN_HOLD (BIT(19)) #define SPI_USR_DIN_HOLD_M (BIT(19)) #define SPI_USR_DIN_HOLD_V 0x1 #define SPI_USR_DIN_HOLD_S 19 /* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/ +/*description: spi is hold at data out state the bit are combined with spi_usr_hold_pol + bit. Can be configured in CONF state.*/ #define SPI_USR_DOUT_HOLD (BIT(18)) #define SPI_USR_DOUT_HOLD_M (BIT(18)) #define SPI_USR_DOUT_HOLD_V 0x1 #define SPI_USR_DOUT_HOLD_S 18 /* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ /*description: It is combined with hold bits to set the polarity of spi hold - line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ + line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state.*/ #define SPI_USR_HOLD_POL (BIT(17)) #define SPI_USR_HOLD_POL_M (BIT(17)) #define SPI_USR_HOLD_POL_V 0x1 #define SPI_USR_HOLD_POL_S 17 /* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ /*description: Set the bit to enable 3-line half duplex communication mosi and - miso signals share the same pin. 1: enable 0: disable.*/ + miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ #define SPI_SIO (BIT(16)) #define SPI_SIO_M (BIT(16)) #define SPI_SIO_V 0x1 #define SPI_SIO_S 16 +/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: Enable the DMA CONF phase of next seg-trans operation which + means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (BIT(15)) +#define SPI_USR_CONF_NXT_V 0x1 +#define SPI_USR_CONF_NXT_S 15 +/* SPI_FWRITE_OCT : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 8 signals. Can + be configured in CONF state.*/ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (BIT(14)) +#define SPI_FWRITE_OCT_V 0x1 +#define SPI_FWRITE_OCT_S 14 /* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 4 signals*/ +/*description: In the write operations read-data phase apply 4 signals. Can + be configured in CONF state.*/ #define SPI_FWRITE_QUAD (BIT(13)) #define SPI_FWRITE_QUAD_M (BIT(13)) #define SPI_FWRITE_QUAD_V 0x1 #define SPI_FWRITE_QUAD_S 13 /* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 2 signals*/ +/*description: In the write operations read-data phase apply 2 signals. Can + be configured in CONF state.*/ #define SPI_FWRITE_DUAL (BIT(12)) #define SPI_FWRITE_DUAL_M (BIT(12)) #define SPI_FWRITE_DUAL_V 0x1 #define SPI_FWRITE_DUAL_S 12 /* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ +/*description: In command address write-data (MOSI) phases 1: big-endian 0: + litte_endian. Can be configured in CONF state.*/ #define SPI_WR_BYTE_ORDER (BIT(11)) #define SPI_WR_BYTE_ORDER_M (BIT(11)) #define SPI_WR_BYTE_ORDER_V 0x1 #define SPI_WR_BYTE_ORDER_S 11 /* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/ +/*description: In read-data (MISO) phase 1: big-endian 0: little_endian. Can + be configured in CONF state.*/ #define SPI_RD_BYTE_ORDER (BIT(10)) #define SPI_RD_BYTE_ORDER_M (BIT(10)) #define SPI_RD_BYTE_ORDER_V 0x1 #define SPI_RD_BYTE_ORDER_S 10 /* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal + delay mode. Can be configured in CONF state.*/ #define SPI_CK_OUT_EDGE (BIT(9)) #define SPI_CK_OUT_EDGE_M (BIT(9)) #define SPI_CK_OUT_EDGE_V 0x1 @@ -375,13 +431,15 @@ extern "C" { #define SPI_RSCK_I_EDGE_V 0x1 #define SPI_RSCK_I_EDGE_S 8 /* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: + disable. Can be configured in CONF state.*/ #define SPI_CS_SETUP (BIT(7)) #define SPI_CS_SETUP_M (BIT(7)) #define SPI_CS_SETUP_V 0x1 #define SPI_CS_SETUP_S 7 /* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. + Can be configured in CONF state.*/ #define SPI_CS_HOLD (BIT(6)) #define SPI_CS_HOLD_M (BIT(6)) #define SPI_CS_HOLD_V 0x1 @@ -393,30 +451,25 @@ extern "C" { #define SPI_TSCK_I_EDGE_M (BIT(5)) #define SPI_TSCK_I_EDGE_V 0x1 #define SPI_TSCK_I_EDGE_S 5 -/* SPI_TX_START_BIT : R/W ;bitpos:[3:1] ;default: 3'd7 ; */ -/*description: It determines the start time of tx output data. It can be used - for timing adjustment in MISO slave mode.*/ -#define SPI_TX_START_BIT 0x00000007 -#define SPI_TX_START_BIT_M ((SPI_TX_START_BIT_V)<<(SPI_TX_START_BIT_S)) -#define SPI_TX_START_BIT_V 0x7 -#define SPI_TX_START_BIT_S 1 /* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/ +/*description: Set the bit to enable full duplex communication. 1: enable 0: + disable. Can be configured in CONF state.*/ #define SPI_DOUTDIN (BIT(0)) #define SPI_DOUTDIN_M (BIT(0)) #define SPI_DOUTDIN_V 0x1 #define SPI_DOUTDIN_S 0 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x01C) -/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ -/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ -#define SPI_USR_ADDR_BITLEN 0x0000003F +/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */ +/*description: The length in bits of address phase. The register value shall + be (bit_num-1). Can be configured in CONF state.*/ +#define SPI_USR_ADDR_BITLEN 0x0000001F #define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) -#define SPI_USR_ADDR_BITLEN_V 0x3F -#define SPI_USR_ADDR_BITLEN_S 26 +#define SPI_USR_ADDR_BITLEN_V 0x1F +#define SPI_USR_ADDR_BITLEN_S 27 /* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ /*description: The length in spi_clk cycles of dummy phase. The register value - shall be (cycle_num-1).*/ + shall be (cycle_num-1). Can be configured in CONF state.*/ #define SPI_USR_DUMMY_CYCLELEN 0x000000FF #define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) #define SPI_USR_DUMMY_CYCLELEN_V 0xFF @@ -424,306 +477,513 @@ extern "C" { #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x020) /* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ -/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +/*description: The length in bits of command phase. The register value shall + be (bit_num-1). Can be configured in CONF state.*/ #define SPI_USR_COMMAND_BITLEN 0x0000000F #define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) #define SPI_USR_COMMAND_BITLEN_V 0xF #define SPI_USR_COMMAND_BITLEN_S 28 /* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value of command.*/ +/*description: The value of command. Can be configured in CONF state.*/ #define SPI_USR_COMMAND_VALUE 0x0000FFFF #define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) #define SPI_USR_COMMAND_VALUE_V 0xFFFF #define SPI_USR_COMMAND_VALUE_S 0 #define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x024) -/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/ -#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF +/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ +/*description: The length in bits of write-data. The register value shall be + (bit_num-1). Can be configured in CONF state.*/ +#define SPI_USR_MOSI_DBITLEN 0x007FFFFF #define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) -#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF +#define SPI_USR_MOSI_DBITLEN_V 0x7FFFFF #define SPI_USR_MOSI_DBITLEN_S 0 #define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x028) -/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/ -#define SPI_USR_MISO_DBITLEN 0x00FFFFFF +/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ +/*description: The length in bits of read-data. The register value shall be + (bit_num-1). Can be configured in CONF state.*/ +#define SPI_USR_MISO_DBITLEN 0x007FFFFF #define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) -#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF +#define SPI_USR_MISO_DBITLEN_V 0x7FFFFF #define SPI_USR_MISO_DBITLEN_S 0 #define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x02C) -/* SPI_SLV_WR_STATUS : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: In the master mode this register are the higher 32bits in the - 64 bits address condition.*/ -#define SPI_SLV_WR_STATUS 0xFFFFFFFF -#define SPI_SLV_WR_STATUS_M ((SPI_SLV_WR_STATUS_V)<<(SPI_SLV_WR_STATUS_S)) -#define SPI_SLV_WR_STATUS_V 0xFFFFFFFF -#define SPI_SLV_WR_STATUS_S 0 +/* SPI_OPI_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Just for master mode. 1: spi controller is in OPI mode (all in + 8-b-m). 0: others. Can be configured in CONF state.*/ +#define SPI_OPI_MODE (BIT(1)) +#define SPI_OPI_MODE_M (BIT(1)) +#define SPI_OPI_MODE_V 0x1 +#define SPI_OPI_MODE_S 1 +/* SPI_QPI_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Both for master mode and slave mode. 1: spi controller is in + QPI mode. 0: others. Can be configured in CONF state.*/ +#define SPI_QPI_MODE (BIT(0)) +#define SPI_QPI_MODE_M (BIT(0)) +#define SPI_QPI_MODE_V 0x1 +#define SPI_QPI_MODE_S 0 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x030) /* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: 1: spi quad input swap enable 0: spi quad input swap disable*/ +/*description: 1: spi quad input swap enable 0: spi quad input swap disable. + Can be configured in CONF state.*/ #define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) #define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31)) #define SPI_QUAD_DIN_PIN_SWAP_V 0x1 #define SPI_QUAD_DIN_PIN_SWAP_S 31 /* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: spi cs line keep low when the bit is set.*/ +/*description: spi cs line keep low when the bit is set. Can be configured in CONF state.*/ #define SPI_CS_KEEP_ACTIVE (BIT(30)) #define SPI_CS_KEEP_ACTIVE_M (BIT(30)) #define SPI_CS_KEEP_ACTIVE_V 0x1 #define SPI_CS_KEEP_ACTIVE_S 30 /* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +/*description: 1: spi clk line is high when idle 0: spi clk line is low + when idle. Can be configured in CONF state.*/ #define SPI_CK_IDLE_EDGE (BIT(29)) #define SPI_CK_IDLE_EDGE_M (BIT(29)) #define SPI_CK_IDLE_EDGE_V 0x1 #define SPI_CK_IDLE_EDGE_S 29 -/* SPI_Q_IDLE_OUT : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The idle output value of spi_q.*/ -#define SPI_Q_IDLE_OUT (BIT(27)) -#define SPI_Q_IDLE_OUT_M (BIT(27)) -#define SPI_Q_IDLE_OUT_V 0x1 -#define SPI_Q_IDLE_OUT_S 27 +/* SPI_CD_IDLE_EDGE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: The default value of spi_cd. Can be configured in CONF state.*/ +#define SPI_CD_IDLE_EDGE (BIT(26)) +#define SPI_CD_IDLE_EDGE_M (BIT(26)) +#define SPI_CD_IDLE_EDGE_V 0x1 +#define SPI_CD_IDLE_EDGE_S 26 +/* SPI_CD_CMD_SET : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD + state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ +#define SPI_CD_CMD_SET (BIT(25)) +#define SPI_CD_CMD_SET_M (BIT(25)) +#define SPI_CD_CMD_SET_V 0x1 +#define SPI_CD_CMD_SET_S 25 +/* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The default value of spi_dqs. Can be configured in CONF state.*/ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (BIT(24)) +#define SPI_DQS_IDLE_EDGE_V 0x1 +#define SPI_DQS_IDLE_EDGE_S 24 /* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: spi slave input cs polarity select. 1: inv 0: not change*/ +/*description: spi slave input cs polarity select. 1: inv 0: not change. Can + be configured in CONF state.*/ #define SPI_SLAVE_CS_POL (BIT(23)) #define SPI_SLAVE_CS_POL_M (BIT(23)) #define SPI_SLAVE_CS_POL_V 0x1 #define SPI_SLAVE_CS_POL_S 23 -/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ -/*description: In the master mode the bits are the polarity of spi cs line - the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ -#define SPI_MASTER_CS_POL 0x00000007 +/* SPI_CD_ADDR_SET : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR + state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ +#define SPI_CD_ADDR_SET (BIT(22)) +#define SPI_CD_ADDR_SET_M (BIT(22)) +#define SPI_CD_ADDR_SET_V 0x1 +#define SPI_CD_ADDR_SET_S 22 +/* SPI_CD_DUMMY_SET : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY + state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ +#define SPI_CD_DUMMY_SET (BIT(21)) +#define SPI_CD_DUMMY_SET_M (BIT(21)) +#define SPI_CD_DUMMY_SET_V 0x1 +#define SPI_CD_DUMMY_SET_S 21 +/* SPI_CD_DATA_SET : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT + or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ +#define SPI_CD_DATA_SET (BIT(20)) +#define SPI_CD_DATA_SET_M (BIT(20)) +#define SPI_CD_DATA_SET_V 0x1 +#define SPI_CD_DATA_SET_S 20 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line + the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ +#define SPI_MASTER_CS_POL 0x0000003F #define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) -#define SPI_MASTER_CS_POL_V 0x7 -#define SPI_MASTER_CS_POL_S 6 -/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: 1: spi clk out disable 0: spi clk out enable*/ -#define SPI_CK_DIS (BIT(5)) -#define SPI_CK_DIS_M (BIT(5)) +#define SPI_MASTER_CS_POL_V 0x3F +#define SPI_MASTER_CS_POL_S 7 +/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (BIT(6)) #define SPI_CK_DIS_V 0x1 -#define SPI_CK_DIS_S 5 +#define SPI_CK_DIS_S 6 +/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to + CS5 pin. Can be configured in CONF state.*/ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (BIT(5)) +#define SPI_CS5_DIS_V 0x1 +#define SPI_CS5_DIS_S 5 +/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to + CS4 pin. Can be configured in CONF state.*/ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (BIT(4)) +#define SPI_CS4_DIS_V 0x1 +#define SPI_CS4_DIS_S 4 +/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: reserved*/ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (BIT(3)) +#define SPI_CS3_DIS_V 0x1 +#define SPI_CS3_DIS_S 3 /* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin*/ +/*description: SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to + CS2 pin. Can be configured in CONF state.*/ #define SPI_CS2_DIS (BIT(2)) #define SPI_CS2_DIS_M (BIT(2)) #define SPI_CS2_DIS_V 0x1 #define SPI_CS2_DIS_S 2 /* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin*/ +/*description: SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to + CS1 pin. Can be configured in CONF state.*/ #define SPI_CS1_DIS (BIT(1)) #define SPI_CS1_DIS_M (BIT(1)) #define SPI_CS1_DIS_V 0x1 #define SPI_CS1_DIS_S 1 /* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin*/ +/*description: SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to + CS0 pin. Can be configured in CONF state.*/ #define SPI_CS0_DIS (BIT(0)) #define SPI_CS0_DIS_M (BIT(0)) #define SPI_CS0_DIS_V 0x1 #define SPI_CS0_DIS_S 0 #define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x034) -/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Software reset enable reset the spi clock line cs line and data lines.*/ -#define SPI_SYNC_RESET (BIT(31)) -#define SPI_SYNC_RESET_M (BIT(31)) -#define SPI_SYNC_RESET_V 0x1 -#define SPI_SYNC_RESET_S 31 +/* SPI_SOFT_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Software reset enable reset the spi clock line cs line and data + lines. Can be configured in CONF state.*/ +#define SPI_SOFT_RESET (BIT(31)) +#define SPI_SOFT_RESET_M (BIT(31)) +#define SPI_SOFT_RESET_V 0x1 +#define SPI_SOFT_RESET_S 31 /* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set SPI work mode. 1: slave mode 0: master mode.*/ +/*description: Set SPI work mode. 1: slave mode 0: master mode. Can be configured + in CONF state.*/ #define SPI_SLAVE_MODE (BIT(30)) #define SPI_SLAVE_MODE_M (BIT(30)) #define SPI_SLAVE_MODE_V 0x1 #define SPI_SLAVE_MODE_S 30 +/* SPI_TRANS_DONE_AUTO_CLR_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: spi_trans_done auto clear enable clear it 3 apb cycles after + the pos edge of spi_trans_done. 0:disable. 1: enable. Can be configured in CONF state.*/ +#define SPI_TRANS_DONE_AUTO_CLR_EN (BIT(29)) +#define SPI_TRANS_DONE_AUTO_CLR_EN_M (BIT(29)) +#define SPI_TRANS_DONE_AUTO_CLR_EN_V 0x1 +#define SPI_TRANS_DONE_AUTO_CLR_EN_S 29 /* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ /*description: The operations counter in both the master mode and the slave mode.*/ #define SPI_TRANS_CNT 0x0000000F #define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) #define SPI_TRANS_CNT_V 0xF #define SPI_TRANS_CNT_S 23 +/* SPI_SEG_MAGIC_ERR_INT_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1: Enable seg magic value error interrupt. 0: Others. Can be + configured in CONF state.*/ +#define SPI_SEG_MAGIC_ERR_INT_EN (BIT(11)) +#define SPI_SEG_MAGIC_ERR_INT_EN_M (BIT(11)) +#define SPI_SEG_MAGIC_ERR_INT_EN_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_EN_S 11 +/* SPI_INT_DMA_SEG_TRANS_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable. + Can be configured in CONF state.*/ +#define SPI_INT_DMA_SEG_TRANS_EN (BIT(10)) +#define SPI_INT_DMA_SEG_TRANS_EN_M (BIT(10)) +#define SPI_INT_DMA_SEG_TRANS_EN_V 0x1 +#define SPI_INT_DMA_SEG_TRANS_EN_S 10 /* SPI_INT_TRANS_DONE_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: spi_trans_done Interrupt enable. 1: enable 0: disable*/ +/*description: spi_trans_done Interrupt enable. 1: enable 0: disable. Can be + configured in CONF state.*/ #define SPI_INT_TRANS_DONE_EN (BIT(9)) #define SPI_INT_TRANS_DONE_EN_M (BIT(9)) #define SPI_INT_TRANS_DONE_EN_V 0x1 #define SPI_INT_TRANS_DONE_EN_S 9 /* SPI_INT_WR_DMA_DONE_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: spi_slv_wr_dma Interrupt enable. 1: enable 0: disable*/ +/*description: spi_slv_wr_dma Interrupt enable. 1: enable 0: disable. Can be + configured in CONF state.*/ #define SPI_INT_WR_DMA_DONE_EN (BIT(8)) #define SPI_INT_WR_DMA_DONE_EN_M (BIT(8)) #define SPI_INT_WR_DMA_DONE_EN_V 0x1 #define SPI_INT_WR_DMA_DONE_EN_S 8 /* SPI_INT_RD_DMA_DONE_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: spi_slv_rd_dma Interrupt enable. 1: enable 0: disable*/ +/*description: spi_slv_rd_dma Interrupt enable. 1: enable 0: disable. Can be + configured in CONF state.*/ #define SPI_INT_RD_DMA_DONE_EN (BIT(7)) #define SPI_INT_RD_DMA_DONE_EN_M (BIT(7)) #define SPI_INT_RD_DMA_DONE_EN_V 0x1 #define SPI_INT_RD_DMA_DONE_EN_S 7 /* SPI_INT_WR_BUF_DONE_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: spi_slv_wr_buf Interrupt enable. 1: enable 0: disable*/ +/*description: spi_slv_wr_buf Interrupt enable. 1: enable 0: disable. Can be + configured in CONF state.*/ #define SPI_INT_WR_BUF_DONE_EN (BIT(6)) #define SPI_INT_WR_BUF_DONE_EN_M (BIT(6)) #define SPI_INT_WR_BUF_DONE_EN_V 0x1 #define SPI_INT_WR_BUF_DONE_EN_S 6 /* SPI_INT_RD_BUF_DONE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: spi_slv_rd_buf Interrupt enable. 1: enable 0: disable*/ +/*description: spi_slv_rd_buf Interrupt enable. 1: enable 0: disable. Can be + configured in CONF state.*/ #define SPI_INT_RD_BUF_DONE_EN (BIT(5)) #define SPI_INT_RD_BUF_DONE_EN_M (BIT(5)) #define SPI_INT_RD_BUF_DONE_EN_V 0x1 #define SPI_INT_RD_BUF_DONE_EN_S 5 /* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ /*description: The interrupt raw bit for the completion of any operation in - both the master mode and the slave mode.*/ + both the master mode and the slave mode. Can not be changed by CONF_buf.*/ #define SPI_TRANS_DONE (BIT(4)) #define SPI_TRANS_DONE_M (BIT(4)) #define SPI_TRANS_DONE_V 0x1 #define SPI_TRANS_DONE_S 4 #define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x038) -/* SPI_SLV_LAST_ADDR : R/W ;bitpos:[21:15] ;default: 7'b0 ; */ +/* SPI_SLV_LAST_ADDR : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ /*description: In the slave mode it is the value of address.*/ -#define SPI_SLV_LAST_ADDR 0x0000007F +#define SPI_SLV_LAST_ADDR 0x000000FF #define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S)) -#define SPI_SLV_LAST_ADDR_V 0x7F -#define SPI_SLV_LAST_ADDR_S 15 -/* SPI_SLV_LAST_COMMAND : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ +#define SPI_SLV_LAST_ADDR_V 0xFF +#define SPI_SLV_LAST_ADDR_S 24 +/* SPI_SLV_LAST_COMMAND : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ /*description: In the slave mode it is the value of command.*/ -#define SPI_SLV_LAST_COMMAND 0x00000007 +#define SPI_SLV_LAST_COMMAND 0x000000FF #define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) -#define SPI_SLV_LAST_COMMAND_V 0x7 -#define SPI_SLV_LAST_COMMAND_S 12 -/* SPI_SLV_WR_DMA_DONE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +#define SPI_SLV_LAST_COMMAND_V 0xFF +#define SPI_SLV_LAST_COMMAND_S 16 +/* SPI_SLV_WR_DMA_DONE : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: The interrupt raw bit for the completion of dma write operation - in the slave mode.*/ -#define SPI_SLV_WR_DMA_DONE (BIT(11)) -#define SPI_SLV_WR_DMA_DONE_M (BIT(11)) + in the slave mode. Can not be changed by CONF_buf.*/ +#define SPI_SLV_WR_DMA_DONE (BIT(15)) +#define SPI_SLV_WR_DMA_DONE_M (BIT(15)) #define SPI_SLV_WR_DMA_DONE_V 0x1 -#define SPI_SLV_WR_DMA_DONE_S 11 -/* SPI_SLV_WR_ADDR_BYTELEN : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: In the slave mode it is the address length in bytes for write-buffer - operation. The register value shall be byte_num.*/ -#define SPI_SLV_WR_ADDR_BYTELEN 0x0000000F -#define SPI_SLV_WR_ADDR_BYTELEN_M ((SPI_SLV_WR_ADDR_BYTELEN_V)<<(SPI_SLV_WR_ADDR_BYTELEN_S)) -#define SPI_SLV_WR_ADDR_BYTELEN_V 0xF -#define SPI_SLV_WR_ADDR_BYTELEN_S 4 -/* SPI_SLV_RD_ADDR_BYTELEN : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: In the slave mode it is the address length in bytes for read-buffer - operation. The register value shall be byte_num.*/ -#define SPI_SLV_RD_ADDR_BYTELEN 0x0000000F -#define SPI_SLV_RD_ADDR_BYTELEN_M ((SPI_SLV_RD_ADDR_BYTELEN_V)<<(SPI_SLV_RD_ADDR_BYTELEN_S)) -#define SPI_SLV_RD_ADDR_BYTELEN_V 0xF -#define SPI_SLV_RD_ADDR_BYTELEN_S 0 +#define SPI_SLV_WR_DMA_DONE_S 15 +/* SPI_SLV_CMD_ERR : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: 1: The command value of the last SPI transfer is not supported + by SPI slave. 0: The command value is supported or no command value is received.*/ +#define SPI_SLV_CMD_ERR (BIT(14)) +#define SPI_SLV_CMD_ERR_M (BIT(14)) +#define SPI_SLV_CMD_ERR_V 0x1 +#define SPI_SLV_CMD_ERR_S 14 +/* SPI_SLV_ADDR_ERR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: 1: The address value of the last SPI transfer is not supported + by SPI slave. 0: The address value is supported or no address value is received.*/ +#define SPI_SLV_ADDR_ERR (BIT(13)) +#define SPI_SLV_ADDR_ERR_M (BIT(13)) +#define SPI_SLV_ADDR_ERR_V 0x1 +#define SPI_SLV_ADDR_ERR_S 13 #define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x03C) /* SPI_SLV_RD_DMA_DONE : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for the completion of dma read operation - in the slave mode.*/ +/*description: The interrupt raw bit for the completion of Rd-DMA operation + in the slave mode. Can not be changed by CONF_buf.*/ #define SPI_SLV_RD_DMA_DONE (BIT(8)) #define SPI_SLV_RD_DMA_DONE_M (BIT(8)) #define SPI_SLV_RD_DMA_DONE_V 0x1 #define SPI_SLV_RD_DMA_DONE_S 8 -/* SPI_SLV_WR_DUMMY_BYTELEN : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ -/*description: In the slave mode it is the length in spi_clk byte cycles of - dummy phase for write operations.*/ -#define SPI_SLV_WR_DUMMY_BYTELEN 0x0000000F -#define SPI_SLV_WR_DUMMY_BYTELEN_M ((SPI_SLV_WR_DUMMY_BYTELEN_V)<<(SPI_SLV_WR_DUMMY_BYTELEN_S)) -#define SPI_SLV_WR_DUMMY_BYTELEN_V 0xF -#define SPI_SLV_WR_DUMMY_BYTELEN_S 4 -/* SPI_SLV_RD_DUMMY_BYTELEN : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: In the slave mode it is the length in spi_clk byte cycles of - dummy phase for read operations.*/ -#define SPI_SLV_RD_DUMMY_BYTELEN 0x0000000F -#define SPI_SLV_RD_DUMMY_BYTELEN_M ((SPI_SLV_RD_DUMMY_BYTELEN_V)<<(SPI_SLV_RD_DUMMY_BYTELEN_S)) -#define SPI_SLV_RD_DUMMY_BYTELEN_V 0xF -#define SPI_SLV_RD_DUMMY_BYTELEN_S 0 #define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x040) +/* SPI_CONF_BASE_BITLEN : R/W ;bitpos:[31:25] ;default: 7'd108 ; */ +/*description: The basic spi_clk cycles of CONF state. The real cycle length + of CONF state if spi_usr_conf is enabled is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0].*/ +#define SPI_CONF_BASE_BITLEN 0x0000007F +#define SPI_CONF_BASE_BITLEN_M ((SPI_CONF_BASE_BITLEN_V)<<(SPI_CONF_BASE_BITLEN_S)) +#define SPI_CONF_BASE_BITLEN_V 0x7F +#define SPI_CONF_BASE_BITLEN_S 25 /* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */ /*description: The interrupt raw bit for the completion of write-buffer operation - in the slave mode.*/ + in the slave mode. Can not be changed by CONF_buf.*/ #define SPI_SLV_WR_BUF_DONE (BIT(24)) #define SPI_SLV_WR_BUF_DONE_M (BIT(24)) #define SPI_SLV_WR_BUF_DONE_V 0x1 #define SPI_SLV_WR_BUF_DONE_S 24 -/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: In the slave mode it is the length in bits for write-buffer operations. - The register value shall be (bit_num-1).*/ -#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF -#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) -#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF -#define SPI_SLV_WRBUF_DBITLEN_S 0 #define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x044) +/* SPI_SEG_MAGIC_ERR : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: The recent magic value in CONF buffer is not right in master + DMA seg-trans mode. 0: others.*/ +#define SPI_SEG_MAGIC_ERR (BIT(25)) +#define SPI_SEG_MAGIC_ERR_M (BIT(25)) +#define SPI_SEG_MAGIC_ERR_V 0x1 +#define SPI_SEG_MAGIC_ERR_S 25 /* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */ /*description: The interrupt raw bit for the completion of read-buffer operation - in the slave mode.*/ + in the slave mode. Can not be changed by CONF_buf.*/ #define SPI_SLV_RD_BUF_DONE (BIT(24)) #define SPI_SLV_RD_BUF_DONE_M (BIT(24)) #define SPI_SLV_RD_BUF_DONE_V 0x1 #define SPI_SLV_RD_BUF_DONE_S 24 -/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ -/*description: In the slave mode it is the length in bits for read-buffer operations. - The register value shall be (bit_num-1).*/ -#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF -#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) -#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF -#define SPI_SLV_RDBUF_DBITLEN_S 0 +/* SPI_SLV_DMA_RD_BYTELEN : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: In the slave mode it is the length in bytes for read operations. + The register value shall be byte_num.*/ +#define SPI_SLV_DMA_RD_BYTELEN 0x000FFFFF +#define SPI_SLV_DMA_RD_BYTELEN_M ((SPI_SLV_DMA_RD_BYTELEN_V)<<(SPI_SLV_DMA_RD_BYTELEN_S)) +#define SPI_SLV_DMA_RD_BYTELEN_V 0xFFFFF +#define SPI_SLV_DMA_RD_BYTELEN_S 0 #define SPI_SLV_RD_BYTE_REG(i) (REG_SPI_BASE(i) + 0x048) -/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ -/*description: In the slave mode it is the byte number of read data.*/ -#define SPI_SLV_RDATA_BIT 0x00FFFFFF -#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) -#define SPI_SLV_RDATA_BIT_V 0xFFFFFF -#define SPI_SLV_RDATA_BIT_S 0 +/* SPI_USR_CONF : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: Enable the DMA CONF phase of current seg-trans operation + which means seg-trans will start. 0: This is not seg-trans mode.*/ +#define SPI_USR_CONF (BIT(31)) +#define SPI_USR_CONF_M (BIT(31)) +#define SPI_USR_CONF_V 0x1 +#define SPI_USR_CONF_S 31 +/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[29:24] ;default: 6'd23 ; */ +/*description: The magic value of BM table in master DMA seg-trans.*/ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000003F +#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S)) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x3F +#define SPI_DMA_SEG_MAGIC_VALUE_S 24 +/* SPI_SLV_WRBUF_BYTELEN_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave + data length in CPU controlled mode(Wr_BUF). 0: others*/ +#define SPI_SLV_WRBUF_BYTELEN_EN (BIT(23)) +#define SPI_SLV_WRBUF_BYTELEN_EN_M (BIT(23)) +#define SPI_SLV_WRBUF_BYTELEN_EN_V 0x1 +#define SPI_SLV_WRBUF_BYTELEN_EN_S 23 +/* SPI_SLV_RDBUF_BYTELEN_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: spi_slv_data_bytelen stores data byte length of master-read-slave + data length in CPU controlled mode(Rd_BUF). 0: others*/ +#define SPI_SLV_RDBUF_BYTELEN_EN (BIT(22)) +#define SPI_SLV_RDBUF_BYTELEN_EN_M (BIT(22)) +#define SPI_SLV_RDBUF_BYTELEN_EN_V 0x1 +#define SPI_SLV_RDBUF_BYTELEN_EN_S 22 +/* SPI_SLV_WRDMA_BYTELEN_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave + data length in DMA controlled mode(Wr_DMA). 0: others*/ +#define SPI_SLV_WRDMA_BYTELEN_EN (BIT(21)) +#define SPI_SLV_WRDMA_BYTELEN_EN_M (BIT(21)) +#define SPI_SLV_WRDMA_BYTELEN_EN_V 0x1 +#define SPI_SLV_WRDMA_BYTELEN_EN_S 21 +/* SPI_SLV_RDDMA_BYTELEN_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: 1: spi_slv_data_bytelen stores data byte length of master-read-slave + data length in DMA controlled mode(Rd_DMA). 0: others*/ +#define SPI_SLV_RDDMA_BYTELEN_EN (BIT(20)) +#define SPI_SLV_RDDMA_BYTELEN_EN_M (BIT(20)) +#define SPI_SLV_RDDMA_BYTELEN_EN_V 0x1 +#define SPI_SLV_RDDMA_BYTELEN_EN_S 20 +/* SPI_SLV_DATA_BYTELEN : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: The full-duplex or half-duplex data byte length of the last SPI + transfer in slave mode. In half-duplex mode this value is controlled by bits [23:20].*/ +#define SPI_SLV_DATA_BYTELEN 0x000FFFFF +#define SPI_SLV_DATA_BYTELEN_M ((SPI_SLV_DATA_BYTELEN_V)<<(SPI_SLV_DATA_BYTELEN_S)) +#define SPI_SLV_DATA_BYTELEN_V 0xFFFFF +#define SPI_SLV_DATA_BYTELEN_S 0 #define SPI_FSM_REG(i) (REG_SPI_BASE(i) + 0x050) -/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/* SPI_MST_DMA_RD_BYTELEN : R/W ;bitpos:[31:12] ;default: 20'h0 ; */ +/*description: Define the master DMA read byte length in non seg-trans or seg-trans + mode. Invalid when spi_rx_eof_en is 0. Can be configured in CONF state..*/ +#define SPI_MST_DMA_RD_BYTELEN 0x000FFFFF +#define SPI_MST_DMA_RD_BYTELEN_M ((SPI_MST_DMA_RD_BYTELEN_V)<<(SPI_MST_DMA_RD_BYTELEN_S)) +#define SPI_MST_DMA_RD_BYTELEN_V 0xFFFFF +#define SPI_MST_DMA_RD_BYTELEN_S 12 +/* SPI_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ /*description: The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ -#define SPI_ST 0x00000007 +#define SPI_ST 0x0000000F #define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) -#define SPI_ST_V 0x7 +#define SPI_ST_V 0xF #define SPI_ST_S 0 #define SPI_HOLD_REG(i) (REG_SPI_BASE(i) + 0x054) +/* SPI_DMA_SEG_TRANS_DONE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: spi master DMA full-duplex/half-duplex seg-trans ends or + slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/ +#define SPI_DMA_SEG_TRANS_DONE (BIT(7)) +#define SPI_DMA_SEG_TRANS_DONE_M (BIT(7)) +#define SPI_DMA_SEG_TRANS_DONE_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_S 7 /* SPI_HOLD_OUT_TIME : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/ +/*description: set the hold cycles of output spi_hold signal when spi_hold_out_en + is enable. Can be configured in CONF state.*/ #define SPI_HOLD_OUT_TIME 0x00000007 #define SPI_HOLD_OUT_TIME_M ((SPI_HOLD_OUT_TIME_V)<<(SPI_HOLD_OUT_TIME_S)) #define SPI_HOLD_OUT_TIME_V 0x7 #define SPI_HOLD_OUT_TIME_S 4 /* SPI_HOLD_OUT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: Enable set spi output hold value to spi_hold_reg. It can be used - to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/ + to hold spi state machine with spi_ext_hold_en and other usr hold signals. Can be configured in CONF state.*/ #define SPI_HOLD_OUT_EN (BIT(3)) #define SPI_HOLD_OUT_EN_M (BIT(3)) #define SPI_HOLD_OUT_EN_V 0x1 #define SPI_HOLD_OUT_EN_S 3 /* SPI_HOLD_VAL_REG : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: spi hold output value which should be used with spi_hold_out_en.*/ +/*description: spi hold output value which should be used with spi_hold_out_en. + Can be configured in CONF state.*/ #define SPI_HOLD_VAL_REG (BIT(2)) #define SPI_HOLD_VAL_REG_M (BIT(2)) #define SPI_HOLD_VAL_REG_V 0x1 #define SPI_HOLD_VAL_REG_S 2 /* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: This register is for two SPI masters to share the same cs clock - and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/ + and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state.*/ #define SPI_INT_HOLD_ENA 0x00000003 #define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) #define SPI_INT_HOLD_ENA_V 0x3 #define SPI_INT_HOLD_ENA_S 0 #define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x058) -/* SPI_CONTINUE_POP_DATA_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Disable spi slave dma to pop data continuously in next transmission - in dma half duplex slave mode. 1: disable continue transmit. 0: enable continue transmit.*/ -#define SPI_CONTINUE_POP_DATA_CLR (BIT(17)) -#define SPI_CONTINUE_POP_DATA_CLR_M (BIT(17)) -#define SPI_CONTINUE_POP_DATA_CLR_V 0x1 -#define SPI_CONTINUE_POP_DATA_CLR_S 17 +/* SPI_EXT_MEM_BK_SIZE : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: Select the external memory block size.*/ +#define SPI_EXT_MEM_BK_SIZE 0x00000003 +#define SPI_EXT_MEM_BK_SIZE_M ((SPI_EXT_MEM_BK_SIZE_V)<<(SPI_EXT_MEM_BK_SIZE_S)) +#define SPI_EXT_MEM_BK_SIZE_V 0x3 +#define SPI_EXT_MEM_BK_SIZE_S 26 +/* SPI_DMA_OUTFIFO_EMPTY_ERR : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which + means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR (BIT(25)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_M (BIT(25)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_S 25 +/* SPI_DMA_INFIFO_FULL_ERR : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1:spi_dma_infifo_full and spi_push_data_prep are valid which + means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/ +#define SPI_DMA_INFIFO_FULL_ERR (BIT(24)) +#define SPI_DMA_INFIFO_FULL_ERR_M (BIT(24)) +#define SPI_DMA_INFIFO_FULL_ERR_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_S 24 +/* SPI_DMA_OUTFIFO_EMPTY_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/ +#define SPI_DMA_OUTFIFO_EMPTY_CLR (BIT(23)) +#define SPI_DMA_OUTFIFO_EMPTY_CLR_M (BIT(23)) +#define SPI_DMA_OUTFIFO_EMPTY_CLR_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_CLR_S 23 +/* SPI_DMA_INFIFO_FULL_CLR : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/ +#define SPI_DMA_INFIFO_FULL_CLR (BIT(22)) +#define SPI_DMA_INFIFO_FULL_CLR_M (BIT(22)) +#define SPI_DMA_INFIFO_FULL_CLR_V 0x1 +#define SPI_DMA_INFIFO_FULL_CLR_S 22 +/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data + bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (BIT(21)) +#define SPI_RX_EOF_EN_V 0x1 +#define SPI_RX_EOF_EN_S 21 +/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 +/* SPI_SLV_LAST_SEG_POP_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: 1: Clear spi_slv_seg_frt_pop_mask. 0 : others*/ +#define SPI_SLV_LAST_SEG_POP_CLR (BIT(17)) +#define SPI_SLV_LAST_SEG_POP_CLR_M (BIT(17)) +#define SPI_SLV_LAST_SEG_POP_CLR_V 0x1 +#define SPI_SLV_LAST_SEG_POP_CLR_S 17 /* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ /*description: spi dma continue tx/rx data.*/ #define SPI_DMA_CONTINUE (BIT(16)) @@ -890,55 +1150,61 @@ extern "C" { #define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x064) /* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for sending all the packets to host done.*/ +/*description: The enable bit for sending all the packets to host done. Can + be configured in CONF state.*/ #define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) #define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) #define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 #define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 /* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for sending a packet to host done.*/ +/*description: The enable bit for sending a packet to host done. Can be configured + in CONF state.*/ #define SPI_OUT_EOF_INT_ENA (BIT(7)) #define SPI_OUT_EOF_INT_ENA_M (BIT(7)) #define SPI_OUT_EOF_INT_ENA_V 0x1 #define SPI_OUT_EOF_INT_ENA_S 7 /* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a outlink descriptor .*/ +/*description: The enable bit for completing usage of a outlink descriptor . + Can be configured in CONF state.*/ #define SPI_OUT_DONE_INT_ENA (BIT(6)) #define SPI_OUT_DONE_INT_ENA_M (BIT(6)) #define SPI_OUT_DONE_INT_ENA_V 0x1 #define SPI_OUT_DONE_INT_ENA_S 6 /* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for completing receiving all the packets from host.*/ +/*description: The enable bit for completing receiving all the packets from + host. Can be configured in CONF state.*/ #define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) #define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) #define SPI_IN_SUC_EOF_INT_ENA_V 0x1 #define SPI_IN_SUC_EOF_INT_ENA_S 5 /* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for receiving error.*/ +/*description: The enable bit for receiving error. Can be configured in CONF state.*/ #define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) #define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) #define SPI_IN_ERR_EOF_INT_ENA_V 0x1 #define SPI_IN_ERR_EOF_INT_ENA_S 4 /* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for completing usage of a inlink descriptor.*/ +/*description: The enable bit for completing usage of a inlink descriptor. Can + be configured in CONF state.*/ #define SPI_IN_DONE_INT_ENA (BIT(3)) #define SPI_IN_DONE_INT_ENA_M (BIT(3)) #define SPI_IN_DONE_INT_ENA_V 0x1 #define SPI_IN_DONE_INT_ENA_S 3 /* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for inlink descriptor error.*/ +/*description: The enable bit for inlink descriptor error. Can be configured in CONF state.*/ #define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) #define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) #define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 #define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 /* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for outlink descriptor error.*/ +/*description: The enable bit for outlink descriptor error. Can be configured in CONF state.*/ #define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) #define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) #define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 #define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 /* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for lack of enough inlink descriptors.*/ +/*description: The enable bit for lack of enough inlink descriptors. Can be + configured in CONF state.*/ #define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) #define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) #define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 @@ -946,55 +1212,60 @@ extern "C" { #define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x068) /* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw bit for sending all the packets to host done.*/ +/*description: The raw bit for sending all the packets to host done. Can be + configured in CONF state.*/ #define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) #define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) #define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 #define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 /* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw bit for sending a packet to host done.*/ +/*description: The raw bit for sending a packet to host done. Can be configured in CONF state.*/ #define SPI_OUT_EOF_INT_RAW (BIT(7)) #define SPI_OUT_EOF_INT_RAW_M (BIT(7)) #define SPI_OUT_EOF_INT_RAW_V 0x1 #define SPI_OUT_EOF_INT_RAW_S 7 /* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a outlink descriptor.*/ +/*description: The raw bit for completing usage of a outlink descriptor. Can + be configured in CONF state.*/ #define SPI_OUT_DONE_INT_RAW (BIT(6)) #define SPI_OUT_DONE_INT_RAW_M (BIT(6)) #define SPI_OUT_DONE_INT_RAW_V 0x1 #define SPI_OUT_DONE_INT_RAW_S 6 /* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit for completing receiving all the packets from host.*/ +/*description: The raw bit for completing receiving all the packets from host. + Can be configured in CONF state.*/ #define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) #define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) #define SPI_IN_SUC_EOF_INT_RAW_V 0x1 #define SPI_IN_SUC_EOF_INT_RAW_S 5 /* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit for receiving error.*/ +/*description: The raw bit for receiving error. Can be configured in CONF state.*/ #define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) #define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) #define SPI_IN_ERR_EOF_INT_RAW_V 0x1 #define SPI_IN_ERR_EOF_INT_RAW_S 4 /* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for completing usage of a inlink descriptor.*/ +/*description: The raw bit for completing usage of a inlink descriptor. Can + be configured in CONF state.*/ #define SPI_IN_DONE_INT_RAW (BIT(3)) #define SPI_IN_DONE_INT_RAW_M (BIT(3)) #define SPI_IN_DONE_INT_RAW_V 0x1 #define SPI_IN_DONE_INT_RAW_S 3 /* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for inlink descriptor error.*/ +/*description: The raw bit for inlink descriptor error. Can be configured in CONF state.*/ #define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) #define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) #define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 #define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 /* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for outlink descriptor error.*/ +/*description: The raw bit for outlink descriptor error. Can be configured in CONF state.*/ #define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) #define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) #define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 #define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 /* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for lack of enough inlink descriptors.*/ +/*description: The raw bit for lack of enough inlink descriptors. Can be configured + in CONF state.*/ #define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) #define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) #define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 @@ -1058,55 +1329,61 @@ extern "C" { #define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x070) /* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The clear bit for sending all the packets to host done.*/ +/*description: The clear bit for sending all the packets to host done. Can be + configured in CONF state.*/ #define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) #define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) #define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 #define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 /* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The clear bit for sending a packet to host done.*/ +/*description: The clear bit for sending a packet to host done. Can be configured + in CONF state.*/ #define SPI_OUT_EOF_INT_CLR (BIT(7)) #define SPI_OUT_EOF_INT_CLR_M (BIT(7)) #define SPI_OUT_EOF_INT_CLR_V 0x1 #define SPI_OUT_EOF_INT_CLR_S 7 /* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a outlink descriptor.*/ +/*description: The clear bit for completing usage of a outlink descriptor. Can + be configured in CONF state.*/ #define SPI_OUT_DONE_INT_CLR (BIT(6)) #define SPI_OUT_DONE_INT_CLR_M (BIT(6)) #define SPI_OUT_DONE_INT_CLR_V 0x1 #define SPI_OUT_DONE_INT_CLR_S 6 /* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The clear bit for completing receiving all the packets from host.*/ +/*description: The clear bit for completing receiving all the packets from host. + Can be configured in CONF state.*/ #define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) #define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) #define SPI_IN_SUC_EOF_INT_CLR_V 0x1 #define SPI_IN_SUC_EOF_INT_CLR_S 5 /* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The clear bit for receiving error.*/ +/*description: The clear bit for receiving error. Can be configured in CONF state.*/ #define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) #define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) #define SPI_IN_ERR_EOF_INT_CLR_V 0x1 #define SPI_IN_ERR_EOF_INT_CLR_S 4 /* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for completing usage of a inlink descriptor.*/ +/*description: The clear bit for completing usage of a inlink descriptor. Can + be configured in CONF state.*/ #define SPI_IN_DONE_INT_CLR (BIT(3)) #define SPI_IN_DONE_INT_CLR_M (BIT(3)) #define SPI_IN_DONE_INT_CLR_V 0x1 #define SPI_IN_DONE_INT_CLR_S 3 /* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for inlink descriptor error.*/ +/*description: The clear bit for inlink descriptor error. Can be configured in CONF state.*/ #define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) #define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) #define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 #define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 /* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for outlink descriptor error.*/ +/*description: The clear bit for outlink descriptor error. Can be configured in CONF state.*/ #define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) #define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) #define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 #define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 /* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for lack of enough inlink descriptors.*/ +/*description: The clear bit for lack of enough inlink descriptors. Can be configured + in CONF state.*/ #define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) #define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) #define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 @@ -1413,253 +1690,410 @@ extern "C" { #define SPI_BUF17_S 0 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x0EC) -/* SPI_DIN3_DLY_EDGE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify input line timing.*/ -#define SPI_DIN3_DLY_EDGE (BIT(21)) -#define SPI_DIN3_DLY_EDGE_M (BIT(21)) -#define SPI_DIN3_DLY_EDGE_V 0x1 -#define SPI_DIN3_DLY_EDGE_S 21 -/* SPI_DIN2_DLY_EDGE : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify input line timing.*/ -#define SPI_DIN2_DLY_EDGE (BIT(20)) -#define SPI_DIN2_DLY_EDGE_M (BIT(20)) -#define SPI_DIN2_DLY_EDGE_V 0x1 -#define SPI_DIN2_DLY_EDGE_S 20 -/* SPI_DIN1_DLY_EDGE : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify input line timing.*/ -#define SPI_DIN1_DLY_EDGE (BIT(19)) -#define SPI_DIN1_DLY_EDGE_M (BIT(19)) -#define SPI_DIN1_DLY_EDGE_V 0x1 -#define SPI_DIN1_DLY_EDGE_S 19 -/* SPI_DIN0_DLY_EDGE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify input line timing.*/ -#define SPI_DIN0_DLY_EDGE (BIT(18)) -#define SPI_DIN0_DLY_EDGE_M (BIT(18)) -#define SPI_DIN0_DLY_EDGE_V 0x1 -#define SPI_DIN0_DLY_EDGE_S 18 -/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/* SPI_TIMING_CLK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.*/ +#define SPI_TIMING_CLK_ENA (BIT(24)) +#define SPI_TIMING_CLK_ENA_M (BIT(24)) +#define SPI_TIMING_CLK_ENA_V 0x1 +#define SPI_TIMING_CLK_ENA_S 24 +/* SPI_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_DIN3_MODE 0x00000003 + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN7_MODE 0x00000007 +#define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S)) +#define SPI_DIN7_MODE_V 0x7 +#define SPI_DIN7_MODE_S 21 +/* SPI_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN6_MODE 0x00000007 +#define SPI_DIN6_MODE_M ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S)) +#define SPI_DIN6_MODE_V 0x7 +#define SPI_DIN6_MODE_S 18 +/* SPI_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN5_MODE 0x00000007 +#define SPI_DIN5_MODE_M ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S)) +#define SPI_DIN5_MODE_V 0x7 +#define SPI_DIN5_MODE_S 15 +/* SPI_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN4_MODE 0x00000007 +#define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S)) +#define SPI_DIN4_MODE_V 0x7 +#define SPI_DIN4_MODE_S 12 +/* SPI_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN3_MODE 0x00000007 #define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S)) -#define SPI_DIN3_MODE_V 0x3 -#define SPI_DIN3_MODE_S 6 -/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +#define SPI_DIN3_MODE_V 0x7 +#define SPI_DIN3_MODE_S 9 +/* SPI_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_DIN2_MODE 0x00000003 + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN2_MODE 0x00000007 #define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S)) -#define SPI_DIN2_MODE_V 0x3 -#define SPI_DIN2_MODE_S 4 -/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +#define SPI_DIN2_MODE_V 0x7 +#define SPI_DIN2_MODE_S 6 +/* SPI_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_DIN1_MODE 0x00000003 + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN1_MODE 0x00000007 #define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S)) -#define SPI_DIN1_MODE_V 0x3 -#define SPI_DIN1_MODE_S 2 -/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +#define SPI_DIN1_MODE_V 0x7 +#define SPI_DIN1_MODE_S 3 +/* SPI_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: input - without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ -#define SPI_DIN0_MODE 0x00000003 + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN0_MODE 0x00000007 #define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S)) -#define SPI_DIN0_MODE_V 0x3 +#define SPI_DIN0_MODE_V 0x7 #define SPI_DIN0_MODE_S 0 #define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x0F0) +/* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN7_NUM 0x00000003 +#define SPI_DIN7_NUM_M ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S)) +#define SPI_DIN7_NUM_V 0x3 +#define SPI_DIN7_NUM_S 14 +/* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN6_NUM 0x00000003 +#define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S)) +#define SPI_DIN6_NUM_V 0x3 +#define SPI_DIN6_NUM_S 12 +/* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN5_NUM 0x00000003 +#define SPI_DIN5_NUM_M ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S)) +#define SPI_DIN5_NUM_V 0x3 +#define SPI_DIN5_NUM_S 10 +/* SPI_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN4_NUM 0x00000003 +#define SPI_DIN4_NUM_M ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S)) +#define SPI_DIN4_NUM_V 0x3 +#define SPI_DIN4_NUM_S 8 /* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DIN3_NUM 0x00000003 #define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S)) #define SPI_DIN3_NUM_V 0x3 #define SPI_DIN3_NUM_S 6 /* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DIN2_NUM 0x00000003 #define SPI_DIN2_NUM_M ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S)) #define SPI_DIN2_NUM_V 0x3 #define SPI_DIN2_NUM_S 4 /* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DIN1_NUM 0x00000003 #define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S)) #define SPI_DIN1_NUM_V 0x3 #define SPI_DIN1_NUM_S 2 /* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: the input signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DIN0_NUM 0x00000003 #define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S)) #define SPI_DIN0_NUM_V 0x3 #define SPI_DIN0_NUM_S 0 #define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x0F4) -/* SPI_DOUT4_DLY_EDGE : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify output line timing.*/ -#define SPI_DOUT4_DLY_EDGE (BIT(22)) -#define SPI_DOUT4_DLY_EDGE_M (BIT(22)) -#define SPI_DOUT4_DLY_EDGE_V 0x1 -#define SPI_DOUT4_DLY_EDGE_S 22 -/* SPI_DOUT3_DLY_EDGE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify output line timing.*/ -#define SPI_DOUT3_DLY_EDGE (BIT(21)) -#define SPI_DOUT3_DLY_EDGE_M (BIT(21)) -#define SPI_DOUT3_DLY_EDGE_V 0x1 -#define SPI_DOUT3_DLY_EDGE_S 21 -/* SPI_DOUT2_DLY_EDGE : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify output line timing.*/ -#define SPI_DOUT2_DLY_EDGE (BIT(20)) -#define SPI_DOUT2_DLY_EDGE_M (BIT(20)) -#define SPI_DOUT2_DLY_EDGE_V 0x1 -#define SPI_DOUT2_DLY_EDGE_S 20 -/* SPI_DOUT1_DLY_EDGE : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify output line timing.*/ -#define SPI_DOUT1_DLY_EDGE (BIT(19)) -#define SPI_DOUT1_DLY_EDGE_M (BIT(19)) -#define SPI_DOUT1_DLY_EDGE_V 0x1 -#define SPI_DOUT1_DLY_EDGE_S 19 -/* SPI_DOUT0_DLY_EDGE : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The bit is used to select the spi clock edge to modify output line timing.*/ -#define SPI_DOUT0_DLY_EDGE (BIT(18)) -#define SPI_DOUT0_DLY_EDGE_M (BIT(18)) -#define SPI_DOUT0_DLY_EDGE_V 0x1 -#define SPI_DOUT0_DLY_EDGE_S 18 -/* SPI_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/* SPI_DOUT7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_DOUT4_MODE 0x00000003 + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT7_MODE 0x00000007 +#define SPI_DOUT7_MODE_M ((SPI_DOUT7_MODE_V)<<(SPI_DOUT7_MODE_S)) +#define SPI_DOUT7_MODE_V 0x7 +#define SPI_DOUT7_MODE_S 21 +/* SPI_DOUT6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT6_MODE 0x00000007 +#define SPI_DOUT6_MODE_M ((SPI_DOUT6_MODE_V)<<(SPI_DOUT6_MODE_S)) +#define SPI_DOUT6_MODE_V 0x7 +#define SPI_DOUT6_MODE_S 18 +/* SPI_DOUT5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT5_MODE 0x00000007 +#define SPI_DOUT5_MODE_M ((SPI_DOUT5_MODE_V)<<(SPI_DOUT5_MODE_S)) +#define SPI_DOUT5_MODE_V 0x7 +#define SPI_DOUT5_MODE_S 15 +/* SPI_DOUT4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT4_MODE 0x00000007 #define SPI_DOUT4_MODE_M ((SPI_DOUT4_MODE_V)<<(SPI_DOUT4_MODE_S)) -#define SPI_DOUT4_MODE_V 0x3 -#define SPI_DOUT4_MODE_S 8 -/* SPI_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +#define SPI_DOUT4_MODE_V 0x7 +#define SPI_DOUT4_MODE_S 12 +/* SPI_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_DOUT3_MODE 0x00000003 + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT3_MODE 0x00000007 #define SPI_DOUT3_MODE_M ((SPI_DOUT3_MODE_V)<<(SPI_DOUT3_MODE_S)) -#define SPI_DOUT3_MODE_V 0x3 -#define SPI_DOUT3_MODE_S 6 -/* SPI_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +#define SPI_DOUT3_MODE_V 0x7 +#define SPI_DOUT3_MODE_S 9 +/* SPI_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_DOUT2_MODE 0x00000003 + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT2_MODE 0x00000007 #define SPI_DOUT2_MODE_M ((SPI_DOUT2_MODE_V)<<(SPI_DOUT2_MODE_S)) -#define SPI_DOUT2_MODE_V 0x3 -#define SPI_DOUT2_MODE_S 4 -/* SPI_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +#define SPI_DOUT2_MODE_V 0x7 +#define SPI_DOUT2_MODE_S 6 +/* SPI_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_DOUT1_MODE 0x00000003 + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT1_MODE 0x00000007 #define SPI_DOUT1_MODE_M ((SPI_DOUT1_MODE_V)<<(SPI_DOUT1_MODE_S)) -#define SPI_DOUT1_MODE_V 0x3 -#define SPI_DOUT1_MODE_S 2 -/* SPI_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +#define SPI_DOUT1_MODE_V 0x7 +#define SPI_DOUT1_MODE_S 3 +/* SPI_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: output - without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ -#define SPI_DOUT0_MODE 0x00000003 + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DOUT0_MODE 0x00000007 #define SPI_DOUT0_MODE_M ((SPI_DOUT0_MODE_V)<<(SPI_DOUT0_MODE_S)) -#define SPI_DOUT0_MODE_V 0x3 +#define SPI_DOUT0_MODE_V 0x7 #define SPI_DOUT0_MODE_S 0 #define SPI_DOUT_NUM_REG(i) (REG_SPI_BASE(i) + 0x0F8) +/* SPI_DOUT7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DOUT7_NUM 0x00000003 +#define SPI_DOUT7_NUM_M ((SPI_DOUT7_NUM_V)<<(SPI_DOUT7_NUM_S)) +#define SPI_DOUT7_NUM_V 0x3 +#define SPI_DOUT7_NUM_S 14 +/* SPI_DOUT6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DOUT6_NUM 0x00000003 +#define SPI_DOUT6_NUM_M ((SPI_DOUT6_NUM_V)<<(SPI_DOUT6_NUM_S)) +#define SPI_DOUT6_NUM_V 0x3 +#define SPI_DOUT6_NUM_S 12 +/* SPI_DOUT5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DOUT5_NUM 0x00000003 +#define SPI_DOUT5_NUM_M ((SPI_DOUT5_NUM_V)<<(SPI_DOUT5_NUM_S)) +#define SPI_DOUT5_NUM_V 0x3 +#define SPI_DOUT5_NUM_S 10 /* SPI_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DOUT4_NUM 0x00000003 #define SPI_DOUT4_NUM_M ((SPI_DOUT4_NUM_V)<<(SPI_DOUT4_NUM_S)) #define SPI_DOUT4_NUM_V 0x3 #define SPI_DOUT4_NUM_S 8 /* SPI_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DOUT3_NUM 0x00000003 #define SPI_DOUT3_NUM_M ((SPI_DOUT3_NUM_V)<<(SPI_DOUT3_NUM_S)) #define SPI_DOUT3_NUM_V 0x3 #define SPI_DOUT3_NUM_S 6 /* SPI_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DOUT2_NUM 0x00000003 #define SPI_DOUT2_NUM_M ((SPI_DOUT2_NUM_V)<<(SPI_DOUT2_NUM_S)) #define SPI_DOUT2_NUM_V 0x3 #define SPI_DOUT2_NUM_S 4 /* SPI_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DOUT1_NUM 0x00000003 #define SPI_DOUT1_NUM_M ((SPI_DOUT1_NUM_V)<<(SPI_DOUT1_NUM_S)) #define SPI_DOUT1_NUM_V 0x3 #define SPI_DOUT1_NUM_S 2 /* SPI_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ /*description: the output signals are delayed by system clock cycles 0: delayed - by 1 cycle 1: delayed by 2 cycles ...*/ + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ #define SPI_DOUT0_NUM 0x00000003 #define SPI_DOUT0_NUM_M ((SPI_DOUT0_NUM_V)<<(SPI_DOUT0_NUM_S)) #define SPI_DOUT0_NUM_V 0x3 #define SPI_DOUT0_NUM_S 0 -#define SPI_SPR_CFG0_REG(i) (REG_SPI_BASE(i) + 0x0FC) -/* SPI_SOP_DQS_EDGE : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SPI_SOP_DQS_EDGE (BIT(21)) -#define SPI_SOP_DQS_EDGE_M (BIT(21)) -#define SPI_SOP_DQS_EDGE_V 0x1 -#define SPI_SOP_DQS_EDGE_S 21 -/* SPI_SOP_WCMD : R/W ;bitpos:[20:13] ;default: 8'd2 ; */ -/*description: */ -#define SPI_SOP_WCMD 0x000000FF -#define SPI_SOP_WCMD_M ((SPI_SOP_WCMD_V)<<(SPI_SOP_WCMD_S)) -#define SPI_SOP_WCMD_V 0xFF -#define SPI_SOP_WCMD_S 13 -/* SPI_SOP_RCMD : R/W ;bitpos:[12:5] ;default: 8'd3 ; */ -/*description: */ -#define SPI_SOP_RCMD 0x000000FF -#define SPI_SOP_RCMD_M ((SPI_SOP_RCMD_V)<<(SPI_SOP_RCMD_S)) -#define SPI_SOP_RCMD_V 0xFF -#define SPI_SOP_RCMD_S 5 -/* SPI_SOP_MODE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ -/*description: */ -#define SPI_SOP_MODE 0x0000000F -#define SPI_SOP_MODE_M ((SPI_SOP_MODE_V)<<(SPI_SOP_MODE_S)) -#define SPI_SOP_MODE_V 0xF -#define SPI_SOP_MODE_S 1 -/* SPI_SOP_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SPI_SOP_EN (BIT(0)) -#define SPI_SOP_EN_M (BIT(0)) -#define SPI_SOP_EN_V 0x1 -#define SPI_SOP_EN_S 0 +#define SPI_LCD_CTRL_REG(i) (REG_SPI_BASE(i) + 0x0FC) +/* SPI_LCD_SRGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: Enable LCD mode output vsync hsync de. 0: Disable. Can be + configured in CONF state.*/ +#define SPI_LCD_SRGB_MODE_EN (BIT(31)) +#define SPI_LCD_SRGB_MODE_EN_M (BIT(31)) +#define SPI_LCD_SRGB_MODE_EN_V 0x1 +#define SPI_LCD_SRGB_MODE_EN_S 31 +/* SPI_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */ +/*description: It is the vertical total height of a frame. Can be configured in CONF state.*/ +#define SPI_LCD_VT_HEIGHT 0x000003FF +#define SPI_LCD_VT_HEIGHT_M ((SPI_LCD_VT_HEIGHT_V)<<(SPI_LCD_VT_HEIGHT_S)) +#define SPI_LCD_VT_HEIGHT_V 0x3FF +#define SPI_LCD_VT_HEIGHT_S 21 +/* SPI_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */ +/*description: It is the vertical active height of a frame. Can be configured in CONF state.*/ +#define SPI_LCD_VA_HEIGHT 0x000003FF +#define SPI_LCD_VA_HEIGHT_M ((SPI_LCD_VA_HEIGHT_V)<<(SPI_LCD_VA_HEIGHT_S)) +#define SPI_LCD_VA_HEIGHT_V 0x3FF +#define SPI_LCD_VA_HEIGHT_S 11 +/* SPI_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */ +/*description: It is the horizontal blank front porch of a frame. Can be configured + in CONF state.*/ +#define SPI_LCD_HB_FRONT 0x000007FF +#define SPI_LCD_HB_FRONT_M ((SPI_LCD_HB_FRONT_V)<<(SPI_LCD_HB_FRONT_S)) +#define SPI_LCD_HB_FRONT_V 0x7FF +#define SPI_LCD_HB_FRONT_S 0 -#define SPI_SPR_CFG1_REG(i) (REG_SPI_BASE(i) + 0x100) -/* SPI_SOP_DC_MODE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SPI_SOP_DC_MODE (BIT(24)) -#define SPI_SOP_DC_MODE_M (BIT(24)) -#define SPI_SOP_DC_MODE_V 0x1 -#define SPI_SOP_DC_MODE_S 24 -/* SPI_SOP_DLEN : R/W ;bitpos:[23:18] ;default: 6'd0 ; */ -/*description: */ -#define SPI_SOP_DLEN 0x0000003F -#define SPI_SOP_DLEN_M ((SPI_SOP_DLEN_V)<<(SPI_SOP_DLEN_S)) -#define SPI_SOP_DLEN_V 0x3F -#define SPI_SOP_DLEN_S 18 -/* SPI_SOP_LEN : R/W ;bitpos:[17:12] ;default: 6'd0 ; */ -/*description: */ -#define SPI_SOP_LEN 0x0000003F -#define SPI_SOP_LEN_M ((SPI_SOP_LEN_V)<<(SPI_SOP_LEN_S)) -#define SPI_SOP_LEN_V 0x3F -#define SPI_SOP_LEN_S 12 -/* SPI_SOP_ITL : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ -/*description: */ -#define SPI_SOP_ITL 0x00000FFF -#define SPI_SOP_ITL_M ((SPI_SOP_ITL_V)<<(SPI_SOP_ITL_S)) -#define SPI_SOP_ITL_V 0xFFF -#define SPI_SOP_ITL_S 0 +#define SPI_LCD_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x0100) +/* SPI_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */ +/*description: It is the horizontal total width of a frame. Can be configured in CONF state.*/ +#define SPI_LCD_HT_WIDTH 0x00000FFF +#define SPI_LCD_HT_WIDTH_M ((SPI_LCD_HT_WIDTH_V)<<(SPI_LCD_HT_WIDTH_S)) +#define SPI_LCD_HT_WIDTH_V 0xFFF +#define SPI_LCD_HT_WIDTH_S 20 +/* SPI_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */ +/*description: It is the horizontal active width of a frame. Can be configured in CONF state.*/ +#define SPI_LCD_HA_WIDTH 0x00000FFF +#define SPI_LCD_HA_WIDTH_M ((SPI_LCD_HA_WIDTH_V)<<(SPI_LCD_HA_WIDTH_S)) +#define SPI_LCD_HA_WIDTH_V 0xFFF +#define SPI_LCD_HA_WIDTH_S 8 +/* SPI_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: It is the vertical blank front porch of a frame. Can be configured + in CONF state.*/ +#define SPI_LCD_VB_FRONT 0x000000FF +#define SPI_LCD_VB_FRONT_M ((SPI_LCD_VB_FRONT_V)<<(SPI_LCD_VB_FRONT_S)) +#define SPI_LCD_VB_FRONT_V 0xFF +#define SPI_LCD_VB_FRONT_S 0 + +#define SPI_LCD_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x0104) +/* SPI_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: It is the position of spi_hsync_out active pulse in a line. Can + be configured in CONF state.*/ +#define SPI_LCD_HSYNC_POSITION 0x000000FF +#define SPI_LCD_HSYNC_POSITION_M ((SPI_LCD_HSYNC_POSITION_V)<<(SPI_LCD_HSYNC_POSITION_S)) +#define SPI_LCD_HSYNC_POSITION_V 0xFF +#define SPI_LCD_HSYNC_POSITION_S 24 +/* SPI_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: It is the idle value of spi_hsync_out. Can be configured in CONF state.*/ +#define SPI_HSYNC_IDLE_POL (BIT(23)) +#define SPI_HSYNC_IDLE_POL_M (BIT(23)) +#define SPI_HSYNC_IDLE_POL_V 0x1 +#define SPI_HSYNC_IDLE_POL_S 23 +/* SPI_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd0 ; */ +/*description: It is the position of spi_hsync_out active pulse in a line. Can + be configured in CONF state.*/ +#define SPI_LCD_HSYNC_WIDTH 0x0000007F +#define SPI_LCD_HSYNC_WIDTH_M ((SPI_LCD_HSYNC_WIDTH_V)<<(SPI_LCD_HSYNC_WIDTH_S)) +#define SPI_LCD_HSYNC_WIDTH_V 0x7F +#define SPI_LCD_HSYNC_WIDTH_S 16 +/* SPI_LCD_VSYNC_POSITION : R/W ;bitpos:[15:8] ;default: 8'd0 ; */ +/*description: It is the position of spi_vsync_out active pulse in a line. Can + be configured in CONF state.*/ +#define SPI_LCD_VSYNC_POSITION 0x000000FF +#define SPI_LCD_VSYNC_POSITION_M ((SPI_LCD_VSYNC_POSITION_V)<<(SPI_LCD_VSYNC_POSITION_S)) +#define SPI_LCD_VSYNC_POSITION_V 0xFF +#define SPI_LCD_VSYNC_POSITION_S 8 +/* SPI_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: It is the idle value of spi_vsync_out. Can be configured in CONF state.*/ +#define SPI_VSYNC_IDLE_POL (BIT(7)) +#define SPI_VSYNC_IDLE_POL_M (BIT(7)) +#define SPI_VSYNC_IDLE_POL_V 0x1 +#define SPI_VSYNC_IDLE_POL_S 7 +/* SPI_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/*description: It is the position of spi_vsync_out active pulse in a line. Can + be configured in CONF state.*/ +#define SPI_LCD_VSYNC_WIDTH 0x0000007F +#define SPI_LCD_VSYNC_WIDTH_M ((SPI_LCD_VSYNC_WIDTH_V)<<(SPI_LCD_VSYNC_WIDTH_S)) +#define SPI_LCD_VSYNC_WIDTH_V 0x7F +#define SPI_LCD_VSYNC_WIDTH_S 0 + +#define SPI_LCD_D_MODE_REG(i) (REG_SPI_BASE(i) + 0x108) +/* SPI_D_VSYNC_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: the output spi_vsync is delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_D_VSYNC_MODE 0x00000007 +#define SPI_D_VSYNC_MODE_M ((SPI_D_VSYNC_MODE_V)<<(SPI_D_VSYNC_MODE_S)) +#define SPI_D_VSYNC_MODE_V 0x7 +#define SPI_D_VSYNC_MODE_S 12 +/* SPI_D_HSYNC_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: the output spi_hsync is delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_D_HSYNC_MODE 0x00000007 +#define SPI_D_HSYNC_MODE_M ((SPI_D_HSYNC_MODE_V)<<(SPI_D_HSYNC_MODE_S)) +#define SPI_D_HSYNC_MODE_V 0x7 +#define SPI_D_HSYNC_MODE_S 9 +/* SPI_D_DE_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ +/*description: the output spi_de is delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_D_DE_MODE 0x00000007 +#define SPI_D_DE_MODE_M ((SPI_D_DE_MODE_V)<<(SPI_D_DE_MODE_S)) +#define SPI_D_DE_MODE_V 0x7 +#define SPI_D_DE_MODE_S 6 +/* SPI_D_CD_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ +/*description: the output spi_cd is delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_D_CD_MODE 0x00000007 +#define SPI_D_CD_MODE_M ((SPI_D_CD_MODE_V)<<(SPI_D_CD_MODE_S)) +#define SPI_D_CD_MODE_V 0x7 +#define SPI_D_CD_MODE_S 3 +/* SPI_D_DQS_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: the output spi_dqs is delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ +#define SPI_D_DQS_MODE 0x00000007 +#define SPI_D_DQS_MODE_M ((SPI_D_DQS_MODE_V)<<(SPI_D_DQS_MODE_S)) +#define SPI_D_DQS_MODE_V 0x7 +#define SPI_D_DQS_MODE_S 0 + +#define SPI_LCD_D_NUM_REG(i) (REG_SPI_BASE(i) + 0x10C) +/* SPI_D_VSYNC_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the output spi_vsync is delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_D_VSYNC_NUM 0x00000003 +#define SPI_D_VSYNC_NUM_M ((SPI_D_VSYNC_NUM_V)<<(SPI_D_VSYNC_NUM_S)) +#define SPI_D_VSYNC_NUM_V 0x3 +#define SPI_D_VSYNC_NUM_S 8 +/* SPI_D_HSYNC_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the output spi_hsync is delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_D_HSYNC_NUM 0x00000003 +#define SPI_D_HSYNC_NUM_M ((SPI_D_HSYNC_NUM_V)<<(SPI_D_HSYNC_NUM_S)) +#define SPI_D_HSYNC_NUM_V 0x3 +#define SPI_D_HSYNC_NUM_S 6 +/* SPI_D_DE_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the output spi_de is delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_D_DE_NUM 0x00000003 +#define SPI_D_DE_NUM_M ((SPI_D_DE_NUM_V)<<(SPI_D_DE_NUM_S)) +#define SPI_D_DE_NUM_V 0x3 +#define SPI_D_DE_NUM_S 4 +/* SPI_D_CD_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the output spi_cd is delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_D_CD_NUM 0x00000003 +#define SPI_D_CD_NUM_M ((SPI_D_CD_NUM_V)<<(SPI_D_CD_NUM_S)) +#define SPI_D_CD_NUM_V 0x3 +#define SPI_D_CD_NUM_S 2 +/* SPI_D_DQS_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the output spi_dqs is delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_D_DQS_NUM 0x00000003 +#define SPI_D_DQS_NUM_M ((SPI_D_DQS_NUM_V)<<(SPI_D_DQS_NUM_S)) +#define SPI_D_DQS_NUM_V 0x3 +#define SPI_D_DQS_NUM_S 0 #define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC) -/* SPI_DATE : RW ;bitpos:[27:0] ;default: 32'h1810100 ; */ +/* SPI_DATE : RW ;bitpos:[27:0] ;default: 28'h1902200 ; */ /*description: SPI register version.*/ #define SPI_DATE 0x0FFFFFFF #define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/spi_struct.h b/components/soc/esp32s2beta/include/soc/spi_struct.h index 9a87736973..2c55313fb9 100644 --- a/components/soc/esp32s2beta/include/soc/spi_struct.h +++ b/components/soc/esp32s2beta/include/soc/spi_struct.h @@ -20,48 +20,51 @@ extern "C" { typedef volatile struct { union { struct { - uint32_t reserved0: 18; /*reserved*/ - uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - uint32_t reserved19:13; + uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state.*/ + uint32_t reserved23: 1; /*reserved*/ + uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ + uint32_t reserved25: 7; /*reserved*/ }; uint32_t val; } cmd; uint32_t addr; /*[31:8]:address to slave [7:0]:Reserved.*/ union { struct { - uint32_t reserved0: 2; /*reserved*/ - uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/ - uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ - uint32_t reserved4: 1; /*reserved*/ - uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable*/ - uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable*/ - uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ - uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ - uint32_t reserved9: 4; - uint32_t fast_rd_mode: 1; /*Enable 2/4 lines addr command including read and write command.*/ - uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ - uint32_t reserved15: 3; - uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ - uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ - uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ - uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ - uint32_t reserved22: 3; /*reserved*/ - uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ - uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ - uint32_t define_addr: 1; /*set spi_usr_addr and spi_usr_addr_value in spi defined slave mode. 1: disable 0:enable.*/ - uint32_t reserved28: 4; /*reserved*/ + uint32_t reserved0: 2; /*reserved*/ + uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/ + uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ + uint32_t reserved4: 1; /*reserved*/ + uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable*/ + uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable*/ + uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable*/ + uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t reserved11: 3; /*reserved*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t reserved17: 1; /*reserved*/ + uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ + uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ + uint32_t reserved20: 1; /*reserved*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t reserved22: 3; /*reserved*/ + uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ + uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ + uint32_t reserved27: 5; /*reserved*/ }; uint32_t val; } ctrl; union { struct { uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ - uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]*/ + uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/ uint32_t w16_17_wr_ena: 1; /*1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written.*/ uint32_t reserved5: 9; /*reserved*/ uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles.*/ - uint32_t reserved20: 12; + uint32_t reserved20: 12; /*reserved*/ }; uint32_t val; } ctrl1; @@ -69,10 +72,9 @@ typedef volatile struct { struct { uint32_t cs_setup_time:13; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit.*/ uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/ - uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t cs_delay_mode: 3; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ uint32_t cs_delay_num: 2; /*spi_cs signal is delayed by system clock cycles*/ - uint32_t reserved30: 1; /*reserved*/ - uint32_t cs_delay_edge: 1; + uint32_t reserved31: 1; /*reserved*/ }; uint32_t val; } ctrl2; @@ -100,8 +102,8 @@ typedef volatile struct { uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ - uint32_t reserved14: 1; /*reserved*/ - uint32_t reserved15: 1; /*reserved*/ + uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals*/ + uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode.*/ uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/ @@ -124,8 +126,8 @@ typedef volatile struct { union { struct { uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ - uint32_t reserved8: 18; /*reserved*/ - uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t reserved8: 19; /*reserved*/ + uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ }; uint32_t val; } user1; @@ -139,15 +141,15 @@ typedef volatile struct { } user2; union { struct { - uint32_t usr_mosi_bit_len:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ - uint32_t reserved24: 8; /*reserved*/ + uint32_t usr_mosi_bit_len:23; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved23: 9; /*reserved*/ }; uint32_t val; } mosi_dlen; union { struct { - uint32_t usr_miso_bit_len:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ - uint32_t reserved24: 8; /*reserved*/ + uint32_t usr_miso_bit_len:23; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved23: 9; /*reserved*/ }; uint32_t val; } miso_dlen; @@ -157,14 +159,20 @@ typedef volatile struct { uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin*/ uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin*/ uint32_t cs2_dis: 1; /*SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin*/ - uint32_t reserved3: 2; /*reserved*/ + uint32_t cs3_dis: 1; /*reserved*/ + uint32_t cs4_dis: 1; /*SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to CS4 pin*/ + uint32_t cs5_dis: 1; /*SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to CS5 pin*/ uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ - uint32_t master_cs_pol: 3; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ - uint32_t reserved9: 14; /*reserved*/ + uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ + uint32_t reserved13: 7; /*reserved*/ + uint32_t cd_data_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge.*/ + uint32_t cd_dummy_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: spi_cd = spi_cd_idle_edge.*/ + uint32_t cd_addr_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = spi_cd_idle_edge.*/ uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change*/ - uint32_t reserved24: 3; /*reserved*/ - uint32_t q_idle_out: 1; /*The idle output value of spi_q.*/ - uint32_t reserved28: 1; /*reserved*/ + uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs.*/ + uint32_t cd_cmd_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. 0: spi_cd = spi_cd_idle_edge.*/ + uint32_t cd_idle_edge: 1; /*The default value of spi_cd.*/ + uint32_t reserved27: 2; /*reserved*/ uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable*/ @@ -173,41 +181,39 @@ typedef volatile struct { } misc; union { struct { - uint32_t reserved0: 4; /*reserved*/ - uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ - uint32_t int_rd_buf_done_en: 1; /*spi_slv_rd_buf Interrupt enable. 1: enable 0: disable*/ - uint32_t int_wr_buf_done_en: 1; /*spi_slv_wr_buf Interrupt enable. 1: enable 0: disable*/ - uint32_t int_rd_dma_done_en: 1; /*spi_slv_rd_dma Interrupt enable. 1: enable 0: disable*/ - uint32_t int_wr_dma_done_en: 1; /*spi_slv_wr_dma Interrupt enable. 1: enable 0: disable*/ - uint32_t int_trans_done_en: 1; /*spi_trans_done Interrupt enable. 1: enable 0: disable*/ - uint32_t reserved10: 13; /*reserved*/ - uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/ - uint32_t reserved27: 1; /*reserved*/ - uint32_t reserved28: 1; /*reserved*/ - uint32_t reserved29: 1; /*reserved*/ - uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ - uint32_t sync_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines.*/ + uint32_t reserved0: 4; /*reserved*/ + uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/ + uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/ + uint32_t rd_dma_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/ + uint32_t wr_dma_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/ + uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t reserved10:13; /*reserved*/ + uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/ + uint32_t reserved27: 1; /*reserved*/ + uint32_t reserved28: 1; /*reserved*/ + uint32_t reserved29: 1; /*reserved*/ + uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ + uint32_t sync_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines.*/ }; uint32_t val; } slave; union { struct { - uint32_t rd_addr_bytelen: 4; /*In the slave mode it is the address length in bytes for read-buffer operation. The register value shall be byte_num.*/ - uint32_t wr_addr_bytelen: 4; /*In the slave mode it is the address length in bytes for write-buffer operation. The register value shall be byte_num.*/ - uint32_t reserved8: 3; /*reserved*/ - uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode.*/ - uint32_t last_command: 3; /*In the slave mode it is the value of command.*/ - uint32_t last_addr: 7; /*In the slave mode it is the value of address.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t reserved0: 13; /*reserved*/ + uint32_t addr_err: 1; /*1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received.*/ + uint32_t cmd_err: 1; /*1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received.*/ + uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf.*/ + uint32_t last_command: 8; /*In the slave mode it is the value of command.*/ + uint32_t last_addr: 8; /*In the slave mode it is the value of address.*/ }; uint32_t val; } slave1; union { struct { - uint32_t rd_dummy_bytelen: 4; /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for read operations.*/ - uint32_t wr_dummy_bytelen: 4; /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for write operations.*/ - uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of dma read operation in the slave mode.*/ - uint32_t reserved9: 23; /*reserved*/ + uint32_t reserved0: 8; + uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf.*/ + uint32_t reserved9: 23; /*reserved*/ }; uint32_t val; } slave2; @@ -237,45 +243,52 @@ typedef volatile struct { uint32_t reserved_4c; union { struct { - uint32_t st: 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ - uint32_t reserved3: 29; /*reserved*/ + uint32_t st: 4; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ + uint32_t reserved4: 8; /*reserved*/ + uint32_t mst_dma_rd_bytelen:20; /*Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid when spi_rx_eof_en is 0.*/ }; uint32_t val; } fsm; union { struct { - uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/ - uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en.*/ - uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/ - uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/ - uint32_t reserved7: 25; /*reserved*/ + uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase.*/ + uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en.*/ + uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/ + uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/ + uint32_t dma_seg_trans_done: 1; /*1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/ + uint32_t reserved8: 24; /*reserved*/ }; uint32_t val; } hold; union { struct { - uint32_t reserved0: 2; /*reserved*/ - uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ - uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ - uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/ - uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/ - uint32_t in_loop_test: 1; /*Set bit to test in link.*/ - uint32_t out_loop_test: 1; /*Set bit to test out link.*/ - uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/ - uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ - uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ - uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ - uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ - uint32_t mem_trans_en: 1; - uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ - uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ - uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ - uint32_t continue_pop_data_clr: 1; /*Disable spi slave dma to pop data continuously in next transmission in dma half duplex slave mode. 1: disable continue transmit. 0: enable continue transmit.*/ - uint32_t slv_rx_seg_trans_en: 1; /*enable DMA segment transfer in slave mode*/ - uint32_t reserved19: 3; /*reserved*/ - uint32_t infifo_full_clr: 1; - uint32_t outfifo_empty_clr: 1; - uint32_t reserved24: 8; + uint32_t reserved0: 2; /*reserved*/ + uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ + uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ + uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/ + uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/ + uint32_t in_loop_test: 1; /*Set bit to test in link.*/ + uint32_t out_loop_test: 1; /*Set bit to test out link.*/ + uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/ + uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ + uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ + uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ + uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ + uint32_t mem_trans_en: 1; + uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ + uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ + uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ + uint32_t last_seg_pop_clr: 1; /*1: Clear spi_slv_seg_frt_pop_mask. 0 : others*/ + uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ + uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ + uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ + uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ + uint32_t infifo_full_clr: 1; /*1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/ + uint32_t outfifo_empty_clr: 1; /*1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/ + uint32_t infifo_full_err: 1; /*1:spi_dma_infifo_full and spi_push_data_prep are valid which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/ + uint32_t outfifo_empty_err: 1; /*1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/ + uint32_t ext_mem_bk_size: 2; /*Select the external memory block size.*/ + uint32_t reserved28: 4; /*reserved*/ }; uint32_t val; } dma_conf; @@ -397,16 +410,16 @@ typedef volatile struct { uint32_t data_buf[18]; /*data buffer*/ union { struct { - uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ - uint32_t reserved8: 10; - uint32_t din0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t din1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t din2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t din3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify input line timing.*/ - uint32_t reserved22: 10; /*reserved*/ + uint32_t din0_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din1_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din2_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din3_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din4_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din5_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din6_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din7_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t timing_clk_ena: 1; /*1:enable hclk in spi_timing.v. 0: disable it.*/ + uint32_t reserved25: 7; /*reserved*/ }; uint32_t val; } din_mode; @@ -416,24 +429,25 @@ typedef volatile struct { uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved8: 24; /*reserved*/ + uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved16:16; /*reserved*/ }; uint32_t val; } din_num; union { struct { - uint32_t dout0_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout1_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout2_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout3_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout4_mode: 2; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t reserved10: 8; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ - uint32_t dout0_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout1_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout2_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout3_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t dout4_dly_edge: 1; /*The bit is used to select the spi clock edge to modify output line timing.*/ - uint32_t reserved23: 9; /*reserved*/ + uint32_t dout0_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout1_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout2_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout3_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout4_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout5_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout6_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout7_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t reserved24: 8; /*reserved*/ }; uint32_t val; } dout_mode; @@ -444,34 +458,63 @@ typedef volatile struct { uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ - uint32_t reserved10:22; /*reserved*/ + uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved16:16; /*reserved*/ }; uint32_t val; } dout_num; union { struct { - uint32_t sop_en: 1; - uint32_t sop_mode: 4; - uint32_t sop_rcmd: 8; - uint32_t sop_wcmd: 8; - uint32_t sop_dqs_edge: 1; - uint32_t reserved22: 10; + uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame.*/ + uint32_t lcd_va_height: 10; /*It is the vertical active height of a frame.*/ + uint32_t lcd_vt_height: 10; /*It is the vertical total height of a frame.*/ + uint32_t lcd_srgb_mode_en: 1; /*1: Enable LCD mode output vsync hsync de. 0: Disable.*/ }; uint32_t val; - } spr_cfg0; + } lcd_ctrl; union { struct { - uint32_t sop_itl: 12; - uint32_t sop_len: 6; - uint32_t sop_dlen: 6; - uint32_t sop_dc_mode: 1; - uint32_t reserved25: 7; + uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame.*/ + uint32_t lcd_ha_width:12; /*It is the horizontal active width of a frame.*/ + uint32_t lcd_ht_width:12; /*It is the horizontal total width of a frame.*/ }; uint32_t val; - } spr_cfg1; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; + } lcd_ctrl1; + union { + struct { + uint32_t lcd_vsync_width: 7; /*It is the position of spi_vsync_out active pulse in a line.*/ + uint32_t vsync_idle_pol: 1; /*It is the idle value of spi_vsync_out.*/ + uint32_t lcd_vsync_position: 8; /*It is the position of spi_vsync_out active pulse in a line.*/ + uint32_t lcd_hsync_width: 7; /*It is the position of spi_hsync_out active pulse in a line.*/ + uint32_t hsync_idle_pol: 1; /*It is the idle value of spi_hsync_out.*/ + uint32_t lcd_hsync_position: 8; /*It is the position of spi_hsync_out active pulse in a line.*/ + }; + uint32_t val; + } lcd_ctrl2; + union { + struct { + uint32_t d_dqs_mode: 3; /*the output spi_dqs is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t d_cd_mode: 3; /*the output spi_cd is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t d_de_mode: 3; /*the output spi_de is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t d_hsync_mode: 3; /*the output spi_hsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t d_vsync_mode: 3; /*the output spi_vsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t reserved15: 17; /*reserved*/ + }; + uint32_t val; + } lcd_d_mode; + union { + struct { + uint32_t d_dqs_num: 2; /*the output spi_dqs is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t d_cd_num: 2; /*the output spi_cd is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t d_de_num: 2; /*the output spi_de is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t d_hsync_num: 2; /*the output spi_hsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t d_vsync_num: 2; /*the output spi_vsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } lcd_d_num; uint32_t reserved_110; uint32_t reserved_114; uint32_t reserved_118; @@ -669,7 +712,6 @@ typedef volatile struct { } spi_dev_t; extern spi_dev_t GPSPI2; //FSPI extern spi_dev_t GPSPI3; //HSPI -extern spi_dev_t GPSPI4; //VSPI _Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi"); diff --git a/components/soc/esp32s2beta/include/soc/syscon_reg.h b/components/soc/esp32s2beta/include/soc/syscon_reg.h index efa9a0ba78..9a9d92a0b8 100644 --- a/components/soc/esp32s2beta/include/soc/syscon_reg.h +++ b/components/soc/esp32s2beta/include/soc/syscon_reg.h @@ -20,16 +20,6 @@ extern "C" { #endif #include "soc.h" #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) -/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ -/*description: */ -#define SYSCON_SOC_CLK_SEL 0x00000003 -#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V)<<(SYSCON_SOC_CLK_SEL_S)) -#define SYSCON_SOC_CLK_SEL_V 0x3 -#define SYSCON_SOC_CLK_SEL_S 14 -#define SYSCON_SOC_CLK_SEL_XTL 0 -#define SYSCON_SOC_CLK_SEL_PLL 1 -#define SYSCON_SOC_CLK_SEL_8M 2 -#define SYSCON_SOC_CLK_SEL_APLL 3 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: */ #define SYSCON_RST_TICK_CNT (BIT(12)) @@ -48,12 +38,6 @@ extern "C" { #define SYSCON_CLK_320M_EN_M (BIT(10)) #define SYSCON_CLK_320M_EN_V 0x1 #define SYSCON_CLK_320M_EN_S 10 -/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: */ -#define SYSCON_PRE_DIV_CNT 0x000003FF -#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) -#define SYSCON_PRE_DIV_CNT_V 0x3FF -#define SYSCON_PRE_DIV_CNT_S 0 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ @@ -75,297 +59,7 @@ extern "C" { #define SYSCON_XTAL_TICK_NUM_V 0xFF #define SYSCON_XTAL_TICK_NUM_S 0 -#define SYSCON_SARADC_CTRL_REG (DR_REG_SYSCON_BASE + 0x008) -/* SYSCON_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ -/*description: force option to xpd sar blocks*/ -#define SYSCON_SARADC_XPD_SAR_FORCE 0x00000003 -#define SYSCON_SARADC_XPD_SAR_FORCE_M ((SYSCON_SARADC_XPD_SAR_FORCE_V)<<(SYSCON_SARADC_XPD_SAR_FORCE_S)) -#define SYSCON_SARADC_XPD_SAR_FORCE_V 0x3 -#define SYSCON_SARADC_XPD_SAR_FORCE_S 27 -/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data - is from GPIO matrix*/ -#define SYSCON_SARADC_DATA_TO_I2S (BIT(26)) -#define SYSCON_SARADC_DATA_TO_I2S_M (BIT(26)) -#define SYSCON_SARADC_DATA_TO_I2S_V 0x1 -#define SYSCON_SARADC_DATA_TO_I2S_S 26 -/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data - in this case the resolution should not be larger than 11 bits.*/ -#define SYSCON_SARADC_DATA_SAR_SEL (BIT(25)) -#define SYSCON_SARADC_DATA_SAR_SEL_M (BIT(25)) -#define SYSCON_SARADC_DATA_SAR_SEL_V 0x1 -#define SYSCON_SARADC_DATA_SAR_SEL_S 25 -/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ -#define SYSCON_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) -#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) -#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V 0x1 -#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S 24 -/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ -#define SYSCON_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) -#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) -#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V 0x1 -#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S 23 -/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define SYSCON_SARADC_SAR2_PATT_LEN 0x0000000F -#define SYSCON_SARADC_SAR2_PATT_LEN_M ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S)) -#define SYSCON_SARADC_SAR2_PATT_LEN_V 0xF -#define SYSCON_SARADC_SAR2_PATT_LEN_S 19 -/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ -/*description: 0 ~ 15 means length 1 ~ 16*/ -#define SYSCON_SARADC_SAR1_PATT_LEN 0x0000000F -#define SYSCON_SARADC_SAR1_PATT_LEN_M ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S)) -#define SYSCON_SARADC_SAR1_PATT_LEN_V 0xF -#define SYSCON_SARADC_SAR1_PATT_LEN_S 15 -/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ -/*description: SAR clock divider*/ -#define SYSCON_SARADC_SAR_CLK_DIV 0x000000FF -#define SYSCON_SARADC_SAR_CLK_DIV_M ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S)) -#define SYSCON_SARADC_SAR_CLK_DIV_V 0xFF -#define SYSCON_SARADC_SAR_CLK_DIV_S 7 -/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SYSCON_SARADC_SAR_CLK_GATED (BIT(6)) -#define SYSCON_SARADC_SAR_CLK_GATED_M (BIT(6)) -#define SYSCON_SARADC_SAR_CLK_GATED_V 0x1 -#define SYSCON_SARADC_SAR_CLK_GATED_S 6 -/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ -#define SYSCON_SARADC_SAR_SEL (BIT(5)) -#define SYSCON_SARADC_SAR_SEL_M (BIT(5)) -#define SYSCON_SARADC_SAR_SEL_V 0x1 -#define SYSCON_SARADC_SAR_SEL_S 5 -/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ -/*description: 0: single mode 1: double mode 2: alternate mode*/ -#define SYSCON_SARADC_WORK_MODE 0x00000003 -#define SYSCON_SARADC_WORK_MODE_M ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S)) -#define SYSCON_SARADC_WORK_MODE_V 0x3 -#define SYSCON_SARADC_WORK_MODE_S 3 -/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_SARADC_START (BIT(1)) -#define SYSCON_SARADC_START_M (BIT(1)) -#define SYSCON_SARADC_START_V 0x1 -#define SYSCON_SARADC_START_S 1 -/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_SARADC_START_FORCE (BIT(0)) -#define SYSCON_SARADC_START_FORCE_M (BIT(0)) -#define SYSCON_SARADC_START_FORCE_V 0x1 -#define SYSCON_SARADC_START_FORCE_S 0 - -#define SYSCON_SARADC_CTRL2_REG (DR_REG_SYSCON_BASE + 0x00C) -/* SYSCON_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: to enable saradc timer trigger*/ -#define SYSCON_SARADC_TIMER_EN (BIT(20)) -#define SYSCON_SARADC_TIMER_EN_M (BIT(20)) -#define SYSCON_SARADC_TIMER_EN_V 0x1 -#define SYSCON_SARADC_TIMER_EN_S 20 -/* SYSCON_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */ -/*description: to set saradc timer target*/ -#define SYSCON_SARADC_TIMER_TARGET 0x000000FF -#define SYSCON_SARADC_TIMER_TARGET_M ((SYSCON_SARADC_TIMER_TARGET_V)<<(SYSCON_SARADC_TIMER_TARGET_S)) -#define SYSCON_SARADC_TIMER_TARGET_V 0xFF -#define SYSCON_SARADC_TIMER_TARGET_S 12 -/* SYSCON_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: 1: select saradc timer 0: i2s_ws trigger*/ -#define SYSCON_SARADC_TIMER_SEL (BIT(11)) -#define SYSCON_SARADC_TIMER_SEL_M (BIT(11)) -#define SYSCON_SARADC_TIMER_SEL_V 0x1 -#define SYSCON_SARADC_TIMER_SEL_S 11 -/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ -#define SYSCON_SARADC_SAR2_INV (BIT(10)) -#define SYSCON_SARADC_SAR2_INV_M (BIT(10)) -#define SYSCON_SARADC_SAR2_INV_V 0x1 -#define SYSCON_SARADC_SAR2_INV_S 10 -/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ -#define SYSCON_SARADC_SAR1_INV (BIT(9)) -#define SYSCON_SARADC_SAR1_INV_M (BIT(9)) -#define SYSCON_SARADC_SAR1_INV_V 0x1 -#define SYSCON_SARADC_SAR1_INV_S 9 -/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ -/*description: max conversion number*/ -#define SYSCON_SARADC_MAX_MEAS_NUM 0x000000FF -#define SYSCON_SARADC_MAX_MEAS_NUM_M ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S)) -#define SYSCON_SARADC_MAX_MEAS_NUM_V 0xFF -#define SYSCON_SARADC_MAX_MEAS_NUM_S 1 -/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: */ -#define SYSCON_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define SYSCON_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) -#define SYSCON_SARADC_MEAS_NUM_LIMIT_V 0x1 -#define SYSCON_SARADC_MEAS_NUM_LIMIT_S 0 - -#define SYSCON_SARADC_FSM_REG (DR_REG_SYSCON_BASE + 0x010) -/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */ -/*description: sample cycles*/ -#define SYSCON_SARADC_SAMPLE_CYCLE 0x000000FF -#define SYSCON_SARADC_SAMPLE_CYCLE_M ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S)) -#define SYSCON_SARADC_SAMPLE_CYCLE_V 0xFF -#define SYSCON_SARADC_SAMPLE_CYCLE_S 24 -/* SYSCON_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */ -/*description: sample number*/ -#define SYSCON_SARADC_SAMPLE_NUM 0x000000FF -#define SYSCON_SARADC_SAMPLE_NUM_M ((SYSCON_SARADC_SAMPLE_NUM_V)<<(SYSCON_SARADC_SAMPLE_NUM_S)) -#define SYSCON_SARADC_SAMPLE_NUM_V 0xFF -#define SYSCON_SARADC_SAMPLE_NUM_S 16 - -#define SYSCON_SARADC_FSM_WAIT_REG (DR_REG_SYSCON_BASE + 0x014) -/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ -/*description: */ -#define SYSCON_SARADC_STANDBY_WAIT 0x000000FF -#define SYSCON_SARADC_STANDBY_WAIT_M ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S)) -#define SYSCON_SARADC_STANDBY_WAIT_V 0xFF -#define SYSCON_SARADC_STANDBY_WAIT_S 16 -/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ -/*description: */ -#define SYSCON_SARADC_RSTB_WAIT 0x000000FF -#define SYSCON_SARADC_RSTB_WAIT_M ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S)) -#define SYSCON_SARADC_RSTB_WAIT_V 0xFF -#define SYSCON_SARADC_RSTB_WAIT_S 8 -/* SYSCON_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ -/*description: */ -#define SYSCON_SARADC_XPD_WAIT 0x000000FF -#define SYSCON_SARADC_XPD_WAIT_M ((SYSCON_SARADC_XPD_WAIT_V)<<(SYSCON_SARADC_XPD_WAIT_S)) -#define SYSCON_SARADC_XPD_WAIT_V 0xFF -#define SYSCON_SARADC_XPD_WAIT_S 0 - -#define SYSCON_SARADC_SAR1_STATUS_REG (DR_REG_SYSCON_BASE + 0x018) -/* SYSCON_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_SARADC_SAR1_STATUS 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_STATUS_M ((SYSCON_SARADC_SAR1_STATUS_V)<<(SYSCON_SARADC_SAR1_STATUS_S)) -#define SYSCON_SARADC_SAR1_STATUS_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_STATUS_S 0 - -#define SYSCON_SARADC_SAR2_STATUS_REG (DR_REG_SYSCON_BASE + 0x01C) -/* SYSCON_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: */ -#define SYSCON_SARADC_SAR2_STATUS 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_STATUS_M ((SYSCON_SARADC_SAR2_STATUS_V)<<(SYSCON_SARADC_SAR2_STATUS_S)) -#define SYSCON_SARADC_SAR2_STATUS_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_STATUS_S 0 - -#define SYSCON_SARADC_SAR1_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x020) -/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ -#define SYSCON_SARADC_SAR1_PATT_TAB1 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB1_M ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S)) -#define SYSCON_SARADC_SAR1_PATT_TAB1_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB1_S 0 - -#define SYSCON_SARADC_SAR1_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x024) -/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ -#define SYSCON_SARADC_SAR1_PATT_TAB2 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB2_M ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S)) -#define SYSCON_SARADC_SAR1_PATT_TAB2_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB2_S 0 - -#define SYSCON_SARADC_SAR1_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x028) -/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ -#define SYSCON_SARADC_SAR1_PATT_TAB3 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB3_M ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S)) -#define SYSCON_SARADC_SAR1_PATT_TAB3_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB3_S 0 - -#define SYSCON_SARADC_SAR1_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x02C) -/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ -#define SYSCON_SARADC_SAR1_PATT_TAB4 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB4_M ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S)) -#define SYSCON_SARADC_SAR1_PATT_TAB4_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR1_PATT_TAB4_S 0 - -#define SYSCON_SARADC_SAR2_PATT_TAB1_REG (DR_REG_SYSCON_BASE + 0x030) -/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ -#define SYSCON_SARADC_SAR2_PATT_TAB1 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB1_M ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S)) -#define SYSCON_SARADC_SAR2_PATT_TAB1_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB1_S 0 - -#define SYSCON_SARADC_SAR2_PATT_TAB2_REG (DR_REG_SYSCON_BASE + 0x034) -/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ -#define SYSCON_SARADC_SAR2_PATT_TAB2 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB2_M ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S)) -#define SYSCON_SARADC_SAR2_PATT_TAB2_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB2_S 0 - -#define SYSCON_SARADC_SAR2_PATT_TAB3_REG (DR_REG_SYSCON_BASE + 0x038) -/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ -#define SYSCON_SARADC_SAR2_PATT_TAB3 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB3_M ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S)) -#define SYSCON_SARADC_SAR2_PATT_TAB3_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB3_S 0 - -#define SYSCON_SARADC_SAR2_PATT_TAB4_REG (DR_REG_SYSCON_BASE + 0x03C) -/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */ -/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ -#define SYSCON_SARADC_SAR2_PATT_TAB4 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB4_M ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S)) -#define SYSCON_SARADC_SAR2_PATT_TAB4_V 0xFFFFFFFF -#define SYSCON_SARADC_SAR2_PATT_TAB4_S 0 - -#define SYSCON_ADC_ARB_CTRL_REG (DR_REG_SYSCON_BASE + 0x040) -/* SYSCON_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: adc2 arbiter uses fixed priority*/ -#define SYSCON_ADC_ARB_FIX_PRIORITY (BIT(12)) -#define SYSCON_ADC_ARB_FIX_PRIORITY_M (BIT(12)) -#define SYSCON_ADC_ARB_FIX_PRIORITY_V 0x1 -#define SYSCON_ADC_ARB_FIX_PRIORITY_S 12 -/* SYSCON_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ -/*description: Set adc2 arbiter wifi priority*/ -#define SYSCON_ADC_ARB_WIFI_PRIORITY 0x00000003 -#define SYSCON_ADC_ARB_WIFI_PRIORITY_M ((SYSCON_ADC_ARB_WIFI_PRIORITY_V)<<(SYSCON_ADC_ARB_WIFI_PRIORITY_S)) -#define SYSCON_ADC_ARB_WIFI_PRIORITY_V 0x3 -#define SYSCON_ADC_ARB_WIFI_PRIORITY_S 10 -/* SYSCON_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ -/*description: Set adc2 arbiter rtc priority*/ -#define SYSCON_ADC_ARB_RTC_PRIORITY 0x00000003 -#define SYSCON_ADC_ARB_RTC_PRIORITY_M ((SYSCON_ADC_ARB_RTC_PRIORITY_V)<<(SYSCON_ADC_ARB_RTC_PRIORITY_S)) -#define SYSCON_ADC_ARB_RTC_PRIORITY_V 0x3 -#define SYSCON_ADC_ARB_RTC_PRIORITY_S 8 -/* SYSCON_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ -/*description: Set adc2 arbiter apb priority*/ -#define SYSCON_ADC_ARB_APB_PRIORITY 0x00000003 -#define SYSCON_ADC_ARB_APB_PRIORITY_M ((SYSCON_ADC_ARB_APB_PRIORITY_V)<<(SYSCON_ADC_ARB_APB_PRIORITY_S)) -#define SYSCON_ADC_ARB_APB_PRIORITY_V 0x3 -#define SYSCON_ADC_ARB_APB_PRIORITY_S 6 -/* SYSCON_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: adc2 arbiter force grant*/ -#define SYSCON_ADC_ARB_GRANT_FORCE (BIT(5)) -#define SYSCON_ADC_ARB_GRANT_FORCE_M (BIT(5)) -#define SYSCON_ADC_ARB_GRANT_FORCE_V 0x1 -#define SYSCON_ADC_ARB_GRANT_FORCE_S 5 -/* SYSCON_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable wifi controller*/ -#define SYSCON_ADC_ARB_WIFI_FORCE (BIT(4)) -#define SYSCON_ADC_ARB_WIFI_FORCE_M (BIT(4)) -#define SYSCON_ADC_ARB_WIFI_FORCE_V 0x1 -#define SYSCON_ADC_ARB_WIFI_FORCE_S 4 -/* SYSCON_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enable rtc controller*/ -#define SYSCON_ADC_ARB_RTC_FORCE (BIT(3)) -#define SYSCON_ADC_ARB_RTC_FORCE_M (BIT(3)) -#define SYSCON_ADC_ARB_RTC_FORCE_V 0x1 -#define SYSCON_ADC_ARB_RTC_FORCE_S 3 -/* SYSCON_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: adc2 arbiter force to enableapb controller*/ -#define SYSCON_ADC_ARB_APB_FORCE (BIT(2)) -#define SYSCON_ADC_ARB_APB_FORCE_M (BIT(2)) -#define SYSCON_ADC_ARB_APB_FORCE_V 0x1 -#define SYSCON_ADC_ARB_APB_FORCE_S 2 - -#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x044) +#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ /*description: */ #define SYSCON_CLK_XTAL_OEN (BIT(10)) @@ -433,25 +127,7 @@ extern "C" { #define SYSCON_CLK20_OEN_V 0x1 #define SYSCON_CLK20_OEN_S 0 -#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x048) -/* SYSCON_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI_PRIOR (BIT(13)) -#define SYSCON_SPI_PRIOR_M (BIT(13)) -#define SYSCON_SPI_PRIOR_V 0x1 -#define SYSCON_SPI_PRIOR_S 13 -/* SYSCON_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI1_HOLD (BIT(9)) -#define SYSCON_SPI1_HOLD_M (BIT(9)) -#define SYSCON_SPI1_HOLD_V 0x1 -#define SYSCON_SPI1_HOLD_S 9 -/* SYSCON_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI0_HOLD (BIT(8)) -#define SYSCON_SPI0_HOLD_M (BIT(8)) -#define SYSCON_SPI0_HOLD_V 0x1 -#define SYSCON_SPI0_HOLD_S 8 +#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x00C) /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /*description: */ #define SYSCON_PERI_IO_SWAP 0x000000FF @@ -459,7 +135,7 @@ extern "C" { #define SYSCON_PERI_IO_SWAP_V 0xFF #define SYSCON_PERI_IO_SWAP_S 0 -#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x04C) +#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x010) /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ #define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) @@ -467,7 +143,7 @@ extern "C" { #define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 #define SYSCON_EXT_MEM_PMS_LOCK_S 0 -#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x050) +#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x014) /* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_FLASH_ACE0_ATTR 0x00000007 @@ -475,7 +151,7 @@ extern "C" { #define SYSCON_FLASH_ACE0_ATTR_V 0x7 #define SYSCON_FLASH_ACE0_ATTR_S 0 -#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x054) +#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x018) /* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_FLASH_ACE1_ATTR 0x00000007 @@ -483,7 +159,7 @@ extern "C" { #define SYSCON_FLASH_ACE1_ATTR_V 0x7 #define SYSCON_FLASH_ACE1_ATTR_S 0 -#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x058) +#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x01C) /* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_FLASH_ACE2_ATTR 0x00000007 @@ -491,7 +167,7 @@ extern "C" { #define SYSCON_FLASH_ACE2_ATTR_V 0x7 #define SYSCON_FLASH_ACE2_ATTR_S 0 -#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C) +#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x020) /* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_FLASH_ACE3_ATTR 0x00000007 @@ -499,7 +175,7 @@ extern "C" { #define SYSCON_FLASH_ACE3_ATTR_V 0x7 #define SYSCON_FLASH_ACE3_ATTR_S 0 -#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x060) +#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x024) /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF @@ -507,7 +183,7 @@ extern "C" { #define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF #define SYSCON_FLASH_ACE0_ADDR_S_S 0 -#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x064) +#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x028) /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ /*description: */ #define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF @@ -515,7 +191,7 @@ extern "C" { #define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF #define SYSCON_FLASH_ACE1_ADDR_S_S 0 -#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x068) +#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x02C) /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ /*description: */ #define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF @@ -523,7 +199,7 @@ extern "C" { #define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF #define SYSCON_FLASH_ACE2_ADDR_S_S 0 -#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C) +#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x030) /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ /*description: */ #define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF @@ -531,7 +207,7 @@ extern "C" { #define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF #define SYSCON_FLASH_ACE3_ADDR_S_S 0 -#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x070) +#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x034) /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF @@ -539,7 +215,7 @@ extern "C" { #define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF #define SYSCON_FLASH_ACE0_SIZE_S 0 -#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x074) +#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x038) /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF @@ -547,7 +223,7 @@ extern "C" { #define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF #define SYSCON_FLASH_ACE1_SIZE_S 0 -#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x078) +#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x03C) /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF @@ -555,7 +231,7 @@ extern "C" { #define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF #define SYSCON_FLASH_ACE2_SIZE_S 0 -#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C) +#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x040) /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF @@ -563,7 +239,7 @@ extern "C" { #define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF #define SYSCON_FLASH_ACE3_SIZE_S 0 -#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x080) +#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x044) /* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_SRAM_ACE0_ATTR 0x00000007 @@ -571,7 +247,7 @@ extern "C" { #define SYSCON_SRAM_ACE0_ATTR_V 0x7 #define SYSCON_SRAM_ACE0_ATTR_S 0 -#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x084) +#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x048) /* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_SRAM_ACE1_ATTR 0x00000007 @@ -579,7 +255,7 @@ extern "C" { #define SYSCON_SRAM_ACE1_ATTR_V 0x7 #define SYSCON_SRAM_ACE1_ATTR_S 0 -#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x088) +#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x04C) /* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_SRAM_ACE2_ATTR 0x00000007 @@ -587,7 +263,7 @@ extern "C" { #define SYSCON_SRAM_ACE2_ATTR_V 0x7 #define SYSCON_SRAM_ACE2_ATTR_S 0 -#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x08C) +#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x050) /* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ /*description: */ #define SYSCON_SRAM_ACE3_ATTR 0x00000007 @@ -595,7 +271,7 @@ extern "C" { #define SYSCON_SRAM_ACE3_ATTR_V 0x7 #define SYSCON_SRAM_ACE3_ATTR_S 0 -#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x090) +#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x054) /* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF @@ -603,7 +279,7 @@ extern "C" { #define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF #define SYSCON_SRAM_ACE0_ADDR_S_S 0 -#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x094) +#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x058) /* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ /*description: */ #define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF @@ -611,7 +287,7 @@ extern "C" { #define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF #define SYSCON_SRAM_ACE1_ADDR_S_S 0 -#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x098) +#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x05C) /* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ /*description: */ #define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF @@ -619,7 +295,7 @@ extern "C" { #define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF #define SYSCON_SRAM_ACE2_ADDR_S_S 0 -#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x09C) +#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x060) /* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ /*description: */ #define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF @@ -627,7 +303,7 @@ extern "C" { #define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF #define SYSCON_SRAM_ACE3_ADDR_S_S 0 -#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A0) +#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x064) /* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF @@ -635,7 +311,7 @@ extern "C" { #define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF #define SYSCON_SRAM_ACE0_SIZE_S 0 -#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A4) +#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x068) /* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF @@ -643,7 +319,7 @@ extern "C" { #define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF #define SYSCON_SRAM_ACE1_SIZE_S 0 -#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x0A8) +#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x06C) /* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF @@ -651,7 +327,7 @@ extern "C" { #define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF #define SYSCON_SRAM_ACE2_SIZE_S 0 -#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x0AC) +#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x070) /* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ /*description: */ #define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF @@ -659,63 +335,35 @@ extern "C" { #define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF #define SYSCON_SRAM_ACE3_SIZE_S 0 -#define SYSCON_SPI0_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B0) -/* SYSCON_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ +#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x074) +/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ /*description: */ -#define SYSCON_SPI0_REJECT_CDE 0x0000001F -#define SYSCON_SPI0_REJECT_CDE_M ((SYSCON_SPI0_REJECT_CDE_V)<<(SYSCON_SPI0_REJECT_CDE_S)) -#define SYSCON_SPI0_REJECT_CDE_V 0x1F -#define SYSCON_SPI0_REJECT_CDE_S 2 -/* SYSCON_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F +#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) +#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F +#define SYSCON_SPI_MEM_REJECT_CDE_S 2 +/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_SPI0_REJECT_CLR (BIT(1)) -#define SYSCON_SPI0_REJECT_CLR_M (BIT(1)) -#define SYSCON_SPI0_REJECT_CLR_V 0x1 -#define SYSCON_SPI0_REJECT_CLR_S 1 -/* SYSCON_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ +#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 +#define SYSCON_SPI_MEM_REJECT_CLR_S 1 +/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ /*description: */ -#define SYSCON_SPI0_REJECT_INT (BIT(0)) -#define SYSCON_SPI0_REJECT_INT_M (BIT(0)) -#define SYSCON_SPI0_REJECT_INT_V 0x1 -#define SYSCON_SPI0_REJECT_INT_S 0 +#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 +#define SYSCON_SPI_MEM_REJECT_INT_S 0 -#define SYSCON_SPI0_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B4) -/* SYSCON_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x078) +/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ -#define SYSCON_SPI0_REJECT_ADDR 0xFFFFFFFF -#define SYSCON_SPI0_REJECT_ADDR_M ((SYSCON_SPI0_REJECT_ADDR_V)<<(SYSCON_SPI0_REJECT_ADDR_S)) -#define SYSCON_SPI0_REJECT_ADDR_V 0xFFFFFFFF -#define SYSCON_SPI0_REJECT_ADDR_S 0 +#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) +#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 -#define SYSCON_SPI1_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B8) -/* SYSCON_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ -/*description: */ -#define SYSCON_SPI1_REJECT_CDE 0x0000001F -#define SYSCON_SPI1_REJECT_CDE_M ((SYSCON_SPI1_REJECT_CDE_V)<<(SYSCON_SPI1_REJECT_CDE_S)) -#define SYSCON_SPI1_REJECT_CDE_V 0x1F -#define SYSCON_SPI1_REJECT_CDE_S 2 -/* SYSCON_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI1_REJECT_CLR (BIT(1)) -#define SYSCON_SPI1_REJECT_CLR_M (BIT(1)) -#define SYSCON_SPI1_REJECT_CLR_V 0x1 -#define SYSCON_SPI1_REJECT_CLR_S 1 -/* SYSCON_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SYSCON_SPI1_REJECT_INT (BIT(0)) -#define SYSCON_SPI1_REJECT_INT_M (BIT(0)) -#define SYSCON_SPI1_REJECT_INT_V 0x1 -#define SYSCON_SPI1_REJECT_INT_S 0 - -#define SYSCON_SPI1_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC) -/* SYSCON_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SYSCON_SPI1_REJECT_ADDR 0xFFFFFFFF -#define SYSCON_SPI1_REJECT_ADDR_M ((SYSCON_SPI1_REJECT_ADDR_V)<<(SYSCON_SPI1_REJECT_ADDR_S)) -#define SYSCON_SPI1_REJECT_ADDR_V 0xFFFFFFFF -#define SYSCON_SPI1_REJECT_ADDR_S 0 - -#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x0C0) +#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x07C) /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ /*description: */ #define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) @@ -723,7 +371,7 @@ extern "C" { #define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 #define SYSCON_SDIO_WIN_ACCESS_EN_S 0 -#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x0C4) +#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x080) /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ #define SYSCON_REDCY_ANDOR (BIT(31)) @@ -737,7 +385,7 @@ extern "C" { #define SYSCON_REDCY_SIG0_V 0x7FFFFFFF #define SYSCON_REDCY_SIG0_S 0 -#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x0C8) +#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x084) /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ /*description: */ #define SYSCON_REDCY_NANDOR (BIT(31)) @@ -751,7 +399,7 @@ extern "C" { #define SYSCON_REDCY_SIG1_V 0x7FFFFFFF #define SYSCON_REDCY_SIG1_S 0 -#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x0CC) +#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x088) /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SYSCON_WIFI_BB_CFG 0xFFFFFFFF @@ -759,7 +407,7 @@ extern "C" { #define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF #define SYSCON_WIFI_BB_CFG_S 0 -#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x0D0) +#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x08C) /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF @@ -767,7 +415,7 @@ extern "C" { #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF #define SYSCON_WIFI_BB_CFG_2_S 0 -#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x0D4) +#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x090) /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ /*description: */ #define SYSCON_WIFI_CLK_EN 0xFFFFFFFF @@ -775,7 +423,7 @@ extern "C" { #define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF #define SYSCON_WIFI_CLK_EN_S 0 -#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x0D8) +#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x094) /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /*description: */ #define SYSCON_WIFI_RST 0xFFFFFFFF @@ -793,9 +441,9 @@ extern "C" { /* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 Bit15 not included here because of the bit now can't be cleared */ -#define DPORT_WIFI_CLK_WIFI_EN 0x00008040 +#define DPORT_WIFI_CLK_WIFI_EN 0x003807cf #define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S)) -#define DPORT_WIFI_CLK_WIFI_EN_V 0x0804 +#define DPORT_WIFI_CLK_WIFI_EN_V 0x7cf #define DPORT_WIFI_CLK_WIFI_EN_S 0 /* Mask for all Bluetooth clock bits - 11, 16, 17 */ #define DPORT_WIFI_CLK_BT_EN 0x61 @@ -803,7 +451,7 @@ extern "C" { #define DPORT_WIFI_CLK_BT_EN_V 0x61 #define DPORT_WIFI_CLK_BT_EN_S 11 /* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ -#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x0038078f +#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 /* Digital team to check */ //bluetooth baseband bit11 @@ -839,7 +487,7 @@ extern "C" { #define DPORT_FE_RST (BIT(1)) #define DPORT_BB_RST (BIT(0)) -#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x0DC) +#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098) /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ /*description: */ #define SYSCON_DC_MEM_FORCE_PD (BIT(5)) @@ -878,7 +526,7 @@ extern "C" { #define SYSCON_AGC_MEM_FORCE_PU_S 0 #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) -/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */ +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907010 ; */ /*description: */ #define SYSCON_DATE 0xFFFFFFFF #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/syscon_struct.h b/components/soc/esp32s2beta/include/soc/syscon_struct.h index 8278a82008..d40e2dff50 100644 --- a/components/soc/esp32s2beta/include/soc/syscon_struct.h +++ b/components/soc/esp32s2beta/include/soc/syscon_struct.h @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -13,7 +13,6 @@ // limitations under the License. #ifndef _SOC_SYSCON_STRUCT_H_ #define _SOC_SYSCON_STRUCT_H_ - #ifdef __cplusplus extern "C" { #endif @@ -30,7 +29,7 @@ typedef volatile struct { uint32_t reserved16: 16; }; uint32_t val; - } clk_conf; + } apb_ctrl_sysclk_conf; union { struct { uint32_t xtal_tick: 8; @@ -39,76 +38,7 @@ typedef volatile struct { uint32_t reserved17: 15; }; uint32_t val; - } tick_conf; - union { - struct { - uint32_t start_force: 1; - uint32_t start: 1; - uint32_t reserved2: 1; - uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ - uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ - uint32_t sar_clk_gated: 1; - uint32_t sar_clk_div: 8; /*SAR clock divider*/ - uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ - uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ - uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ - uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ - uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ - uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ - uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ - uint32_t reserved29: 3; - }; - uint32_t val; - } saradc_ctrl; - union { - struct { - uint32_t meas_num_limit: 1; - uint32_t max_meas_num: 8; /*max conversion number*/ - uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ - uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ - uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/ - uint32_t timer_target: 8; /*to set saradc timer target*/ - uint32_t timer_en: 1; /*to enable saradc timer trigger*/ - uint32_t reserved21: 11; - }; - uint32_t val; - } saradc_ctrl2; - union { - struct { - uint32_t reserved0: 16; - uint32_t sample_num: 8; /*sample number*/ - uint32_t sample_cycle: 8; /*sample cycles*/ - }; - uint32_t val; - } saradc_fsm; - union { - struct { - uint32_t xpd_wait: 8; - uint32_t rstb_wait: 8; - uint32_t standby_wait: 8; - uint32_t reserved24: 8; - }; - uint32_t val; - } saradc_fsm_wait; - uint32_t saradc_sar1_status; /**/ - uint32_t saradc_sar2_status; /**/ - uint32_t saradc_sar1_patt_tab[4]; /*item 0 ~ 15 for pattern table 1 (each item one byte)*/ - uint32_t saradc_sar2_patt_tab[4]; /*item 0 ~ 15 for pattern table 2 (each item one byte)*/ - union { - struct { - uint32_t reserved0: 2; - uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ - uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ - uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ - uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ - uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ - uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ - uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ - uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ - uint32_t reserved13: 19; - }; - uint32_t val; - } adc_arb_ctrl; + } apb_ctrl_tick_conf; union { struct { uint32_t clk20_oen: 1; @@ -125,15 +55,11 @@ typedef volatile struct { uint32_t reserved11: 21; }; uint32_t val; - } clk_out_en; + } apb_ctrl_clk_out_en; union { struct { uint32_t peri_io_swap: 8; - uint32_t spi0_hold: 1; - uint32_t spi1_hold: 1; - uint32_t reserved10: 3; - uint32_t spi_prior: 1; - uint32_t reserved14: 18; + uint32_t reserved8: 24; }; uint32_t val; } host_inf_sel; @@ -172,10 +98,10 @@ typedef volatile struct { }; uint32_t val; } flash_ace3_attr; - uint32_t flash_ace0_addr; /**/ - uint32_t flash_ace1_addr; /**/ - uint32_t flash_ace2_addr; /**/ - uint32_t flash_ace3_addr; /**/ + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ union { struct { uint32_t flash_ace0_size:16; @@ -232,10 +158,10 @@ typedef volatile struct { }; uint32_t val; } sram_ace3_attr; - uint32_t sram_ace0_addr; /**/ - uint32_t sram_ace1_addr; /**/ - uint32_t sram_ace2_addr; /**/ - uint32_t sram_ace3_addr; /**/ + uint32_t sram_ace0_addr; /**/ + uint32_t sram_ace1_addr; /**/ + uint32_t sram_ace2_addr; /**/ + uint32_t sram_ace3_addr; /**/ union { struct { uint32_t sram_ace0_size:16; @@ -266,24 +192,14 @@ typedef volatile struct { } sram_ace3_size; union { struct { - uint32_t spi0_reject_int: 1; - uint32_t spi0_reject_clr: 1; - uint32_t spi0_reject_cde: 5; - uint32_t reserved7: 25; + uint32_t spi_mem_reject_int: 1; + uint32_t spi_mem_reject_clr: 1; + uint32_t spi_mem_reject_cde: 5; + uint32_t reserved7: 25; }; uint32_t val; - } spi0_pms_ctrl; - uint32_t spi0_reject_addr; /**/ - union { - struct { - uint32_t spi1_reject_int: 1; - uint32_t spi1_reject_clr: 1; - uint32_t spi1_reject_cde: 5; - uint32_t reserved7: 25; - }; - uint32_t val; - } spi1_pms_ctrl; - uint32_t spi1_reject_addr; /**/ + } spi_mem_pms_ctrl; + uint32_t spi_mem_reject_addr; /**/ union { struct { uint32_t sdio_win_access_en: 1; @@ -305,10 +221,10 @@ typedef volatile struct { }; uint32_t val; } redcy_sig1; - uint32_t wifi_bb_cfg; /**/ - uint32_t wifi_bb_cfg_2; /**/ - uint32_t wifi_clk_en; /**/ - uint32_t wifi_rst_en; /**/ + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ union { struct { uint32_t agc_mem_force_pu: 1; @@ -321,6 +237,23 @@ typedef volatile struct { }; uint32_t val; } front_end_mem_pd; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; uint32_t reserved_e0; uint32_t reserved_e4; uint32_t reserved_e8; @@ -520,11 +453,11 @@ typedef volatile struct { uint32_t reserved_3f0; uint32_t reserved_3f4; uint32_t reserved_3f8; - uint32_t date; /**/ + uint32_t date; /**/ } syscon_dev_t; - +extern syscon_dev_t SYSCON; #ifdef __cplusplus } #endif -extern syscon_dev_t SYSCON; + #endif /* _SOC_SYSCON_STRUCT_H_ */ diff --git a/components/soc/esp32s2beta/include/soc/system_reg.h b/components/soc/esp32s2beta/include/soc/system_reg.h index 2fc5512e07..79b89368d4 100644 --- a/components/soc/esp32s2beta/include/soc/system_reg.h +++ b/components/soc/esp32s2beta/include/soc/system_reg.h @@ -28,12 +28,18 @@ extern "C" { #define DPORT_ROM_FO_S 0 #define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004) -/* DPORT_ROM_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* DPORT_ROM_FORCE_PU : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ /*description: */ -#define DPORT_ROM_PD 0x00000003 -#define DPORT_ROM_PD_M ((DPORT_ROM_PD_V)<<(DPORT_ROM_PD_S)) -#define DPORT_ROM_PD_V 0x3 -#define DPORT_ROM_PD_S 0 +#define DPORT_ROM_FORCE_PU 0x00000003 +#define DPORT_ROM_FORCE_PU_M ((DPORT_ROM_FORCE_PU_V)<<(DPORT_ROM_FORCE_PU_S)) +#define DPORT_ROM_FORCE_PU_V 0x3 +#define DPORT_ROM_FORCE_PU_S 2 +/* DPORT_ROM_FORCE_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define DPORT_ROM_FORCE_PD 0x00000003 +#define DPORT_ROM_FORCE_PD_M ((DPORT_ROM_FORCE_PD_V)<<(DPORT_ROM_FORCE_PD_S)) +#define DPORT_ROM_FORCE_PD_V 0x3 +#define DPORT_ROM_FORCE_PD_S 0 #define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008) /* DPORT_SRAM_FO : R/W ;bitpos:[21:0] ;default: ~22'b0 ; */ @@ -44,12 +50,12 @@ extern "C" { #define DPORT_SRAM_FO_S 0 #define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C) -/* DPORT_SRAM_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/* DPORT_SRAM_FORCE_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ /*description: */ -#define DPORT_SRAM_PD 0x003FFFFF -#define DPORT_SRAM_PD_M ((DPORT_SRAM_PD_V)<<(DPORT_SRAM_PD_S)) -#define DPORT_SRAM_PD_V 0x3FFFFF -#define DPORT_SRAM_PD_S 0 +#define DPORT_SRAM_FORCE_PD 0x003FFFFF +#define DPORT_SRAM_FORCE_PD_M ((DPORT_SRAM_FORCE_PD_V)<<(DPORT_SRAM_FORCE_PD_S)) +#define DPORT_SRAM_FORCE_PD_V 0x3FFFFF +#define DPORT_SRAM_FORCE_PD_S 0 #define DPORT_PERI_CLK_EN_REG DPORT_CPU_PERI_CLK_EN_REG #define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010) @@ -65,50 +71,8 @@ extern "C" { #define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6)) #define DPORT_CLK_EN_ASSIST_DEBUG_V 0x1 #define DPORT_CLK_EN_ASSIST_DEBUG_S 6 -/* DPORT_CLK_EN_DIGITAL_SIGNATURE : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CLK_EN_DIGITAL_SIGNATURE (BIT(5)) -#define DPORT_CLK_EN_DIGITAL_SIGNATURE_M (BIT(5)) -#define DPORT_CLK_EN_DIGITAL_SIGNATURE_V 0x1 -#define DPORT_CLK_EN_DIGITAL_SIGNATURE_S 5 -/* DPORT_CLK_EN_HMAC : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CLK_EN_HMAC (BIT(4)) -#define DPORT_CLK_EN_HMAC_M (BIT(4)) -#define DPORT_CLK_EN_HMAC_V 0x1 -#define DPORT_CLK_EN_HMAC_S 4 -/* DPORT_CLK_EN_SECURE_BOOT : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CLK_EN_SECURE_BOOT (BIT(3)) -#define DPORT_CLK_EN_SECURE_BOOT_M (BIT(3)) -#define DPORT_CLK_EN_SECURE_BOOT_V 0x1 -#define DPORT_CLK_EN_SECURE_BOOT_S 3 -/* DPORT_CLK_EN_RSA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CLK_EN_RSA (BIT(2)) -#define DPORT_CLK_EN_RSA_M (BIT(2)) -#define DPORT_CLK_EN_RSA_V 0x1 -#define DPORT_CLK_EN_RSA_S 2 -/* DPORT_CLK_EN_SHA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CLK_EN_SHA (BIT(1)) -#define DPORT_CLK_EN_SHA_M (BIT(1)) -#define DPORT_CLK_EN_SHA_V 0x1 -#define DPORT_CLK_EN_SHA_S 1 -/* DPORT_CLK_EN_AES : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_CLK_EN_AES (BIT(0)) -#define DPORT_CLK_EN_AES_M (BIT(0)) -#define DPORT_CLK_EN_AES_V 0x1 -#define DPORT_CLK_EN_AES_S 0 -#define DPORT_PERI_EN_AES DPORT_CLK_EN_AES -#define DPORT_PERI_EN_SHA DPORT_CLK_EN_SHA -#define DPORT_PERI_EN_RSA DPORT_CLK_EN_RSA -/* NB: Secure boot reset will hold SHA & AES in reset */ -#define DPORT_PERI_EN_SECUREBOOT DPORT_CLK_EN_SECURE_BOOT /* NB: Digital signature reset will hold AES & RSA in reset */ -#define DPORT_PERI_EN_DIGITAL_SIGNATURE DPORT_CLK_EN_DIGITAL_SIGNATURE #define DPORT_PERI_EN_ASSIST_DEBUG DPORT_CLK_EN_ASSIST_DEBUG #define DPORT_PERI_RST_EN_REG DPORT_CPU_PERI_RST_EN_REG @@ -125,44 +89,14 @@ extern "C" { #define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6)) #define DPORT_RST_EN_ASSIST_DEBUG_V 0x1 #define DPORT_RST_EN_ASSIST_DEBUG_S 6 -/* DPORT_RST_EN_DIGITAL_SIGNATURE : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_RST_EN_DIGITAL_SIGNATURE (BIT(5)) -#define DPORT_RST_EN_DIGITAL_SIGNATURE_M (BIT(5)) -#define DPORT_RST_EN_DIGITAL_SIGNATURE_V 0x1 -#define DPORT_RST_EN_DIGITAL_SIGNATURE_S 5 -/* DPORT_RST_EN_HMAC : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_RST_EN_HMAC (BIT(4)) -#define DPORT_RST_EN_HMAC_M (BIT(4)) -#define DPORT_RST_EN_HMAC_V 0x1 -#define DPORT_RST_EN_HMAC_S 4 -/* DPORT_RST_EN_SECURE_BOOT : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_RST_EN_SECURE_BOOT (BIT(3)) -#define DPORT_RST_EN_SECURE_BOOT_M (BIT(3)) -#define DPORT_RST_EN_SECURE_BOOT_V 0x1 -#define DPORT_RST_EN_SECURE_BOOT_S 3 -/* DPORT_RST_EN_RSA : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_RST_EN_RSA (BIT(2)) -#define DPORT_RST_EN_RSA_M (BIT(2)) -#define DPORT_RST_EN_RSA_V 0x1 -#define DPORT_RST_EN_RSA_S 2 -/* DPORT_RST_EN_SHA : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_RST_EN_SHA (BIT(1)) -#define DPORT_RST_EN_SHA_M (BIT(1)) -#define DPORT_RST_EN_SHA_V 0x1 -#define DPORT_RST_EN_SHA_S 1 -/* DPORT_RST_EN_AES : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define DPORT_RST_EN_AES (BIT(0)) -#define DPORT_RST_EN_AES_M (BIT(0)) -#define DPORT_RST_EN_AES_V 0x1 -#define DPORT_RST_EN_AES_S 0 #define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) +/* DPORT_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: */ +#define DPORT_CPU_WAITI_DELAY_NUM 0x0000000F +#define DPORT_CPU_WAITI_DELAY_NUM_M ((DPORT_CPU_WAITI_DELAY_NUM_V)<<(DPORT_CPU_WAITI_DELAY_NUM_S)) +#define DPORT_CPU_WAITI_DELAY_NUM_V 0xF +#define DPORT_CPU_WAITI_DELAY_NUM_S 4 /* DPORT_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ /*description: */ #define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3)) @@ -449,13 +383,44 @@ extern "C" { #define DPORT_TIMERS_CLK_EN_V 0x1 #define DPORT_TIMERS_CLK_EN_S 0 +#define DPORT_CPU_PERIP_CLK_EN1_REG DPORT_PERIP_CLK_EN1_REG #define DPORT_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x044) -/* DPORT_SPI_SHARED_DMA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* DPORT_CRYPTO_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ -#define DPORT_SPI_SHARED_DMA_CLK_EN (BIT(0)) -#define DPORT_SPI_SHARED_DMA_CLK_EN_M (BIT(0)) -#define DPORT_SPI_SHARED_DMA_CLK_EN_V 0x1 -#define DPORT_SPI_SHARED_DMA_CLK_EN_S 0 +#define DPORT_CRYPTO_DMA_CLK_EN (BIT(6)) +#define DPORT_CRYPTO_DMA_CLK_EN_M (BIT(6)) +#define DPORT_CRYPTO_DMA_CLK_EN_V 0x1 +#define DPORT_CRYPTO_DMA_CLK_EN_S 6 +/* DPORT_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define DPORT_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define DPORT_CRYPTO_HMAC_CLK_EN_V 0x1 +#define DPORT_CRYPTO_HMAC_CLK_EN_S 5 +/* DPORT_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_DS_CLK_EN (BIT(4)) +#define DPORT_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define DPORT_CRYPTO_DS_CLK_EN_V 0x1 +#define DPORT_CRYPTO_DS_CLK_EN_S 4 +/* DPORT_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_RSA_CLK_EN (BIT(3)) +#define DPORT_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define DPORT_CRYPTO_RSA_CLK_EN_V 0x1 +#define DPORT_CRYPTO_RSA_CLK_EN_S 3 +/* DPORT_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_SHA_CLK_EN (BIT(2)) +#define DPORT_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define DPORT_CRYPTO_SHA_CLK_EN_V 0x1 +#define DPORT_CRYPTO_SHA_CLK_EN_S 2 +/* DPORT_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_CRYPTO_AES_CLK_EN (BIT(1)) +#define DPORT_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define DPORT_CRYPTO_AES_CLK_EN_V 0x1 +#define DPORT_CRYPTO_AES_CLK_EN_S 1 #define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG #define DPORT_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x048) @@ -652,13 +617,44 @@ extern "C" { #define DPORT_TIMERS_RST_V 0x1 #define DPORT_TIMERS_RST_S 0 +#define DPORT_CPU_PERIP_RST_EN1_REG DPORT_PERIP_RST_EN1_REG #define DPORT_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x04C) -/* DPORT_SPI_SHARED_DMA_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* DPORT_CRYPTO_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ /*description: */ -#define DPORT_SPI_SHARED_DMA_RST (BIT(0)) -#define DPORT_SPI_SHARED_DMA_RST_M (BIT(0)) -#define DPORT_SPI_SHARED_DMA_RST_V 0x1 -#define DPORT_SPI_SHARED_DMA_RST_S 0 +#define DPORT_CRYPTO_DMA_RST (BIT(6)) +#define DPORT_CRYPTO_DMA_RST_M (BIT(6)) +#define DPORT_CRYPTO_DMA_RST_V 0x1 +#define DPORT_CRYPTO_DMA_RST_S 6 +/* DPORT_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_HMAC_RST (BIT(5)) +#define DPORT_CRYPTO_HMAC_RST_M (BIT(5)) +#define DPORT_CRYPTO_HMAC_RST_V 0x1 +#define DPORT_CRYPTO_HMAC_RST_S 5 +/* DPORT_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_DS_RST (BIT(4)) +#define DPORT_CRYPTO_DS_RST_M (BIT(4)) +#define DPORT_CRYPTO_DS_RST_V 0x1 +#define DPORT_CRYPTO_DS_RST_S 4 +/* DPORT_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_RSA_RST (BIT(3)) +#define DPORT_CRYPTO_RSA_RST_M (BIT(3)) +#define DPORT_CRYPTO_RSA_RST_V 0x1 +#define DPORT_CRYPTO_RSA_RST_S 3 +/* DPORT_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_SHA_RST (BIT(2)) +#define DPORT_CRYPTO_SHA_RST_M (BIT(2)) +#define DPORT_CRYPTO_SHA_RST_V 0x1 +#define DPORT_CRYPTO_SHA_RST_S 2 +/* DPORT_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define DPORT_CRYPTO_AES_RST (BIT(1)) +#define DPORT_CRYPTO_AES_RST_M (BIT(1)) +#define DPORT_CRYPTO_AES_RST_V 0x1 +#define DPORT_CRYPTO_AES_RST_S 1 #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x050) /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ @@ -745,6 +741,18 @@ extern "C" { #define DPORT_CPU_INTR_FROM_CPU_3_S 0 #define DPORT_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x068) +/* DPORT_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RSA_MEM_FORCE_PD (BIT(2)) +#define DPORT_RSA_MEM_FORCE_PD_M (BIT(2)) +#define DPORT_RSA_MEM_FORCE_PD_V 0x1 +#define DPORT_RSA_MEM_FORCE_PD_S 2 +/* DPORT_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define DPORT_RSA_MEM_FORCE_PU (BIT(1)) +#define DPORT_RSA_MEM_FORCE_PU_M (BIT(1)) +#define DPORT_RSA_MEM_FORCE_PU_V 0x1 +#define DPORT_RSA_MEM_FORCE_PU_S 1 /* DPORT_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define DPORT_RSA_MEM_PD (BIT(0)) @@ -753,16 +761,7 @@ extern "C" { #define DPORT_RSA_MEM_PD_S 0 #define DPORT_RSA_PD DPORT_RSA_MEM_PD -#define DPORT_SPI_DMA_CHAN_SEL_REG DPORT_SPI_SHARED_DMA_SEL_REG -#define DPORT_SPI_SHARED_DMA_SEL_REG (DR_REG_SYSTEM_BASE + 0x06C) -/* DPORT_SPI_SHARED_DMA_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define DPORT_SPI_SHARED_DMA_SEL (BIT(0)) -#define DPORT_SPI_SHARED_DMA_SEL_M (BIT(0)) -#define DPORT_SPI_SHARED_DMA_SEL_V 0x1 -#define DPORT_SPI_SHARED_DMA_SEL_S 0 - -#define DPORT_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x070) +#define DPORT_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x06C) /* DPORT_BUSTOEXTMEM_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define DPORT_BUSTOEXTMEM_ENA (BIT(0)) @@ -770,7 +769,7 @@ extern "C" { #define DPORT_BUSTOEXTMEM_ENA_V 0x1 #define DPORT_BUSTOEXTMEM_ENA_S 0 -#define DPORT_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x074) +#define DPORT_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x070) /* DPORT_PRO_CACHE_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ /*description: */ #define DPORT_PRO_CACHE_RESET (BIT(2)) @@ -790,7 +789,7 @@ extern "C" { #define DPORT_PRO_ICACHE_CLK_ON_V 0x1 #define DPORT_PRO_ICACHE_CLK_ON_S 0 -#define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x078) +#define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x074) /* DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: */ #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) @@ -816,7 +815,7 @@ extern "C" { #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_S 0 -#define DPORT_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x07C) +#define DPORT_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x078) /* DPORT_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ /*description: */ #define DPORT_RTC_MEM_CRC_FINISH (BIT(31)) @@ -842,7 +841,7 @@ extern "C" { #define DPORT_RTC_MEM_CRC_START_V 0x1 #define DPORT_RTC_MEM_CRC_START_S 8 -#define DPORT_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x080) +#define DPORT_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x07C) /* DPORT_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /*description: */ #define DPORT_RTC_MEM_CRC_RES 0xFFFFFFFF @@ -850,7 +849,7 @@ extern "C" { #define DPORT_RTC_MEM_CRC_RES_V 0xFFFFFFFF #define DPORT_RTC_MEM_CRC_RES_S 0 -#define DPORT_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x084) +#define DPORT_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x080) /* DPORT_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define DPORT_REDUNDANT_ECO_RESULT (BIT(1)) @@ -864,7 +863,7 @@ extern "C" { #define DPORT_REDUNDANT_ECO_DRIVE_V 0x1 #define DPORT_REDUNDANT_ECO_DRIVE_S 0 -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x088) +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x084) /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: */ #define SYSTEM_CLK_EN (BIT(0)) @@ -872,8 +871,42 @@ extern "C" { #define SYSTEM_CLK_EN_V 0x1 #define SYSTEM_CLK_EN_S 0 +#define DPORT_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x088) +/* DPORT_SRAM_FORCE_PU : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ +/*description: */ +#define DPORT_SRAM_FORCE_PU 0x003FFFFF +#define DPORT_SRAM_FORCE_PU_M ((DPORT_SRAM_FORCE_PU_V)<<(DPORT_SRAM_FORCE_PU_S)) +#define DPORT_SRAM_FORCE_PU_V 0x3FFFFF +#define DPORT_SRAM_FORCE_PU_S 0 + +#define DPORT_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x08C) +/* DPORT_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define DPORT_CLK_DIV_EN (BIT(19)) +#define DPORT_CLK_DIV_EN_M (BIT(19)) +#define DPORT_CLK_DIV_EN_V 0x1 +#define DPORT_CLK_DIV_EN_S 19 +/* DPORT_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ +/*description: */ +#define DPORT_CLK_XTAL_FREQ 0x0000007F +#define DPORT_CLK_XTAL_FREQ_M ((DPORT_CLK_XTAL_FREQ_V)<<(DPORT_CLK_XTAL_FREQ_S)) +#define DPORT_CLK_XTAL_FREQ_V 0x7F +#define DPORT_CLK_XTAL_FREQ_S 12 +/* DPORT_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define DPORT_SOC_CLK_SEL 0x00000003 +#define DPORT_SOC_CLK_SEL_M ((DPORT_SOC_CLK_SEL_V)<<(DPORT_SOC_CLK_SEL_S)) +#define DPORT_SOC_CLK_SEL_V 0x3 +#define DPORT_SOC_CLK_SEL_S 10 +/* DPORT_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define DPORT_PRE_DIV_CNT 0x000003FF +#define DPORT_PRE_DIV_CNT_M ((DPORT_PRE_DIV_CNT_V)<<(DPORT_PRE_DIV_CNT_S)) +#define DPORT_PRE_DIV_CNT_V 0x3FF +#define DPORT_PRE_DIV_CNT_S 0 + #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) -/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810300 ; */ +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908020 ; */ /*description: */ #define SYSTEM_DATE 0x0FFFFFFF #define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/timer_group_struct.h b/components/soc/esp32s2beta/include/soc/timer_group_struct.h index 4240d41cf3..0f16144d27 100644 --- a/components/soc/esp32s2beta/include/soc/timer_group_struct.h +++ b/components/soc/esp32s2beta/include/soc/timer_group_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -92,8 +92,9 @@ typedef volatile struct { } rtc_cali_cfg; union { struct { - uint32_t reserved0: 7; - uint32_t value: 25; + uint32_t cycling_data_vld: 1; + uint32_t reserved1: 6; + uint32_t value: 25; }; uint32_t val; } rtc_cali_cfg1; diff --git a/components/soc/esp32s2beta/include/soc/touch_sensor_channel.h b/components/soc/esp32s2beta/include/soc/touch_sensor_channel.h index a405a6bd1c..64fa7c6e89 100644 --- a/components/soc/esp32s2beta/include/soc/touch_sensor_channel.h +++ b/components/soc/esp32s2beta/include/soc/touch_sensor_channel.h @@ -25,40 +25,25 @@ #define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2 #define TOUCH_PAD_NUM2_GPIO_NUM 2 -#define TOUCH_PAD_GPIO3_CHANNEL TOUCH_PAD_NUM3 -#define TOUCH_PAD_NUM3_GPIO_NUM 3 +#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3 +#define TOUCH_PAD_NUM3_GPIO_NUM 15 -#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM4 -#define TOUCH_PAD_NUM4_GPIO_NUM 4 +#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4 +#define TOUCH_PAD_NUM4_GPIO_NUM 13 -#define TOUCH_PAD_GPIO5_CHANNEL TOUCH_PAD_NUM5 -#define TOUCH_PAD_NUM5_GPIO_NUM 5 +#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5 +#define TOUCH_PAD_NUM5_GPIO_NUM 12 -#define TOUCH_PAD_GPIO6_CHANNEL TOUCH_PAD_NUM6 -#define TOUCH_PAD_NUM6_GPIO_NUM 6 +#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6 +#define TOUCH_PAD_NUM6_GPIO_NUM 14 -#define TOUCH_PAD_GPIO7_CHANNEL TOUCH_PAD_NUM7 -#define TOUCH_PAD_NUM7_GPIO_NUM 7 +#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7 +#define TOUCH_PAD_NUM7_GPIO_NUM 27 -#define TOUCH_PAD_GPIO8_CHANNEL TOUCH_PAD_NUM8 -#define TOUCH_PAD_NUM8_GPIO_NUM 8 +#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8 +#define TOUCH_PAD_NUM8_GPIO_NUM 33 -#define TOUCH_PAD_GPIO9_CHANNEL TOUCH_PAD_NUM9 -#define TOUCH_PAD_NUM9_GPIO_NUM 9 - -#define TOUCH_PAD_GPIO10_CHANNEL TOUCH_PAD_NUM10 -#define TOUCH_PAD_NUM10_GPIO_NUM 10 - -#define TOUCH_PAD_GPIO11_CHANNEL TOUCH_PAD_NUM11 -#define TOUCH_PAD_NUM11_GPIO_NUM 11 - -#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM12 -#define TOUCH_PAD_NUM12_GPIO_NUM 12 - -#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM13 -#define TOUCH_PAD_NUM13_GPIO_NUM 13 - -#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM14 -#define TOUCH_PAD_NUM14_GPIO_NUM 14 +#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9 +#define TOUCH_PAD_NUM9_GPIO_NUM 32 #endif diff --git a/components/soc/esp32s2beta/include/soc/uart_reg.h b/components/soc/esp32s2beta/include/soc/uart_reg.h index ee6ffdd421..f17cacc3cb 100644 --- a/components/soc/esp32s2beta/include/soc/uart_reg.h +++ b/components/soc/esp32s2beta/include/soc/uart_reg.h @@ -594,6 +594,12 @@ extern "C" { #define UART_RXFIFO_CNT_S 0 #define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */ +/*description: */ +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (BIT(28)) +#define UART_MEM_CLK_EN_V 0x1 +#define UART_MEM_CLK_EN_S 28 /* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ /*description: */ #define UART_TICK_REF_ALWAYS_ON (BIT(27)) @@ -984,6 +990,18 @@ extern "C" { #define UART_AT_CMD_CHAR_S 0 #define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (BIT(27)) +#define UART_MEM_FORCE_PU_V 0x1 +#define UART_MEM_FORCE_PU_S 27 +/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (BIT(26)) +#define UART_MEM_FORCE_PD_V 0x1 +#define UART_MEM_FORCE_PD_S 26 /* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */ /*description: */ #define UART_RX_TOUT_THRHD 0x000003FF @@ -1008,12 +1026,6 @@ extern "C" { #define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) #define UART_RX_SIZE_V 0x7 #define UART_RX_SIZE_S 1 -/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define UART_MEM_PD (BIT(0)) -#define UART_MEM_PD_M (BIT(0)) -#define UART_MEM_PD_V 0x1 -#define UART_MEM_PD_S 0 #define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) /* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */ @@ -1074,7 +1086,7 @@ extern "C" { #define UART_NEGEDGE_MIN_CNT_S 0 #define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x74) -/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h18082800 ; */ +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h19031400 ; */ /*description: */ #define UART_DATE 0xFFFFFFFF #define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/uart_struct.h b/components/soc/esp32s2beta/include/soc/uart_struct.h index 07f27e905b..a470b6b968 100644 --- a/components/soc/esp32s2beta/include/soc/uart_struct.h +++ b/components/soc/esp32s2beta/include/soc/uart_struct.h @@ -20,8 +20,7 @@ extern "C" { typedef volatile struct { union { struct { - uint8_t rw_byte; - uint8_t reserved[3]; + uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/ }; uint32_t val; } ahb_fifo; @@ -189,7 +188,8 @@ typedef volatile struct { uint32_t clk_en: 1; uint32_t err_wr_mask: 1; uint32_t tick_ref_always_on: 1; - uint32_t reserved28: 4; + uint32_t mem_clk_en: 1; + uint32_t reserved29: 3; }; uint32_t val; } conf0; @@ -313,12 +313,14 @@ typedef volatile struct { } at_cmd_char; union { struct { - uint32_t mem_pd: 1; + uint32_t reserved0: 1; uint32_t rx_size: 3; uint32_t tx_size: 3; uint32_t rx_flow_thrhd: 9; uint32_t rx_tout_thrhd:10; - uint32_t reserved26: 6; + uint32_t force_pd: 1; + uint32_t force_pu: 1; + uint32_t reserved28: 4; }; uint32_t val; } mem_conf; diff --git a/components/soc/esp32s2beta/include/soc/wdev_reg.h b/components/soc/esp32s2beta/include/soc/wdev_reg.h index 093989f067..f258088a24 100644 --- a/components/soc/esp32s2beta/include/soc/wdev_reg.h +++ b/components/soc/esp32s2beta/include/soc/wdev_reg.h @@ -17,5 +17,5 @@ #include "soc.h" /* Hardware random number generator register */ -#define WDEV_RND_REG 0x6003510C +#define WDEV_RND_REG 0x60035100 diff --git a/components/soc/esp32s2beta/rtc_clk.c b/components/soc/esp32s2beta/rtc_clk.c index 2f9ef41adc..a74cf81ece 100644 --- a/components/soc/esp32s2beta/rtc_clk.c +++ b/components/soc/esp32s2beta/rtc_clk.c @@ -1,4 +1,4 @@ -// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -16,6 +16,7 @@ #include #include #include +#include "sdkconfig.h" #include "esp32s2beta/rom/ets_sys.h" #include "esp32s2beta/rom/rtc.h" #include "esp32s2beta/rom/uart.h" @@ -32,71 +33,7 @@ #include "sdkconfig.h" #include "xtensa/core-macros.h" - -#define MHZ (1000000) - -/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */ -#define RTC_FAST_CLK_FREQ_8M 8500000 -#define RTC_SLOW_CLK_FREQ_90K 90000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - -static const char* TAG = "rtc_clk"; - -/* Various constants related to the analog internals of the chip. - * Defined here because they don't have any use outside of this file. - */ - -#define BBPLL_ENDIV5_VAL_320M 0x43 -#define BBPLL_BBADC_DSMP_VAL_320M 0x84 -#define BBPLL_ENDIV5_VAL_480M 0xc3 -#define BBPLL_BBADC_DSMP_VAL_480M 0x74 - -#define APLL_SDM_STOP_VAL_1 0x09 -#define APLL_SDM_STOP_VAL_2_REV0 0x69 -#define APLL_SDM_STOP_VAL_2_REV1 0x49 - -#define APLL_CAL_DELAY_1 0x0f -#define APLL_CAL_DELAY_2 0x3f -#define APLL_CAL_DELAY_3 0x1f - -#define XTAL_32K_DAC_VAL 1 -#define XTAL_32K_DRES_VAL 3 -#define XTAL_32K_DGM_VAL 0 - -#define XTAL_32K_BOOTSTRAP_DAC_VAL 3 -#define XTAL_32K_BOOTSTRAP_DRES_VAL 3 -#define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0 -#define XTAL_32K_BOOTSTRAP_TIME_US 7 - -/* Delays for various clock sources to be enabled/switched. - * All values are in microseconds. - * TODO: some of these are excessive, and should be reduced. - */ -#define DELAY_PLL_DBIAS_RAISE 3 -#define DELAY_PLL_ENABLE_WITH_150K 80 -#define DELAY_PLL_ENABLE_WITH_32K 160 -#define DELAY_FAST_CLK_SWITCH 3 -#define DELAY_SLOW_CLK_SWITCH 300 -#define DELAY_8M_ENABLE 50 - -/* Number of 8M/256 clock cycles to use for XTAL frequency estimation. - * 10 cycles will take approximately 300 microseconds. - */ -#define XTAL_FREQ_EST_CYCLES 10 - -/* Core voltage needs to be increased in two cases: - * 1. running at 240 MHz - * 2. running with 80MHz Flash frequency - */ -#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 -#else -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 -#endif -#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25 -#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 +static const char *TAG = "rtc_clk"; /* PLL currently enabled, if any */ typedef enum { @@ -109,71 +46,28 @@ static rtc_pll_t s_cur_pll = RTC_PLL_NONE; /* Current CPU frequency; saved in a variable for faster freq. switching */ static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL; -void rtc_clk_32k_enable_internal(int dac, int dres, int dgm) +void rtc_clk_32k_enable_internal(x32k_config_t cfg) { - SET_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL); - SET_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL); - CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32P_FUN_IE | RTC_IO_X32P_RDE); - CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_RUE | RTC_IO_X32N_FUN_IE | RTC_IO_X32N_RDE); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, dac); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, dres); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, dgm); - - /* Differential buffer option. May need to change */ - // CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K); - - /* Clear xpd force to use xtal32k watch dog to control xtal pxd. default on */ - CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, cfg.dac); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, cfg.dres); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, cfg.dgm); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); + SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); } void rtc_clk_32k_enable(bool enable) { if (enable) { - rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DGM_VAL); + x32k_config_t cfg = X32K_CONFIG_DEFAULT(); + rtc_clk_32k_enable_internal(cfg); } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE); + CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K); } } -/* Helping external 32kHz crystal to start up. - * External crystal connected to outputs GPIO32 GPIO33. - * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal. - */ -/* I doudt whether the old function can work correctly on ESP32...Need to review when having time */ void rtc_clk_32k_bootstrap(uint32_t cycle) { - /* Config a clock to stimulate xtal, this clock is divided by a clock mux - * The default selection of the clock mux is to use 8M, but it may not have enough accuracy compared with 40M xtal - * This clock will be a pulse clk with a double frequency of 32.768k. - * and then it will become a 32.768k clock with 50% duty cycle in RTC. - * (40M / 32.768k) * 2 = 2441 + 13/32 - */ - REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 2441); - REG_SET_FIELD(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_BT_LPCK_DIV_A, 32); - REG_SET_FIELD(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_BT_LPCK_DIV_B, 13); - - /* Enable clock mux with 40M */ - SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); - CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M); - SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL); - - /* connect clock to RTC */ - SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN); - /* connect clock to analog */ - SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_ENCKINIT_XTAL_32K); - - /* Enable 32k xtal */ - rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL, XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL); - - /* wait 32k xtal to be stable. Need to find a better way */ - ets_delay_us(cycle); - - /* Close clock source */ - CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL); - CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_ENCKINIT_XTAL_32K); - CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN); } bool rtc_clk_32k_enabled(void) @@ -195,7 +89,7 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) if (clk_8m_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); /* no need to wait once enabled by software */ - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); ets_delay_us(DELAY_8M_ENABLE); } else { SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); @@ -228,7 +122,7 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm /* BIAS I2C not exist any more, but not sure how to get the same effect yet... * if (!enable && - * REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL) != SYSCON_SOC_CLK_SEL_PLL) { + * REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL) != DPORT_SOC_CLK_SEL_PLL) { * REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); * } else { * REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); @@ -296,12 +190,12 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq) * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead? */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); /* The clk_8m_d256 will be closed when rtc_state in SLEEP, so if the slow_clk is 8md256, clk_8m must be force power on */ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG,RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0); rtc_clk_set_xtal_wait(); ets_delay_us(DELAY_SLOW_CLK_SWITCH); } @@ -313,10 +207,10 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void) uint32_t rtc_clk_slow_freq_get_hz(void) { - switch(rtc_clk_slow_freq_get()) { - case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_90K; - case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; - case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; + switch (rtc_clk_slow_freq_get()) { + case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K; + case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K; + case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256; } return 0; } @@ -399,7 +293,7 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq) if (cal_result == 0) { break; } - if(ext_cap == 15) { + if (ext_cap == 15) { SOC_LOGE(TAG, "BBPLL SOFTWARE CAL FAIL"); } } @@ -425,8 +319,8 @@ static void rtc_clk_cpu_freq_to_xtal(void) rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); ets_update_cpu_frequency(xtal_freq); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0); - REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_XTL); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 0); /* Why we need to do this ? */ //DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL @@ -467,7 +361,7 @@ static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq) DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 2); freq = 240; } - // REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_PLL); + // REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); rtc_clk_apb_freq_update(80 * MHZ); ets_update_cpu_frequency(freq); s_cur_freq = cpu_freq; @@ -494,8 +388,8 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); /* Switch CPU to XTAL frequency first */ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_XTL); - REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 0); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); ets_update_cpu_frequency(xtal_freq); /* Frequency switch is synchronized to SLOW_CLK cycle. Wait until the switch * is complete before disabling the PLL. @@ -507,8 +401,8 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) /* BBPLL force power down won't affect force power up setting */ SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, - RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | - RTC_CNTL_BBPLL_I2C_FORCE_PD); + RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | + RTC_CNTL_BBPLL_I2C_FORCE_PD); s_cur_pll = RTC_PLL_NONE; rtc_clk_apb_freq_update(xtal_freq * MHZ); @@ -526,7 +420,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) /* already at XTAL, nothing to do */ } else if (cpu_freq == RTC_CPU_FREQ_2M) { /* set up divider to produce 2MHz from XTAL */ - REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, (xtal_freq / 2) - 1); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, (xtal_freq / 2) - 1); ets_update_cpu_frequency(2); rtc_clk_apb_freq_update(2 * MHZ); /* lower the voltage */ @@ -534,8 +428,8 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) } else { /* use PLL as clock source */ CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, - RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); + RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); if (cpu_freq > RTC_CPU_FREQ_2M) { rtc_clk_bbpll_set(xtal_freq, RTC_PLL_320M); s_cur_pll = RTC_PLL_320M; @@ -557,7 +451,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2); ets_update_cpu_frequency(240); } - REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_PLL); + REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 1); //rtc_clk_wait_for_slow_cycle(); rtc_clk_apb_freq_update(80 * MHZ); } @@ -566,64 +460,77 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) rtc_cpu_freq_t rtc_clk_cpu_freq_get(void) { - uint32_t soc_clk_sel = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL); + uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); switch (soc_clk_sel) { - case SYSCON_SOC_CLK_SEL_XTL: { - uint32_t pre_div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT); - if (pre_div == 0) { - return RTC_CPU_FREQ_XTAL; - } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) { - return RTC_CPU_FREQ_2M; - } else { - assert(false && "unsupported frequency"); - } - break; - } - case SYSCON_SOC_CLK_SEL_PLL: { - uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); - if (cpuperiod_sel == 0) { - return RTC_CPU_FREQ_80M; - } else if (cpuperiod_sel == 1) { - return RTC_CPU_FREQ_160M; - } else if (cpuperiod_sel == 2) { - return RTC_CPU_FREQ_240M; - } else { - assert(false && "unsupported frequency"); - } - break; - } - case SYSCON_SOC_CLK_SEL_APLL: - case SYSCON_SOC_CLK_SEL_8M: - default: + case 0: { + uint32_t pre_div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT); + if (pre_div == 0) { + return RTC_CPU_FREQ_XTAL; + } else if (pre_div == 1) { + return RTC_CPU_FREQ_XTAL_DIV2; + } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) { + return RTC_CPU_FREQ_2M; + } else { assert(false && "unsupported frequency"); + } + break; } - return SYSCON_SOC_CLK_SEL_XTL; + case 1: { + uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); + uint32_t pllfreq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL); + if (cpuperiod_sel == 0) { + if (pllfreq_sel == 1) { + return RTC_CPU_FREQ_80M; + } else { + return RTC_CPU_320M_80M; + } + } else if (cpuperiod_sel == 1) { + if (pllfreq_sel == 1) { + return RTC_CPU_FREQ_160M; + } else { + return RTC_CPU_320M_160M; + } + } else if (cpuperiod_sel == 2) { + return RTC_CPU_FREQ_240M; + } else { + assert(false && "unsupported frequency"); + } + break; + } + case 2: + case 3: + default: + assert(false && "unsupported frequency"); + } + return 0; } uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) { switch (cpu_freq) { - case RTC_CPU_FREQ_XTAL: - return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ; - case RTC_CPU_FREQ_2M: - return 2 * MHZ; - case RTC_CPU_FREQ_80M: - return 80 * MHZ; - case RTC_CPU_FREQ_160M: - return 160 * MHZ; - case RTC_CPU_FREQ_240M: - return 240 * MHZ; - case RTC_CPU_320M_80M: - return 80 * MHZ; - case RTC_CPU_320M_160M: - return 160 * MHZ; - default: - assert(false && "invalid rtc_cpu_freq_t value"); - return 0; + case RTC_CPU_FREQ_XTAL: + return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ; + case RTC_CPU_FREQ_XTAL_DIV2: + return ((uint32_t) rtc_clk_xtal_freq_get()) / 2 * MHZ; + case RTC_CPU_FREQ_2M: + return 2 * MHZ; + case RTC_CPU_FREQ_80M: + return 80 * MHZ; + case RTC_CPU_FREQ_160M: + return 160 * MHZ; + case RTC_CPU_FREQ_240M: + return 240 * MHZ; + case RTC_CPU_320M_80M: + return 80 * MHZ; + case RTC_CPU_320M_160M: + return 160 * MHZ; + default: + assert(false && "invalid rtc_cpu_freq_t value"); + return 0; } } -bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t* out_val) +bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t *out_val) { if (mhz == 240) { *out_val = RTC_CPU_FREQ_240M; @@ -633,6 +540,8 @@ bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t* out_val) *out_val = RTC_CPU_FREQ_80M; } else if (mhz == (int) rtc_clk_xtal_freq_get()) { *out_val = RTC_CPU_FREQ_XTAL; + } else if (mhz == (int) rtc_clk_xtal_freq_get() / 2) { + *out_val = RTC_CPU_FREQ_XTAL_DIV2; } else if (mhz == 2) { *out_val = RTC_CPU_FREQ_2M; } else { @@ -645,23 +554,25 @@ bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t* out_val) * lower and upper 16-bit halves. These are the routines to work with such a * representation. */ -static bool clk_val_is_valid(uint32_t val) { +static bool clk_val_is_valid(uint32_t val) +{ return (val & 0xffff) == ((val >> 16) & 0xffff) && - val != 0 && - val != UINT32_MAX; + val != 0 && + val != UINT32_MAX; } -static uint32_t reg_val_to_clk_val(uint32_t val) { +static uint32_t reg_val_to_clk_val(uint32_t val) +{ return val & UINT16_MAX; } -static uint32_t clk_val_to_reg_val(uint32_t val) { +static uint32_t clk_val_to_reg_val(uint32_t val) +{ return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) { - /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); if (!clk_val_is_valid(xtal_freq_reg)) { SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg); @@ -715,7 +626,7 @@ void rtc_clk_init(rtc_clk_config_t cfg) * PLL is configured for 480M, but it takes less time to switch to 40M and * run the following code than querying the PLL does. */ - if (REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL) == SYSCON_SOC_CLK_SEL_PLL) { + if (REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL) == 1) { rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); } diff --git a/components/soc/esp32s2beta/rtc_init.c b/components/soc/esp32s2beta/rtc_init.c index 29d53753af..b2277f335f 100644 --- a/components/soc/esp32s2beta/rtc_init.c +++ b/components/soc/esp32s2beta/rtc_init.c @@ -1,4 +1,4 @@ -// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,7 +13,6 @@ // limitations under the License. #include - #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" @@ -21,31 +20,9 @@ #include "soc/efuse_periph.h" #include "soc/gpio_reg.h" #include "soc/spi_mem_reg.h" +#include "soc/extmem_reg.h" #include "i2c_rtc_clk.h" -/* Various delays to be programmed into power control state machines */ -#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 -#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 -#define RTC_CNTL_CK8M_WAIT_SLP 4 -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#ifndef CONFIG_HARDWARE_IS_FPGA void rtc_init(rtc_config_t cfg) { CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU); @@ -63,20 +40,21 @@ void rtc_init(rtc_config_t cfg) * REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES); */ // set wifi timer - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_CYCLES); + rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT(); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); // set rtc peri timer - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, RTC_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, RTC_WAIT_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles); // set digital wrap timer - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, DG_WRAP_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, DG_WRAP_WAIT_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles); // set rtc memory timer - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_CYCLES); + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles); SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG, - RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD); + RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD); /* Reset RTC bias to default value (needed if waking up from deep sleep) */ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); @@ -84,14 +62,14 @@ void rtc_init(rtc_config_t cfg) if (cfg.clkctl_init) { //clear CMMU clock force on - CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_MMU_POWER_CTRL_REG, DPORT_PRO_CACHE_MMU_MEM_FORCE_ON); + CLEAR_PERI_REG_MASK(EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG, EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON); //clear rom clock force on REG_SET_FIELD(DPORT_ROM_CTRL_0_REG, DPORT_ROM_FO, 0); //clear sram clock force on REG_SET_FIELD(DPORT_SRAM_CTRL_0_REG, DPORT_SRAM_FO, 0); //clear tag clock force on - CLEAR_PERI_REG_MASK(DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG, DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON); - CLEAR_PERI_REG_MASK(DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG, DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON); + CLEAR_PERI_REG_MASK(EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON); + CLEAR_PERI_REG_MASK(EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON); //clear register clock force on CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN); CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN); @@ -105,14 +83,6 @@ void rtc_init(rtc_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU); } - // cancel BIAS force pu - // CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU); - // CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); - // bias follow 8M - // SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M); - // SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M); - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M); // CLEAR APLL close CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); @@ -128,7 +98,7 @@ void rtc_init(rtc_config_t cfg) SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } //cancel RTC REG force PU - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PWC_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); @@ -141,8 +111,12 @@ void rtc_init(rtc_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); } + //cancel sar i2c pd force + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_SAR_I2C_FORCE_PD); //cancel digital pu force CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); + //cannel i2c_reset_protect pd force + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_I2C_RESET_POR_FORCE_PD); /* If this mask is enabled, all soc memories cannot enter power down mode */ /* We should control soc memory power down mode from RTC, so we will not touch this register any more */ @@ -161,27 +135,17 @@ void rtc_init(rtc_config_t cfg) // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO); CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO); //cancel digital PADS force no iso - if (cfg.cpu_waiti_clk_gate){ + if (cfg.cpu_waiti_clk_gate) { CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_CPU_WAIT_MODE_FORCE_ON); - } - else{ + } else { SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_CPU_WAIT_MODE_FORCE_ON); } /*if DPORT_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/ -#ifdef CONFIG_CHIP_IS_ESP32 - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_UNHOLD); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_NOISO); -#endif CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO); -#ifdef CONFIG_CHIP_IS_ESP32 - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_AUTOHOLD_EN); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN); -#endif } } -#endif rtc_vddsdio_config_t rtc_vddsdio_get_config(void) { @@ -199,6 +163,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void) } else { result.force = 0; } +#if 0 // ToDo: re-enable the commented codes uint32_t efuse_reg = REG_READ(EFUSE_RD_REPEAT_DATA1_REG); if (efuse_reg & EFUSE_SDIO_FORCE) { // Get configuration from EFUSE @@ -213,7 +178,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void) return result; } - +#endif // Otherwise, VDD_SDIO is controlled by bootstrapping pin uint32_t strap_reg = REG_READ(GPIO_STRAP_REG); result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V; diff --git a/components/soc/esp32s2beta/rtc_sleep.c b/components/soc/esp32s2beta/rtc_sleep.c index 56865ce74c..15fde3237e 100644 --- a/components/soc/esp32s2beta/rtc_sleep.c +++ b/components/soc/esp32s2beta/rtc_sleep.c @@ -1,4 +1,4 @@ -// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -27,8 +27,6 @@ #include "soc/rtc.h" #include "esp32s2beta/rom/ets_sys.h" -#define MHZ (1000000) - /** * Configure whether certain peripherals are powered down in deep sleep * @param cfg power down flags as rtc_sleep_pd_config_t structure @@ -38,7 +36,6 @@ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); - //DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu); REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu); REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu); @@ -55,27 +52,11 @@ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) void rtc_sleep_init(rtc_sleep_config_t cfg) { - /* Already defined in rtc init - // set 5 PWC state machine times to fit in main state machine time - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_SLP); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP); - */ - /* I don't think it worthes to run this function everytime as it is just a test option */ - if (cfg.lslp_mem_inf_fpu) - { + if (cfg.lslp_mem_inf_fpu) { rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(1); rtc_sleep_pd(pd_cfg); } - /* This option seems to be unneccessary - if (cfg.rtc_mem_inf_fpu) { - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); - } - */ - if (cfg.rtc_mem_inf_follow_cpu) { SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU); } else { @@ -84,22 +65,22 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) if (cfg.rtc_fastmem_pd_en) { SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_FASTMEM_FORCE_NOISO); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO); } if (cfg.rtc_slowmem_pd_en) { SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG,RTC_CNTL_SLOWMEM_FORCE_NOISO); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO); } if (cfg.rtc_peri_pd_en) { @@ -114,38 +95,21 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } - /* -#ifdef CONFIG_CHIP_IS_ESP32 - if (cfg.rom_mem_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN); - } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN); - } -#endif - */ - if (cfg.deep_slp) { - /* redundant ? People may not want to touch such registers after init - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, - RTC_CNTL_DG_PAD_FORCE_ISO | RTC_CNTL_DG_PAD_FORCE_NOISO); - - CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, - RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_DG_WRAP_FORCE_PD); - -#ifdef CONFIG_CHIP_IS_ESP32 - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); -#endif - */ - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - // Shut down parts of RTC which may have been left enabled by the wireless drivers CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, - RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | - RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); + RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | + RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 6); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); } + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); /* enable VDDSDIO control by state machine */ REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); @@ -175,23 +139,18 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG, - RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) { + RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) { ; } /* In deep sleep mode, we never get here */ uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW); SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, - RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); + RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); /* restore config if it is a light sleep */ - if (lslp_mem_inf_fpu) - { + if (lslp_mem_inf_fpu) { rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0); rtc_sleep_pd(pd_cfg); } - /* move setting from init to sleep, so we don't need to have this any more - * restore DBG_ATTEN to the default value - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT); - */ return reject; } diff --git a/components/soc/esp32s2beta/rtc_time.c b/components/soc/esp32s2beta/rtc_time.c index af7829a72f..52d63934b3 100644 --- a/components/soc/esp32s2beta/rtc_time.c +++ b/components/soc/esp32s2beta/rtc_time.c @@ -1,4 +1,4 @@ -// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -18,8 +18,6 @@ #include "soc/rtc_cntl_reg.h" #include "soc/timer_group_reg.h" -#define MHZ (1000000) - /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. * This feature counts the number of XTAL clock cycles within a given number of * RTC_SLOW_CLK cycles. @@ -56,7 +54,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) */ if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { - while(!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)); + while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)); } } CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING); @@ -66,14 +64,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles) /* Set timeout reg and expect time delay*/ uint32_t expected_freq; if (cal_clk == RTC_CAL_32K_XTAL) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 13)); - expected_freq = 32768; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_32K; } else if (cal_clk == RTC_CAL_8MD256) { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 13)); - expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_8MD256; } else { - REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 11)); - expected_freq = 90000; + REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles)); + expected_freq = RTC_SLOW_CLK_FREQ_150K; } uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq); /* Start calibration */ @@ -138,10 +136,12 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) uint64_t rtc_time_get(void) { SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); +#if 0 // ToDo: Re-enable it in the future while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { ets_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus } SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR); +#endif uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; return t; diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c index 5d6f680ce2..bbcecc0531 100644 --- a/components/soc/esp32s2beta/soc_memory_layout.c +++ b/components/soc/esp32s2beta/soc_memory_layout.c @@ -1,4 +1,4 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -16,10 +16,10 @@ #include #include +#include "sdkconfig.h" #include "soc/soc.h" #include "soc/soc_memory_layout.h" #include "esp_heap_caps.h" -#include "sdkconfig.h" /* Memory layout for ESP32 SoC */ @@ -51,11 +51,6 @@ const soc_memory_type_desc_t soc_memory_types[] = { //Type 4: SPI SRAM data //TODO, in fact, part of them support EDMA, to be supported. { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, - //Type 5: SPI SRAM data from AHB DBUS3, slower than normal - //TODO, add a bit to control the access of it -#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM - { "SPIRAM(Slow)", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, -#endif }; const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t); @@ -69,9 +64,6 @@ from low to high start address. const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available -#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM - { SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available -#endif #endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB #if CONFIG_ESP32S2_DATA_CACHE_0KB @@ -116,21 +108,18 @@ const soc_memory_region_t soc_memory_regions[] = { const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t); -extern int _data_start_xtos; +extern int _dram0_rtos_reserved_start; /* Reserved memory regions These are removed from the soc_memory_regions array when heaps are created. */ //ROM data region -SOC_RESERVE_MEMORY_REGION(0x3fffc000, (intptr_t)&_data_start_xtos, rom_data_region); +SOC_RESERVE_MEMORY_REGION((intptr_t)&_dram0_rtos_reserved_start, SOC_BYTE_ACCESSIBLE_HIGH, rom_data_region); // TODO: soc_memory_layout: handle trace memory regions - IDF-750 #ifdef CONFIG_SPIRAM SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); //SPI RAM gets added later if needed, in spiram.c; reserve it for now -#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM -SOC_RESERVE_MEMORY_REGION( SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH, extram_slow_data_region); //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now -#endif #endif diff --git a/components/soc/esp32s2beta/spi_periph.c b/components/soc/esp32s2beta/spi_periph.c index 9c8fe230b1..8f092af2a7 100644 --- a/components/soc/esp32s2beta/spi_periph.c +++ b/components/soc/esp32s2beta/spi_periph.c @@ -1,4 +1,4 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -18,7 +18,7 @@ /* Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc */ -const spi_signal_conn_t spi_periph_signal[4] = { +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { { .spiclk_out = SPICLK_OUT_IDX, .spiclk_in = 0,/* SPI clock is not an input signal*/ @@ -39,12 +39,13 @@ const spi_signal_conn_t spi_periph_signal[4] = { .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, .irq = ETS_SPI1_INTR_SOURCE, - .irq_dma = ETS_SPI1_DMA_INTR_SOURCE, + //TODO: SPI1 do not have DMA + /*.irq_dma = ETS_SPI1_DMA_INTR_SOURCE,*/ .module = PERIPH_SPI_MODULE, .hw = (spi_dev_t *) &SPIMEM1, .func = SPI_FUNC_NUM, }, { - .spiclk_out = FSPICLK_OUT_MUX_IDX, + .spiclk_out = FSPICLK_OUT_IDX, .spiclk_in = FSPICLK_IN_IDX, .spid_out = FSPID_OUT_IDX, .spiq_out = FSPIQ_OUT_IDX, @@ -93,31 +94,5 @@ const spi_signal_conn_t spi_periph_signal[4] = { .module = PERIPH_HSPI_MODULE, .hw = &GPSPI3, .func = -1, - }, { - .spiclk_out = SPI4_CLK_OUT_MUX_IDX, - .spiclk_in = SPI4_CLK_IN_IDX, - .spid_out = SPI4_D_OUT_IDX, - .spiq_out = SPI4_Q_OUT_IDX, - //SPI4 doesn't have wp and hd signals - .spiwp_out = -1, - .spihd_out = -1, - .spid_in = SPI4_D_IN_IDX, - .spiq_in = SPI4_Q_IN_IDX, - .spiwp_in = -1, - .spihd_in = -1, - .spics_out = {SPI4_CS0_OUT_IDX, SPI4_CS1_OUT_IDX, SPI4_CS2_OUT_IDX}, - .spics_in = SPI4_CS0_IN_IDX, - //SPI4 doesn't have iomux pins - .spiclk_iomux_pin = -1, - .spid_iomux_pin = -1, - .spiq_iomux_pin = -1, - .spiwp_iomux_pin = -1, - .spihd_iomux_pin = -1, - .spics0_iomux_pin = -1, - .irq = ETS_SPI4_INTR_SOURCE, - .irq_dma = ETS_SPI4_DMA_INTR_SOURCE, - .module = PERIPH_VSPI_MODULE, - .hw = &GPSPI4, - .func = -1, } }; diff --git a/components/soc/esp32s2beta/touch_sensor_periph.c b/components/soc/esp32s2beta/touch_sensor_periph.c index 6f5284ec67..8cb93711e7 100644 --- a/components/soc/esp32s2beta/touch_sensor_periph.c +++ b/components/soc/esp32s2beta/touch_sensor_periph.c @@ -27,9 +27,4 @@ const int touch_sensor_channel_io_map[SOC_TOUCH_SENSOR_NUM] = { TOUCH_PAD_NUM7_GPIO_NUM, TOUCH_PAD_NUM8_GPIO_NUM, TOUCH_PAD_NUM9_GPIO_NUM, - TOUCH_PAD_NUM10_GPIO_NUM, - TOUCH_PAD_NUM11_GPIO_NUM, - TOUCH_PAD_NUM12_GPIO_NUM, - TOUCH_PAD_NUM13_GPIO_NUM, - TOUCH_PAD_NUM14_GPIO_NUM }; diff --git a/components/soc/include/soc/interrupts.h b/components/soc/include/soc/interrupts.h index 50295d6262..cb2527eeb8 100644 --- a/components/soc/include/soc/interrupts.h +++ b/components/soc/include/soc/interrupts.h @@ -15,6 +15,7 @@ #pragma once #include "stdint.h" #include "soc/soc.h" +#include "soc/periph_defs.h" #ifdef __cplusplus extern "C" diff --git a/components/soc/include/soc/spi_periph.h b/components/soc/include/soc/spi_periph.h index a6ca2acb0a..1c3c94e2cc 100644 --- a/components/soc/include/soc/spi_periph.h +++ b/components/soc/include/soc/spi_periph.h @@ -33,7 +33,7 @@ extern "C" { #endif -#ifdef CONFIG_IDF_TARGET_ESP32S2BETA +#if CONFIG_IDF_TARGET_ESP32S2BETA #define SPI_FREAD_DIO 0 #define SPI_FREAD_QIO 0 #define SPI_FWRITE_DIO 0 diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c index f529d21a78..277e102820 100644 --- a/components/spi_flash/cache_utils.c +++ b/components/spi_flash/cache_utils.c @@ -26,6 +26,8 @@ #elif CONFIG_IDF_TARGET_ESP32S2BETA #include "esp32s2beta/rom/spi_flash.h" #include "esp32s2beta/rom/cache.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #endif #include #include @@ -36,7 +38,7 @@ #include "esp_spi_flash.h" #include "esp_log.h" -static __attribute__((unused)) const char* TAG = "cache"; +static __attribute__((unused)) const char *TAG = "cache"; #define DPORT_CACHE_BIT(cpuid, regid) DPORT_ ## cpuid ## regid @@ -51,7 +53,7 @@ static __attribute__((unused)) const char* TAG = "cache"; #define DPORT_CACHE_GET_VAL(cpuid) (cpuid == 0) ? DPORT_CACHE_VAL(PRO) : DPORT_CACHE_VAL(APP) #define DPORT_CACHE_GET_MASK(cpuid) (cpuid == 0) ? DPORT_CACHE_MASK(PRO) : DPORT_CACHE_MASK(APP) -static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state); +static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state); static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state); static uint32_t s_flash_op_cache_state[2]; @@ -86,7 +88,7 @@ void spi_flash_op_unlock(void) when accessing psram from the former CPU. */ -void IRAM_ATTR spi_flash_op_block_func(void* arg) +void IRAM_ATTR spi_flash_op_block_func(void *arg) { // Disable scheduler on this CPU vTaskSuspendAll(); @@ -136,7 +138,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void) // Signal to the spi_flash_op_block_task on the other CPU that we need it to // disable cache there and block other tasks from executing. s_flash_op_can_start = false; - esp_err_t ret = esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void*) other_cpuid); + esp_err_t ret = esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void *) other_cpuid); assert(ret == ESP_OK); while (!s_flash_op_can_start) { // Busy loop and wait for spi_flash_op_block_func to disable cache @@ -274,7 +276,7 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void) * function in ROM. They are used to work around a bug where Cache_Read_Disable requires a call to * Cache_Flush before Cache_Read_Enable, even if cached data was not modified. */ -static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state) +static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state) { #if CONFIG_IDF_TARGET_ESP32 uint32_t ret = 0; @@ -298,9 +300,6 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_st *saved_state = ret; #elif CONFIG_IDF_TARGET_ESP32S2BETA *saved_state = Cache_Suspend_ICache(); - if (!Cache_Drom0_Using_ICache()) { - *(saved_state + 1) = Cache_Suspend_DCache(); - } #endif } @@ -320,9 +319,6 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta #endif #elif CONFIG_IDF_TARGET_ESP32S2BETA Cache_Resume_ICache(saved_state); - if (!Cache_Drom0_Using_ICache()) { - Cache_Resume_DCache(s_flash_op_cache_state[1]); - } #endif } @@ -330,14 +326,11 @@ IRAM_ATTR bool spi_flash_cache_enabled(void) { #if CONFIG_IDF_TARGET_ESP32 bool result = (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) != 0); -#elif CONFIG_IDF_TARGET_ESP32S2BETA - bool result = (DPORT_REG_GET_BIT(DPORT_PRO_ICACHE_CTRL_REG, DPORT_PRO_ICACHE_ENABLE) != 0); - if (!Cache_Drom0_Using_ICache()) { - result = result && (DPORT_REG_GET_BIT(DPORT_PRO_DCACHE_CTRL_REG, DPORT_PRO_DCACHE_ENABLE) != 0); - } -#endif #if portNUM_PROCESSORS == 2 result = result && (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) != 0); +#endif +#elif CONFIG_IDF_TARGET_ESP32S2BETA + bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); #endif return result; } @@ -356,19 +349,13 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void) Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); cache_size = CACHE_SIZE_16KB; #endif -#if CONFIG_ESP32S2_INSTRUCTION_CACHE_4WAYS cache_ways = CACHE_4WAYS_ASSOC; -#else - cache_ways = CACHE_8WAYS_ASSOC; -#endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B cache_line_size = CACHE_LINE_SIZE_16B; -#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B - cache_line_size = CACHE_LINE_SIZE_32B; #else - cache_line_size = CACHE_LINE_SIZE_64B; + cache_line_size = CACHE_LINE_SIZE_32B; #endif - ESP_EARLY_LOGI(TAG, "Instruction cache \t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16,cache_ways == CACHE_4WAYS_ASSOC ? 4: 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64)); + ESP_EARLY_LOGI(TAG, "Instruction cache \t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); Cache_Suspend_ICache(); Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size); Cache_Invalidate_ICache_All(); @@ -399,32 +386,17 @@ IRAM_ATTR void esp_config_data_cache_mode(void) #endif #endif -#if CONFIG_ESP32S2_DATA_CACHE_4WAYS cache_ways = CACHE_4WAYS_ASSOC; -#else - cache_ways = CACHE_8WAYS_ASSOC; -#endif #if CONFIG_ESP32S2_DATA_CACHE_LINE_16B cache_line_size = CACHE_LINE_SIZE_16B; -#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B - cache_line_size = CACHE_LINE_SIZE_32B; #else - cache_line_size = CACHE_LINE_SIZE_64B; + cache_line_size = CACHE_LINE_SIZE_32B; #endif - ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4: 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64)); + ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, 4, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : 32); Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size); Cache_Invalidate_DCache_All(); } -void esp_switch_rodata_to_dcache(void) -{ - REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DROM0); - Cache_Drom0_Source_DCache(); - MMU_Drom_ICache_Unmap(); - REG_SET_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0); - ESP_EARLY_LOGI(TAG, "Switch rodata load path to data cache."); -} - static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) { uint32_t i_autoload, d_autoload; @@ -434,7 +406,7 @@ static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) if (dcache) { d_autoload = Cache_Suspend_DCache(); } - REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_FLASH_WRAP_AROUND); + REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND); if (icache) { Cache_Resume_ICache(i_autoload); } @@ -453,7 +425,7 @@ static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) if (dcache) { d_autoload = Cache_Suspend_DCache(); } - REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND); + REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND); if (icache) { Cache_Resume_ICache(i_autoload); } @@ -466,38 +438,36 @@ static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable) { int icache_wrap_size = 0, dcache_wrap_size = 0; - int flash_wrap_sizes[2]={-1, -1}, spiram_wrap_sizes[2]={-1, -1}; + int flash_wrap_sizes[2] = {-1, -1}, spiram_wrap_sizes[2] = {-1, -1}; int flash_wrap_size = 0, spiram_wrap_size = 0; int flash_count = 0, spiram_count = 0; int i; bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true; + uint32_t drom0_in_icache = 1;//always 1 in esp32s2 + if (icache_wrap_enable) { #if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B icache_wrap_size = 16; -#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B - icache_wrap_size = 32; #else - icache_wrap_size = 64; + icache_wrap_size = 32; #endif } if (dcache_wrap_enable) { #if CONFIG_ESP32S2_DATA_CACHE_LINE_16B dcache_wrap_size = 16; -#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B - dcache_wrap_size = 32; #else - dcache_wrap_size = 64; + dcache_wrap_size = 32; #endif } uint32_t instruction_use_spiram = 0; uint32_t rodata_use_spiram = 0; #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS -extern uint32_t esp_spiram_instruction_access_enabled(); + extern uint32_t esp_spiram_instruction_access_enabled(); instruction_use_spiram = esp_spiram_instruction_access_enabled(); #endif #if CONFIG_SPIRAM_RODATA -extern uint32_t esp_spiram_rodata_access_enabled(); + extern uint32_t esp_spiram_rodata_access_enabled(); rodata_use_spiram = esp_spiram_rodata_access_enabled(); #endif @@ -507,7 +477,7 @@ extern uint32_t esp_spiram_rodata_access_enabled(); flash_wrap_sizes[0] = icache_wrap_size; } if (rodata_use_spiram) { - if (Cache_Drom0_Using_ICache()) { + if (drom0_in_icache) { spiram_wrap_sizes[0] = icache_wrap_size; } else { spiram_wrap_sizes[1] = dcache_wrap_size; @@ -517,7 +487,7 @@ extern uint32_t esp_spiram_rodata_access_enabled(); spiram_wrap_sizes[1] = dcache_wrap_size; #endif } else { - if (Cache_Drom0_Using_ICache()) { + if (drom0_in_icache) { flash_wrap_sizes[0] = icache_wrap_size; } else { flash_wrap_sizes[1] = dcache_wrap_size; @@ -573,14 +543,19 @@ extern uint32_t esp_spiram_rodata_access_enabled(); return ESP_FAIL; } +#ifdef CONFIG_FLASHMODE_QIO + flash_support_wrap = true; extern bool spi_flash_support_wrap_size(uint32_t wrap_size); if (!spi_flash_support_wrap_size(flash_wrap_size)) { flash_support_wrap = false; ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size); } +#else + ESP_EARLY_LOGW(TAG, "Flash is not in QIO mode, do not support wrap."); +#endif #ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT -extern bool psram_support_wrap_size(uint32_t wrap_size); + extern bool psram_support_wrap_size(uint32_t wrap_size); if (!psram_support_wrap_size(spiram_wrap_size)) { spiram_support_wrap = false; ESP_EARLY_LOGW(TAG, "SPIRAM do not support wrap size %d.", spiram_wrap_size); @@ -592,16 +567,16 @@ extern bool psram_support_wrap_size(uint32_t wrap_size); return ESP_FAIL; } -extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size); + extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size); if (flash_support_wrap && flash_wrap_size > 0) { - ESP_EARLY_LOGI(TAG, "Flash wrap enabled."); + ESP_EARLY_LOGI(TAG, "Flash wrap enabled, size = %d.", flash_wrap_size); spi_flash_enable_wrap(flash_wrap_size); esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0)); } #if CONFIG_ESP32S2_SPIRAM_SUPPORT -extern esp_err_t psram_enable_wrap(uint32_t wrap_size); + extern esp_err_t psram_enable_wrap(uint32_t wrap_size); if (spiram_support_wrap && spiram_wrap_size > 0) { - ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled."); + ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled, size = %d.", spiram_wrap_size); psram_enable_wrap(spiram_wrap_size); esp_enable_cache_spiram_wrap((spiram_wrap_sizes[0] > 0), (spiram_wrap_sizes[1] > 0)); } diff --git a/components/spi_flash/cache_utils.h b/components/spi_flash/cache_utils.h index e57494c5af..11bf35f73a 100644 --- a/components/spi_flash/cache_utils.h +++ b/components/spi_flash/cache_utils.h @@ -50,17 +50,23 @@ void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void); // This function is implied to be called when other CPU is not running or running code from IRAM. void spi_flash_enable_interrupts_caches_no_os(void); -// Flushes cache if address range has corresponding valid cache mappings -// Recommended to use post flash program operation (erase or write) +// Mark the pages containing a flash region as having been +// erased or written to. This means the flash cache needs +// to be evicted before these pages can be flash_mmap()ed again, +// as they may contain stale data +// // Only call this while holding spi_flash_op_lock() // Returns true if cache was flushed, false otherwise bool spi_flash_check_and_flush_cache(uint32_t start_addr, uint32_t length); //config cache mode #ifdef CONFIG_IDF_TARGET_ESP32S2BETA +//config instrcutin cache size and cache block size by menuconfig void esp_config_instruction_cache_mode(void); +//config data cache size and cache block size by menuconfig void esp_config_data_cache_mode(void); -void esp_switch_rodata_to_dcache(void); +//enable cache wrap mode for instruction cache and data cache +esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable); #endif diff --git a/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c b/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c index e6656e2fb9..d0b08967b7 100644 --- a/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c +++ b/components/spi_flash/esp32s2beta/spi_flash_rom_patch.c @@ -194,10 +194,10 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t * uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG; if (g_rom_spiflash_dummy_len_plus[1] == 0) { + REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY); while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) { WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_RDSR); - REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_USR_DUMMY); while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask); @@ -255,7 +255,7 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chi if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) { //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN)); REG_WRITE(SPI_MEM_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_MEM_USR_MISO_DBITLEN_S); - WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8); + WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr); REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_MEM_USR); while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); @@ -266,7 +266,7 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chi temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM; } else { //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN )); - WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8); + WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr); REG_WRITE(SPI_MEM_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_MEM_USR_MISO_DBITLEN_S); REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_MEM_USR); while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); @@ -321,7 +321,7 @@ static void spi_cache_mode_switch(uint32_t modebit) } else if ((modebit & SPI_MEM_FREAD_DUAL)) { REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x3B); - } else{ + } else { REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, 0x0B); } diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index 7299cb47ba..459ba16396 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -50,6 +50,7 @@ __attribute__((unused)) static const char TAG[] = "spi_flash"; #define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD #endif +#if CONFIG_IDF_TARGET_ESP32 #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ .host_id = SPI_HOST,\ .speed = DEFAULT_FLASH_SPEED, \ @@ -57,6 +58,16 @@ __attribute__((unused)) static const char TAG[] = "spi_flash"; .iomux = false, \ .input_delay_ns = 0,\ } +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/efuse.h" +#define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \ + .host_id = SPI_HOST,\ + .speed = DEFAULT_FLASH_SPEED, \ + .cs_num = 0, \ + .iomux = true, \ + .input_delay_ns = 0,\ +} +#endif esp_flash_t *esp_flash_default_chip = NULL; @@ -181,6 +192,12 @@ static DRAM_ATTR esp_flash_t default_chip = { esp_err_t esp_flash_init_default_chip(void) { memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT(); + + #ifdef CONFIG_IDF_TARGET_ESP32S2BETA + // For esp32s2 spi IOs are configured as from IO MUX by default + cfg.iomux = ets_efuse_get_spiconfig() == 0 ? true : false; + #endif + //the host is already initialized, only do init for the data and load it to the host spi_flash_hal_init(&default_driver_data, &cfg); default_chip.host->driver_data = &default_driver_data; diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index f2ede57daa..7d6285ba48 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -38,6 +38,8 @@ #include "esp32s2beta/rom/spi_flash.h" #include "esp32s2beta/rom/cache.h" #include "esp32s2beta/spiram.h" +#include "soc/extmem_reg.h" +#include "soc/cache_memory.h" #endif #ifndef NDEBUG @@ -46,31 +48,31 @@ #endif #include "sys/queue.h" -#define PAGES_PER_REGION 64 #ifdef CONFIG_IDF_TARGET_ESP32 #define REGIONS_COUNT 4 #define IROM0_PAGES_START 64 #define IROM0_PAGES_END 256 #define DROM0_PAGES_START 0 #define DROM0_PAGES_END 64 - #define PAGE_IN_FLASH(page) (page) - -#elif CONFIG_IDF_TARGET_ESP32S2BETA -#define REGIONS_COUNT 8 -#define IROM0_PAGES_START (PRO_CACHE_IBUS0_MMU_START / sizeof(uint32_t)) -#define IROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t)) -#define DROM0_PAGES_START (Cache_Drom0_Using_ICache()? PRO_CACHE_IBUS3_MMU_START / sizeof(uint32_t) : PRO_CACHE_DBUS3_MMU_START /sizeof(uint32_t)) -#define DROM0_PAGES_END (Cache_Drom0_Using_ICache()? PRO_CACHE_IBUS3_MMU_END / sizeof(uint32_t) : PRO_CACHE_DBUS3_MMU_END / sizeof(uint32_t)) - -#define PAGE_IN_FLASH(page) ((page) | DPORT_MMU_ACCESS_FLASH) - -#endif +#define INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL #define MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#define REGIONS_COUNT 6 +#define IROM0_PAGES_START (PRO_CACHE_IBUS0_MMU_START / sizeof(uint32_t)) +#define IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t)) +#define DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t)) +#define DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t)) +#define DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define MMU_ADDR_MASK MMU_ADDRESS_MASK +#define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#endif + +#define PAGES_PER_REGION 64 #define IROM0_PAGES_NUM (IROM0_PAGES_END - IROM0_PAGES_START) #define DROM0_PAGES_NUM (DROM0_PAGES_END - DROM0_PAGES_START) #define PAGES_LIMIT (IROM0_PAGES_END > DROM0_PAGES_END ? IROM0_PAGES_END:DROM0_PAGES_END) -#define INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL #define VADDR0_START_ADDR SOC_DROM_LOW #define VADDR1_START_ADDR 0x40000000 #define VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW @@ -103,16 +105,16 @@ static void IRAM_ATTR spi_flash_mmap_init(void) if (entry_pro != entry_app) { // clean up entries used by boot loader - entry_pro = DPORT_FLASH_MMU_TABLE_INVALID_VAL; - DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; + entry_pro = INVALID_ENTRY_VAL; + DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; } #endif if ((entry_pro & INVALID_ENTRY_VAL) == 0 && (i == DROM0_PAGES_START || i == PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) { s_mmap_page_refcnt[i] = 1; } else { - DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; + DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; #if !CONFIG_FREERTOS_UNICORE - DPORT_APP_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; + DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; #endif } } diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index a8ffc78106..fe6962f60f 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include #include @@ -32,8 +30,12 @@ #include "esp_spi_flash.h" #include "esp_log.h" #if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/spi_flash.h" +#include "esp32/rom/cache.h" #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/spi_flash.h" +#include "esp32s2beta/rom/cache.h" #include "esp32s2beta/clk.h" #include "soc/spi_mem_reg.h" #include "soc/spi_mem_struct.h" @@ -804,7 +806,7 @@ esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode) SPIFLASH.user.fwrite_dio = 0; SPIFLASH.user.fwrite_dual = 0; SPIFLASH.user.fwrite_qio = 1; - SPIFLASH.user.fwrite_quad = 0; + SPIFLASH.user.fwrite_quad = 0; SPIFLASH.ctrl.fcmd_dual = 0; SPIFLASH.ctrl.fcmd_quad = 0; SPIFLASH.user.usr_dummy = 0; diff --git a/components/spi_flash/spi_flash_os_func_app.c b/components/spi_flash/spi_flash_os_func_app.c index d1f0d2b210..13c6269301 100644 --- a/components/spi_flash/spi_flash_os_func_app.c +++ b/components/spi_flash/spi_flash_os_func_app.c @@ -20,9 +20,9 @@ #include "hal/spi_types.h" -#ifdef CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/ets_sys.h" -#else +#elif CONFIG_IDF_TARGET_ESP32S2BETA #include "esp32s2beta/rom/ets_sys.h" #endif diff --git a/components/ulp/include/esp32s2/ulp.h b/components/ulp/include/esp32s2/ulp.h new file mode 100644 index 0000000000..58331cf52c --- /dev/null +++ b/components/ulp/include/esp32s2/ulp.h @@ -0,0 +1,839 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include +#include "esp_err.h" +#include "soc/soc.h" +#include "ulp_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */ +#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */ + +/** + * @defgroup ulp_registers ULP coprocessor registers + * @{ + */ + + +#define R0 0 /*!< general purpose register 0 */ +#define R1 1 /*!< general purpose register 1 */ +#define R2 2 /*!< general purpose register 2 */ +#define R3 3 /*!< general purpose register 3 */ +/**@}*/ + +/** @defgroup ulp_opcodes ULP coprocessor opcodes, sub opcodes, and various modifiers/flags + * + * These definitions are not intended to be used directly. + * They are used in definitions of instructions later on. + * + * @{ + */ + +#define OPCODE_WR_REG 1 /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define OPCODE_RD_REG 2 /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_I2C 3 /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */ + +#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ + +#define OPCODE_DELAY 4 /*!< Instruction: delay (nop) for a given number of cycles */ + +#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */ + +#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */ +#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */ + +#define OPCODE_ALU 7 /*!< Arithmetic instructions */ +#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */ +#define SUB_OPCODE_ALU_IMM 1 /*!< Arithmetic instruction, one source value is an immediate */ +#define SUB_OPCODE_ALU_CNT 2 /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/ +#define ALU_SEL_ADD 0 /*!< Addition */ +#define ALU_SEL_SUB 1 /*!< Subtraction */ +#define ALU_SEL_AND 2 /*!< Logical AND */ +#define ALU_SEL_OR 3 /*!< Logical OR */ +#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */ +#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */ +#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */ + +#define OPCODE_BRANCH 8 /*!< Branch instructions */ +#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */ +#define BX_JUMP_TYPE_DIRECT 0 /*!< Unconditional jump */ +#define BX_JUMP_TYPE_ZERO 1 /*!< Branch if last ALU result is zero */ +#define BX_JUMP_TYPE_OVF 2 /*!< Branch if last ALU operation caused and overflow */ +#define SUB_OPCODE_B 1 /*!< Branch to a relative offset */ +#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */ +#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */ + +#define OPCODE_END 9 /*!< Stop executing the program */ +#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */ +#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */ + +#define OPCODE_TSENS 10 /*!< Instruction: temperature sensor measurement (not implemented yet) */ + +#define OPCODE_HALT 11 /*!< Halt the coprocessor */ + +#define OPCODE_LD 13 /*!< Indirect load lower 16 bits from RTC memory */ + +#define OPCODE_MACRO 15 /*!< Not a real opcode. Used to identify labels and branches in the program */ +#define SUB_OPCODE_MACRO_LABEL 0 /*!< Label macro */ +#define SUB_OPCODE_MACRO_BRANCH 1 /*!< Branch macro */ +/**@}*/ + +/** + * @brief Instruction format structure + * + * All ULP instructions are 32 bit long. + * This union contains field layouts used by all of the supported instructions. + * This union also includes a special "macro" instruction layout. + * This is not a real instruction which can be executed by the CPU. It acts + * as a token which is removed from the program by the + * ulp_process_macros_and_load function. + * + * These structures are not intended to be used directly. + * Preprocessor definitions provided below fill the fields of these structure with + * the right arguments. + */ +union ulp_insn { + + struct { + uint32_t cycles : 16; /*!< Number of cycles to sleep */ + uint32_t unused : 12; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_DELAY) */ + } delay; /*!< Format of DELAY instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains data to store */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ST) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ST) */ + } st; /*!< Format of ST instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where the data should be loaded to */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 7; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_LD) */ + } ld; /*!< Format of LD instruction */ + + struct { + uint32_t unused : 28; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_HALT) */ + } halt; /*!< Format of HALT instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */ + uint32_t addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t reg : 1; /*!< Target PC in register (1) or immediate (0) */ + uint32_t type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } bx; /*!< Format of BRANCH instruction (absolute address) */ + + struct { + uint32_t imm : 16; /*!< Immediate value to compare against */ + uint32_t cmp : 1; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */ + uint32_t offset : 7; /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */ + uint32_t sign : 1; /*!< Sign of target PC offset: 0: positive, 1: negative */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_B) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } b; /*!< Format of BRANCH instruction (relative address) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t treg : 2; /*!< Register with operand B */ + uint32_t unused : 15; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t imm : 16; /*!< Immediate value of operand B */ + uint32_t unused : 1; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_imm; /*!< Format of ALU instruction (one source is an immediate) */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t data : 8; /*!< 8 bits of data to write */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } wr_reg; /*!< Format of WR_REG instruction */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } rd_reg; /*!< Format of RD_REG instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store ADC result */ + uint32_t mux : 4; /*!< Select SARADC pad (mux + 1) */ + uint32_t sar_sel : 1; /*!< Select SARADC0 (0) or SARADC1 (1) */ + uint32_t unused1 : 1; /*!< Unused */ + uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_ADC) */ + } adc; /*!< Format of ADC instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store temperature measurement result */ + uint32_t wait_delay: 14; /*!< Cycles to wait after measurement is done */ + uint32_t reserved: 12; /*!< Reserved, set to 0 */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_TSENS) */ + } tsens; /*!< Format of TSENS instruction */ + + struct { + uint32_t i2c_addr : 8; /*!< I2C slave address */ + uint32_t data : 8; /*!< Data to read or write */ + uint32_t low_bits : 3; /*!< TBD */ + uint32_t high_bits : 3; /*!< TBD */ + uint32_t i2c_sel : 4; /*!< TBD, select reg_i2c_slave_address[7:0] */ + uint32_t unused : 1; /*!< Unused */ + uint32_t rw : 1; /*!< Write (1) or read (0) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_I2C) */ + } i2c; /*!< Format of I2C instruction */ + + struct { + uint32_t wakeup : 1; /*!< Set to 1 to wake up chip */ + uint32_t unused : 24; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } end; /*!< Format of END instruction with wakeup */ + + struct { + uint32_t cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */ + uint32_t unused : 21; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } sleep; /*!< Format of END instruction with sleep */ + + struct { + uint32_t label : 16; /*!< Label number */ + uint32_t unused : 8; /*!< Unused */ + uint32_t sub_opcode : 4; /*!< SUB_OPCODE_MACRO_LABEL or SUB_OPCODE_MACRO_BRANCH */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_MACRO) */ + } macro; /*!< Format of tokens used by LABEL and BRANCH macros */ + +}; + +typedef union ulp_insn ulp_insn_t; + +_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes"); + +/** + * Delay (nop) for a given number of cycles + */ +#define I_DELAY(cycles_) { .delay = {\ + .cycles = cycles_, \ + .unused = 0, \ + .opcode = OPCODE_DELAY } } + +/** + * Halt the coprocessor. + * + * This instruction halts the coprocessor, but keeps ULP timer active. + * As such, ULP program will be restarted again by timer. + * To stop the program and prevent the timer from restarting the program, + * use I_END(0) instruction. + */ +#define I_HALT() { .halt = {\ + .unused = 0, \ + .opcode = OPCODE_HALT } } + +/** + * Map SoC peripheral register to periph_sel field of RD_REG and WR_REG + * instructions. + * + * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. + * @return periph_sel value for the peripheral to which this register belongs. + */ +static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { + uint32_t ret = 3; + if (reg < DR_REG_RTCCNTL_BASE) { + assert(0 && "invalid register base"); + } else if (reg < DR_REG_RTCIO_BASE) { + ret = RD_REG_PERIPH_RTC_CNTL; + } else if (reg < DR_REG_SENS_BASE) { + ret = RD_REG_PERIPH_RTC_IO; + } else if (reg < DR_REG_RTC_I2C_BASE){ + ret = RD_REG_PERIPH_SENS; + } else if (reg < DR_REG_IO_MUX_BASE){ + ret = RD_REG_PERIPH_RTC_I2C; + } else { + assert(0 && "invalid register base"); + } + return ret; +} + +/** + * Write literal value to a peripheral register + * + * reg[high_bit : low_bit] = val + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .data = val, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_WR_REG } } + +/** + * Read from peripheral register into R0 + * + * R0 = reg[high_bit : low_bit] + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .unused = 0, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_RD_REG } } + +/** + * Set or clear a bit in the peripheral register. + * + * Sets bit (1 << shift) of register reg to value val. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) + +/** + * Wake the SoC from deep sleep. + * + * This instruction initiates wake up from deep sleep. + * Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup + * triggered by the ULP before going into deep sleep. + * Note that ULP program will still keep running until the I_HALT + * instruction, and it will still be restarted by timer at regular + * intervals, even when the SoC is woken up. + * + * To stop the ULP program, use I_HALT instruction. + * + * To disable the timer which start ULP program, use I_END() + * instruction. I_END instruction clears the + * RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG + * register, which controls the ULP timer. + */ +#define I_WAKE() { .end = { \ + .wakeup = 1, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_END, \ + .opcode = OPCODE_END } } + +/** + * Stop ULP program timer. + * + * This is a convenience macro which disables the ULP program timer. + * Once this instruction is used, ULP program will not be restarted + * anymore until ulp_run function is called. + * + * ULP program will continue running after this instruction. To stop + * the currently running program, use I_HALT(). + */ +#define I_END() \ + I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0) +/** + * Select the time interval used to run ULP program. + * + * This instructions selects which of the SENS_SLEEP_CYCLES_Sx + * registers' value is used by the ULP program timer. + * When the ULP program stops at I_HALT instruction, ULP program + * timer start counting. When the counter reaches the value of + * the selected SENS_SLEEP_CYCLES_Sx register, ULP program + * start running again from the start address (passed to the ulp_run + * function). + * There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5. + * + * By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP + * program timer. + */ +#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \ + .cycle_sel = timer_idx, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_SLEEP, \ + .opcode = OPCODE_END } } + +/** + * Perform temperature sensor measurement and store it into reg_dest. + * + * Delay can be set between 1 and ((1 << 14) - 1). Higher values give + * higher measurement resolution. + */ +#define I_TSENS(reg_dest, delay) { .tsens = { \ + .dreg = reg_dest, \ + .wait_delay = delay, \ + .reserved = 0, \ + .opcode = OPCODE_TSENS } } + +/** + * Perform ADC measurement and store result in reg_dest. + * + * adc_idx selects ADC (0 or 1). + * pad_idx selects ADC pad (0 - 7). + */ +#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ + .dreg = reg_dest, \ + .mux = pad_idx + 1, \ + .sar_sel = adc_idx, \ + .unused1 = 0, \ + .cycles = 0, \ + .unused2 = 0, \ + .opcode = OPCODE_ADC } } + +/** + * Store value from register reg_val into RTC memory. + * + * The value is written to an offset calculated by adding value of + * reg_addr register and offset_ field (this offset is expressed in 32-bit words). + * 32 bits written to RTC memory are built as follows: + * - bits [31:21] hold the PC of current instruction, expressed in 32-bit words + * - bits [20:16] = 5'b1 + * - bits [15:0] are assigned the contents of reg_val + * + * RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] } + */ +#define I_ST(reg_val, reg_addr, offset_) { .st = { \ + .dreg = reg_val, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .sub_opcode = SUB_OPCODE_ST, \ + .opcode = OPCODE_ST } } + + +/** + * Load value from RTC memory into reg_dest register. + * + * Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and + * value of offset_. + */ +#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ + .dreg = reg_dest, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .opcode = OPCODE_LD } } + + +/** + * Branch relative if R0 less than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BL(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_L, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch relative if R0 greater or equal than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BGE(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_GE, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXZR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXZI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, address in register + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXFR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, immediate address + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXFI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + + +/** + * Addition: dest = src1 + src2 + */ +#define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Subtraction: dest = src1 - src2 + */ +#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND: dest = src1 & src2 + */ +#define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR: dest = src1 | src2 + */ +#define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Copy: dest = src + */ +#define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = 0, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left: dest = src << shift + */ +#define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right: dest = src >> shift + */ +#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Add register and an immediate value: dest = src1 + imm + */ +#define I_ADDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Subtract register and an immediate value: dest = src - imm + */ +#define I_SUBI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND register and an immediate value: dest = src & imm + */ +#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR register and an immediate value: dest = src | imm + */ +#define I_ORI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Copy an immediate value into register: dest = imm + */ +#define I_MOVI(reg_dest, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = 0, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left register value by an immediate: dest = src << imm + */ +#define I_LSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right register value by an immediate: dest = val >> imm + */ +#define I_RSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Define a label with number label_num. + * + * This is a macro which doesn't generate a real instruction. + * The token generated by this macro is removed by ulp_process_macros_and_load + * function. Label defined using this macro can be used in branch macros defined + * below. + */ +#define M_LABEL(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_LABEL, \ + .opcode = OPCODE_MACRO } } + +/** + * Token macro used by M_B and M_BX macros. Not to be used directly. + */ +#define M_BRANCH(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_BRANCH, \ + .opcode = OPCODE_MACRO } } + +/** + * Macro: branch to label label_num if R0 is less than immediate value. + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BL(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BL(0, imm_value) + +/** + * Macro: branch to label label_num if R0 is greater or equal than immediate value + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BGE(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BGE(0, imm_value) + +/** + * Macro: unconditional branch to label + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BX(label_num) \ + M_BRANCH(label_num), \ + I_BXI(0) + +/** + * Macro: branch to label if ALU result is zero + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXZ(label_num) \ + M_BRANCH(label_num), \ + I_BXZI(0) + +/** + * Macro: branch to label if ALU overflow + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXF(label_num) \ + M_BRANCH(label_num), \ + I_BXFI(0) + + + +#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */ + +#ifdef __cplusplus +} +#endif diff --git a/components/wpa_supplicant/src/rsn_supp/wpa.h b/components/wpa_supplicant/src/rsn_supp/wpa.h index ef958d72eb..f3ddd14d61 100644 --- a/components/wpa_supplicant/src/rsn_supp/wpa.h +++ b/components/wpa_supplicant/src/rsn_supp/wpa.h @@ -19,7 +19,7 @@ #ifdef CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/ets_sys.h" -#else +#elif CONFIG_IDF_TARGET_ESP32S2BETA #include "esp32s2beta/rom/ets_sys.h" #endif #include "utils/common.h" @@ -111,7 +111,7 @@ struct l2_ethhdr { * handler if send_eapol() is used. */ -#define KEYENTRY_TABLE_MAP(key_entry_valid) ((key_entry_valid)%5) +#define KEYENTRY_TABLE_MAP(key_entry_valid) ((key_entry_valid)%5) void pp_michael_mic_failure(u16 isunicast); diff --git a/components/xtensa/debug_helpers.c b/components/xtensa/debug_helpers.c index 74f66a6cc4..ff457c7fc0 100644 --- a/components/xtensa/debug_helpers.c +++ b/components/xtensa/debug_helpers.c @@ -20,9 +20,9 @@ #include "soc/soc_memory_layout.h" #include "soc/cpu.h" -#ifdef CONFIG_IDF_TARGET_ESP32 +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/ets_sys.h" -#else +#elif CONFIG_IDF_TARGET_ESP32S2BETA #include "esp32s2beta/rom/ets_sys.h" #endif diff --git a/examples/get-started/hello_world/main/hello_world_main.c b/examples/get-started/hello_world/main/hello_world_main.c index 2586eb1a84..e77056c6cb 100644 --- a/examples/get-started/hello_world/main/hello_world_main.c +++ b/examples/get-started/hello_world/main/hello_world_main.c @@ -13,14 +13,6 @@ #include "esp_system.h" #include "esp_spi_flash.h" -#ifdef CONFIG_IDF_TARGET_ESP32 -#define CHIP_NAME "ESP32" -#endif - -#ifdef CONFIG_IDF_TARGET_ESP32S2BETA -#define CHIP_NAME "ESP32-S2 Beta" -#endif - void app_main(void) { printf("Hello world!\n"); @@ -29,7 +21,7 @@ void app_main(void) esp_chip_info_t chip_info; esp_chip_info(&chip_info); printf("This is %s chip with %d CPU cores, WiFi%s%s, ", - CHIP_NAME, + CONFIG_IDF_TARGET, chip_info.cores, (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "", (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : ""); diff --git a/tools/ci/executable-list.txt b/tools/ci/executable-list.txt index bea16d10f5..b17e9511ed 100644 --- a/tools/ci/executable-list.txt +++ b/tools/ci/executable-list.txt @@ -56,7 +56,6 @@ tools/cmake/convert_to_cmake.py tools/cmake/run_cmake_lint.sh tools/docker/entrypoint.sh tools/docker/hooks/build -tools/elf_to_ld.sh tools/esp_app_trace/logtrace_proc.py tools/esp_app_trace/sysviewtrace_proc.py tools/esp_app_trace/test/logtrace/test.sh diff --git a/tools/cmake/toolchain-esp32s2.cmake b/tools/cmake/toolchain-esp32s2.cmake new file mode 100644 index 0000000000..3ec83543af --- /dev/null +++ b/tools/cmake/toolchain-esp32s2.cmake @@ -0,0 +1,9 @@ +set(CMAKE_SYSTEM_NAME Generic) + +set(CMAKE_C_COMPILER xtensa-esp32s2-elf-gcc) +set(CMAKE_CXX_COMPILER xtensa-esp32s2-elf-g++) +set(CMAKE_ASM_COMPILER xtensa-esp32s2-elf-gcc) + +set(CMAKE_EXE_LINKER_FLAGS "-nostdlib" CACHE STRING "Linker Base Flags") +set(CMAKE_C_FLAGS "-mlongcalls" CACHE STRING "C Compiler Base Flags") +set(CMAKE_CXX_FLAGS "-mlongcalls" CACHE STRING "C++ Compiler Base Flags") diff --git a/tools/elf_to_ld.sh b/tools/elf_to_ld.sh deleted file mode 100755 index 138f24d602..0000000000 --- a/tools/elf_to_ld.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/bash - -echo '/*' -echo 'ESP32 ROM address table' -echo 'Generated for ROM with MD5sum:' -md5sum $1 -echo '*/' -xtensa-esp108-elf-nm $1 | grep '[0-9a-f] [TBRD]' | while read adr ttp nm; do - if ! echo "$nm" | grep -q -e '^_bss' -e '_heap'; then - echo "PROVIDE ( $nm = 0x$adr );"; - fi -done \ No newline at end of file diff --git a/tools/idf_py_actions/constants.py b/tools/idf_py_actions/constants.py index a7e81a2b29..0534f6c11a 100644 --- a/tools/idf_py_actions/constants.py +++ b/tools/idf_py_actions/constants.py @@ -35,4 +35,4 @@ GENERATORS = { } } -SUPPORTED_TARGETS = ["esp32", "esp32s2beta"] +SUPPORTED_TARGETS = ["esp32", "esp32s2beta", "esp32s2"] diff --git a/tools/unit-test-app/tools/UnitTestParser.py b/tools/unit-test-app/tools/UnitTestParser.py index eff151f11d..edb04c4ab8 100644 --- a/tools/unit-test-app/tools/UnitTestParser.py +++ b/tools/unit-test-app/tools/UnitTestParser.py @@ -70,6 +70,21 @@ class Parser(object): :param config_output_folder: build folder of this config :param config_name: built unit test config name """ + tags = self.parse_tags(os.path.join(config_output_folder, self.SDKCONFIG_FILE)) + print("Tags of config %s: %s" % (config_name, tags)) + # Search in tags to set the target + target_tag_dict = {"ESP32_IDF": "esp32", "ESP32S2BETA_IDF": "esp32s2beta"} + for tag in target_tag_dict: + if tag in tags: + target = target_tag_dict[tag] + break + else: + target = "esp32" + + if target == "esp32s2beta": + # Unit tests temporarily disabled for beta chip + return [] + test_groups = self.get_test_groups(os.path.join(configs_folder, config_name)) elf_file = os.path.join(config_output_folder, self.ELF_FILE) @@ -78,8 +93,6 @@ class Parser(object): subprocess.check_output('xtensa-esp32-elf-objdump -s {} > section_table.tmp'.format(elf_file), shell=True) table = CreateSectionTable.SectionTable("section_table.tmp") - tags = self.parse_tags(os.path.join(config_output_folder, self.SDKCONFIG_FILE)) - print("Tags of config %s: %s" % (config_name, tags)) test_cases = [] # we could split cases of same config into multiple binaries as we have limited rom space @@ -102,15 +115,6 @@ class Parser(object): desc = table.get_string("any", desc_addr) file_name = table.get_string("any", file_name_addr) - # Search in tags to set the target - target_tag_dict = {"ESP32_IDF": "esp32", "ESP32S2BETA_IDF": "esp32s2beta"} - for tag in target_tag_dict: - if tag in tags: - target = target_tag_dict[tag] - break - else: - target = "esp32" - tc = self.parse_one_test_case(name, desc, file_name, config_name, stripped_config_name, tags, target) # check if duplicated case names